Multi-pulse test circuit and test method for simultaneously testing multiple power semiconductors
By designing a multi-pulse test circuit and method, the problem of being unable to simulate real continuous working conditions and evaluate device reliability in existing technologies has been solved. This enables performance comparison and reliability testing of multiple power semiconductor devices, provides a test environment consistent with actual operating conditions, and reduces test losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA THREE GORGES CORPORATION
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-17
AI Technical Summary
Existing dual-pulse testing methods cannot simulate real continuous operating conditions, cannot assess the long-term reliability of devices, and cannot test and compare the characteristic parameters of different devices in the same circuit.
A multi-pulse test circuit and method are designed using a bidirectional power conversion circuit, which can simultaneously test multiple power semiconductor devices in the same circuit, including DC adjustable power supplies, charging switches, anti-reverse diodes, DC capacitors, inductors and energy storage batteries. The multi-pulse test simulates the actual working conditions of the devices through various test modes.
It enables the comparison of performance parameters of multiple power semiconductor devices in the same circuit, and can evaluate the reliability and dynamic characteristics of the devices, providing a test environment consistent with actual operating conditions and reducing the energy loss of test power supply and load.
Smart Images
Figure CN121878413A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of power semiconductor testing technology, and in particular relates to a multi-pulse test circuit and test method for simultaneously testing multiple power semiconductors. Background Technology
[0002] The switching and reverse recovery characteristics of power semiconductor devices are tested using a double-pulse test, a technique that has been used on Si devices for over 20 years. The double-pulse test is a recognized standard testing method in industry and academia, ensuring comparability of test results from different devices or laboratories, and serving as a crucial basis for device selection and performance evaluation.
[0003] The dual-pulse test provides an environment close to the actual operating conditions of power semiconductor devices, allowing testing under high voltage and high current (typically reaching the device's rated values), which is closer to real-world application scenarios than simple parameter tables or simulations. Furthermore, test conditions can be flexibly adjusted, such as DC bus voltage (Vdc), load current (IL), gate resistance (Rg), and junction temperature (Tj), to study their impact on switching characteristics.
[0004] Dual-pulse testing precisely controls the switching process of the device under test (DUT) under specific voltage and current conditions by applying two narrow pulses, thereby measuring key dynamic parameters. The dual-pulse test circuit can accurately measure dynamic parameters, including switching time (turn-on delay, rise time, turn-off delay, fall time), switching losses (turn-on loss Eon, turn-off loss Eoff), and reverse recovery characteristics (for freewheeling diodes), clearly distinguishing between the on and off processes. The dual-pulse waveform clearly displays phenomena such as voltage and current overshoot, oscillation, Miller plateau, diode reverse recovery current, and voltage and current tailing, aiding in the diagnosis of parasitic parameter effects (such as parasitic inductance and capacitance), drive circuit design problems, and the inherent characteristics of the device.
[0005] A typical dual-pulse test circuit consists of a test power supply, a DC capacitor, a switch under test, a test diode, and a load inductor. The circuit is relatively simple and the cost is moderate. Compared with a complex full-power continuous operation test platform, the DPT circuit topology is simple and relatively convenient to build and implement.
[0006] The dual-pulse test circuit has certain limitations in device testing, mainly in the following aspects: 1. Unable to simulate real continuous working conditions With a short interval between the two pulses, the junction temperature of the device remains basically at the initial ambient temperature, which cannot reflect the steady-state junction temperature under actual continuous switching and its impact on switching characteristics, such as increased switching losses and changes in threshold voltage at high temperatures.
[0007] Examining only a single or a few switching transients makes it impossible to assess reliability issues under long-term operation, such as threshold voltage drift, gate aging, and material fatigue. It also makes it impossible to accurately evaluate the device's loss characteristics.
[0008] 2. It is impossible to test and compare the characteristic parameters of different components in the same circuit. Double-pulse testing reflects a single switching event of a single device under specific conditions. Only a single device can be tested in the same circuit, while device performance may vary in real-world applications. It is impossible to compare and analyze the differences between different devices within the same circuit. Summary of the Invention
[0009] To address the aforementioned issues, this disclosure employs a bidirectional power conversion circuit, enabling the device to be tested under conditions as similar as possible to the actual operating circuit. This results in low losses and a simple control method, allowing for batch reliability testing of semiconductor devices and achieving effective evaluation of the package reliability and dynamic characteristics of semiconductor devices.
[0010] In a first aspect, embodiments of this disclosure provide a multi-pulse test circuit for simultaneously testing multiple power semiconductors, including a DC adjustable power supply, a charging switch, a reverse protection diode, a DC capacitor, an inductor, and an energy storage battery; The positive terminal of the DC adjustable power supply, the charging switch, the positive terminal of the anti-reverse diode, the inductor, the positive terminal of the energy storage battery, the negative terminal of the energy storage battery, and the negative terminal of the DC adjustable power supply are connected in series to form a circuit. The positive terminal of the DC capacitor is connected to the negative terminal of the anti-reverse diode, and the negative terminal of the DC capacitor is connected to the negative terminal of the DC adjustable power supply. Specifically, a first measuring point is set between the positive terminal of the DC capacitor and the inductor to connect the first device under test; a second measuring point is set between the connection point of the first measuring point and the inductor and the negative terminal of the energy storage battery to connect the second device under test.
[0011] Furthermore, The first device under test is a first diode under test and / or a first controllable switch transistor under test; The second device under test is a second diode under test and / or a second controllable switch transistor under test.
[0012] Furthermore, The first diode under test, the first controllable switch under test, the second diode under test, and the second controllable switch under test can each be a single device, or multiple devices of the same type connected in series or in parallel.
[0013] Furthermore, The first diode under test and the first controllable switch under test are each individually connected to the first test point, or the first diode under test and the first controllable switch under test are connected in parallel to the first test point.
[0014] Furthermore, The second diode under test and the second controllable switch under test are each individually connected to the second test point, or the second diode under test and the second controllable switch under test are connected in parallel to the second test point.
[0015] Furthermore, Devices under test with different substrate materials are connected simultaneously at the first and second measurement points.
[0016] Secondly, based on the same inventive concept, embodiments of this disclosure also provide a multi-pulse testing method for simultaneously testing multiple power semiconductors, applicable to any of the aforementioned circuits, the method comprising: Select a test mode, which includes multi-pulse power cycle mode, forward mode, reverse mode, and equalization or current equalization characteristic mode; According to the selected test mode, connect the device under test to the first test point and the second test point; To start the test, close the charging switch and charge the DC capacitor to the target test voltage via the anti-reverse diode. Perform the test according to the selected test mode and record the test parameters.
[0017] Furthermore, In the multi-pulse power cycling mode, the charging switch is turned off, and the on / off state of the controllable switch tube connected to the first test point and the controllable switch tube connected to the second test point is controlled to cycle through charging and discharging of the energy storage battery, and multi-pulse testing is performed on the device under test connected to the first and second test points.
[0018] Furthermore, In the forward mode, the charging switch is turned off and the controllable switch connected to the second test point is connected; the on / off state of the controllable switch connected to the first test point is controlled to perform multi-pulse testing on the device under test connected to the second test point.
[0019] Furthermore, In reverse mode, the charging switch is disconnected and the controllable switch at the first test point is connected; the on / off state of the controllable switch at the second test point is controlled to perform multi-pulse testing on the device under test connected to the first test point.
[0020] Compared with the prior art, this disclosure provides a multi-pulse test circuit and test method for simultaneously testing multiple power semiconductors, which has the following advantages: 1. It can test different types of devices simultaneously in the same circuit, providing test points for multiple test objects. It can simultaneously measure multiple different power semiconductor switching devices and diode devices, and compare the performance parameters of SiC-based and Si-based IGBT and diode devices in the same test circuit environment.
[0021] 2. The test circuit of this disclosure embodiment can operate in multiple modes such as forward, reverse, and bidirectional power cycling, so that the device can be tested under conditions that are as similar as possible to the actual working circuit.
[0022] 3. In power cycling mode, voltage equalization tests can be performed on devices under series conditions and current equalization tests under parallel conditions.
[0023] 4. In power cycling mode, the energy storage battery is used as the load or power source to achieve bidirectional power conversion; the DC power supply only needs to cover the losses of this circuit itself, which reduces the capacity requirements of the test power supply and also reduces the energy loss of the load during the test.
[0024] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 A schematic diagram of a multi-pulse test circuit topology for simultaneously testing multiple power semiconductors according to an embodiment of the present disclosure is shown. Figure 2 A schematic diagram illustrating the principle of forward testing of a multi-pulse test circuit according to an embodiment of the present disclosure is shown; Figure 3 A schematic diagram illustrating the principle of reverse testing of a multi-pulse test circuit according to an embodiment of the present disclosure is shown; Figure 4 A schematic diagram of the series connection structure of the semiconductor device under test according to an embodiment of the present disclosure is shown; Figure 5 A schematic diagram of the parallel connection structure of the semiconductor devices under test according to an embodiment of the present disclosure is shown. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0028] Figure 1 This invention discloses a multi-pulse test circuit topology for simultaneously testing multiple power semiconductors according to an embodiment of the present disclosure. The multi-pulse test circuit of the present disclosure includes a DC adjustable power supply Uc, a charging switch K1, a reverse protection diode Df, a DC capacitor C, an inductor L, and an energy storage battery E.
[0029] The positive terminal of the DC adjustable power supply Uc, the charging switch K1, the positive terminal of the anti-reverse diode Df, the inductor L, the positive terminal of the energy storage battery E, the negative terminal of the energy storage battery E, and the negative terminal of the DC adjustable power supply Uc are connected in series to form a circuit. The positive terminal of the DC capacitor C is connected to the negative terminal of the anti-reverse diode Df, and the negative terminal of the DC capacitor C is connected to the negative terminal of the DC adjustable power supply Uc. A first test point is set between the positive terminal of the DC capacitor C and the inductor L for connecting a first device under test (DUT). A second test point is set between the connection point of the first test point and the inductor L and the negative terminal of the energy storage battery E for connecting a second DUT. The first DUT is the first diode D2 and / or the first controllable switch T2; the second DUT is the second diode D1 and / or the second controllable switch T1.
[0030] As an alternative approach, the first diode under test D2, the first controllable switch under test T2, the second diode under test D1, and the second controllable switch under test T1 can be a single device, or multiple devices of the same type connected in series or in parallel.
[0031] The first diode under test D2 and the first controllable switch under test T2 are each individually connected to the first test point, or the first diode under test D2 and the first controllable switch under test T2 are connected in parallel to the first test point.
[0032] The second diode under test D1 and the second controllable switch under test T1 are each individually connected to the second test point, or the second diode under test D1 and the second controllable switch under test T1 are connected in parallel to the second test point.
[0033] The first and second measurement points allow for simultaneous parameter comparison tests on semiconductor devices with different substrate materials (such as Si substrate or SiC substrate).
[0034] The adjustable DC power supply UC provides an adjustable DC voltage to the test circuit. Upon initial test startup, closing the charging switch K1 charges the DC capacitor C to the target test voltage via the anti-reverse diode D.
[0035] Specifically, when the test circuit in this embodiment is working, it can use a forward loop test mode to provide a multi-pulse test environment for the second diode under test (D1) and the first controllable switch under test (T2); it can use a reverse loop test mode to provide a multi-pulse test environment for the first diode under test (D2) and the second controllable switch under test (T1); or it can use a forward and reverse power cycle test mode to simultaneously provide a test environment for all four devices under test: the second diode under test (D1), the first controllable switch under test (T2), the first diode under test (D2), and the second controllable switch under test (T1). During circuit operation, parameter optimization design ensures that the DC capacitor and the energy storage battery do not exceed their maximum operating voltage.
[0036] In the forward loop, as shown in the attached diagram. Figure 2 As shown, the circuit is a Buck converter. The DC capacitor C forms a circuit through the second diode under test (DUT), the first controllable switch under test (T2), the inductor L, and the energy storage battery E, charging the battery E. The second DUT, D1, and the first TUT are the devices under test (DUTs). By controlling the on / off state of the first TUT, multi-pulse testing of the second DUT, D1, and T2 is achieved to verify static characteristics, threshold voltage drift, gate aging, material fatigue, and loss characteristics.
[0037] In the reverse loop, as shown in the attached diagram. Figure 3 As shown, the circuit is a Boost converter. A loop is formed by the DC capacitor C, the first diode under test (D2), the second controllable switch under test (T1), the inductor L, and the energy storage battery E. The energy storage battery E discharges into the DC capacitor C. The first D2 and the second T1 are the devices under test. By controlling the switching of the second T1, multi-pulse testing of the first D2 and the second T1 is achieved to verify the static characteristics of the devices, including threshold voltage drift, gate aging, material fatigue, and loss characteristics.
[0038] In the power cycle test mode, the energy storage battery E serves as the load. By turning on and off the first controllable switch T2 and the second controllable switch T1, a bidirectional DC-DC circuit is formed to realize active power cycle multi-pulse test and verify the static characteristics of the devices at the first and second test points, such as threshold voltage drift, gate aging, material fatigue, and loss characteristics.
[0039] Furthermore, in the test circuit of this embodiment, both the first and second test points can test the parallel or series connection of semiconductor devices under power cycling test conditions, to verify the voltage sharing characteristics under series connection and the current sharing characteristics under parallel connection. The series structure of the semiconductor devices is as follows: Figure 4 , Figure 5 As shown.
[0040] The test circuit in this embodiment can provide an operating environment consistent with the actual operating conditions of power semiconductor devices. It has comprehensive testing functions, low loss and simple control methods, and can complete batch reliability testing of semiconductor devices, thus achieving effective evaluation of the package reliability and dynamic characteristics of power semiconductor devices.
[0041] Based on the same inventive concept disclosed above, this disclosure also provides a multi-pulse test method for simultaneously testing multiple power semiconductors, applicable to the aforementioned test circuit, the method comprising: Select a test mode, which includes multi-pulse power cycle mode, forward mode, reverse mode, and equalization or current equalization characteristic mode; According to the selected test mode, connect the device under test to the first test point and the second test point; To start the test, close the charging switch K1 and charge the DC capacitor C to the target test voltage through the anti-reverse diode D. Perform the test according to the selected test mode and record the test parameters.
[0042] In the multi-pulse power cycling mode, the charging switch is turned off, and the on / off state of the controllable switch tube connected to the first test point and the controllable switch tube connected to the second test point is controlled to cycle through charging and discharging of the energy storage battery, and multi-pulse testing is performed on the device under test connected to the first and second test points.
[0043] In the forward mode, the charging switch is turned off and the controllable switch connected to the second test point is connected; the on / off state of the controllable switch connected to the first test point is controlled to perform multi-pulse testing on the device under test connected to the second test point.
[0044] In reverse mode, the charging switch is disconnected and the controllable switch at the first test point is connected; the on / off state of the controllable switch at the second test point is controlled to perform multi-pulse testing on the device under test connected to the first test point.
[0045] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A multi-pulse test circuit for simultaneously testing multiple power semiconductors, characterized in that, Includes DC adjustable power supply, charging switch, reverse protection diode, DC capacitor, inductor, and energy storage battery; The positive terminal of the DC adjustable power supply, the charging switch, the positive terminal of the anti-reverse diode, the inductor, the positive terminal of the energy storage battery, the negative terminal of the energy storage battery, and the negative terminal of the DC adjustable power supply are connected in series to form a circuit. The positive terminal of the DC capacitor is connected to the negative terminal of the anti-reverse diode, and the negative terminal of the DC capacitor is connected to the negative terminal of the DC adjustable power supply. Specifically, a first measuring point is set between the positive terminal of the DC capacitor and the inductor to connect the first device under test; a second measuring point is set between the connection point of the first measuring point and the inductor and the negative terminal of the energy storage battery to connect the second device under test.
2. The circuit according to claim 1, characterized in that, The first device under test is a first diode under test and / or a first controllable switch transistor under test; The second device under test is a second diode under test and / or a second controllable switch transistor under test.
3. The circuit according to claim 2, characterized in that, The first diode under test, the first controllable switch under test, the second diode under test, and the second controllable switch under test can each be a single device, or multiple devices of the same type connected in series or in parallel.
4. The circuit according to claim 2, characterized in that, The first diode under test and the first controllable switch under test are each individually connected to the first test point, or the first diode under test and the first controllable switch under test are connected in parallel to the first test point.
5. The circuit according to any one of claims 2-4, characterized in that, The second diode under test and the second controllable switch under test are each individually connected to the second test point, or the second diode under test and the second controllable switch under test are connected in parallel to the second test point.
6. The circuit according to any one of claims 1-4, characterized in that, Devices under test with different substrate materials are connected simultaneously at the first and second measurement points.
7. A multi-pulse test method for simultaneously testing a plurality of power semiconductors, suitable for use in the circuit of any one of claims 1 to 6, characterized in that, The method includes: Select a test mode, which includes multi-pulse power cycle mode, forward mode, reverse mode, and equalization or current equalization characteristic mode; According to the selected test mode, connect the device under test to the first test point and the second test point; To start the test, close the charging switch and charge the DC capacitor to the target test voltage via the anti-reverse diode. Perform the test according to the selected test mode and record the test parameters.
8. The method according to claim 7, characterized in that, wherein In the multi-pulse power cycling mode, the charging switch is turned off, and the on / off state of the controllable switch tube connected to the first test point and the controllable switch tube connected to the second test point is controlled to cycle through charging and discharging of the energy storage battery, and multi-pulse testing is performed on the device under test connected to the first and second test points.
9. The method according to claim 7, characterized in that, in, In forward mode, the charging switch is turned off and the controllable switch connected to the second test point is connected; the on / off state of the controllable switch connected to the first test point is controlled to perform multi-pulse testing on the device under test connected to the second test point.
10. The method according to claim 7, characterized in that, in, In reverse mode, the charging switch is disconnected and the controllable switch at the first test point is connected; the on / off state of the controllable switch at the second test point is controlled to perform multi-pulse testing on the device under test connected to the first test point.