True random number generator, true random number generation method, chip and electronic equipment
By using an adjustable entropy source and control circuit in a true random number generator to monitor and adjust the clock frequency, the periodicity problem of random number sequences in existing technologies is solved, and high-quality random number output is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO LTD
- Filing Date
- 2026-01-09
- Publication Date
- 2026-04-17
AI Technical Summary
Existing true random number generators based on dual-entropy source sampling are difficult to control precisely in actual implementation, resulting in the output sequence having a periodic '101010' sequence and lacking randomness.
An adjustable entropy source and control circuit are used to monitor the metastable state of the acquisition circuit through alarm signals. The frequencies of the first and second clocks are adjusted to ensure that the acquisition circuit is in a metastable state and outputs high-quality true random numbers.
It improves the randomness of the true random number generator output, avoids the occurrence of periodic sequences, and meets application requirements.
Smart Images
Figure CN121879719A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic technology, specifically relating to a true random number generator, a true random number generation method, a chip, and an electronic device. Background Technology
[0002] In information security, cryptography, and modern digital chip design, the True Random Number Generator (TRNG) is a core hardware module for building the foundation of cryptographic security. Unlike pseudo-random number generators based on deterministic algorithms, the unpredictability of TRNGs stems directly from random phenomena in the physical world (i.e., entropy sources). Therefore, the quality and reliability of the entropy source directly determine the performance of the entire system.
[0003] Currently, one of the most commonly used TRNG structures in digital chips is based on a "dual entropy source sampling" scheme. In this structure, both entropy sources are typically implemented using ring oscillators (ROs), and their output signals are connected to the data (D) and clock (CLK) terminals of a D flip-flop (DFF), respectively. Theoretically, the frequencies of the two clock sources must satisfy a fixed non-integer ratio, usually set to (2M+1) / 2, where M is a positive integer. When the edges of the two clocks with this specific frequency relationship are nearly aligned, the DFF will enter a metastable state due to a violation of the setup or hold time, thus outputting an unpredictable random bit.
[0004] However, the TRNG structure described above has obvious limitations in actual implementation: since the frequency of RO can only be discretely controlled by the number of buffers or inverters, it is difficult to accurately achieve the ideal frequency ratio of (2M+1) / 2, which may cause the DFF used for sampling to continuously deviate from the metastable state in a certain direction, resulting in the output sequence having a periodic "101010" sequence and lacking randomness. Summary of the Invention
[0005] Therefore, the purpose of this application is to provide a true random number generator, a true random number generation method, a chip, and an electronic device to improve the randomness of the true random numbers output by the true random number generator.
[0006] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a true random number generator, comprising: a first adjustable entropy source, a second adjustable entropy source, a data acquisition circuit, and a control circuit; the data acquisition circuit is connected to the first adjustable entropy source and the second adjustable entropy source respectively, and the control circuit is connected to the first adjustable entropy source, the second adjustable entropy source, and the data acquisition circuit respectively; the first adjustable entropy source is configured to generate a first clock; the second adjustable entropy source is configured to generate a second clock, wherein the frequency of the first clock is less than the frequency of the second clock; the data acquisition circuit is configured to sample the second clock based on the first clock, and output a true random number and an alarm signal, wherein the alarm signal is used to characterize whether the data acquisition circuit is in a metastable state; the control circuit is configured to, when the alarm signal characterizes that the data acquisition circuit is in a non-metastable state, control the first adjustable entropy source to adjust the frequency of the first clock and control the second adjustable entropy source to adjust the frequency of the second clock, so that the data acquisition circuit is in a metastable state.
[0007] In the above implementation scheme, the acquisition circuit can output a true random number while simultaneously outputting an alarm signal to characterize whether the acquisition circuit is in a metastable state. This alarm signal allows the control circuit to determine whether the acquisition circuit is in a metastable state. If the acquisition circuit is not in a metastable state, the first adjustable entropy source and the second adjustable entropy source are controlled to adjust the frequencies of the first clock and the second clock to bring the acquisition circuit into a metastable state, thereby improving the quality of the true random number. This ensures that even if post-silicon testing reveals metastable deviations or periodicity in the output random number sequence caused by frequency mismatch, these issues can be effectively remedied by adjusting parameter configurations. Ultimately, the randomness of the sequence output by the true random number generator meets the application requirements.
[0008] In one possible implementation of the first aspect embodiment, the acquisition circuit includes: a sampler, a delay chain, and a flip detection circuit. The delay chain is connected to the main latch in the sampler, and the flip detection circuit is connected to the delay chain. The sampler is configured to sample the second clock based on the first clock and output a true random number. The delay chain is configured to delay the output signal of the main latch. The flip detection circuit is configured to detect the flip of the output signal of the delay chain based on the inverted signal of the first clock and output the alarm signal.
[0009] In the above implementation scheme, a sampler is used to output true random numbers, and a delay chain is used to delay the output signal of the master latch in the sampler. Then, the flip detection circuit is driven to output an alarm signal. In this way, it is possible to accurately determine whether the sampler is in a metastable state, thereby ensuring the quality of the true random number output and realizing the "health monitoring" of the true random number entropy source.
[0010] In one possible implementation of the first aspect embodiment, the delay chain is an adjustable delay chain, which is configured to adjust the delay time of the output signal of the master latch based on the input delay control signal.
[0011] In the above implementation scheme, the delay size of the adjustable delay chain is adjusted by the delay control signal, thereby adjusting the size of the detection window and the detection sensitivity of the acquisition circuit, so as to flexibly cope with the influence of PVT changes and improve the robustness of the circuit in actual use.
[0012] In one possible implementation of the first aspect embodiment, the sampler, the delay chain, and the flip detection circuit are integrated into one unit.
[0013] In the above implementation scheme, by adopting an integrated setup, this highly integrated design is easy to implement in the back end and can be seamlessly compatible with integrated circuit back-end design processes such as placement and routing, resulting in minimal power consumption and area overhead.
[0014] In one possible implementation of the first aspect embodiment, both the first adjustable entropy source and the second adjustable entropy source include: a ring oscillator and a selector; the selector is located on the loop of the ring oscillator, and a plurality of first terminals of the selector are respectively connected to different inverters of the ring oscillator, the second terminal of the selector is connected to the loop, and the selection terminal of the selector is connected to the control circuit.
[0015] In the above implementation scheme, by improving the ring oscillator and adding a selector to the loop to connect different inverters (usually containing two buffers), the number of buffers connected to the ring oscillator is selected by controlling the selector, that is, the effective part of the entropy source main body connected circuit is adjusted, thereby changing the frequency of its output signal. Even if the metastability deviation caused by frequency mismatch or the periodicity of the output random number sequence is found in the true random number generator during post-silicon testing, it can be effectively remedied by adjusting the parameter configuration of the true random number generator, and finally the randomness of the output sequence of the true random number generator meets the application requirements.
[0016] In one possible implementation of the first aspect embodiment, the selector is a multiplexer, with the first terminal being the input terminal of the multiplexer and the second terminal being the output terminal of the multiplexer; or, the selector is a demultiplexer, with the first terminal being the output terminal of the demultiplexer and the second terminal being the input terminal of the demultiplexer.
[0017] In the above implementation scheme, a multiplexer with multiple inputs and a demultiplexer with a single input and multiple outputs can be used to select the number of buffers connected to the ring oscillator. Since both multiplexers and demultiplexers are mature and reliable devices, they can improve the stability and reliability of the circuit while achieving the purpose of the invention.
[0018] In one possible implementation of the first aspect embodiment, the control circuit is specifically configured to generate digital signals that increment or decrement in value to control the selector, wherein different digital signals enable different numbers of inverters in the ring oscillator.
[0019] In the above implementation scheme, the control circuit controls the selector to select the number of buffers connected to the ring oscillator by generating digital signals that increase or decrease in value. This is beneficial for the circuit to achieve precise digital adjustment of frequency, improve the stability, integrability and scalability of the system, and adapt to the needs of various application scenarios.
[0020] Secondly, embodiments of this application also provide a chip, including a true random number generator as provided in any possible implementation of the first aspect embodiments and / or in combination with the first aspect embodiments.
[0021] Thirdly, embodiments of this application also provide an electronic device, including: a chip as provided in the second aspect of the embodiments described above.
[0022] Fourthly, embodiments of this application also provide a method for generating true random numbers, comprising: controlling a first adjustable entropy source to generate a first clock, and controlling a second adjustable entropy source to generate a second clock; wherein the frequency of the first clock is less than the frequency of the second clock; an acquisition circuit samples the second clock based on the first clock, and outputs true random numbers and an alarm signal; wherein the alarm signal is used to characterize whether the acquisition circuit is in a metastable state; when the alarm signal characterizes that the acquisition circuit is in a non-metastable state, a control circuit controls the first adjustable entropy source and the second adjustable entropy source to adjust the frequencies of the first clock and the second clock, so that the acquisition circuit is in a metastable state.
[0023] The technical effects of any of the implementation methods in the second to fourth aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.
[0024] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.
[0026] Figure 1 A schematic diagram of a true random number generator provided in an embodiment of this application is shown.
[0027] Figure 2a A circuit diagram of a ring oscillator provided in an embodiment of this application is shown.
[0028] Figure 2b A circuit diagram of an adjustable entropy source provided in an embodiment of this application is shown.
[0029] Figure 2c This paper illustrates a circuit diagram of yet another adjustable entropy source provided in an embodiment of this application. Figure 3 A schematic diagram of a data acquisition circuit provided in an embodiment of this application is shown.
[0030] Figure 4 A circuit diagram of a sampler provided in an embodiment of this application is shown.
[0031] Figure 5 A circuit diagram of a data acquisition circuit provided in an embodiment of this application is shown.
[0032] Figure 6 A circuit diagram of a flip detection circuit provided in an embodiment of this application is shown.
[0033] Figure 7 for Figure 6 The diagram shows a possible timing sequence for the flip detection circuit.
[0034] Figure 8 for Figure 5 The diagram shows a possible timing sequence for the flip detection circuit.
[0035] Figure 9 A flowchart illustrating a true random number generation method provided in an embodiment of this application is shown.
[0036] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation
[0037] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.
[0038] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus.
[0039] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0040] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.
[0041] To improve the randomness of the truly random numbers output by a True Random Number Generator (TRNG), this application provides a true random number generator, a true random number generation method, a chip, and an electronic device. By providing a structurally adjustable true random number generator, even if post-silicon testing reveals metastability issues due to frequency mismatch or periodicity in the output random number sequence, these problems can be effectively remedied by adjusting the generator's parameter configuration, ultimately ensuring that the randomness of the output sequence meets application requirements.
[0042] In this application, metastability refers to a state in which the acquisition circuit (or sampler) deviates from its digital abstract model due to a violation of timing rules (i.e., setup or hold time violations) by establishing a specific non-integer multiple frequency relationship between the first and second clocks. In this state, the behavior of the acquisition circuit (or sampler) is dominated by analog physical characteristics, and its output is ultimately determined by intrinsic noise, exhibiting an unpredictable and random bit.
[0043] The following is combined Figure 1 The structure of the true random number generator provided in this application embodiment is described below. The true random number generator includes: a first adjustable entropy source, a second adjustable entropy source, a data acquisition circuit, and a control circuit. The first adjustable entropy source and the second adjustable entropy source are both connected to the data acquisition circuit, and the control circuit is connected to the first adjustable entropy source, the second adjustable entropy source, and the data acquisition circuit, respectively.
[0044] In this configuration, a first adjustable entropy source is configured to generate a first clock (i.e., a clock signal, such as CLK1). A second adjustable entropy source is configured to generate a second clock (i.e., a clock signal, such as CLK2), wherein the frequency of the first clock is less than the frequency of the second clock. In some implementations, the frequencies of the first and second clocks are set to (2M+1) / 2, where M is a positive integer.
[0045] The acquisition circuit is configured to sample a second clock based on a first clock, outputting a true random number and an alarm signal (e.g., represented by W). Specifically, the clock input (CLK) of the acquisition circuit receives the first clock, and the data input (D) receives the second clock. The alarm signal is used to indicate whether the acquisition circuit is in a metastable state. For example, a high level W indicates a non-metastable state, and a low level W indicates a metastable state.
[0046] The control circuit is configured to, when the alarm signal characterization acquisition circuit is in a non-metastable state, control a first adjustable entropy source to adjust the frequency of a first clock and control a second adjustable entropy source to adjust the frequency of a second clock, so that the acquisition circuit is in a metastable state, thereby improving the randomness of the true random numbers output by the true random number generator. For example, when the W signal is high, the frequency of the first clock and the frequency of the second clock are adjusted to make the W signal low.
[0047] This application improves upon existing true random number generators by enabling the acquisition circuit to output both true random numbers and an alarm signal indicating whether the acquisition circuit is in a metastable state. The control circuit uses this alarm signal to determine if the acquisition circuit is in a metastable state. When the acquisition circuit is not in a metastable state, the first and second adjustable entropy sources adjust the frequencies of the first and second clocks to bring the acquisition circuit into a metastable state, thereby improving the quality of the true random numbers. This allows for effective remediation of issues such as metastable deviations due to frequency mismatch or periodicity in the output random number sequence, even if post-silicon testing reveals such problems, through parameter adjustments. Ultimately, the randomness of the output random number sequence meets application requirements. The true random number generator provided in this application achieves better random sequence output, preventing the acquisition circuit from continuously deviating from a metastable state in one direction, resulting in the output of a continuous 101010 sequence.
[0048] The specific implementations of the first adjustable entropy source, the second adjustable entropy source, the acquisition circuit, and the control circuit described above will be explained below.
[0049] The entropy source bodies of the first and second adjustable entropy sources in this application can be implemented using ring oscillators, relaxation oscillators, or chaotic circuits, etc. By configuring selectors connected to different positions of the entropy source bodies and controlling the input or output of the selectors, the effective portion of the entropy source bodies connected to the circuit can be adjusted, thereby changing the frequency of their output signals.
[0050] For ease of understanding, the following explanation uses a ring oscillator as the primary entropy source. The implementation using a relaxation oscillator or chaotic circuit is similar (i.e., adjusting the effective portion of the entropy source connected to the circuit by adding a selector, thereby changing the frequency of its output signal), and will not be elaborated further. In some possible implementations, both the first and second adjustable entropy sources include a ring oscillator and a selector. The structure of the ring oscillator is as follows... Figure 2a As shown, it includes an enable-controlled NAND gate and an odd number of inverters. Each stage of the delay chain of the odd number of inverters connected in series is often implemented using a buffer, and a buffer is typically composed of two inverters connected in series to provide in-phase drive and delay.
[0051] The selector is located on the loop of the ring oscillator, and its multiple first terminals are connected to different inverters of the ring oscillator. The second terminal of the selector is connected to the loop, and the selection terminal of the selector is connected to the control circuit to receive the selection control signal (e.g., represented by delay_config). In some possible configurations, the selector can be a multiplexer (mux), in which case the first terminal is the input of the multiplexer and the second terminal is the output; or, the selector can be a demultiplexer (demux), in which case the first terminal is the output of the demultiplexer and the second terminal is the input.
[0052] In some possible implementations, the structures of the first tunable entropy source and the second tunable entropy source can be as follows: Figure 2b , Figure 2c As shown. Among them, in Figure 2a The schematic diagram after adding a multiplexer (mux) to the existing structure is as follows: Figure 2b As shown, in Figure 2a The schematic diagram after adding a demultiplexer is shown below. Figure 2c As shown. It is understandable that... Figure 2b , Figure 2c The position of the selector is not limited to this. By selecting the control signal, the input or output of the selector can be controlled, thereby selecting the number of buffers connected to the ring oscillator, thus realizing the adjustment of the clock frequency.
[0053] The structure of the first adjustable entropy source and the structure of the second adjustable entropy source can be exactly the same or different. For example, the selector of the first adjustable entropy source is implemented based on a multiplexer (or demultiplexer), while the selector of the second adjustable entropy source is implemented based on a demultiplexer (or multiplexer). Although both contain selectors, the specific implementations of the selectors are different.
[0054] In some implementations, the acquisition circuit may employ a Razor-type DFF (D flip-flop) with alarm functionality. In addition to standard data input (D), clock (CLK), and data output (Q) ports, this flip-flop adds an alarm signal output terminal W. The W alarm signal is used to indicate whether the flip-flop is in a metastable state. Outside the alarm window, a high level is output (W alarm signal is high), while within the alarm window, a low level is output (W signal is low). Furthermore, the flip-flop may optionally include a delay control signal input terminal (e.g., IB terminal). By receiving an externally provided delay control signal (e.g., represented by the IB signal), this signal can adjust the detection window width (i.e., alarm sensitivity) of the Razor-type flip-flop, thereby achieving different control accuracies. This adapts to the varying metastable windows caused by changes in the intrinsic setup and hold times of the Razor-type flip-flop due to variations in PVT (including Process, Voltage, and Temperature) during actual chip manufacturing.
[0055] In some implementations, such as Figure 3 As shown, the acquisition circuit includes a sampler, a delay chain, and a toggle detection circuit. The delay chain is connected to the main latch in the sampler, and the toggle detection circuit is connected to the delay chain. The sampler is configured to sample a second clock based on a first clock and output a true random number. The delay chain is configured to delay the output signal of the main latch. The toggle detection circuit is configured to detect the toggle of the output signal of the delay chain based on the inverted signal of the first clock (e.g., represented by CLK1B) and output an alarm signal.
[0056] In some implementations, the sampler can be a DFF flip-flop. In some implementations, the sampler's circuit structure can be as follows: Figure 4 As shown, the clock signals received by the CLK and CLKB terminals are mutually inverted clock signals. For example, the CLK terminal is used to receive the CLK1 signal, while the CLKB terminal is used to receive the inverted version of the CLK1 signal. An inverter can be connected in series between the CLK and CLKB terminals to obtain the inverted version of the CLK1 signal.
[0057] Figure 4 The input of the first-level buffer is connected to the D terminal of the sampler to receive the CLK2 signal. Figure 4TG1 and LH1 form the master latch, used to latch the signal input through the first-level buffer when CLK1 is low. The output signal Mout of the master latch is used to drive the slave latch composed of TG2 and LH2, and also drives the delay chain to drive the toggle detection circuit to output the alarm signal W. The slave latch latches the Mout signal when CLK1 is high, and the Sout signal output by the slave latch is output to the Q terminal of the sampler after passing through the second-level buffer.
[0058] The delay chain in the acquisition circuit can be a fixed delay chain or an adjustable delay chain. An adjustable delay chain is configured to adjust the delay time of the output signal of the master latch based on the input delay control signal, thereby adjusting the detection window (i.e., alarm sensitivity) of the acquisition circuit. This adjustable delay chain can be implemented using adjustable delay chains in related technologies, which will not be described further here.
[0059] In some possible implementations, the sampler, delay chain, and flip-flop detection circuit can be integrated into a single unit. This highly integrated design is easy to implement in the back-end and seamlessly compatible with integrated circuit back-end design flows such as placement and routing, resulting in minimal power consumption and area overhead. In one implementation, the circuit structure of the acquisition circuit can be as follows: Figure 5 As shown, Figure 5 The IB signal in the input is the external delay control signal, used to adjust the delay of the adjustable delay chain.
[0060] The flip detection circuit can employ a flip detection circuit from related technologies used to detect the flipping of the input signal. In one embodiment, the circuit structure of the flip detection circuit can be as follows: Figure 6 As shown, the circuit includes: an input buffer stage (containing transistors P1 and N1), a latch (containing transistors P2, N2, and P4), an output buffer stage (containing transistors P3 and N3), a filter capacitor (containing transistor N0), and a control switch (containing transistor N4). This flip-flop detection circuit comprises a clock dynamic logic circuit consisting of nine transistors. P1 and N1 form the input buffer stage, P2 and N2 form an inverter, and together with the pseudo-inverter P4 for feedback, they form the latch. P3 and N3 form the output buffer stage for the VVSS node. N0 is a filter capacitor used to prevent overshoot at the Y node. It is understood that the filter capacitor can also be implemented using a capacitor instead of a transistor.
[0061] When the clock signal at input CLK1B is valid (i.e., CLK1B is high), transistor N4 is turned on, and node VVSS is pulled low. Regardless of how the input signal IN (i.e., the signal after the delay chain of the Mout signal) changes, the signal at node X is always the inverted signal of input signal IN, and the signal at node Y is the same as the input signal IN. The input signal IN is latched in the latch composed of P2, N2, and P4, and the output W is high. However, once the clock signal at input CLKB is invalid (i.e., CLK1B is low), transistor N4 is turned off. When the input signal IN changes from 1 to 0 (or from 0 to 1), node Y will charge node VVSS rapidly through transistor N2 (or node X through transistor N1), thereby raising the level of node VVSS. This will cause the output buffer stage composed of transistors P3 and N3 to flip, and the output W will be low.
[0062] In one embodiment, the timing diagram of the flip detection circuit is as follows: Figure 7 As shown, when the clock signal (CLK1B) at the CLKB terminal is invalid (negative half-cycle), a low-level alarm signal is output by detecting the toggle of the input signal IN. That is, when the input signal IN changes from 0 to 1, or from 1 to 0, the W signal is low. Figure 6 The flip detection circuit shown is connected to Figure 5 In the acquisition circuit shown, since the clock signal CLK1B at the input CLK B terminal is the inverted signal of CLK1, it is possible to achieve effective W (low level) detection output during the positive half-cycle of the clock signal (CLK1).
[0063] In one implementation method, Figure 5 The timing diagram of the acquisition circuit shown is as follows: Figure 8 As shown, if the signal at input D does not change at the rising edge of clock CLK ( Figure 8 As shown in ①), the sampler will not enter a metastable state, meaning the sampler is non-metastable, and the W signal remains high. Once the signal at the input D terminal changes at the rising edge of the clock CLK, and this change falls within the sampler's own setup time t... su Duration t hd and margin t margin Within the detection window formed ( Figure 8 As shown in ②), the W signal immediately goes low, indicating that the sampler has entered a metastable state. Furthermore, Figure 8 Another example is shown Figure 5 The timing relationship between the Mot signal, the Y node signal, the Sout signal, and the clock CLK.
[0064] The delay value of the adjustable delay chain can be adjusted via the IB signal, thereby configuring t. marginThe width of t is adjusted, thereby controlling the size of the detection window and the detection sensitivity. margin This width-based approach allows for flexible adaptation to the effects of PVT variations, improving the robustness of the circuit in practical applications.
[0065] It should be noted that, Figure 8 The timing diagram shown is based on the case where the CLK pin of the sampler is active with a positive edge. If the CLK pin of the sampler changes to CLKB, then the sampler becomes active with a negative edge.
[0066] The control circuit in this application is mainly used to control the first adjustable entropy source and the second adjustable entropy source to adjust the frequencies of the first clock and the second clock when the alarm signal characterization acquisition circuit is in a non-metastable state, so as to make the acquisition circuit in a metastable state. In some embodiments, the control circuit is specifically used to generate digital signals that increase or decrease in value to control the selector, and the number of inverters of the ring oscillator activated by different digital signals is different.
[0067] For ease of understanding, the following will use... Figure 2b or Figure 2c The adjustable entropy source shown is used as an example for explanation. When delay_config is at different values, the input or output of the selector is different, thus selecting the number of buffers connected to the ring oscillator, thereby adjusting the clock frequency. The control circuit controls the first adjustable entropy source (low-frequency clock source) and the second adjustable entropy source (high-frequency clock source) in a similar principle. Here, we will explain the control of the first adjustable entropy source. Assuming that initially, the number of buffers connected to the ring oscillator in the first adjustable entropy source is at its maximum value, the number of buffers connected to the ring oscillator in the second adjustable entropy source can be kept constant. By changing the value of delay_config, the number of buffers connected to the ring oscillator in the first adjustable entropy source is gradually reduced until the W signal changes from high level to low level. If the W signal is still high level after one round of adjustment, the number of buffers connected to the ring oscillator in the second adjustable entropy source is increased or decreased. Then, keeping the number of buffers connected to the ring oscillator in the second adjustable entropy source constant, the number of buffers connected to the ring oscillator in the first adjustable entropy source is gradually increased by changing the value of delay_config until the W signal changes from high level to low level. If, after another round of adjustments, the W signal remains high, the number of buffers connected to the ring oscillator from the second adjustable entropy source is increased or decreased. Then, keeping the number of buffers connected to the ring oscillator from the second adjustable entropy source constant, the number of buffers connected to the ring oscillator from the first adjustable entropy source is gradually decreased by changing the value of delay_config until the W signal changes from high to low. This process is repeated until the frequencies of the first and second clocks are adjusted, ultimately maintaining the W signal at a low level. At this point, the acquisition circuit is in a metastable state.
[0068] The above example is based on the initial maximum number of buffers connected to the ring oscillator by the first adjustable entropy source. If the initial maximum number of buffers connected to the ring oscillator by the first adjustable entropy source is the minimum, then the number of buffers connected to the ring oscillator by the second adjustable entropy source can be kept unchanged. The number of buffers connected to the ring oscillator in the first adjustable entropy source can be gradually increased by changing the value of delay_config until the W signal changes from high level to low level.
[0069] It is understandable that the delay_config signal input to the first adjustable entropy source is different from the delay_config signal input to the second adjustable entropy source. The delay_config signal can be a binary signal, and its bit width depends on the number of signals at the input (or output) terminals of the selector. For example, if the selector is an 8-input, 1-output multiplexer, or an 8-input, 8-output demultiplexer, then the bit width of the delay_config signal is 3, and its value ranges from 000 to 111. If the selector is a 16-input, 1-output multiplexer, or an 16-input, 16-output demultiplexer, then the bit width of the delay_config signal is 4, and its value ranges from 0000 to 1111.
[0070] The control circuit of this application may include a first control branch and a second control branch, wherein the first control branch is used to input a delay_config signal to a first adjustable entropy source, and the second control branch is used to input a delay_config signal to a second adjustable entropy source. The first control branch and the second control branch may be various circuits capable of outputting binary signals, such as, but not limited to, finite state machines, state registers, etc.
[0071] This application also provides a method for generating truly random numbers, which will be described below in conjunction with... Figure 9 The principle behind it will be explained.
[0072] S10: Control the first adjustable entropy source to generate the first clock, and control the second adjustable entropy source to generate the second clock.
[0073] In one possible implementation, an enable signal can be used to control a first adjustable entropy source to generate a first clock, and a second adjustable entropy source to generate a second clock. For example, for Figure 2b or Figure 2c The adjustable entropy source shown can be controlled by an enable signal. Figure 2b or Figure 2c The adjustable entropy source shown operates to generate a first clock and a second clock, wherein the frequency of the first clock is less than the frequency of the second clock.
[0074] S20: The acquisition circuit samples the second clock based on the first clock and outputs a true random number and an alarm signal.
[0075] After obtaining the first clock and the second clock, the acquisition circuit samples the second clock based on the first clock and outputs a true random number and an alarm signal.
[0076] The structure of this acquisition circuit can be referenced from the acquisition circuit described above, and will not be described again here. The alarm signal is used to characterize whether the acquisition circuit is in a metastable state.
[0077] S30: When the alarm signal characterization acquisition circuit is in a non-metastable state, the control circuit controls the first adjustable entropy source and the second adjustable entropy source to adjust the frequency of the first clock and the second clock so that the acquisition circuit is in a metastable state.
[0078] When the alarm signal characterization acquisition circuit is in a non-metastable state, the first adjustable entropy source can be controlled by the control circuit to adjust the frequency of the first clock, and the second adjustable entropy source can be controlled by the control circuit to adjust the frequency of the second clock, so that the acquisition circuit is in a metastable state.
[0079] The control circuit controls the first adjustable entropy source to adjust the frequency of the first clock and controls the second adjustable entropy source to adjust the frequency of the second clock, as described above and will not be repeated here.
[0080] The method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned true random number generator embodiment. For the sake of brevity, any part not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned true random number generator embodiment.
[0081] This application also provides a chip that includes the aforementioned true random number generator. The chip can be any chip that requires true random numbers, such as an encryption chip, a communication chip, or a processing chip. In one embodiment, the chip can be a processor.
[0082] The chip provided in this application embodiment has the same implementation principle and the same technical effect as the aforementioned true random number generator embodiment. For the sake of brevity, any parts not mentioned in the chip embodiment can be referred to the corresponding content in the aforementioned true random number generator embodiment. This application also provides an electronic device, which includes the chip described above. A structural block diagram of the electronic device is shown in one embodiment. Figure 10 As shown. The electronic device includes: a transceiver, a memory, a communication bus, and a processor. The processor can be the chip mentioned above that includes a true random number generator. The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, which include at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor executes the software functional modules or computer programs stored in the memory.
[0083] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.
[0084] A processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. Alternatively, the processor can be any conventional processor.
[0085] The aforementioned electronic devices include, but are not limited to, mobile devices, computing devices, security devices, network and communication devices, and vehicles. Mobile devices include, but are not limited to, smartphones, tablets, and wearable devices. Computing devices include, but are not limited to, personal computers, servers, and computing cards. Security devices include, but are not limited to, cameras, smart locks, and access control systems. Network and communication devices include, but are not limited to, routers, switches, and firewalls. Vehicles include, but are not limited to, various vehicles containing electronic control units.
[0086] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0087] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A true random number generator, characterized in that, include: The first adjustable entropy source is configured to generate the first clock; A second adjustable entropy source is configured to generate a second clock, wherein the frequency of the first clock is less than the frequency of the second clock; The acquisition circuit is connected to the first adjustable entropy source and the second adjustable entropy source respectively. The acquisition circuit is configured to sample the second clock based on the first clock and output a true random number and an alarm signal. The alarm signal is used to characterize whether the acquisition circuit is in a metastable state. A control circuit is connected to the first adjustable entropy source, the second adjustable entropy source, and the acquisition circuit, respectively. The control circuit is configured to control the first adjustable entropy source to adjust the frequency of the first clock and control the second adjustable entropy source to adjust the frequency of the second clock when the alarm signal indicates that the acquisition circuit is in a non-metastable state, so as to make the acquisition circuit in a metastable state.
2. The true random number generator according to claim 1, characterized in that, The acquisition circuit includes: The sampler is configured to sample the second clock based on the first clock and output a true random number; A delay chain, connected to the master latch in the sampler, is configured to delay the output signal of the master latch; A flip detection circuit is connected to the delay chain. The flip detection circuit is configured to detect the flipping of the output signal of the delay chain based on the inverted signal of the first clock, and output the alarm signal.
3. The true random number generator according to claim 2, characterized in that, The delay chain is an adjustable delay chain, which is configured to adjust the delay time of the output signal of the master latch based on the input delay control signal.
4. The true random number generator according to claim 3, characterized in that, The sampler, the delay chain, and the flip detection circuit are integrated into one unit.
5. The true random number generator according to any one of claims 1-4, characterized in that, Both the first adjustable entropy source and the second adjustable entropy source include: Ring oscillator; A selector is located on the loop of the ring oscillator, and the multiple first terminals of the selector are respectively connected to different inverters of the ring oscillator. The second terminal of the selector is connected to the loop, and the selection terminal of the selector is connected to the control circuit.
6. The true random number generator according to claim 5, characterized in that, The selector is a multiplexer, with the first terminal being the input terminal of the multiplexer and the second terminal being the output terminal of the multiplexer; or... The selector is a demultiplexer, the first terminal is the output terminal of the demultiplexer, and the second terminal is the input terminal of the demultiplexer.
7. The true random number generator according to claim 5, characterized in that, The control circuit is specifically used to generate digital signals that increment or decrement to control the selector, and different digital signals activate different numbers of inverters in the ring oscillator.
8. A chip, characterized in that, Includes, as in any one of claims 1-7, a true random number generator.
9. An electronic device, characterized in that, include: The chip as described in claim 8.
10. A method for generating truly random numbers, characterized in that, include: A first adjustable entropy source is controlled to generate a first clock, and a second adjustable entropy source is controlled to generate a second clock; wherein the frequency of the first clock is less than the frequency of the second clock; The acquisition circuit samples the second clock based on the first clock and outputs a true random number and an alarm signal; wherein, the alarm signal is used to characterize whether the acquisition circuit is in a metastable state; When the alarm signal indicates that the acquisition circuit is in a non-metastable state, the control circuit controls the first adjustable entropy source and the second adjustable entropy source to adjust the frequencies of the first clock and the second clock so that the acquisition circuit is in a metastable state.