TTL serial port controller based on FPGA

Abstract

The invention relates to a TTL (transistor-transistor logic) serial port controller based on an FPGA (field programmable gate array), and belongs to the technical field of serial communication. According to the serial port controller realized based on the FPGA, parameter configuration, data coding and analysis, parity check and automatic switching of TTL serial port receiving / sending directions of serial ports can be realized. The configuration of serial port parameters is realized in a register configuration issuing mode; realizing bit and byte conversion of received / sent data and parity check of the data through logic coding and decoding; by monitoring a bottom layer receiving / sending FIFO state and a data line data transceiving state machine, the receiving / sending direction of a single-line TTL serial port is controlled in a combinational logic mode, and non-inductive direction switching of a driving layer is achieved.

Description

Technical Field

[0001] This invention belongs to the field of serial communication technology, specifically relating to an FPGA-based TTL serial port controller. Background Technology

[0002] Serial ports, or asynchronous serial communication interfaces, are a very basic and long-established communication method. Even in today's era of numerous high-speed interfaces, they still play an irreplaceable role in specific fields due to their simple voltage levels and stable communication. TTL level serial ports are the simplest type of serial communication voltage level definition, requiring only a receive line, a transmit line, and a ground line to achieve communication. Summary of the Invention

[0003] (a) Technical problems to be solved The technical problem to be solved by this invention is: to design a serial port controller to solve the problem of long switching time for transmit and receive directions in the upper layer driver.

[0004] (II) Technical Solution To address the aforementioned technical problems, this invention provides a design method for an FPGA-based TTL serial port controller, which is designed to include a register configuration module and a data parsing and verification logic module. The register configuration module is used to initialize the serial port controller by writing to the control register and the baud rate configuration register, and to read the transmit / receive FIFO status, parity check mode information, frame error information and transmit / receive control status during the serial port operation. The data parsing and verification logic module is used to read information from the control register, parse out configuration information such as serial port start bit, serial port stop bit, and parity check mode, and parse and verify the data sent and received during communication. (III) Beneficial Effects This invention designs a serial port controller based on FPGA, which can realize serial port parameter configuration, data encoding and parsing, parity checking, and automatic switching of TTL serial port receive / transmit direction. Serial port parameters are configured through register configuration; bit-to-byte conversion and parity checking of received / transmitted data are achieved through logic encoding and decoding; and the receive / transmit direction of a single-wire TTL serial port is controlled through combinational logic by monitoring the underlying receive / transmit FIFO state and the data line transceiver state machine, achieving seamless direction switching at the driver layer. Attached Figure Description

[0005] Figure 1 This is a flowchart of the data parsing and verification logic control of the present invention; Figure 2This is a flowchart illustrating the read / write direction switching process of the present invention. Detailed Implementation

[0006] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0007] Typically, TTL serial port direction switching requires driver layer intervention, achieved through register configuration. However, software-level scheduling significantly increases switching latency, potentially missing data exchange cycles and causing communication failures. This invention designs a logic-based serial port controller and customizes it to generate a receive / transmit direction switching signal by rationally combining the underlying receive / transmit FIFO states and data line transmit / receive states, thus achieving automated low-level control of the serial port direction. This invention designs and implements a TTL serial port controller that achieves serial communication using only a single data transmit / receive line (data line) and a ground line through logic control. The timely switching of transmit and receive directions via logic control solves the problem of long switching times in the upper-layer driver.

[0008] (I) Serial Port Controller Configuration Logic Design This invention implements a general-purpose serial port controller through logical design, enabling the configuration of serial communication-related registers and the reception and transmission of data. The FPGA-based TTL controller of this invention mainly consists of a register configuration module, a receiving module, a transmitting module, a data parsing and verification logic module, and a transmit / receive direction control logic module.

[0009] (1) Register configuration module The register configuration module is mainly used to initialize the serial port controller by writing to the control register and the baud rate configuration register, and to read the transmit / receive FIFO status, parity check mode information, frame error information, and transmit / receive control status during serial port operation. The registers that need to be configured through the register configuration module include the control register and the baud rate configuration register, whose definitions and descriptions are shown in Table 1.

[0010] Table 1 Register Description Table (2) Data parsing and verification logic module The system reads information from the control register (LCR), parses out configuration information such as the serial port start bit, serial port stop bit, parity mode, and data bit width, and parses and verifies the data transmitted and received during communication. Data parsing and verification includes both receiving and transmitting directions. The logic control process is as follows: Figure 1As shown. First, the serial port configuration parameters are obtained by reading the baud rate configuration register to confirm the communication baud rate, encoding mode, parity check mode, and data / stop bit configuration. Then, in the data transmission phase, the byte data to be transmitted is first retrieved from the transmit FIFO. According to the encoding mode configuration parameters, the byte data to be transmitted is encoded into bit data. According to the parity check mode, parity bits are added to the encoded bit data. Then, start and stop information is added to the bit data according to the serial port start and stop bits. Finally, the bit data is converted into electrical signals and transmitted on the physical leads. In the data reception phase, data is received bit by bit on the data transmit and receive lines. The received bit data is truncated (segmented) according to the serial port start and stop bits. Then, parity check is performed on the truncated (segmented) data according to the parity check mode. If the check is correct, it is restored to the byte encoding format and then buffered in the receive FIFO; otherwise, the parity status register is filled.

[0011] (3) Receiving module and sending module The receiving and transmitting modules primarily process single-bit data on the data transceiver lines. In the receiving direction, the receiving module byte-codes the received single-bit data and stores it in the receive FIFO, triggering a read interrupt and waiting for the host computer to process the data. In the transmitting direction, the host computer writes the data to be transmitted into the transmit FIFO and triggers a transmit interrupt. The transmitting module then breaks down the byte data into single-bit data, adds a parity bit, and transmits it bit by bit on the data transceiver line. (4) Transmit / receive direction control logic module This invention features a customized transmit / receive direction control logic module designed specifically for the communication characteristics of TTL serial ports. This module enables automated switching between read and write directions. The specific design method will be explained in the following section on the transmit / receive read / write direction control logic design.

[0012] The above four modules are the four components of the TTL serial port controller. Each part is independent of the others and plays a role in different stages of the serial port controller's operation. Through these roles, the serial port controller as a whole realizes its functions.

[0013] (II) Design of Receive / Transmit Direction Control Logic This invention utilizes the inout type GPIO pins of an FPGA chip as data transceiver lines. These lines are implemented with a single physical wire, enabling both data reception and transmission. Therefore, the transmit / receive direction control logic module of this invention includes a data read / write direction control module, a transmit FIFO, a transmit state machine, a receive FIFO, a CPU, and memory. Through the designed transmit FIFO, transmit state machine, and effective data delay mechanism, automatic switching between data transmission and reception directions is achieved. The decision process is as follows: Figure 2As shown.

[0014] The serial port controller initially defaults to receiving data on its data transceiver lines. After initialization, the serial port controller enters a data reading state. After the other end sends data, the data is buffered in the receive FIFO, and the CPU is notified via a receive interrupt to move the buffered data to memory for processing through the driver. When the CPU needs to send data, it triggers a transmission interrupt, and the driver layer sends the data to the transmit FIFO. When the transmit FIFO is not empty, the data transmit / receive line direction is switched to transmit, and the transmission process is triggered. Simultaneously, the receive FIFO is reset to prevent data residue. The data read / write direction logic control module monitors the transmit FIFO until it is empty. However, even when the transmit FIFO is empty, the data transmit / receive line direction cannot be immediately switched to receive because the data transmission on the transmit / receive line is not yet complete. Switching to read at this point would not only result in incomplete data transmission but also incorrectly loop back the residual data on the data line. Therefore, this invention uses the data read / write direction logic control module to simultaneously monitor the transmit state machine. After the transmit state machine enters the IDLE state, a 50ms delay is applied to ensure no signal residue on the transmit / receive line before switching the data transmit / receive line direction to receive, ready to receive data from the other end.

[0015] During the aforementioned data transmission and reception direction switching process, for the inout type interface in the FPGA chip, the compilation and synthesis result is a tri-state gate circuit. In addition to the data pin, this logic gate also brings out a direction enable pin. When the enable signal of the direction enable pin is pulled high, the interface will switch to transmission; when the enable signal is pulled low, the interface will switch to reception.

[0016] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A design method for a TTL serial port controller based on FPGA, characterized in that, The serial port controller is designed to include a register configuration module and a data parsing and verification logic module. The register configuration module is used to initialize the serial port controller by writing to the control register and the baud rate configuration register, and to read the transmit / receive FIFO status, parity check mode information, frame error information and transmit / receive control status during the serial port operation. The data parsing and verification logic module is used to read information from the control register, parse out configuration information such as serial port start bit, serial port stop bit, and parity check mode, and parse and verify the data sent and received during communication.

2. The method as described in claim 1, characterized in that, The data parsing and verification logic module performs data parsing and verification in two directions: receiving and sending. The specific process is as follows: First, the serial port configuration parameters are obtained by reading the baud rate configuration register to confirm the communication baud rate, encoding mode, parity check mode, and data bit / stop bit configuration. Then, in the data sending stage, the byte data to be sent is first retrieved from the send FIFO. According to the encoding mode configuration parameters, the byte data to be sent is encoded into bit data. According to the parity check mode, parity bits are added to the encoded bit data. Then, start and stop information is added to the bit data according to the serial port start and stop bits. Finally, the bit data is converted into electrical signals and transmitted on the physical leads. In the data receiving stage, data is first received bit by bit on the data transmit / receive line. The received bit data is segmented. Then, parity check is performed on the segmented data according to the parity check mode. After the check is successful, the data is restored to the byte encoding format and then buffered in the receive FIFO.

3. The method as described in claim 2, characterized in that, The serial port controller also includes a receiving module and a transmitting module. The receiving module and the transmitting module process single-bit data on the data transceiver lines. In the receiving direction, the receiving module byte-izes the received single-bit data and stores it in the receiving FIFO, triggering a read interrupt and waiting for the external host computer to process the data. In the transmitting direction, the host computer writes the data to be transmitted into the transmitting FIFO and triggers a transmitting interrupt. The transmitting module decomposes the byte data into single-bit data, adds a parity bit, and then transmits it bit by bit on the data transceiver lines.

4. The method as described in claim 3, characterized in that, The serial port controller also includes a transmit / receive direction control logic module, which is used to automatically switch between data transmission and reception directions.

5. The method according to claim 1, characterized in that, In this method, the inout type GPIO pin in the FPGA chip is used as the data transceiver line. The data transceiver line is implemented through a single physical lead and is used to realize data reception and transmission.

6. The method of claim 4, characterized in that, The transmit / receive direction control logic module includes a data read / write direction logic control module, a transmit FIFO, a transmit state machine, a receive FIFO, a CPU, and memory. The serial port controller defaults to a receive direction for its data transmit / receive line. After initialization, the serial port controller is in a read data state. After the peer sends data, it buffers the data in the receive FIFO and notifies the CPU via a receive interrupt to move the buffered data to memory for processing. When the CPU needs to send data, it triggers a transmit interrupt, sending the data to the transmit FIFO. When the transmit FIFO is not empty, the data transmit / receive line direction is switched to transmit, triggering the transmit process. Simultaneously, the receive FIFO is reset. The data read / write direction logic control module monitors the transmit FIFO until it is empty. Simultaneously, the data read / write direction logic control module monitors the transmit state machine, waiting for it to enter the IDLE state, then waiting for a period before switching the data transmit / receive line direction back to receive, waiting to receive data from the peer.

7. The method according to claim 4, characterized in that, The transmit / receive direction control logic module is designed for the communication characteristics of TTL serial ports.

8. A serial port controller designed using the method described in any one of claims 1 to 7.

9. A method for operating the serial port controller as described in claim 8.

10. An application of the serial port controller as described in claim 8 in serial communication.

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