Memory controller, control method of memory controller and computer equipment

Abstract

The invention provides a memory controller, a control method of the memory controller and computer equipment, and relates to the technical field of integrated circuits. A DRAM interface; a shared memory unit; the control unit is configured to monitor a runtime working load characteristic of a memory access request received through the on-chip interconnection interface; in response to determining that the workload feature satisfies the first condition, configuring the memory controller into a read-only reorder buffer mode; in response to determining that the workload feature meets the second condition, configuring the memory controller to be in a last-level-only cache mode; in response to determining that the workload feature satisfies a third condition, the shared memory cell is divided into a first logical region as a read reorder buffer and a second logical region as a last level buffer. And efficient utilization and flexible adaptation of on-chip storage resources in the memory controller are realized.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a memory controller, a control method for the memory controller, a computer device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In modern System-on-a-Chip (SoC) architectures, the memory subsystem is a critical component determining overall system performance. It typically includes a DDR memory controller (DDR MC) and a last-level cache (LLC). The DDR MC manages communication with external DRAM. To maximize DRAM bandwidth utilization, the DDR MC usually contains a Read Reorder Buffer (Read ROB) to reorder read commands, ensuring memory accesses comply with DRAM timing constraints. It also reassembles the returned out-of-order data according to the original AXI ID order before returning it to the host.

[0003] On the other hand, the Last Level Cache (LLC) is typically deployed between the On-Chip Interconnect (NoC) and the DDR MC to cache frequently used data (such as hot data, instruction code, etc.).

[0004] With the diversification of application scenarios, different workloads, such as large-scale streaming access and random small data access, place different demands on the bandwidth and latency of the memory subsystem. How to utilize on-chip storage resources more efficiently and enable the memory controller to flexibly adapt to different runtime workload characteristics is a direction that this field continues to explore. Summary of the Invention

[0005] This disclosure provides a memory controller, a method for controlling the memory controller, a computer device, a computer-readable storage medium, and a computer program product.

[0006] According to one aspect of this disclosure, a memory controller is provided, comprising: an on-chip interconnect interface for receiving memory access requests; a DRAM interface for communicating with an external DRAM; a shared memory unit composed of an SRAM physical array; and a control unit coupled to the on-chip interconnect interface, the DRAM interface, and the shared memory unit, the control unit being configured to: monitor runtime workload characteristics of memory access requests received through the on-chip interconnect interface; in response to determining that the workload characteristics satisfy a first condition, configure the memory controller in a read-only reordering buffer mode, wherein in the read-only reordering buffer mode, the shared memory unit is configured as a read reordering buffer for caching read transactions to be reordered; in response to determining that the workload characteristics satisfy a second condition, configure the memory controller in a last-level cache-only mode, wherein in the last-level cache-only mode, the shared memory unit is configured as a last-level cache for caching data copies; and in response to determining that the workload characteristics satisfy a third condition, configure the memory controller in a hybrid mode, wherein in the hybrid mode, the shared memory unit is divided into a first logical region serving as a read reordering buffer and a second logical region serving as a last-level cache.

[0007] In some embodiments, the control unit maintains storage entries with a uniform format in the shared storage unit and performs reuse interpretation of the uniform format storage entries according to the current mode of the memory controller.

[0008] In some embodiments, in the read-only reordering buffer mode, the control unit is further configured to: interpret storage entries in the shared storage unit as transaction queues constrained by DDR command timing; and sort and schedule the read transactions according to the DDR command timing.

[0009] In some embodiments, in the last-level-only caching mode, the control unit is further configured to: interpret storage entries in the shared storage unit as content-addressable data cache lines; and index and access the data copy using cache tags.

[0010] In some embodiments, in the hybrid mode, the control unit is further configured to: dynamically maintain a first logical region for read reordering and a second logical region for last-level caching in the shared storage unit; and determine, based on line buffer locality hints, to allocate a new memory access request to the first logical region or the second logical region.

[0011] In some embodiments, the runtime workload characteristics include at least one of the following statistical parameters: read miss rate, row buffer hit rate, and transaction queue depth, and wherein the control unit is further configured to: determine that the first condition is met in response to determining that the read miss rate is not lower than a first threshold or the row buffer hit rate is not lower than a second threshold, thereby triggering the read-only reorder buffer mode; determine that the second condition is met in response to determining that the read miss rate is lower than a third threshold or the row buffer hit rate is lower than a fourth threshold, thereby triggering the last-level cache-only mode, wherein the third threshold is less than the first threshold and the fourth threshold is less than the second threshold; and determine that the third condition is met in response to determining that the read miss rate is not lower than the third threshold and is lower than the first threshold, or determining that the transaction queue depth is not lower than a fifth threshold, thereby triggering the hybrid mode.

[0012] In some embodiments, the DDR command timing constraints include a refresh blocking window corresponding to an external DRAM refresh operation, and the control unit is further configured to: during the refresh blocking window, buffer received read transactions using the shared memory unit without blocking the on-chip interconnect interface; within the shared memory unit, pre-sort the buffered read transactions based on row address hits; and in response to the end of the refresh blocking window, send the pre-sorted read transactions as a continuous burst sequence to the external DRAM.

[0013] In some embodiments, the control unit is further configured to manage the ports of the shared storage unit in a time-division multiplexing manner, wherein, in the hybrid mode, the ports of the shared storage unit are allocated to the first logical region and the second logical region in turn in the time domain according to burst groups or quality of service categories.

[0014] According to one aspect of this disclosure, a method for controlling a memory controller is provided, the memory controller including a shared storage unit composed of an SRAM physical array, the method comprising: monitoring runtime workload characteristics of received memory access requests; in response to determining that the workload characteristics satisfy a first condition, configuring the memory controller in a read-only reordering buffer mode and configuring the shared storage unit as a read reordering buffer for caching read transactions to be reordered; in response to determining that the workload characteristics satisfy a second condition, configuring the memory controller in a last-level cache-only mode and configuring the shared storage unit as a last-level cache for caching data copies; and in response to determining that the workload characteristics satisfy a third condition, configuring the memory controller in a mixed mode and dividing the shared storage unit into a first logical region serving as a read reordering buffer and a second logical region serving as a last-level cache.

[0015] According to another aspect of this disclosure, a computer device is provided, comprising: at least one processor; and a memory having a computer program stored thereon, wherein the computer program, when executed by the at least one processor, causes the at least one processor to perform the methods provided above in this disclosure.

[0016] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0017] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0018] According to one or more embodiments of this disclosure, a memory controller is provided that achieves efficient utilization and flexible adaptation of on-chip storage resources in the memory controller by dynamically configuring a shared SRAM physical array as a read reordering buffer, a last-level cache, or a hybrid mode based on runtime workload characteristics.

[0019] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0020] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0021] Figure 1 This is a schematic block diagram illustrating a memory controller according to an exemplary embodiment.

[0022] Figure 2 This is a schematic diagram illustrating data reading and writing by a memory controller according to an exemplary embodiment.

[0023] Figure 3 This is a flowchart illustrating a control method for a memory controller according to an exemplary embodiment.

[0024] Figure 4 This is a block diagram illustrating an exemplary computer device that can be applied to an exemplary embodiment. Detailed Implementation

[0025] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0026] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0027] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0028] In related technologies, a physically separate DDR memory controller (DDR MC) and last-level cache (LLC) scheme is typically employed. In this architecture, the read reorder buffer (Read ROB) is used to match DDR bandwidth and restore data order, while the LLC is used to cache frequently accessed data to reduce external access. However, this separate architecture has significant drawbacks.

[0029] First, it results in low hardware resource utilization and wasted space. LLC and Read ROB are usually the largest storage units in an on-chip system, but their application scenarios are often mutually exclusive. For example, in scenarios involving large-scale streaming access or large-block data transfer, the data reuse rate is extremely low. LLC not only fails to improve performance but also wastes a large area of ​​SRAM resources due to being bypassed or idle. Conversely, in compute-intensive scenarios, Read ROB only requires a small depth, and the fixed allocation of large-capacity ROB space also results in waste.

[0030] Secondly, the lengthy data path leads to increased power consumption and latency. In a discrete architecture, data typically needs to be written from DRAM to the Read ROB, read out, written to the LLC, and finally transmitted to the on-chip interconnect. This additional data reading, writing, and movement between the Read ROB and LLC significantly increases the system's dynamic power consumption and data access latency.

[0031] To address the aforementioned issues, this paper proposes a multi-functional memory controller capable of dynamically configuring shared SRAM based on workload characteristics. By dynamically configuring the shared SRAM physical array as a read reordering buffer, last-level cache, or a hybrid mode according to runtime workload characteristics, efficient utilization and flexible adaptation of on-chip storage resources in the memory controller are achieved.

[0032] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a schematic block diagram illustrating a memory controller according to an exemplary embodiment.

[0034] like Figure 1 As shown, the memory controller 100 includes: an on-chip interconnect interface 101 for receiving memory access requests; a DRAM interface 102 for communicating with external DRAM; a shared memory unit 103 composed of an SRAM physical array; and a control unit 104 coupled to the on-chip interconnect interface 101, the DRAM interface 102, and the shared memory unit 103. The control unit 104 is configured to: monitor runtime workload characteristics of memory access requests received through the on-chip interconnect interface 101; and, in response to determining that the workload characteristics satisfy a first condition, configure the memory controller 100 in a read-only reordering buffer mode, wherein the read-only reordering buffer mode... In sorting buffer mode, the shared storage unit 103 is configured as a read reordering buffer to cache read transactions to be reordered; in response to determining that the workload characteristics meet a second condition, the memory controller 100 is configured as a last-level cache-only mode, wherein in the last-level cache-only mode, the shared storage unit 103 is configured as a last-level cache to cache data copies; and in response to determining that the workload characteristics meet a third condition, the memory controller 100 is configured as a hybrid mode, wherein in the hybrid mode, the shared storage unit 103 is divided into a first logical region as a read reordering buffer and a second logical region as a last-level cache.

[0035] As can be seen, the memory controller 100 breaks the architectural limitation of physically separating the DDR memory controller DDR MC and the last-level cache LLC in traditional SoCs. Traditional architectures typically implement an independent read reordering buffer (ReadROB) on each port and separately position the LLC between the NoC and the DDR MC. This separate architecture often results in the LLC and Read ROB not being used efficiently at the same time, leading to a waste of SRAM area.

[0036] The core of the memory controller 100 lies in the unified management and dynamic configuration of a large-capacity, high-bandwidth single-port SRAM physical array, namely the shared memory unit 103, through the control unit 104. By multiplexing the read and write ports of the SRAM, for example, by selecting multiplexers and demultiplexers, the control unit 104 can flexibly define the functional attributes of the storage space according to system requirements based on the shared physical memory.

[0037] Specifically, when configured in read-only reorder buffer mode (ROB-only), the entire SRAM space is used to support a large number of incomplete transactions, and each AXI ID can be allocated a separate queue space to maximize DDR bandwidth utilization; when configured in last-level cache only mode (LLC-only), the entire SRAM space is configured as cache lines based on cache channels and paths to store hot data, code segments, or page tables; when configured in hybrid mode, the SRAM space is logically divided into two parts, which simultaneously undertake reordering and caching functions, and the capacity ratio between the two is not statically fixed, but can be flexibly adjusted according to the needs of the scenario.

[0038] By integrating a shared SRAM physical array within the memory controller, the chip area can be significantly reduced, avoiding resource waste caused by idle LLCs or ROBs in discrete architectures. Simultaneously, since data is stored on the same physical medium, the cumbersome process of writing, reading, and rewriting data between independent Read ROBs and independent LLCs is avoided, thus eliminating additional data movement power consumption and improving the overall energy efficiency of the memory system. Furthermore, the dynamic switching mechanism between the three modes allows the memory controller to adapt to various drastically different application scenarios, from sequential movement of large blocks of data to random access to small data, effectively improving data read performance.

[0039] According to some embodiments, the shared memory unit 103 provided in this disclosure is an SRAM located inside a DDR MC.

[0040] To fully leverage the flexibility of the shared storage architecture, the control unit needs intelligent decision-making capabilities to accurately determine the current application scenario of the system and automatically switch to the most suitable operating mode. Therefore, this application further introduces a closed-loop adaptive control mechanism based on runtime workload characteristics.

[0041] According to some embodiments, the runtime workload characteristics include at least one of the following statistical parameters: read miss rate, row-buffer hit rate, and transaction queue depth.

[0042] For example, the control unit 104 can use its built-in hardware performance counter to collect statistical information, including the above-mentioned parameters, of the memory access request stream flowing through the on-chip interconnect interface 101 in real time.

[0043] According to some embodiments, the control unit is further configured to: determine that the first condition is met in response to determining that the read miss rate is not lower than a first threshold or the row buffer hit rate is not lower than a second threshold, thereby triggering the read-only reorder buffer mode; determine that the second condition is met in response to determining that the read miss rate is lower than a third threshold or the row buffer hit rate is lower than a fourth threshold, thereby triggering the last-level cache-only mode, wherein the third threshold is less than the first threshold and the fourth threshold is less than the second threshold; and determine that the third condition is met in response to determining that the read miss rate is not lower than the third threshold and is lower than the first threshold, or determining that the transaction queue depth is not lower than a fifth threshold, thereby triggering the hybrid mode.

[0044] It is understood that the control unit 104 does not rely on a preset static configuration, but rather forms a closed-loop feedback control by monitoring runtime statistical parameters in real time. For example, the decision logic of the control unit 104 is described as follows.

[0045] When the read miss rate is too high (not lower than the first threshold), it indicates that the current working set is much larger than the cache capacity or the data lacks reusability. At this time, LLC is experiencing thrashing, and continuing to maintain the cache is not only useless but also a waste of resources. Therefore, the LLC function should be bypassed to trigger the read-only reorder buffer mode (ROB-only). Alternatively, when the row buffer hit rate is very high (not lower than the second threshold), it indicates that the main access is sequential or streaming. At this time, DDR bandwidth utilization is the bottleneck, and the ROB-only mode should be triggered to use all resources for ROB to aggregate read and write commands and optimize DDR timing scheduling.

[0046] When the read miss rate is very low (below the third threshold), it indicates that there is a large amount of hot data (such as shared data or code segments), and the cache hit rate is high. The LLC capacity should be maximized to reduce access latency, and the LLC-only mode is triggered. Alternatively, when the row buffer hit rate is very low (below the fourth threshold), it indicates random access and low DDR efficiency. The LLC-only mode is triggered to use the LLC to mask the long latency of accessing external DRAM.

[0047] When the read miss rate is in the middle range (not lower than the third threshold and lower than the first threshold), it indicates that the system has both some caching benefits and faces some DDR bandwidth pressure. At this time, a hybrid mode is needed to balance latency and bandwidth. In addition, when the transaction queue depth is too large (not lower than the fifth threshold), it indicates that the memory subsystem is congested. It is necessary to dynamically allocate SRAM resources, both by alleviating queuing pressure through ROB and by reserving some LLC to reduce the number of DRAM requests.

[0048] By introducing multi-dimensional statistical parameters, including read miss rate, row buffer hit rate, and queue depth, the memory controller can accurately perceive software behavior. By setting high and low thresholds and hysteresis intervals, this mechanism can automatically identify different operating conditions such as high-reuse-rate hotspot access, large-scale streaming, and complex mixed scenarios, and automatically switch to the optimal hardware resource allocation mode. This not only avoids the complexity of manual static tuning but also ensures that the memory controller 100 always operates with the lowest latency or highest throughput under dynamically changing workloads.

[0049] It should be noted that the specific values ​​of the first to fifth thresholds mentioned above can be flexibly set and adjusted according to the actual hardware specifications (e.g., the total capacity of the shared SRAM), the specific application scenario, and the emphasis on performance indicators. This application does not limit this.

[0050] Having determined the optimal operating mode, the next step is to determine how to implement different logical functions, namely caching and reordering, on the same physical SRAM. To this end, this application proposes a storage architecture based on a unified metadata format, enabling physical storage bits in SRAM to be assigned different semantics according to the mode.

[0051] According to some embodiments, the control unit maintains storage entries with a uniform format in the shared storage unit and performs reuse interpretation of the uniform format storage entries according to the current mode of the memory controller.

[0052] For example, each physical storage unit in shared storage unit 103 is defined as a storage entry with a uniform format. This entry physically includes a common header field and a data payload field. Control unit 104 includes configurable interpretation logic: when in LLC mode, specific bits in the common header are interpreted as cache tag, validity bit, and MESI consistency status bit.

[0053] When in ROB mode, bits at the same physical location are reinterpreted as transaction ID (AXI ID), transaction age, dependency vector, or reordering status bits.

[0054] This reuse is not limited to status bits but can also be extended to data fields. For example, in ROB mode, some unused metadata bits can be used to store additional DDR Bank mapping information.

[0055] By using a unified format for storage entries, the overhead of physical data migration or reformatting between different modes can be avoided. The SRAM physical array does not require separate read / write circuits for LLC and ROB; instead, function switching is completed instantaneously by changing the interpretation method. This significantly saves chip area, eliminates redundancy in dedicated metadata storage areas in traditional separate architectures, and improves the response speed of mode switching.

[0056] Based on the unified storage structure described above, when the content controller enters ROB-only mode, its control logic will no longer follow the cache lookup rules, but will instead focus on meeting the stringent timing requirements of the DDR physical interface in order to maximize bus efficiency.

[0057] According to some embodiments, in the read-only reordering buffer mode, the control unit is further configured to: interpret storage entries in the shared storage unit as transaction queues constrained by DDR command timing; and sort and schedule the read transactions according to the DDR command timing.

[0058] When SRAM is used as a ROB (Read-Only Block), it is not merely a first-in, first-out queue, but a timing-aware scheduling pool. The control unit 104 scans all pending read transactions stored in the shared memory unit 103 and makes decisions based on the current DDR command timing constraints.

[0059] DDR command timing includes, but is not limited to: a four-activation-window (tFAW) limit, i.e., the number of activation commands allowed within a rolling time window; row activation to row activation delay (tRRD); and column command to column command delay (tCCD). The control unit prioritizes scheduling transactions that can hit the currently active row and do not violate the above timing constraints, thereby generating a valid and compact DDR command sequence.

[0060] Unlike general-purpose buffer queues, this embodiment utilizes the large capacity of shared SRAM to construct a deep scheduling window. This gives the controller more opportunities to find combinations that meet DDR timing constraints among a large number of requests, significantly reducing idle bubbles and row precharge / activation overhead on the DRAM bus. This deep optimization for DDR physical characteristics can transform out-of-order, fragmented CPU read requests into DRAM-friendly streaming access, greatly improving effective bandwidth utilization.

[0061] While focusing on DDR timing constraints, the unique refresh operation of DRAM is often a key factor causing system performance jitter. To further optimize performance, this application also introduces a special scheduling mechanism for the refresh cycle in ROB mode.

[0062] According to some embodiments, the DDR command timing constraints include a refresh blocking window corresponding to an external DRAM refresh operation, and the control unit is further configured to: during the refresh blocking window, utilize the shared memory unit to buffer received read transactions without blocking the on-chip interconnect interface; within the shared memory unit, pre-sort the buffered read transactions based on row address hits; and in response to the end of the refresh blocking window, send the pre-sorted read transactions as a continuous burst sequence to the external DRAM.

[0063] Understandably, DRAM requires periodic refresh operations to maintain data, during which time (refresh blocking window, tRFC) it cannot respond to read and write commands.

[0064] In this embodiment, when the external DRAM enters the refresh state, the control unit 104 does not suspend the on-chip interconnect interface 101, but continues to receive read requests from the host and store them in the shared memory unit 103. Since the SRAM does not require refreshing and is fast, the host does not perceive the DRAM pause.

[0065] During the DRAM idle period, the control unit uses the internal logic of SRAM to pre-order the accumulated requests. For example, requests to access the same Bank and Row are grouped and aggregated.

[0066] Once the refresh window ends, the control unit immediately sends these optimized requests to the DRAM in a back-to-back burst format.

[0067] The above mechanism effectively reduces DRAM refresh overhead. By caching during refresh and sending in bursts after refresh, it avoids host pipeline interruptions and significantly reduces access tail latency. This is especially important for applications with high real-time requirements, such as video processing or real-time inference.

[0068] In many compute-intensive scenarios, reducing data acquisition latency is a primary goal. In this case, the control unit 104 will switch to LLC-only mode to fully utilize the data retention capabilities of SRAM.

[0069] According to some embodiments, in the last-level-only caching mode, the control unit is further configured to: interpret storage entries in the shared storage unit as content-addressable data cache lines; and index and access the data copy using cache tags.

[0070] When entering LLC-only mode, the control unit 104 switches the logical view of the shared storage unit 103 to a standard cache structure (such as a set-associative structure). At this time, the common header of the storage entry is interpreted as a cache tag.

[0071] When a read request is received, the control unit extracts the index and tag bits from the address and performs content addressing or tag comparison in the shared memory unit. If a match is found, the data is returned directly from the SRAM without accessing the external DRAM; if a mismatch is found, a request is sent to the DRAM and the retrieved data is filled into the SRAM.

[0072] In this mode, the shared memory unit significantly reduces the number of accesses to off-chip DRAM by caching highly reusable data copies, which not only reduces the average memory access latency but also significantly reduces the system power consumption caused by frequent flipping of off-chip I / O pins.

[0073] In real-world SoC operation, pure streaming access or pure hotspot access is often extreme; a hybrid of both is more common. To address this complex scenario, this application proposes the most flexible hybrid mode and introduces a fine-grained resource allocation strategy within it.

[0074] According to some embodiments, in the hybrid mode, the control unit is further configured to: dynamically maintain a first logical region for read reordering and a second logical region for last-level caching in the shared storage unit; and determine whether to allocate a new memory access request to the first logical region or the second logical region based on line buffer locality hints.

[0075] It is understood that the hybrid mode provided in this application does not simply divide the SRAM into two fixed blocks, but is based on the dynamic maintenance of logical regions.

[0076] The control unit 104 uses row buffer locality hints carried in the request or generated internally to determine the data flow. Specifically, if the hint indicates that the request has a high row buffer hit rate, i.e., it is streaming data and is likely to be followed by consecutive address accesses, the control unit allocates it to the first logical region (ROB functional area). This is done to allow the request to participate in DDR scheduling as soon as possible, sending or retrieving it using burst transfers without polluting the cache. If the hint indicates that the request has a high data reuse rate but poor row locality, such as random hotspot access, it is allocated to the second logical region (LLC functional area) for long-term residence.

[0077] This intelligent data routing strategy based on row buffer locality hints solves the problem of streaming data flushing out hot data in traditional hybrid modes. It ensures that every bit of SRAM space is fully utilized: streaming data is accelerated via SRAM, while hot data resides in SRAM for reuse, thus achieving a dual optimization of high bandwidth and low latency on the same physical medium.

[0078] In hybrid mode, SRAM simultaneously performs read and write operations for both LLC and ROB roles, which poses a challenge to the bandwidth of a single-port SRAM. To ensure that the two functions operate without interference and efficiently, this application further improves the underlying access mechanism.

[0079] According to some embodiments, the control unit is further configured to manage the ports of the shared storage unit in a time-division multiplexing manner, wherein, in the hybrid mode, the ports of the shared storage unit are allocated to the first logical region and the second logical region in turn in the time domain according to burst groups or quality of service categories.

[0080] Since high-density SRAM typically employs a single read / write port design, the control unit 104 uses a time-division multiplexing (TDM) strategy to simultaneously serve LLC lookup and ROB scheduling in mixed mode.

[0081] The control unit divides SRAM access time into several time slices based on the Quality of Service (QoS) category of the burst group or request. For example, the first time slice serves tag matching and data reading for LLC, and the second time slice serves DDR command scheduling and writing for ROB. This allocation is not fixed and can be dynamically adjusted according to current QoS requirements. For example, when LLC is under heavy load, more time slices can be allocated to LLC.

[0082] The TDM mechanism logically treats a single-port SRAM as a virtual multi-port memory, resolving port conflict issues in hybrid modes without increasing SRAM hardware costs. Simultaneously, QoS-based scheduling ensures that high-priority tasks receive timely service, guaranteeing real-time performance.

[0083] Figure 2 This is a schematic diagram illustrating data reading and writing by a memory controller according to an exemplary embodiment.

[0084] Combination Figure 2 As shown, in order to achieve the above-mentioned flexible mode switching and resource sharing at the hardware level, the internal architecture of the memory controller has been further refined.

[0085] like Figure 2 As shown, SRAM is located at the core of the architecture, serving as the physical carrier of shared memory units. This SRAM is equipped with read / write ports for writing and reading data. Since SRAM is typically a high-density single-port design, a TDM arbitrator is introduced into the architecture to resolve conflicts arising from concurrent access across multiple functions.

[0086] The TDM arbitrator is directly coupled to the read / write port of the SRAM. It is responsible for receiving access requests from different functional logic blocks at the lower level and arbitrating them according to the preset time-division multiplexing strategy (such as based on QoS priority or burst group) to determine which party has the right to use the SRAM port in the current clock cycle.

[0087] At the lower level of the TDM arbitrator, the logical functions of the control unit are visualized as two parallel sub-control modules. The read reordering buffer controller is responsible for executing the logical functions described in the ROB mode. It maintains the order of transactions, generates scheduling instructions based on DDR command timing constraints (such as tFAW and tRRD), and interprets entries in SRAM as transaction queues. The last-level cache controller is responsible for executing the logical functions described in the LLC mode. It manages cache tag alignment, valid bit checks, and MESI status maintenance, and interprets entries in SRAM as cache lines.

[0088] Figure 2 The trapezoidal symbols on either side represent multiplexer and demultiplexer networks. The data path on the right connects to the on-chip interconnect interface (e.g., AXI bus) and is responsible for receiving read and write requests from the host. The data path on the left connects to the DRAM interface and is responsible for interacting with external memory.

[0089] During operation, when the memory controller is configured in read-only reorder buffer mode, the data path is selected to the read-only reorder buffer controller, and the TDM arbitrator allocates all time slices to this controller, allowing it to exclusively use the SRAM bandwidth to maximize throughput. When configured in last-level cache only mode, the data path is selected to the last-level cache controller, and the SRAM is used entirely for data cache lookup and access. In mixed mode, the data path dynamically switches between the two controllers, and the TDM arbitrator allocates SRAM ports between the two controllers in a round-robin fashion according to real-time needs, thereby achieving logical dual-function parallelism on a single physical medium.

[0090] This architecture, based on a TDM arbitrator and a parallel function controller, effectively solves the hardware challenge of decoupling and dynamically scheduling logical functions on shared physical SRAM, ensuring smooth data transmission and efficient processing in different modes.

[0091] According to some embodiments, the SRAM physical array of the shared memory unit 103 is divided into multiple memory banks; the control unit is configured to support heterogeneous bit-width configuration, configuring the first group of memory banks to adapt to the first bit width of the read reordering buffer entry, and configuring the second group of memory banks to adapt to the second bit width of the last-level cache line.

[0092] Understandably, traditional SRAMs typically employ a uniform bit width design, but this is not suitable for the hybrid mode described in this application. ROB entries are usually narrower because they only store transaction state and metadata, while LLC cache lines are usually wider because they store actual data blocks. This embodiment utilizes the multi-bank characteristic of SRAM to divide the physical array into different groups.

[0093] For example, the control unit 104 can configure the first group of banks in a narrow bit-width mode, dedicated to efficiently storing ROB entries; and configure the second group of banks in a wide bit-width mode, dedicated to storing LLC data. This hardware-level partitioning ensures that both data structures can be stored in their most natural physical form, avoiding wasted bit width.

[0094] According to some embodiments, the control unit 104 also includes a packer allocator, which is configured to pack multiple read reordering buffer entries with smaller bit widths into a single physical row of the shared memory unit in the hybrid mode to reduce internal storage fragmentation.

[0095] In hybrid mode, storing narrow ROB entries into wide SRAM rows can lead to significant internal fragmentation. To address this, the control unit 104 introduces a packer allocator. This allocator can pack multiple small-width ROB entries belonging to different transactions into the same physical row of shared memory. For example, a 256-bit wide physical row can store four 64-bit ROB entries.

[0096] Therefore, by employing bank-level heterogeneous configuration and row-level packing strategies, the storage density and utilization of SRAM can be significantly improved. Especially in hybrid mode, this mechanism significantly reduces internal storage fragmentation caused by differences in data granularity, allowing limited on-chip storage resources to simultaneously accommodate more cache lines and deeper transaction queues, thereby further enhancing the overall system performance.

[0097] In addition to serving as a core runtime storage resource, the large capacity and high bandwidth of the shared memory unit 103 also make it an ideal carrier for chip testing and debugging. To enhance the design-for-testability (DFT) capabilities of the SoC, this application utilizes shared SRAM to implement two special auxiliary operating modes.

[0098] According to some embodiments, the memory controller is also configured to operate in NoCLoopback Mode. In NoCLoopback Mode, the control unit intercepts memory access requests for specific address ranges and redirects them to the shared memory unit for read / write operations, instead of sending them to external DRAM, thereby using the shared memory unit to simulate external DRAM and perform bandwidth testing on the on-chip interconnect interface.

[0099] During chip return testing or the initial phase, the external DRAM may not be initialized or may be uncertain. In this case, the control unit 104 can enter loopback mode, using internal SRAM to simulate the behavior of the external DRAM. The control unit intercepts read / write requests destined for a specific DRAM address range and redirects them to shared memory unit 103 for processing. Because the SRAM is directly integrated inside the controller, this mode can generate extremely high throughput for stress testing the extreme bandwidth performance of on-chip interconnects without relying on external memory devices.

[0100] According to some embodiments, the memory controller is also configured to operate in a trace buffer mode, in which the shared memory unit is used to record command streams or data streams received through the on-chip interconnect interface for system debugging.

[0101] During system debugging, developers often need to analyze real-time behavior on the bus. Control unit 104 can utilize shared SRAM as a large circular log buffer. It can record command streams (such as AXI read / write instructions) or critical data streams flowing through on-chip interconnect interface 101 in real time. This recorded data can then be read through the debug interface to help engineers reproduce system behavior or locate faults.

[0102] These two auxiliary modes significantly expand the functional boundaries of the memory controller. The NoC loopback mode allows for full-speed stress testing of the on-chip bus without external DRAM, accelerating the chip verification cycle. The trace buffer mode provides a zero-cost (no additional dedicated RAM required) on-chip logic analyzer function, utilizing storage resources originally used for LLC / ROB to capture in-depth debug information, significantly reducing the difficulty and cost of system debugging.

[0103] In summary, the memory controller solution with integrated shared memory provided in this application achieves the following significant technical effects through architectural innovation and deep integration of control algorithms.

[0104] First, there's the optimization of chip area and cost. By breaking away from the traditional separate architecture and merging LLC and Read ROB into the same physical SRAM array, wasted area due to single-function idleness is eliminated. Combined with a packer allocator and heterogeneous bank configuration, internal fragmentation is further reduced, maximizing storage density.

[0105] Secondly, there is a significant improvement in energy efficiency. Data residing on the same physical medium avoids repeated data transfer between independent modules, directly eliminating additional read / write power consumption.

[0106] Furthermore, it exhibits high performance in dynamic adaptation. Closed-loop control based on load characteristics such as read miss rate and row hit rate enables the controller to automatically switch between low-latency caching mode and high-bandwidth reordering mode. Whether dealing with throughput bottlenecks in streaming big data or latency bottlenecks in handling random hot data, it always operates at the optimal point.

[0107] Embodiments of this disclosure also provide a method for controlling a memory controller.

[0108] Figure 3 This is a flowchart illustrating a control method for a memory controller according to an exemplary embodiment, the memory controller including a shared memory cell composed of an SRAM physical array.

[0109] like Figure 3 As shown, the control method 300 for the memory controller includes:

[0110] Step S301: Monitor the runtime workload characteristics of the received memory access requests; Step S302: In response to determining that the workload characteristics meet the first condition, the memory controller is configured to read-only reordering buffer mode, and the shared storage unit is configured as a read reordering buffer for caching read transactions to be reordered; Step S303: In response to determining that the workload characteristics satisfy the second condition, configure the memory controller to last-level cache-only mode and configure the shared memory unit as a last-level cache for caching data copies; and Step S304: In response to determining that the workload characteristics meet the third condition, the memory controller is configured to a hybrid mode, and the shared storage unit is divided into a first logical region as a read reordering buffer and a second logical region as a last-level cache.

[0111] In step S301, the characteristics of traffic entering through the on-chip interconnect interface are monitored in real time. For example, the memory controller can utilize internally integrated hardware performance counters to statistically analyze key runtime parameters. These parameters include, but are not limited to: read miss rate, used to assess the reuse of current data in the cache; line buffer hit rate, used to assess the spatial locality of the current access flow, determining whether it is random or sequential streaming access; and transaction queue depth, used to assess the current system congestion.

[0112] This enables the memory controller to accurately perceive the behavior patterns of the upper-layer software without relying on pre-configured static software or manual tuning, thus allowing it to adapt to dynamically changing application scenarios.

[0113] Step S302 is executed when the monitored workload meets the first condition. For example, when the read miss rate is higher than a preset first threshold, it indicates that the cache jitter or row buffer hit rate is higher than a second threshold, indicating that it is streaming, and the ROB-only mode is adopted.

[0114] In this mode, the controller can perform the following operations as an example.

[0115] For the first time, uniform storage entries in shared SRAM are interpreted as transaction queues constrained by DDR command timing. The original cache tag field is reused and interpreted as a transaction ID or sorting weight.

[0116] Secondly, the controller uses SRAM as a deep buffer pool to reorder read transactions according to the strict timing constraints of the DDR physical layer (such as four active windows tFAW, row activation delay tRRD, and column command delay tCCD).

[0117] In some examples, SRAM temporary requests are utilized during the DRAM refresh blocking window and sent in burst sequence after the refresh is complete.

[0118] This effectively solves performance bottlenecks in scenarios involving large-volume streaming data transfer or excessively large working sets. By bypassing the LLC function, unnecessary cache replacement and lookup overhead are avoided. Utilizing the large capacity of SRAM for deep reordering maximizes DDR bus bandwidth utilization and significantly reduces access tail latency caused by DRAM refreshes.

[0119] When the workload is monitored and meets the second condition, step S303 is executed. For example, when the read miss rate is lower than the preset third threshold, it indicates that the data reuse rate is extremely high, and the LLC-only mode is adopted.

[0120] In this mode, the controller can perform the following operations as an example.

[0121] First, uniform storage entries in shared SRAM are interpreted as content-addressed data cache lines. Metadata fields are then reinterpreted as cache tags and consistency states.

[0122] Secondly, standard caching logic (such as set-associative mapping) is used to index and access data copies.

[0123] The steps described above are optimized for computationally intensive or latency-sensitive scenarios. By maximizing the use of SRAM as a cache, a large number of repetitive memory access requests are intercepted, thereby reducing the number of accesses to external DRAM. This not only significantly reduces average memory access latency but also reduces power consumption caused by off-chip I / O flip-flops.

[0124] When the workload is monitored to meet the third condition, step S304 is executed. For example, when the read miss rate is in the middle range, or when the queue depth is congested, a hybrid mode is used.

[0125] In this mode, the controller can perform the following operations as an example.

[0126] Within the same physical SRAM array, a first region for reordering and a second region for caching are logically maintained simultaneously. Decisions are made based on line buffer locality cues carried in memory requests: highly streaming requests are allocated to the reordering region to accelerate transmission, while reusable requests are allocated to the caching region for residing. Furthermore, time-division multiplexing scheduling is applied to the single-port SRAM, with reordering and caching logic served in turn according to burst groups or QoS categories.

[0127] The above steps offer maximum flexibility, solving the problem of streaming data overflowing hot data in complex scenarios. It ensures that SRAM resources are used judiciously, alleviating DDR bandwidth pressure through ROB while retaining critical hot data through LLC, achieving a dynamic balance between bandwidth and latency.

[0128] In summary, Figure 3 The memory controller control method 300 shown maximizes resource utilization by implementing dynamic logic reconfiguration on a unified shared physical storage medium. This completely solves the SRAM area waste problem caused by static partitioning of LLC and ROB in traditional separate architectures, significantly reducing chip area costs. Simultaneously, it avoids the power consumption overhead of data transfer between different physical modules. Furthermore, through a closed-loop adaptive mechanism, it ensures that the system always operates at its optimal performance point, regardless of streaming, random access, or mixed loads.

[0129] According to one aspect of this disclosure, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0130] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0131] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0132] In the following text, combined with Figure 4 Illustrative examples of such computer devices, non-transitory computer-readable storage media, and computer program products are described.

[0133] Figure 4 An example computer device 400 is shown in which any of the embodiments described herein may be implemented. Computer device 400 may be used to implement one or more components of the systems and methods described above. Computer device 400 may include a bus 402 or other communication mechanism for communicating information, and one or more processors 404 coupled to the bus 402 for processing information. Processor 404 may be, for example, one or more general-purpose microprocessors.

[0134] Computer device 400 may also include main memory 406, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 402, for storing information and instructions to be executed by processor 404. Main memory 406 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 404. Such instructions, when stored in a storage medium accessible to processor 404, can make computer device 400 a special-purpose machine customized to perform the operations specified in the instructions. Main memory 406 may include non-volatile media and / or volatile media. Non-volatile media may include, for example, optical discs or magnetic disks. Volatile media may include dynamic memory. Common media formats may include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs (read-only optical disc drives), any other optical data storage media, any physical media with a perforated arrangement, RAM (random access memory), DRAM (dynamic random access memory), PROM (programmable read-only memory) and EPROM (erasable programmable read-only memory), FLASH-EPROM (fast erase programmable read-only memory), NVRAM (non-volatile random access memory), any other memory chips or tape cartridges, or network versions of the above.

[0135] Computer device 400 may implement the techniques described herein using custom hardwired logic, one or more ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), firmware, and / or program logic, which, when combined with computer device 400, enable computer device 400 to become a special-purpose machine or to be programmed therein. According to one embodiment, the techniques described herein are executed by computer device 400 in response to processor 404 executing one or more sequences of one or more instructions contained in main memory 406. Such instructions may be read into main memory 406 from another storage medium, such as storage device 408. Executing the sequence of instructions contained in main memory 406 causes processor 404 to perform the processing steps described herein. For example, the processes / methods disclosed herein may be implemented by computer program instructions stored in main memory 406. When these instructions are executed by processor 404, they may perform the steps shown in the corresponding figures and as described above. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0136] Computer device 400 also includes a network interface 410 coupled to bus 402. Network interface 410 can provide bidirectional data communication coupled to one or more network links connected to one or more networks. As another example, network interface 410 can be a local area network (LAN) card to provide data communication connectivity with a compatible LAN (or a WAN component communicating with a WAN (wide area network)). Wireless links can also be implemented.

[0137] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0138] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by them. These processes and algorithms can be implemented, in part or in whole, in a specific application circuit.

[0139] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, can be embodied in the form of a software product. This software product can be stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the methods described in the embodiments of this application. The storage medium may include a flash drive, a portable hard drive, ROM, RAM, a magnetic disk, an optical disk, another medium suitable for storing program code, or any combination thereof.

[0140] The embodiments disclosed herein can be implemented via a cloud platform, server, or group of servers that interact with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can install platform applications.

[0141] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0142] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.

[0143] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.

[0144] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0145] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0146] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.

[0147] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.

[0148] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.

Claims

1. A memory controller, comprising: The memory controller includes: On-chip interconnect interface, used to receive memory access requests; DRAM interface, used for communication with external DRAM; Shared memory cells, consisting of an SRAM physical array; and The control unit, coupled to the on-chip interconnect interface, the DRAM interface, and the shared memory unit, is configured to: Monitor the runtime workload characteristics of memory access requests received through the on-chip interconnect interface; In response to determining that the workload characteristics meet a first condition, the memory controller is configured in read-only reordering buffer mode, wherein in read-only reordering buffer mode, the shared storage unit is configured as a read reordering buffer to cache read transactions to be reordered; In response to determining that the workload characteristics satisfy a second condition, the memory controller is configured to a last-level cache-only mode, wherein, in the last-level cache-only mode, the shared memory unit is configured as a last-level cache for caching data copies; and In response to determining that the workload characteristics satisfy a third condition, the memory controller is configured to a hybrid mode, wherein in the hybrid mode, the shared storage unit is divided into a first logical region as a read reordering buffer and a second logical region as a last-level cache.

2. The memory controller of claim 1, wherein, in, The control unit maintains storage entries with a uniform format in the shared storage unit and performs reuse interpretation of the uniform format storage entries according to the current mode of the memory controller.

3. The memory controller according to claim 1 or 2, characterized in that in, In the read-only reordering buffer mode, the control unit is further configured to: The storage entries in the shared storage unit are interpreted as transaction queues subject to DDR command timing constraints; and The read transactions are sorted and scheduled according to the DDR command timing.

4. The memory controller of claim 1 or 2, wherein, in, In the last-level cache-only mode, the control unit is further configured to: The storage entries in the shared storage unit are interpreted as content-addressed data cache lines; and The data copy is indexed and accessed using cache tags.

5. The memory controller according to claim 1 or 2, characterized in that, in, In the hybrid mode, the control unit is further configured to: The shared storage unit dynamically maintains a first logical region for read reordering and a second logical region for last-level caching; and The allocation of a new memory access request to the first logical region or the second logical region is determined based on the line buffer locality hint.

6. The memory controller according to claim 1 or 2, characterized in that, in, The runtime workload characteristics include at least one of the following statistical parameters: Read miss rate, row buffer hit rate, and transaction queue depth Furthermore, the control unit is further configured as follows: In response to determining that the read missing rate is not lower than a first threshold or the row buffer hit rate is not lower than a second threshold, the first condition is satisfied to trigger the read-only reorder buffer mode; In response to determining that the read miss rate is lower than a third threshold or the row buffer hit rate is lower than a fourth threshold, it is determined that the second condition is met to trigger the last-level-only cache mode, wherein the third threshold is less than the first threshold and the fourth threshold is less than the second threshold; and In response to determining that the read miss rate is not lower than the third threshold and is lower than the first threshold, or determining that the transaction queue depth is not lower than the fifth threshold, the third condition is satisfied to trigger the hybrid mode.

7. The memory controller according to claim 3, characterized in that, in, The DDR command timing constraints include a refresh blocking window corresponding to the external DRAM refresh operation, and the control unit is further configured to: During the refresh blocking window, the received read transactions are buffered using the shared memory unit without blocking the on-chip interconnect interface; Within the shared storage unit, buffered read transactions are pre-sorted based on row address hits; as well as In response to the end of the refresh blocking window, the pre-ordered read transactions are sent to the external DRAM as a continuous burst sequence.

8. The memory controller according to claim 1 or 2, characterized in that, in, The control unit is also configured to manage the ports of the shared storage unit in a time-division multiplexing manner, wherein, in the hybrid mode, the ports of the shared storage unit are allocated to the first logical region and the second logical region in turn in the time domain according to the burst group or quality of service category.

9. A control method for a memory controller, characterized in that, The memory controller includes a shared memory cell composed of an SRAM physical array, and the method includes: Monitor the runtime workload characteristics of received memory access requests; In response to determining that the workload characteristics meet a first condition, the memory controller is configured to read-only reordering buffer mode, and the shared storage unit is configured as a read reordering buffer to cache read transactions to be reordered; In response to determining that the workload characteristics satisfy the second condition, the memory controller is configured to last-level cache-only mode, and the shared memory unit is configured as a last-level cache for caching data copies; and In response to determining that the workload characteristics satisfy the third condition, the memory controller is configured to a hybrid mode, and the shared storage unit is divided into a first logical region as a read reordering buffer and a second logical region as a last-level cache.

10. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of claim 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of claim 9.

12. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of claim 9.

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