Tranformer transfer learning-based analog integrated circuit cross-process performance prediction method and system

Abstract

The invention belongs to the technical field of analog integrated circuit design automation, and discloses an analog integrated circuit cross-process performance prediction method and system based on Transform transfer learning, and the method comprises the steps: 1, carrying out the preprocessing of analog integrated circuit sample data; 2, serializing the sample data according to a preset sequence, mapping each parameter into vector representation, adding a global abstract vector, and splicing according to a fixed sequence to form an input sequence; 3, encoding the input sequence to obtain an output sequence; 4, inputting the global features into the regression head network, and outputting a performance index prediction value; 5, training is carried out, network parameters obtained through pre-training of the source technology are migrated to the target technology, fine adjustment is carried out on part of network parameters of a target technology data set, and cross-technology performance prediction is achieved; and 6, performing forward reasoning on operational amplifier design parameters under a given target process according to the steps 2-4 to obtain a performance prediction result. The method improves the stability and efficiency of performance prediction.

Description

Technical Field

[0001] This application belongs to the field of analog integrated circuit design automation technology, specifically relating to a method and system for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning. Background Technology

[0002] Analog operational amplifiers are one of the fundamental circuit units in analog integrated circuits, widely used in data conversion, signal conditioning, filtering, and communication. Common op-amp topologies include two-stage op-amps and five-transistor op-amps. Their performance is affected by a variety of parameters, including transistor size, bias current, and compensation networks. The design process is highly dependent on the engineer's experience and iterative simulation.

[0003] As process technology evolves from older source process A to more advanced or target process B with different characteristics, the device model, capacitance and resistance distribution, and parasitic effects of the same topology change significantly under different processes, making it difficult to directly reuse existing design experience and size-performance mapping. Traditionally, large-scale simulations and manual parameter tuning are often required for each new process generation, resulting in long design cycles and high costs.

[0004] In recent years, modeling the performance of analog circuits using machine learning methods has become a research hotspot. Existing techniques, such as Multilayer Perceptron (MLP) and Gaussian Process Regression, typically treat circuit dimensions as unordered multidimensional vectors, directly fitting a mapping from "input features of dimension n" to "several performance metrics." These techniques suffer from the following technical problems:

[0005] (1) The structural relationships and coupling information between the design parameters are not explicitly utilized, resulting in insufficient model expressive power in operational amplifier scenarios with strong parameter coupling and obvious nonlinear characteristics.

[0006] (2) Most methods train the model separately according to the process, lack an effective cross-process transfer mechanism, and cannot make full use of the large sample data on the source process A. The prediction performance is unstable under the small sample condition of the target process B.

[0007] (3) Existing methods model each performance index separately, failing to fully utilize the correlation between different performance indices.

[0008] Therefore, there is an urgent need for a new method to predict the cross-process performance of target process B under small sample conditions through the multi-head self-attention mechanism of Transformer. Summary of the Invention

[0009] To address the aforementioned technical problems in the existing technology, the purpose of this invention is to achieve cross-process performance prediction of target process B under small sample conditions. The technical solution is as follows:

[0010] A method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning includes the following steps:

[0011] Step 1: Obtain sample data of analog integrated circuits with the same or similar topology under source process A and target process B, and preprocess the sample data;

[0012] Step 2: Serialize the preprocessed sample data in a preset order, use learnable embedding mapping to map each parameter into a vector representation, add a learnable global summary vector to the beginning of the sequence, and concatenate the global summary vector with the embedding vectors of each parameter in a fixed order to form the input sequence;

[0013] Step 3: Encode the input sequence using a multi-layer Transformer encoder to obtain the output sequence;

[0014] Step 4: Input the global features into the regression head network and output the predicted values ​​of the performance indicators under the target process B;

[0015] Step 5: A phased training strategy is adopted to train between source process A and target process B. The network parameters pre-trained in source process A are transferred to target process B. Based on the target process dataset, some network parameters are fine-tuned to achieve cross-process performance prediction.

[0016] Step 6: After the training is completed, perform forward inference on a set of operational amplifier design parameters under the given target process B according to steps 2 to 4 to obtain the corresponding performance prediction results.

[0017] Furthermore, in step 1, the sample data includes: transistor width, channel length, capacitance, zero-point resistance, DC gain, and bias current;

[0018] The analog integrated circuit includes: a two-stage operational amplifier and a five-transistor operational amplifier;

[0019] The preprocessing includes:

[0020] (1) Linearly normalize the transistor width, channel length, capacitance, and zero-point resistance;

[0021] (2) Perform a logarithmic transformation on the bias current and then normalize it;

[0022] (3) For DC gain, use a linear or logarithmic scale for the index in decibels;

[0023] (4) Perform an angle mapping on the phase margin and constrain it within [0, 360°].

[0024] Furthermore, the two-stage operational amplifier includes a differential input stage, a second-stage gain stage, and a frequency compensation and zero-point adjustment network.

[0025] Furthermore, in step 2, the parameters are mapped to vector representations using a learnable embedding mapping, the expression of which is:

[0026]

[0027] in, Represents the input parameter vector The Middle Each design parameter scalar; This represents the dimension of the model's hidden features, corresponding to the dimension of the embedding vector and the hidden states of each layer; and They represent the first Embedded mapping weight vector and bias vector for each design parameter Indicates the first Embedding vectors of design parameters;

[0028] The expression for the input sequence is:

[0029]

[0030] in, Represents a learnable global summary vector; ~ This represents the embedding vector for 13 design parameters; This represents the input sequence of the Transformer encoder.

[0031] Furthermore, in step 3, the multi-layer Transformer encoder includes:

[0032] (1) Multi-head self-attention sublayer: Self-attention is calculated for the entire sequence to obtain the attention weights between embedding vectors with different parameters. The calculation expression is as follows:

[0033]

[0034] in, This represents the scaled dot product attention function. Indicates a query. Indicates key, Represents value, Represents the normalized exponential function, Indicates the dimension of the query or key vector in each attention head;

[0035] (2) Residual connection and layer normalization: After adding the multi-head self-attention output and the input residual, layer normalization is performed. The expression is as follows:

[0036]

[0037] in, This represents the input hidden state of a certain layer of the Transformer, i.e., the sequence feature matrix; This represents the intermediate hidden state after the output of the multi-head self-attention sub-layer is added to the residual. This indicates a multi-head self-attention module. Representation layer normalization;

[0038] (3) Feedforward sublayer: performs nonlinear transformation and reconstruction on the features at each position in the sequence;

[0039] (4) Residual connection and layer normalization are performed again, and the expression is as follows:

[0040]

[0041] in, Indicates the number of floors. This represents a position-based feedforward neural network. This represents the hidden output state of the next layer after passing through the feedforward network sublayer and residual connection.

[0042] Furthermore, in step 4, the global feature is the hidden vector corresponding to the global summary vector;

[0043] The expression for the predicted value of the output performance index under target process B is:

[0044]

[0045] in, Indicates the sequence in the output sequence of the last encoder layer that is related to... The hidden vector at the corresponding position; This represents the model's prediction result for the performance index vector; , These represent the weight matrix and bias vector of the regression output layer, respectively.

[0046] Furthermore, in step 4, the number of predicted values ​​of the output performance index under target process B. .

[0047] Furthermore, in step 5, the phased training strategy includes the following stages:

[0048] (1) Source Process A Pre-training Stage

[0049] On the source process A sample data, the Transformer encoder and regression head are trained end-to-end to enable the model to fully learn the general mapping relationship between size and performance in the operational amplifier topology.

[0050] (2) Fine-tuning stage of target process B

[0051] The network parameters pre-trained from source process A are transferred to the target process B scenario. Several layers at the bottom of the Transformer encoder are set to freeze, allowing several layers at the top and the regression head parameters to be fine-tuned on the sample data of the target process B.

[0052] The training employs a phased training strategy, and during the training process, a loss function is constructed, including:

[0053] a. The mean square error (MSE) loss of each indicator is expressed as follows:

[0054]

[0055] in, Indicates the mean square error loss. and They represent the first The results of normalizing the true and predicted values ​​of each performance metric during training.

[0056] b. The normalized mean absolute error (NMAE) of each indicator is expressed as follows:

[0057]

[0058]

[0059] in, Indicates the first The mean absolute error of each performance indicator and They represent the first The predicted and actual values ​​of each performance indicator This means taking the arithmetic mean. Indicates the first The normalized mean absolute error of each indicator. and These represent the maximum and minimum values ​​of the indicator in the sample, respectively.

[0060] c. The overall coefficient of determination R².

[0061] Furthermore, in the pre-training, the number of samples in the source process A sample data is greater than the number of samples in the target process B sample data.

[0062] A cross-process performance prediction system for analog integrated circuits based on Transformer transfer learning includes the following modules:

[0063] (1) Data construction module, used to collect and organize the design parameters and performance indicators of analog integrated circuits under source process A and target process B, and form source process dataset and target process dataset;

[0064] (2) Parameter embedding module, used to preprocess and serialize the design parameters and map them into vector representations. Learnable global feature vectors are added to the beginning of the sequence to form the input sequence;

[0065] (3) An encoder module, used to perform Transformer encoding on the input sequence and output a global representation;

[0066] (4) A regression prediction module, used to map the global representation to the predicted value of the at least one performance index;

[0067] (5) Transfer training module, which is used to complete pre-training on the source process dataset and transfer the parameters to the target process dataset for fine-tuning training to achieve cross-process adaptation.

[0068] Beneficial effects: (1) The corresponding design parameters of the op-amp are regarded as an ordered sequence, and the long-range dependence and coupling relationship between the parameters are explicitly modeled through the multi-head self-attention mechanism of Transformer, which better reflects the collaborative constraints between "size-compensation-bias". (2) By pre-training on the source process A and then freezing and migrating some coding layers to the target process B, only the high-level layers are fine-tuned, and the prediction error and R² can still be maintained under the small sample conditions of the target process B. (3) Using the global features corresponding to the global summary vector, multiple key performance parameters such as slewrate_pos, dc_gain, ugf, phase_margin and cmrr are regressed simultaneously. The correlation between the indicators is used to improve the overall prediction stability and efficiency. (4) It has universality and scalability. It is not only applicable to two-stage op-amps, but also to other analog op-amp topologies such as five-transistor op-amps; and the dimensions of design parameters and performance indicators can be extended according to the actual circuit type. Attached Figure Description

[0069] Figure 1 This is a flowchart of the overall process flow of the analog integrated circuit cross-process performance prediction method based on Transformer transfer learning of the present invention.

[0070] Figure 2 This is a two-stage operational amplifier circuit diagram in an embodiment of the present invention;

[0071] Figure 3This is a model architecture diagram of the present invention;

[0072] Figure 4 This is the loss curve of the model after transfer learning in this invention;

[0073] Figure 5 This is a scatter plot comparing the predicted and actual values ​​in target process B according to the present invention.

[0074] Figure 6 This is a schematic diagram showing the statistical results of various performance parameters NMAE and R² on the circuit diagrams of the source process A and the target process B, respectively. Detailed Implementation

[0075] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0076] like Figure 1 As shown, the method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning of the present invention specifically includes the following steps:

[0077] like Figure 2 As shown, this embodiment uses a two-stage operational amplifier (op-amp) as the modeling object. This two-stage op-amp includes a differential input stage, a second-stage gain stage, and frequency compensation and zero-point adjustment networks. The differential input stage is used to initially amplify the differential input signal and provide high common-mode rejection capability. The second-stage gain stage is used to further improve the DC gain. A compensation capacitor Cc is connected between the first and second stages to achieve Miller compensation. A zero-point resistor Cr is connected in series with Cc to introduce zeros in the frequency domain to improve phase margin. The bias current Ibias provides the operating current for each stage through the bias branch. Figure 3 The transistor widths w1 to w5, channel lengths l1 to l5, and Cc, Cr, and Ibias constitute the physical corresponding quantities of the 13 key design parameters in the method of this invention.

[0078] The following preprocessing operations are performed on the raw data, including:

[0079] (1) Linearly normalize the dimensional parameters such as width, length, capacitance, and resistance;

[0080] (2) The bias current Ibias is logarithmically transformed and then normalized to reduce the difference in magnitude;

[0081] (3) For indicators such as dc_gain measured in decibels, linear or logarithmic scales should be used during training as needed;

[0082] (4) Perform angle mapping on the phase margin phase_margin and constrain it within [0, 360°] to avoid the periodic jumps from affecting the training.

[0083] Obtain the training set, validation set, and test set for source process A and target process B, respectively.

[0084] The input design parameter vector and ideal performance index vector expressions are as follows:

[0085]

[0086]

[0087] in, This represents the input design parameter vector. Indicates the transistor channel width. Indicates the transistor channel length. Indicates the compensation capacitor. Represents zero-point resistance. Indicates the bias current; This represents the corresponding ideal performance index vector. Indicates the forward slewing rate, Indicates DC gain, Indicates unity-gain bandwidth, Indicates phase margin, This indicates the common-mode rejection ratio.

[0088] Step S2: Parameter sequence embedding and global vector construction

[0089] like Figure 1 As shown on the left, in this embodiment, multiple design parameters are regarded as a one-dimensional ordered sequence. Each scalar parameter is first embedded and mapped to obtain a corresponding vector representation. Then, a learnable global summary vector is introduced at the front of the sequence to aggregate global design features.

[0090]

[0091] in, Represents the input parameter vector The Middle Each design parameter scalar; This represents the dimension of the model's hidden features, corresponding to the dimension of the embedding vector and the hidden states of each layer; and They represent the first The embedded mapping weight vector and bias vector of each design parameter are both learnable parameters. Indicates the first An embedding vector for each design parameter.

[0092] The global summary vector and the embedding vectors of each parameter are concatenated in a fixed order to obtain the input sequence, which is then used as the input to the Transformer encoder. The expression for the input sequence is as follows:

[0093]

[0094] in, Represents a learnable global summary vector; ~ This represents the embedding vector for 13 design parameters; This represents the input sequence of the Transformer encoder.

[0095] Step S3: Transformer encoder modeling

[0096] like Figure 3 As shown, this embodiment uses a multi-layer Transformer encoder to encode the above sequence. Each encoder layer includes:

[0097] (1) Multi-head self-attention sublayer: Self-attention is calculated for the entire sequence to obtain the attention weights between different parameter embedding vectors, thereby learning the dependencies between various design parameters. The calculation expression is as follows:

[0098]

[0099] in, This represents the scaled dot product attention function; This indicates a query. Indicates key. The values ​​are all obtained by linear transformation of the input features of the current layer; This represents the normalized exponential function; This represents the dimension of the query / key vector in each attention head, used for scaling to stabilize training.

[0100] (2) Residual connection and layer normalization: After adding the self-attention output and the input residual, layer normalization is performed to stabilize the training process. The expression is as follows:

[0101]

[0102] in, This represents the input hidden state (sequence feature matrix) of a certain layer of the Transformer. This represents the intermediate hidden state after the output of the multi-head self-attention sub-layer is added to the residual. This refers to the multi-head self-attention module. Layer Normalization;

[0103] (3) Feedforward sublayer: performs nonlinear transformation and reconstruction on the features at each position in the sequence;

[0104] (4) Residual connection and layer normalization are performed again, and the expression is as follows:

[0105]

[0106] in, Indicates the number of floors. This represents a position-based feed-forward network. This represents the hidden output state of the next layer after passing through the feedforward network sublayer and residual connections.

[0107] After passing through these encoder layers, the output sequence is obtained. In this embodiment, the hidden vector corresponding to the position of the global summary vector is selected as the global summary feature of the sample, which is then used for subsequent regression prediction.

[0108] After stacking L layers, the hidden vector corresponding to the global summary vector is taken as the global feature.

[0109] Step S4: Multi-indicator joint regression prediction

[0110] The global features obtained in step S3 are input into the regression head network. The regression head can adopt a structure of several fully connected layers plus nonlinear activation, and outputs predicted values ​​corresponding to one or more performance indicators, the expression of which is:

[0111]

[0112] in, Indicates the sequence in the output sequence of the last encoder layer that is related to... The hidden vector at the corresponding position; This represents the model's prediction result for the performance index vector; , These represent the weight matrix and bias vector of the regression output layer, respectively.

[0113] Step S5: Cross-process transfer learning training

[0114] like Figure 1 As shown on the right, this embodiment employs a phased training strategy between the source process A and the target process B:

[0115] (1) Source Process A Pre-training Stage

[0116] On the source process A dataset with a large number of samples, the Transformer encoder and regression head are trained end-to-end to enable the model to fully learn the general mapping relationship between size and performance in the op-amp topology.

[0117] (2) Fine-tuning stage of target process B

[0118] The network parameters pre-trained from source process A are transferred to the target process B scenario. Several layers at the bottom of the Transformer encoder are set to frozen, allowing only the top few layers and regression head parameters to be fine-tuned on small sample data of target process B.

[0119] In the pre-training process, the number of samples in the source process A dataset is greater than the number of samples in the target process B dataset. During training, a loss function is constructed, including:

[0120] (1) The mean square error (MSE) loss of each indicator is expressed as follows:

[0121]

[0122] in, Indicates the mean square error loss. and They represent the first The results of normalizing the true and predicted values ​​of each performance metric during training.

[0123] (2) The normalized mean absolute error (NMAE) of each indicator is expressed as follows:

[0124]

[0125]

[0126] in, Indicates the first The mean absolute error of each performance indicator and They represent the first The predicted and actual values ​​of each performance indicator This means taking the arithmetic mean. Indicates the first The normalized mean absolute error of each indicator. and These represent the maximum and minimum values ​​of the indicator in the sample, respectively.

[0127] (3) Overall determination coefficient R² index.

[0128] By monitoring during the training and validation phases R² can be used to comprehensively measure the model's performance in terms of absolute error and goodness of fit.

[0129] like Figure 4 As shown in the figure, this embodiment illustrates how the model's loss function changes with the number of training epochs when performing transfer learning training on the target process B. The horizontal axis represents the number of training epochs, and the vertical axis represents the loss values ​​on the training and validation sets. It can be seen that as the number of training epochs increases, both the training set loss and the validation set loss decrease rapidly and gradually stabilize, without significant oscillations or divergence. This indicates that with the transfer learning strategy of freezing several layers at the bottom of the encoder and only fine-tuning the higher-level coding layers and the regression head, the model can achieve stable convergence on the target process B while maintaining good generalization performance, thus obtaining accurate performance prediction results even under small sample conditions.

[0130] Step S6: Performance Prediction and Design Assistance for Target Process B

[0131] After completing the above transfer learning training, for a set of operational amplifier design parameters (including w1~w5, l1~l5, Cc, Cr and Ibias) under a given target process B, forward inference is performed according to steps S2~S4 to obtain the corresponding performance prediction results.

[0132] like Figure 5 As shown in the figure, this embodiment presents a scatter plot comparing the predicted values ​​and simulated actual values ​​of some performance indicators on the target process B. The horizontal axis represents the actual simulated values, and the vertical axis represents the predicted values. The results show that the cross-process prediction model based on Transformer transfer learning can accurately recover the key performance indicators of the operational amplifier on the target process B.

[0133] like Figure 6 As shown, in this embodiment, a two-stage op-amp is first used as the object. Model training and evaluation are completed on source process A and target process B according to the aforementioned method to obtain the normalized mean absolute error of each performance index. The modeling and transfer learning framework was applied to a five-transistor op-amp (5T Op-Amp) and the coefficient of determination (R²). Based on this, to further verify the generalization capability of the invention across different circuit topologies, the same modeling and transfer learning framework was applied to both source process A and target process B. The results of the R² statistics are also plotted together. Figure 6 middle.

[0134] Depend on Figure 6 It can be seen that, regardless of whether it is a two-stage op-amp or a five-transistor op-amp, the performance indicators of each stage vary at different process nodes. The values ​​are all less than 1%, and the corresponding R² is close to 1, indicating that the method of the present invention can provide prediction results with low error and high fitting degree under various topologies and cross-process scenarios. It can effectively inherit the large sample prior of the source process A, and maintain high prediction accuracy and good topology adaptability and generalization ability under the small sample condition of the target process B.

[0135] Engineers can use this prediction model to quickly evaluate whether different size combinations meet the constraints of indicators such as slewrate_pos, dc_gain, ugf, phase_margin, and cmrr, thereby shortening the simulation iteration time and accelerating the operational amplifier design process under the target process B.

[0136] A cross-process performance prediction system for analog integrated circuits based on Transformer transfer learning includes the following modules:

[0137] The data construction module is used to collect and organize the design parameters and performance indicators of analog integrated circuits under source process A and target process B, forming source process datasets and target process datasets.

[0138] The parameter embedding module is used to preprocess and serialize the design parameters and map them into vector representations. Learnable global feature vectors are added to the beginning of the sequence to form the input sequence.

[0139] The encoder module is used to perform Transformer encoding on the input sequence and output a global representation;

[0140] A regression prediction module is used to map the global representation to the predicted value of the at least one performance indicator;

[0141] The transfer training module is used to perform pre-training on the source process dataset and transfer the parameters to the target process dataset for fine-tuning training to achieve cross-process adaptation.

[0142] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning, characterized in that, Includes the following steps: Step 1: Obtain sample data of analog integrated circuits with the same or similar topology under source process A and target process B, and preprocess the sample data; Step 2: Serialize the preprocessed sample data in a preset order, use learnable embedding mapping to map each parameter into a vector representation, add a learnable global summary vector to the beginning of the sequence, and concatenate the global summary vector with the embedding vectors of each parameter in a fixed order to form the input sequence; Step 3: Encode the input sequence using a multi-layer Transformer encoder to obtain the output sequence; Step 4: Input the global features into the regression head network and output the predicted values ​​of the performance indicators under the target process B; Step 5: A phased training strategy is adopted to train between source process A and target process B. The network parameters pre-trained in source process A are transferred to target process B. Based on the target process dataset, some network parameters are fine-tuned to achieve cross-process performance prediction. Step 6: After the training is completed, perform forward inference on a set of operational amplifier design parameters under the given target process B according to steps 2 to 4 to obtain the corresponding performance prediction results.

2. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 1, characterized in that, In step 1, the sample data includes: transistor width, channel length, capacitance, zero-point resistance, DC gain, and bias current. The analog integrated circuit includes: a two-stage operational amplifier and a five-transistor operational amplifier; The preprocessing includes: (1) Linearly normalize the transistor width, channel length, capacitance, and zero-point resistance; (2) Perform a logarithmic transformation on the bias current and then normalize it; (3) For DC gain, use a linear or logarithmic scale for the index in decibels; (4) Perform an angle mapping on the phase margin and constrain it within [0, 360°].

3. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 2, characterized in that, The two-stage operational amplifier includes a differential input stage, a second-stage gain stage, and a frequency compensation and zero-point adjustment network.

4. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 1, characterized in that, In step 2, the learnable embedding mapping is used to map each parameter into a vector representation, the expression of which is: in, Represents the input parameter vector The Middle Each design parameter scalar; This represents the dimension of the model's hidden features, corresponding to the dimension of the embedding vector and the hidden states of each layer; and They represent the first Embedded mapping weight vector and bias vector for each design parameter Indicates the first Embedding vectors of design parameters; The expression for the input sequence is: in, Represents a learnable global summary vector; ~ An embedding vector representing 13 design parameters; This represents the input sequence of the Transformer encoder.

5. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 1, characterized in that, In step 3, the multi-layer Transformer encoder includes: (1) Multi-head self-attention sublayer: Self-attention is calculated for the entire sequence to obtain the attention weights between embedding vectors with different parameters. The calculation expression is as follows: in, This represents the scaled dot product attention function. Indicates a query. Indicates key, Represents value, Represents the normalized exponential function, Indicates the dimension of the query or key vector in each attention head; (2) Residual connection and layer normalization: After adding the multi-head self-attention output and the input residual, layer normalization is performed. The expression is as follows: in, This represents the input hidden state of a certain layer of the Transformer, i.e., the sequence feature matrix; This represents the intermediate hidden state after the output of the multi-head self-attention sub-layer is added to the residual. This indicates a multi-head self-attention module. Representation layer normalization; (3) Feedforward sublayer: performs nonlinear transformation and reconstruction on the features at each position in the sequence; (4) Residual connection and layer normalization are performed again, and the expression is as follows: in, Indicates the number of floors. This represents a position-based feedforward neural network. This represents the hidden output state of the next layer after passing through the feedforward network sublayer and residual connection.

6. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 1, characterized in that, In step 4, the global feature is the hidden vector corresponding to the global summary vector; The expression for the predicted value of the output performance index under target process B is: in, Indicates the sequence in the output sequence of the last encoder layer that is related to... The hidden vector at the corresponding position; This represents the model's prediction result for the performance index vector; , These represent the weight matrix and bias vector of the regression output layer, respectively.

7. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 1, characterized in that, In step 4, the number of predicted values ​​of the output performance index under target process B. .

8. The method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 1, characterized in that, In step 5, the phased training strategy includes the following stages: (1) Source Process A Pre-training Stage On the source process A sample data, the Transformer encoder and regression head are trained end-to-end to enable the model to fully learn the general mapping relationship between size and performance in the operational amplifier topology. (2) Fine-tuning stage of target process B The network parameters pre-trained from source process A are transferred to the target process B scenario. Several layers at the bottom of the Transformer encoder are set to freeze, allowing several layers at the top and the regression head parameters to be fine-tuned on the sample data of the target process B. The training employs a phased training strategy, and during the training process, a loss function is constructed, including: a. The mean square error (MSE) loss of each indicator is expressed as follows: in, Indicates the mean square error loss. and They represent the first The results of normalizing the true and predicted values ​​of each performance metric during training. b. The normalized mean absolute error (NMAE) of each indicator is expressed as follows: in, Indicates the first The mean absolute error of each performance indicator and They represent the first The predicted and actual values ​​of each performance indicator This means taking the arithmetic mean. Indicates the first The normalized mean absolute error of each indicator. and These represent the maximum and minimum values ​​of the indicator in the sample, respectively. c. The overall coefficient of determination R².

9. A method for predicting the cross-process performance of analog integrated circuits based on Transformer transfer learning according to claim 8 or 1, characterized in that, In the pre-training, the number of samples in the source process A sample data is greater than the number of samples in the target process B sample data.

10. A cross-process performance prediction system for analog integrated circuits based on Transformer transfer learning, characterized in that, Includes the following modules: (1) Data construction module, used to collect and organize the design parameters and performance indicators of analog integrated circuits under source process A and target process B, and form source process dataset and target process dataset; (2) Parameter embedding module, used to preprocess and serialize the design parameters and map them into vector representations. Learnable global feature vectors are added to the beginning of the sequence to form the input sequence; (3) An encoder module, used to perform Transformer encoding on the input sequence and output a global representation; (4) A regression prediction module, used to map the global representation to the predicted value of the at least one performance index; (5) Transfer training module, which is used to complete pre-training on the source process dataset and transfer the parameters to the target process dataset for fine-tuning training to achieve cross-process adaptation.

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