Anti-latch circuit for low earth orbit satellite core component

Abstract

The invention relates to an anti-latch-up circuit for a low-orbit satellite core component. The anti-latch-up circuit comprises a switching power supply and a tested device, and a load, a control module, a current detection chip, a master control MCU and an ADC module. The load is connected with a detected device, and the current detection chip is used for detecting the real-time current of the load, converting the real-time current into a digital signal through the ADC module and transmitting the digital signal to the main control MCU; the main control MCU judges whether the current flowing through the load exceeds a safety threshold value or not based on the digital signal, and outputs a control signal to the control module after the current exceeds the safety threshold value; the control module is connected in a branch where the load is connected with the tested device, and adjusts the magnitude of the current flowing through the load based on the control signal to enable the current to be within a safety threshold value all the time. According to the scheme, almost no voltage fluctuation exists, the influence on the working state of the device can be almost ignored, and the operation risk and the failure risk of a module with the high reliability requirement in the low-orbit satellite can be further reduced.

Description

Technical Field

[0001] This application relates to the field of communications, specifically to an anti-latch-up circuit for a core component of a low-Earth orbit satellite. Background Technology

[0002] In today's rapidly developing space exploration and satellite technology, electronic systems must operate stably and reliably in the extremely harsh space environment. Among these, the space radiation environment is one of the main factors posing a serious threat to spacecraft electronic equipment. High-energy charged particles in space possess extremely high energy, capable of penetrating the spacecraft's outer shell and the encapsulation of electronic devices, directly interacting with semiconductor materials and triggering a series of radiation effects, among which single-event effects (SEEs) are crucial. SEEs refer to the phenomenon where a single high-energy particle, passing through a sensitive area of ​​a microelectronic device, deposits energy through ionization, causing a transient or permanent change in the device's state. Its manifestations are diverse, including soft errors (such as memory bit flips), transient pulses, burnout, and single-event latch-up. SELs (Self-Impact Transformers) are a potentially devastating hardware failure, particularly prone to occur in devices manufactured using bulk silicon processes, such as complementary metal-oxide-semiconductor (CMOS) devices and bipolar junction transistors (BJTs), which internally or directly constitute a PNPN four-layer structure. The typical process structure of CMOS integrated circuits, under parasitic effects, naturally forms a parasitic silicon-controlled rectifier structure composed of vertical NPN and lateral PNP bipolar transistor interconnects. Under normal operating conditions, this parasitic SCR is in a high-resistance off state and has no effect on circuit function. However, when a high-energy single particle (such as a heavy ion or a high-energy proton) is incident on the device substrate or well region (N-well or P-well), it generates a large number of electron-hole pairs through ionization along the incident path. These excess carriers will rapidly separate (drift) under the influence of an electric field and diffuse in all directions driven by the concentration gradient. Some of the holes (minority carriers in N-type substrates or N-wells) may be collected by the adjacent P+ diffusion region (such as P-type source / drain regions). This collection process is equivalent to injecting current into the base region of the parasitic PNP transistor. When this injected current flows through the bulk resistance of the substrate or well, it will generate a significant local voltage drop. If this voltage drop is large enough to forward bias the emitter junction of another parasitic NPN transistor (e.g., forward biasing the junction between the N-well and the P-substrate), it will trigger the NPN transistor to turn on. The conduction of the NPN transistor provides a greater base drive for the PNP transistor, forming a strong positive feedback loop. Once the feedback gain is greater than 1, the parasitic SCR quickly enters a low-resistance conduction state, i.e., "latch-up" occurs. At this time, a low-resistance path that is almost a direct short circuit is formed between the power supply and ground of the device, causing the power supply current to increase sharply, which is only limited by the current limiting capability of the external power supply circuit and the parasitic resistance of the path.

[0003] Once latch-up is established, it can be self-sustaining, even after the single-event transient current that initially triggered it has disappeared. Without emergency measures (such as rapidly cutting off the power supply or drastically reducing the supply voltage), the sustained high current will cause a rapid increase in the local temperature of the device, leading to thermal runaway. In extreme cases, the accumulated heat cannot dissipate in time, and can cause metal interconnects to melt, silicon materials to melt, or the package to be damaged within a very short time (microseconds to milliseconds), ultimately resulting in permanent device burn-out and failure of the entire functional unit.

[0004] Existing technology uses current-limiting resistors. When the current increases, the voltage of the test device decreases accordingly, which can protect the device from being burned out before it self-heals. The disadvantage is that the voltage fluctuates with the load of the test device, which can easily cause abnormal device operation. Summary of the Invention

[0005] The purpose of this application is to overcome the shortcomings of the prior art and provide an anti-latch-up circuit for core components of low-Earth orbit satellites. This circuit has almost no voltage fluctuations and its impact on the operating state of the devices is negligible. It can further reduce the operational and failure risks of modules with high reliability requirements in low-Earth orbit satellites.

[0006] The objective of this application is achieved through the following technical solution:

[0007] This application discloses an anti-latch-up circuit for a core component of a low-Earth orbit satellite, comprising:

[0008] Switching power supply, device under test;

[0009] In addition, there are load, control module, current detection chip, main control MCU, and ADC module;

[0010] The load is connected to the device under test, and the current detection chip is used to detect the real-time current of the load and convert it into a digital signal through the ADC module and transmit it to the main control MCU.

[0011] The main control MCU determines whether the current flowing through the load exceeds a safety threshold based on the digital signal. If the current exceeds the safety threshold, the main control MCU outputs a control signal to the control module.

[0012] The control module is connected in the branch connecting the load and the device under test, and adjusts the current flowing through the load based on the control signal to keep it within a safe threshold.

[0013] Once the load current returns to a safe threshold, the main control MCU controls the control module to gradually exit and the switching power supply resumes power.

[0014] In this application, the current is monitored and sampled in real time. During latch-up, the voltage drops to a certain value and the current is maintained. When the latch-up is restored, the circuit still maintains a constant current state. At this time, the duty cycle rises and the voltage rises until it rises to the normal operating voltage and the constant current is released (Note: If the constant current is not released, the voltage at this moment will definitely exceed the normal operating voltage after the circuit is restored).

[0015] Furthermore, when the control module is always in a constant current state, the main control MCU controls the switching power supply to shut down. In extreme cases where particles cause permanent and irreversible damage to the device, the load is almost in a short-circuit state. When the controller is always in a constant current state, the MCU considers the encountered latch-up state to be irreversible and promptly cuts off the power to prevent the abnormal state from affecting the function or judgment logic of other components.

[0016] Furthermore, the main control MCU is equipped with a dedicated instruction interface for shutting down the switching power supply.

[0017] Furthermore, the safety threshold is no more than 80% of the avalanche breakdown current of the PN junction of the device under test.

[0018] Furthermore, the load is less than 1Ω.

[0019] Furthermore, the control signal is a PWM waveform signal with a certain duty cycle, and the control module adjusts the current flowing through the load based on the current represented by the PWM waveform signal.

[0020] Furthermore, the relationship between the duty cycle of the PWM waveform signal and the load is as follows: Among them, the power supply voltage V0, duty cycle μ, switching loss n, load R, and safe current value I0 are all considered. When latch-up occurs, R decreases, and in order to keep I0 constant, the duty cycle μ also needs to be adjusted down.

[0021] Furthermore, the control module is a programmable resistor, which adjusts the current flowing through the load.

[0022] Furthermore, the control module is a MOSFET, which is connected between the load and the device under test through its source terminal S and drain terminal D, and the current flowing through the load is adjusted by controlling the voltage between its gate terminal G and source terminal S.

[0023] Furthermore, the control module power transistor controls the base current of the power transistor to regulate the current flowing through the load.

[0024] The beneficial effects of this application are:

[0025] This application can employ different processing mechanisms depending on the degree of impact, resulting in enhanced performance. Compared to existing technologies, it uses a load of less than 1Ω, exhibiting virtually no voltage fluctuations in response to dynamic changes in the load of the device under test, and its impact on the device's operating state is negligible. In the event of catastrophic damage, this power supply can be cut off, reducing the impact on surrounding components. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the architecture of this application;

[0027] Figure 2 This is a circuit architecture diagram of an embodiment of this application. Detailed Implementation

[0028] The technical solution of this application is described in further detail below with reference to specific embodiments, but the scope of protection of this application is not limited to the following description.

[0029] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0030] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0031] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0032] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0034] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0035] See Figure 1 , Figure 1This application illustrates an anti-latch-up circuit for a core component of a low-Earth orbit satellite, comprising: a switching power supply, a device under test (DUT) and a load, a control module, a current detection chip, a main control MCU, and an ADC module. The load is connected to the DUT. The current detection chip detects the real-time current of the load and converts it into a digital signal via the ADC module, which is then transmitted to the main control MCU. The main control MCU determines whether the current flowing through the load exceeds a safety threshold based on the digital signal. If the current exceeds the safety threshold, the main control MCU outputs a control signal to the control module. The control module is connected in the branch connecting the load and the DUT, and adjusts the current flowing through the load based on the control signal to keep it within the safety threshold. When the load current returns to the safety threshold, the main control MCU controls the control module to gradually deactivate, and the switching power supply resumes power. In this application, the current is monitored and sampled in real time. During latch-up, the voltage drops to a certain value, and the current remains constant. When the latch-up recovers, the circuit maintains a constant current state. At this time, the duty cycle recovers, and the voltage rises until it reaches the normal operating voltage, at which point the constant current is released (Note: If the constant current is not released, the voltage at this moment will definitely exceed the normal operating voltage after the circuit recovers).

[0036] Furthermore, in a preferred embodiment, a latch-up protection circuit for a low-Earth orbit satellite core component ensures that the main control MCU controls the switching power supply to shut down when the control module is always in a constant current state. The main control MCU has a dedicated instruction interface for shutting down the switching power supply.

[0037] In a preferred embodiment, a latch-up protection circuit for a low-Earth orbit satellite core component has a safety threshold of no more than 80% of the avalanche breakdown current of the PN junction of the device under test.

[0038] In a preferred embodiment, a latch-up protection circuit for a low-Earth orbit satellite core component has a load of less than 1Ω.

[0039] In a preferred embodiment, an anti-latch-up circuit for a low-Earth orbit satellite core component uses a PWM waveform signal with a certain duty cycle as the control signal. The control module adjusts the current flowing through the load based on the current represented by the PWM waveform signal. The relationship between the PWM waveform signal duty cycle and the load is as follows: Among them, the power supply voltage V0, duty cycle μ, switching loss n (specifically referring to the switching loss of the switching power supply), load R, and safe current value I0 are all considered. When latch-up occurs, R decreases, and in order to keep I0 constant, the duty cycle μ also needs to be adjusted downward.

[0040] In a preferred embodiment, a latch-up protection circuit for a low-Earth orbit satellite core component includes a programmable resistor as the control module, which adjusts the current flowing through the load.

[0041] In a preferred embodiment, an anti-latch-up circuit for a core component of a low-Earth orbit satellite uses a MOSFET as its control module. The MOSFET is connected between the load and the device under test (DUT) via its source (S) and drain (D). The current flowing through the load is adjusted by controlling the voltage between its gate (G) and source (S). This embodiment uses an N-channel power MOSFET as the core control module. Its source (S) is connected to the system power supply, and its drain (D) is connected in series in the positive power supply path of the DUT (e.g., a CMOS chip). The load is the DUT itself. The circuit precisely controls the V_GS voltage based on a PWM signal from the main control MCU via a gate drive circuit connected between the MOSFET's gate (G) and source (S). Under normal conditions, the MOSFET operates in a low-resistance state within the variable resistance region, resulting in a higher V_GS voltage, minimizing the voltage drop from the power supply to the load. When the current detection unit detects a sudden increase in latch-up current caused by a single-particle incident event, the MCU immediately and dynamically reduces the duty cycle of the PWM signal, thereby reducing the applied V_GS voltage. This causes the MOSFET to quickly enter or approach its saturation region, increasing its equivalent resistance and forcibly limiting the current flowing through the load to below a preset safe value. This suppresses the positive feedback process of the parasitic PNPN structure and avoids thermal runaway. This dynamic current limiting mechanism creates conditions for the self-recovery of latch-up. After the fault is cleared, the MCU can gradually restore the PWM duty cycle, causing V_GS to rise and the system to return to normal power supply, thus achieving active and recoverable protection for core components under irradiation conditions.

[0042] In a preferred embodiment, a latch-up protection circuit for a core component of a low-Earth orbit satellite controls a power transistor in the control module to regulate the current flowing through the load by controlling the base current of the power transistor.

[0043] refer to Figure 2 In one specific embodiment shown, the switching power supply adopts a Power Controller + DrMOS collaborative working mode. This is a classic controller-actuator architecture and a standard solution for modern high-performance, high-density DC-DC power supplies (especially multi-phase voltage regulation modules powering large chips such as CPUs, GPUs, and FPGAs). The current value of R is monitored in real time by a current sensing chip, sampled by an ADC, and sent to the MCU. When excessive current in R is detected, the MCU outputs a PWM waveform with a certain duty cycle to the controller (i.e., the control module) to ensure that the current in R remains within a safe current range. Upon detection of latch-up recovery, the power supply is gradually restored via the control module. In the event of irreversible damage or even complete failure, the main control MCU controls the Power Controller + DrMOS to power down via the I2C interface to prevent damage to other functional components. The current sensing chip is a general-purpose chip, model IN226.

[0044] This embodiment designs a single-event latch-up protection scheme based on real-time monitoring and intelligent response for the core voltage of the onboard data processing unit. The specific implementation process begins with continuous, real-time measurement of the power supply path current using a high-bandwidth, high-precision zero-resistance current detection chip. This detection signal is digitized by a high-speed ADC module configured with a 1MSPS sampling rate and then continuously sent to the main control MCU, which serves as the control center, for analysis and judgment. When the MCU's algorithm logic, through a fast interrupt service routine, identifies that the current sample value exceeds a preset first-level safety threshold, it means that a single-event latch-up may have been triggered. When the latch-up effect causes a sudden surge in current, the MCU immediately intervenes in the control loop, outputting a PWM waveform with a specific duty cycle from its built-in timer pin. This PWM signal, after being amplified by the gate driver, is applied to the power MOSFET control module connected in series on the main power supply path. By dynamically and frequently adjusting the duty cycle of this PWM, a fast closed-loop feedback control is formed, thereby forcibly clamping and limiting the current flowing through the vulnerable load R within a preset safe current range. The core purpose of this dynamic current limiting state is to provide a valuable self-recovery time window for potential latch-up of the parasitic PNPN structure caused by single-event effects. To avoid irreversible temperature rise and burnout due to excessive current, the system synchronously initiates a fine-grained state diagnosis phase after entering the current-limiting state. The MCU's background task continuously analyzes the steady-state relationship between current and PWM duty cycle. If it detects that the PWM duty cycle required to maintain safe current is continuously and stably decreasing and the current ripple tends to be stable, the algorithm determines that the positive feedback loop of the parasitic silicon controlled rectifier has been broken and the latch-up state has been restored. Subsequently, the control module will execute a pre-programmed gradual recovery program, slowly and linearly increasing the PWM duty cycle over a timescale of milliseconds until it reaches a 100% fully on state, allowing the power supply to resume operation. The system should smoothly recover to the normal voltage level, achieving seamless self-healing of system functions and maximizing task continuity. Conversely, if the status diagnosis algorithm finds that the current cannot be effectively limited or continues to exceed a higher secondary catastrophic threshold, or if the duty cycle required to maintain current limiting is at an extremely high level for a long time, the MCU logic determines that the latch-up event has caused irreversible hardware damage or formed a permanent short circuit. At this time, the system immediately upgrades its response strategy. The MCU first sets the PWM duty cycle of the control MOSFET to zero to achieve local shutdown, and then sends a series of predefined shutdown commands to the intelligent power module based on the Power Controller and DrMOS architecture that supplies power to this circuit through the standard I2C digital communication interface. The commands sequentially disable its PWM output and pull down the enable signal, thereby performing a thorough and rapid power-down operation on the faulty power domain from the source. This precise isolation mechanism effectively prevents the spread of fault current in the power network and avoids the impact of latch-up failure of a single branch on other key functional components powered by the common bus, ensuring the overall functional safety and survivability of the system.This complete solution, through a closed-loop logic of "high-speed monitoring - dynamic current limiting - intelligent diagnosis - gradual recovery / complete isolation," upgrades traditional simple overcurrent protection or one-time fuse blowing into an intelligent power health management system with graded response capabilities. It not only prevents catastrophic thermoelectric failures that could be caused by latch-up through real-time intervention, but more importantly, it significantly improves the probability of the system autonomously recovering from transient radiated interference by creating a "current limiting and survival" window. Furthermore, it can achieve graceful fault containment through digital power interfaces when facing permanent damage. Ultimately, in the harsh space radiation environment, it builds a crucial layer of system-level resilience on top of device-level reliability, achieving a leap from passive protection to active management and adaptation. This has significant engineering application value for improving the on-orbit mission success rate and survivability of long-life, high-reliability spacecraft. Moreover, thanks to its software-configurable parameters and logic, this architecture can flexibly adapt to different current thresholds, response times, and recovery strategies, providing a universal protection framework for diverse aerospace electronic loads.

[0045] This embodiment employs a current sensing chip and an ADC for real-time, high-precision current sampling, enabling immediate capture of sudden current surges in the μs or even nanosecond range during latch-up triggering. The MCU's rapid judgment and PWM output allow intervention before the device's temperature rises to a destructive level, forcibly pulling the power device (R)'s operating point back to a safe zone by limiting the current. This effectively prevents instantaneous device burnout due to heat accumulation, transforming a potentially catastrophic hardware failure into a controllable transient event. Secondly, the core control strategy of this solution is not a simple detection-shutdown, but rather a closed-loop dynamic current limiting using a PWM output with a specific duty cycle. This suppresses the current within a safe range when overcurrent occurs, while maintaining power supply or function to the load as much as possible. When latch-up is caused by a transient single-event effect and does not cause hardware damage, this mechanism creates conditions for the self-recovery of the latch-up state. After the MCU recognizes the recovery, it gradually restores normal power supply, achieving "seamless" self-healing of the system. This greatly reduces unnecessary main power cycle cycles or system restarts, which is crucial for aerospace missions requiring high continuity. The solution employs a clear hierarchical fault response logic: Level 1 Response (Regulation): For recoverable transient overcurrents, PWM current limiting is used. Level 2 Response (Shutdown): When irreversible damage is detected (e.g., continuous overcurrent indicating unrecoverable latch-up or device failure), the MCU controls the upstream PowerController+DrMOS architecture via I2C commands to perform a thorough and rapid partial power-down. This hierarchical strategy achieves precise fault isolation, strictly controlling the impact of failures to a minimum (e.g., a single power supply branch), preventing the fault from spreading to other critical functional components on the same power network, and effectively ensuring the functional safety of the entire system and the survival of core functions. This solution cleverly utilizes the digital management interface inherent in modern high-performance power systems (Power Controller+DrMOS). Through I2C communication, the MCU can perform global power management in the form of high-level commands, making power-down control more reliable and thorough, and easy to integrate with other system health management functions. This reflects a system-level design philosophy, integrating discrete protection, power management, and the main control unit into a unified intelligent power health management system.

[0046] The above description is merely a preferred embodiment of this application. It should be understood that this application is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this application should be within the protection scope of the appended claims.

Claims

1. A latch-up protection circuit for a core component of a low-Earth orbit satellite, characterized in that, include: Switching power supply, device under test; In addition, there are load, control module, current detection chip, main control MCU, and ADC module; The load is connected to the device under test, and the current detection chip is used to detect the real-time current of the load and convert it into a digital signal through the ADC module and transmit it to the main control MCU. The main control MCU determines whether the current flowing through the load exceeds a safety threshold based on the digital signal. If the current exceeds the safety threshold, the main control MCU outputs a control signal to the control module. The control module is connected in the branch connecting the load and the device under test, and adjusts the current flowing through the load based on the control signal to keep it within a safe threshold. Once the load current returns to a safe threshold, the main control MCU controls the control module to gradually exit and the switching power supply resumes power.

2. The anti-latch-up circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, When the control module is always in a constant current state, the main control MCU controls the switching power supply to turn off.

3. The anti-latch-up circuit for a low-Earth orbit satellite core component according to claim 2, characterized in that, The main control MCU is equipped with a dedicated instruction interface for shutting down the switching power supply.

4. The anti-latch-up circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, The safety threshold is no more than 80% of the avalanche breakdown current of the PN junction of the device under test.

5. The anti-latch-up circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, The load is less than 1Ω.

6. The anti-latch-up circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, The control signal is a PWM waveform signal with a certain duty cycle. The control module adjusts the current flowing through the load based on the current represented by the PWM waveform signal.

7. A latch-up protection circuit for a low-Earth orbit satellite core component according to claim 6, characterized in that, The relationship between the duty cycle of the PWM waveform signal and the load is as follows: Among them, the power supply voltage V0, duty cycle μ, switching loss n, load R, and safe current value I0 are all considered. When latch-up occurs, R decreases, and in order to keep I0 constant, the duty cycle μ also needs to be adjusted downward.

8. The anti-latch-up circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, The control module is a programmable resistor, which adjusts the current flowing through the load.

9. A latch-up protection circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, The control module is a MOSFET, which is connected between the load and the device under test through its source terminal S and drain terminal D. The current flowing through the load is adjusted by controlling the voltage between its gate terminal G and source terminal S.

10. A latch-up protection circuit for a low-Earth orbit satellite core component according to claim 1, characterized in that, The control module uses a power transistor to regulate the current flowing through the load by controlling the base current of the power transistor.

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