Sampling circuit, current sharing circuit and multi-phase power supply

Abstract

The invention provides a sampling circuit, a current sharing circuit and a multi-phase power supply, and the sampling circuit comprises a sampling unit which comprises a first sampling tube and a second sampling tube which are connected in series, an intermediate node between the first sampling tube and the second sampling tube is connected with a switching node through a third sampling tube, a first voltage signal is obtained according to the voltage of the switching node, and a second voltage signal is obtained according to the voltage of the switching node; obtaining a second voltage signal according to the voltage of the intermediate node; the extraction unit is used for carrying out difference processing on the first voltage signal and the second voltage signal so as to obtain a sampling voltage representing the average value of the inductive current; when the freewheeling tube is conducted, the third sampling tube controls the voltage of the intermediate node to be the voltage of the switching node, so that the on-resistance of the freewheeling tube is offset through difference operation. According to the sampling circuit, the third sampling tube is arranged and the on-off of the third sampling tube is used for eliminating the on-resistance information of the follow current tube contained in the sampling voltage, so that the on-resistance of the follow current tube does not influence the sampling result any more, and the sampling precision is improved.

Description

Technical Field

[0001] This invention belongs to the field of switching power supplies, specifically relating to a sampling circuit, a current sharing circuit, and a multiphase power supply. Background Technology

[0002] Single-phase converters generate significant output voltage and inductor current ripple when producing output current, leading to reduced efficiency and severe chip overheating. Therefore, current power supply chips are developing towards higher frequency, multi-phase, and lower power consumption.

[0003] With the development of integrated circuits and processes, multiphase power supply chips have made significant progress and demonstrated great advantages and potential in many aspects. In multiphase converters, the switching actions of each phase circuit are staggered, and when the output current is constant, it is evenly distributed across all phase circuits to reduce output voltage ripple and inductor current ripple, minimize switching losses, and improve conversion efficiency. However, during operation, due to the influence of parasitic parameters, heat dissipation conditions, and switching device characteristics of different phase circuits, the inductor current distribution in each phase circuit may become unbalanced. This not only reduces system efficiency but may also lead to overload in some phases, thus affecting system stability and reliability. Therefore, current sharing control technology has become a key technology for multiphase power supplies.

[0004] It is evident that current sampling accuracy is crucial in current sharing techniques, directly impacting the accuracy and reliability of the current sharing effect. Therefore, improving the sampling accuracy of the current sampling circuit is a key issue that requires close attention. Summary of the Invention

[0005] To address the technical problems of insufficient current sampling accuracy and unbalanced currents in phase circuits of multiphase power supplies in existing technologies, this invention proposes a sampling circuit, a current sharing circuit, and a multiphase power supply. The connection point between the main power transistor and the freewheeling transistor in the switching power supply is the switching node. The sampling circuit includes:

[0006] The sampling unit includes a first sampling tube and a second sampling tube connected in series. The intermediate node between the first sampling tube and the second sampling tube is connected to a switching node through a third sampling tube. A first voltage signal is obtained based on the voltage of the switching node, and a second voltage signal is obtained based on the voltage of the intermediate node.

[0007] The extraction unit performs difference processing on the first voltage signal and the second voltage signal to obtain a sampled voltage that characterizes the average value of the inductor current.

[0008] When the freewheeling diode is turned on, the third sampling diode controls the voltage of the intermediate node to be the voltage of the switching node, so that the on-resistance of the freewheeling diode is canceled out through difference calculation.

[0009] Furthermore, the first voltage signal includes the load current and the on-resistance of the freewheeling diode, and the second voltage signal includes the load current and the on-resistance of the freewheeling diode.

[0010] The extraction unit converts the first voltage signal and the second voltage signal into current signals respectively, and performs a difference operation on the current signals to extract the load current.

[0011] Furthermore, the sampling voltage is proportional to the load current, and the proportionality coefficient includes the on-resistance of the main power transistor.

[0012] Furthermore, the main power transistor and the freewheeling transistor are connected between the first node and the second node, and the first sampling transistor and the second sampling transistor are connected in series between the first node and the second node.

[0013] Furthermore, the first sampling tube and the main power tube are switched on and off synchronously, as are the second sampling tube, the third sampling tube, and the freewheeling tube.

[0014] Preferably, the extraction unit includes:

[0015] A first transistor and a second transistor, with their first terminals connected by a first resistor. The gate of the first transistor receives a first voltage signal, and the gate of the second transistor receives a second voltage signal. Equal bias currents flow into the first terminals of both transistors.

[0016] The third, fourth, and fifth transistors are connected at their first terminals and at their second terminals, respectively. The third transistor replicates the current of the first transistor, the fourth transistor replicates the current of the second transistor, and the current flowing through the fifth transistor represents the load current.

[0017] Preferably, the extraction unit further includes a second resistor, the current flowing through the first resistor is the current flowing through the fifth transistor, and the voltage of the second resistor is the sampling voltage.

[0018] Furthermore, the sampling unit also includes a filtering circuit, which filters the voltage of the switching node to obtain a first voltage signal and filters the voltage of the intermediate node to obtain a second voltage signal.

[0019] A current sharing circuit for a multiphase power supply, the multiphase power supply comprising a main phase circuit and N slave phase circuits, where N is a positive integer, and the current sharing circuit comprising N+1 sampling circuits as described above.

[0020] One of the sampling circuits is the main phase sampling circuit, which is connected to the main phase circuit and is used to obtain the main phase sampling voltage that characterizes the average inductor current of the main phase circuit.

[0021] The remaining N sampling circuits are slave phase sampling circuits, which are connected to the N slave phase circuits respectively, and are used to obtain the slave phase sampling voltage that characterizes the average value of the inductor current of the slave phase circuit.

[0022] Furthermore, it also includes:

[0023] N conversion circuits are connected to N slave phase sampling circuits respectively. The i-th conversion circuit receives the main phase sampling voltage and the slave phase sampling voltage of the i-th slave phase circuit to output a first current and a second current.

[0024] N reference circuits are connected to N conversion circuits respectively. The i-th reference circuit adjusts the preset voltage according to the first current and the second current to output the reference voltage.

[0025] The control circuit controls the duty cycle of the i-th slave phase circuit based on the output feedback voltage and the reference voltage of the i-th slave phase circuit, so that the inductor current of the i-th slave phase circuit follows the inductor current of the master phase circuit.

[0026] Here, the first current and the second current both represent the difference between the sampling voltage of the main phase and the sampling voltage of the slave phase, and i is any integer between 1 and N.

[0027] Preferably, the reference circuit includes a voltage-regulating resistor, and the first current, the second current, and the voltage-regulating resistor form a current loop. The preset voltage is adjusted according to the voltage difference of the voltage-regulating resistor.

[0028] The first current and the second current are equal in magnitude but opposite in direction.

[0029] Preferably, the preset voltage is generated by a current source and a resistor connected in series, wherein the potential at one end of the voltage regulating resistor is the preset voltage and the potential reference voltage at the other end is the voltage reference voltage.

[0030] Preferably, the conversion circuit includes:

[0031] The conversion unit converts the main phase sampling voltage into a main phase current signal and the slave phase sampling voltage into a slave phase current signal;

[0032] The first processing unit copies the main phase current signal and the slave phase current signal, and performs calculations on the copied current signal to output the first current;

[0033] The second processing unit copies the main phase current signal and the slave phase current signal, and performs calculations on the copied current signal to output the second current.

[0034] Preferably, the conversion unit includes:

[0035] The sixth transistor and the seventh transistor are connected by a third resistor. The gate of the sixth transistor receives the main phase sampling voltage, and the gate of the seventh transistor receives the slave phase sampling voltage. Equal bias currents flow into the first terminals of the sixth transistor and the seventh transistor.

[0036] Preferably, the first processing unit includes an eighth transistor, a ninth transistor, and a tenth transistor. The first terminals of the eighth transistor and the tenth transistor are connected together, and the second terminals of the eighth transistor and the tenth transistor are connected to the first terminal of the ninth transistor. The eighth transistor replicates the current of the sixth transistor, and the ninth transistor replicates the current of the seventh transistor.

[0037] Preferably, the second processing unit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The first terminals of the eleventh transistor and the thirteenth transistor are connected together, and the second terminals of the eleventh transistor and the thirteenth transistor are connected to the first terminal of the twelfth transistor. The eleventh transistor replicates the current of the seventh transistor, and the twelfth transistor replicates the current of the sixth transistor.

[0038] Preferably, when the sampling voltage of the i-th slave phase circuit is greater than the sampling voltage of the master phase, the reference voltage is less than the preset voltage, and the control circuit controls the duty cycle of the i-th slave phase circuit to decrease; when the sampling voltage of the i-th slave phase circuit is less than the sampling voltage of the master phase, the reference voltage is greater than the preset voltage, and the control circuit controls the duty cycle of the i-th slave phase circuit to increase.

[0039] Preferably, the control circuit uses an error operational amplifier to obtain a compensation voltage from the output feedback voltage and the reference voltage, and controls the duty cycle of the slave phase circuit based on the compensation voltage and the output feedback voltage.

[0040] A multiphase power supply, including the current sharing circuit described above.

[0041] This invention eliminates the on-resistance information of the freewheeling diode included in the sampled voltage by designing the third sampling transistor and its switching. Therefore, the on-resistance of the freewheeling diode no longer affects the numerical fluctuation of the sampled voltage, improving the sampling accuracy of the sampling circuit. By eliminating the influence of the freewheeling diode's on-resistance, the sampling circuit becomes less sensitive to changes in the selection of the freewheeling diode and operating conditions, thereby improving the system's adaptability and robustness. Simultaneously, in this invention, the difference between the main phase sampling voltage Vcs_main and the slave phase sampling voltage Vcs_slave is converted into a first current IN and a second current IP of equal magnitude but opposite direction. This ensures that when the first current IN, the second current IP, and the voltage regulating resistor Rs form a current loop, it will not interfere with the preset voltage Vth, thus guaranteeing the accuracy of the reference voltage Vref and ensuring that the inductor current of the slave phase circuit accurately follows the inductor current of the main phase circuit. Attached Figure Description

[0042] Figure 1 and Figure 2 This is a block diagram of the sampling circuit.

[0043] Figure 3 The specific circuit structure of the sampling unit;

[0044] Figure 4 The specific circuit structure diagram of the extraction unit;

[0045] Figure 5 This is a block diagram of the current sharing circuit.

[0046] Figure 6 A more detailed block diagram of the conversion circuit;

[0047] Figure 7 The specific circuit diagram for the conversion circuit;

[0048] Figure 8 and Figure 9 This is a partial circuit diagram of the control circuit. Detailed Implementation

[0049] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0050] To improve sampling accuracy, our company has proposed a current sampling circuit, as detailed in patent CN117269582A. The final output inductor current sampling signal Vsense of this current sampling circuit is: Vsense=K×IL1×[RQ1×D+RQ2×(1-D)]. Where K is the amplification factor of the error amplifier and is a positive number, RQ1 is the on-resistance of the main power transistor Q1, and RQ2 is the on-resistance of the synchronous rectifier transistor Q2.

[0051] Materials, manufacturing processes, and temperature all affect the on-resistance of the power transistor, which in turn affects the sampling accuracy. Therefore, there is still room for improvement in the sampling accuracy of the aforementioned current sampling circuit. Based on how to further improve the sampling accuracy of existing current sampling circuits, this invention proposes a sampling circuit for a switching power supply, such as... Figure 1 and Figure 2 As shown, the sampling circuit includes:

[0052] The sampling unit includes a first sampling tube and a second sampling tube connected in series. The intermediate node between the first sampling tube and the second sampling tube is connected to a switching node through a third sampling tube. A first voltage signal is obtained based on the voltage of the switching node, and a second voltage signal is obtained based on the voltage of the intermediate node.

[0053] The extraction unit performs difference processing on the first voltage signal and the second voltage signal to obtain the sampling voltage of the average value of the inductor current;

[0054] In this configuration, the main power transistor and the freewheeling transistor are connected between the first node and the second node, and the first sampling transistor and the second sampling transistor are also connected between the first node and the second node. The first sampling transistor and the main power transistor are switched on and off synchronously, as are the second sampling transistor, the third sampling transistor, and the freewheeling transistor.

[0055] When the freewheeling diode is turned on, the voltage of the switching node is affected by the on-resistance of the freewheeling diode. When the freewheeling diode is turned on, the voltage of the intermediate node will be pulled up to the voltage of the switching node. Therefore, the on-resistance of the freewheeling diode will eventually be canceled out by the difference operation, so that the output sampling voltage is not affected by the on-resistance of the freewheeling diode.

[0056] In summary, this invention eliminates the on-resistance information of the freewheeling diode included in the sampled voltage by designing the third sampling transistor and its switching on / off state. Therefore, the on-resistance of the freewheeling diode no longer affects the numerical fluctuation of the sampled voltage, thus improving the sampling accuracy of the sampling circuit. By eliminating the influence of the freewheeling diode's on-resistance, the sampling circuit becomes less sensitive to changes in the selection of the freewheeling diode and operating conditions, thereby improving the system's adaptability and robustness.

[0057] Specifically, taking a switching power supply as a step-down converter as an example, such as... Figure 3 As shown, the first sampling transistor M1 and the second sampling transistor M2 are connected in series between Vin and the ground terminal. The first end of the third sampling transistor M3 is connected to the intermediate node SW2, and the second end of the third sampling transistor M3 is connected to the switching node SW1. The switching node SW1 is connected to a first RC circuit, which filters the voltage of the switching node SW1 to obtain the average voltage of the switching node SW1, which is the first voltage signal V1. The intermediate node SW2 is connected to a second RC circuit, which filters the voltage of the intermediate node SW2 to obtain the average voltage of the intermediate node SW2, which is the second voltage signal V2. Among them, the first sampling transistor M1 and the main power transistor Q1 are both P-type MOSFETs, while the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2 are all N-type MOSFETs. The first sampling transistor M1 and the main power transistor Q1 are switched on and off synchronously, as are the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2.

[0058] When the main power transistor Q1 and the first sampling transistor M1 are turned on, and the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2 are turned off, the voltage at the intermediate node SW2 is VSW2 = Vin, and the voltage at the switching node SW1 is VSW1 = Vin - Iload * Ron1, where Iload is the load current and Ron1 is the on-resistance of the main power transistor Q1. When the main power transistor Q1 and the first sampling transistor M1 are turned off, and the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2 are turned on, the voltage at the intermediate node SW2 and the voltage at the switching node SW1 are equal, VSW1 = VSW2 = -Iload * Ron2, where Iload is the load current and Ron1 is the on-resistance of the freewheeling transistor Q2. After second-order filtering, VSW1 becomes V1 = D * (Vin - Iload * Ron1) + (1 - D) * (-Iload * Ron2). After second-order filtering, VSW2 is obtained as V2=D*Vin+(1-D)*(-Iload*Ron2).

[0059] Clearly, the first voltage signal V1 is less than the second voltage signal V2. The extraction unit performs a difference calculation on the first voltage signal V1 and the second voltage signal V2, yielding: V2 - V1 = D * Iload * Ron1. Therefore, by connecting the third sampling transistor M1 to the switching node SW1 and the intermediate node SW2, the voltage at the intermediate node SW2 is made equal to the voltage at the switching node SW1 during the freewheeling phase. This allows the on-resistance of the freewheeling transistor to be canceled out during the difference processing, meaning the final sampled voltage does not include the on-resistance of the freewheeling transistor. Compared to existing sampling results, the sampling circuit eliminates one influencing factor, further improving sampling accuracy.

[0060] It should be noted that under most steady-state conditions, the load current in a switching power supply can be approximated as the average value of the inductor current. Similarly, when the switching power supply is a boost converter, the operating principle of the sampling circuit is as described above. Figure 2For example, the main power transistor Q1 and the freewheeling transistor Q2 are connected between the ground terminal and the output terminal. The first sampling transistor M1 and the second sampling transistor M2 are connected in series between the ground terminal and the output terminal. A third sampling transistor M3 is connected between the switching node and the intermediate node. The first sampling transistor M1 and the main power transistor Q1 are both P-type MOSFETs, while the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2 are all N-type MOSFETs. The first sampling transistor M1 and the main power transistor Q1 are switched on and off synchronously, as are the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2. When the main power transistor Q1 and the first sampling transistor M1 are on, and the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2 are off, the voltage VSW2 at the intermediate node SW2 is 0, and the voltage VSW1 at the switching node SW1 is 0 + Iload * Ron1, where Iload is the load current and Ron1 is the on-resistance of the main power transistor Q1. When the main power transistor Q1 and the first sampling transistor M1 are turned off, and the second sampling transistor M2, the third sampling transistor M3, and the freewheeling transistor Q2 are turned on, the voltage at the intermediate node SW2 is equal to the voltage at the switching node SW1, VSW1 = VSW2 = Vout + Iload * Ron2, where Iload is the load current and Ron1 is the on-resistance of the freewheeling transistor Q2. After second-order filtering, VSW1 yields V1 = D * Iload * Ron1 + (1 - D) * (Vout + Iload * Ron2). After second-order filtering, VSW2 yields V2 = (1 - D) * (Vout + Iload * Ron2). The extraction unit performs a difference calculation on the first voltage signal V1 and the second voltage signal V2 to obtain: V1 - V2 = D * Iload * Ron1.

[0061] Furthermore, the extraction unit converts the first voltage signal V1 into a current signal I1 and the second voltage signal V2 into a current signal I2, with the same conversion ratio. Then, the difference between the current signals I1 and I2 is calculated to offset the on-resistance of the freewheeling diode Q2 and extract the load current Iload, thereby obtaining a sampled voltage proportional to the load current. Specifically, as shown... Figure 4 As shown, the extraction unit includes:

[0062] The first transistor MOS1 and the second transistor MOS2 are connected. The source of the first transistor MOS1 is connected to the source of the second transistor MOS2 through the first resistor R1. The bias current source provides an equal bias current Ibias to the first transistor MOS1 and the second transistor MOS2. The gate of the first transistor MOS1 receives a first voltage signal V1, and the gate of the second transistor MOS2 receives a second voltage signal V2. The third transistor MOS3, the fourth transistor MOS4, and the fifth transistor MOS5 are connected. The source of the third transistor MOS3 is connected to the source of the fifth transistor MOS5, and the drains of the third transistor MOS3 and the fifth transistor MOS5 are connected to the source of the fourth transistor MOS4. The third transistor MOS3 replicates the current flowing through the second transistor MOS2, and the fourth transistor MOS4 replicates the current flowing through the first transistor MOS1. An equal current flowing through the fifth transistor MOS5 is set to flow through the second resistor R2, thereby obtaining the sampling voltage Vsense.

[0063] Because the second voltage signal V2 is greater than the first voltage signal V1, the current direction of the first resistor R1 is from B to A, and the current magnitude is: (V2-V1) / R1=D*Iload*Ron1 / R1. Therefore, the current of the first transistor MOS1 is: Ibias+D*Iload*Ron1 / R1, and the current of the second transistor MOS2 is: Ibias-D*Iload*Ron1 / R1. Since the third transistor MOS3 replicates the current of the second transistor MOS2, and the fourth transistor MOS4 replicates the current of the first transistor MOS1, the current of the fifth transistor is: (Ibias+D*Iload*Ron1 / R1)-(Ibias-D*Iload*Ron1 / R1)=2*D*Iload*Ron1 / R1. Therefore, Vsense=2*D*Iload*Ron1 / R1*R2. Let the resistance of R2 be k times the resistance of R1, then Vsense=2*D*Iload*Ron1*k. Therefore, it can be seen that the extraction circuit ultimately extracts the information of the load current.

[0064] In summary, the sampling circuit proposed in this invention avoids the influence of the freewheeling diode's on-resistance on the sampling results compared to existing technologies, thereby further improving sampling accuracy.

[0065] Furthermore, based on the above sampling circuit, this invention also proposes a current sharing circuit for a multiphase power supply, specifically, as follows: Figure 5 As shown, the multiphase power supply includes a master phase circuit and N slave phase circuits, where N is a positive integer. It also includes N+1 sampling circuits as described above, with one sampling circuit serving as the master phase sampling circuit and the remaining N sampling circuits serving as slave phase sampling circuits.

[0066] The main phase sampling circuit is connected to the main phase circuit and is used to obtain the main phase sampling voltage, which characterizes the average inductor current of the main phase circuit.

[0067] N slave-phase sampling circuits are connected one-to-one with N slave-phase circuits to obtain the slave-phase sampling voltage, which characterizes the average inductor current of the slave-phase circuit.

[0068] N conversion circuits are connected one-to-one with N slave phase sampling circuits. The i-th conversion circuit receives the main phase sampling voltage and the slave phase sampling voltage of the i-th slave phase circuit to output the first current and the second current.

[0069] N reference circuits are connected to N conversion circuits respectively. The i-th reference circuit adjusts the preset voltage according to the first current and the second current to output the reference voltage.

[0070] The control circuit controls the duty cycle of the i-th slave phase circuit based on the output feedback voltage and the reference voltage, so that the inductor current of the i-th slave phase circuit follows the inductor current of the master phase circuit.

[0071] Wherein, the first current and the second current represent the difference between the sampling voltage of the main phase and the sampling voltage of the slave phase, and i is any integer from 1 to N.

[0072] Furthermore, such as Figure 6 As shown, the preset voltage Vth is generated by a constant current source and a resistor connected in series. In this invention, the difference between the main phase sampling voltage Vcs_main and the slave phase sampling voltage Vcs_slave is converted into a first current IN and a second current IP that are equal in magnitude and opposite in direction. In this way, when the first current IN, the second current IP and the voltage regulating resistor Rs form a current loop, they will not interfere with the preset voltage Vth, so as to ensure the accuracy of the reference voltage Vref, thereby ensuring that the inductor current of the slave phase circuit accurately follows the inductor current of the main phase circuit.

[0073] Specifically, the design principle of extracting units based on sampling units, such as Figure 6 As shown, the conversion circuit includes: a conversion unit that converts the main phase sampling voltage into a main phase current signal and the slave phase sampling voltage into a slave phase current signal; a first processing unit that copies the main phase current signal and the slave phase current signal, and performs calculations on the copied current signal to output a first current, which is the slave phase current signal minus the main phase current signal; and a second processing unit that copies the main phase current signal and the slave phase current signal, and performs calculations on the copied current signal to output a second current, which is the main phase current signal minus the slave phase current signal. Specifically, as shown... Figure 7 As shown,

[0074] The conversion unit includes a sixth transistor MOS6 and a seventh transistor MOS7. The source of the sixth transistor MOS6 and the source of the seventh transistor MOS7 are connected through a third resistor R3. The gate of the sixth transistor MOS6 receives the main phase sampling voltage Vcs_main, and the gate of the seventh transistor MOS7 receives the slave phase sampling voltage Vcs_slave. An equal bias current Ibias flows into the sixth transistor MOS6 and the seventh transistor MOS7. The first processing unit includes an eighth transistor MOS8, a ninth transistor MOS9, and a tenth transistor MOS10. The sources of the eighth transistor MOS8 and the tenth transistor MOS10 are connected, and the drains of the eighth transistor MOS8 and the tenth transistor MOS10 are connected to the source of the ninth transistor MOS9. The eighth transistor MOS8 replicates the current of the sixth transistor MOS6, and the ninth transistor MOS9 replicates the current of the seventh transistor MOS7. The second processing unit includes an eleventh transistor MOS11, a twelfth transistor MOS12, and a thirteenth transistor MOS13. The sources of the eleventh transistor MOS11 and the thirteenth transistor MOS13 are connected, and the drains of the eleventh transistor MOS11 and the thirteenth transistor MOS13 are connected to the source of the twelfth transistor MOS12. The eleventh transistor MOS11 replicates the current of the seventh transistor MOS7, and the twelfth transistor MOS12 replicates the current of the sixth transistor MOS6.

[0075] When Vcs_main > Vcs_slave, the current direction of resistor R3 is from A to B, and the current magnitude is (Vcs_main - Vcs_slave) / R3. Then the current of the sixth transistor MOS6 is Ibias - (Vcs_main - Vcs_slave) / R3, and the current of the seventh transistor MOS7 is Ibias + (Vcs_main - Vcs_slave) / R3. Therefore, the current of the tenth transistor MOS10 (i.e., the first current IN) is: [Ibias + (Vcs_master - Vcs_slave) / R3] - [Ibias - (Vcs_master - Vcs_slave) / R3] = 2*(Vcs_master - Vcs_slave) / R3; the current of the thirteenth transistor MOS13 (i.e., the second current IP) is: [Ibias - (Vcs_master - Vcs_slave) / R3] - [Ibias + (Vcs_master - Vcs_slave) / R3] = -2*(Vcs_master - Vcs_slave) / R3. At this time, the reference voltage Vref = 2*(Vcs_master - Vcs_slave) / R3*Rs + Vth.

[0076] Similarly, when Vcs_main < Vcs_slave, the current direction of resistor R3 is from B to A, and the current magnitude is (Vcs_slave - Vcs_main) / R3. Then the current of the sixth transistor MOS6 is Ibias + (Vcs_slave - Vcs_main) / R3, and the current of the seventh transistor MOS7 is Ibias - (Vcs_slave - Vcs_main) / R3. Therefore, the current of the tenth transistor MOS10 (i.e., the first current IN) is: [Ibias - (Vcs_slave - Vcs_master) / R3] - [Ibias + (Vcs_slave - Vcs_master) / R3] = -2*(Vcs_slave - Vcs_master) / R3; the current of the thirteenth transistor MOS13 (i.e., the second current IP) is: [Ibias + (Vcs_slave - Vcs_master) / R3] - [Ibias - (Vcs_slave - Vcs_master) / R3] = 2*(Vcs_slave - Vcs_master) / R3. At this time, the reference voltage Vref = Vth - [2*(Vcs_slave - Vcs_master) / R3*Rs].

[0077] When Vcs_master = Vcs_slave, the current through resistor R3 is 0, the current through the tenth transistor MOS10 (i.e., the first current IN) is 0, and the current through the thirteenth transistor MOS13 (i.e., the second current IP) is 0. At this time, Vref = Vth.

[0078] The control circuit will be based on current-mode or voltage-mode control, adjusting the duty cycle according to the reference voltage Vref and output feedback voltage Vfb corresponding to each slave phase circuit, thereby making the inductor current of the slave phase circuit follow the inductor current of the master phase circuit. For example, Figure 8 and Figure 9 As shown, in dual-voltage loop control, the error amplifier performs error amplification on the output feedback voltage and the reference voltage to obtain the compensation voltage, and then controls the duty cycle based on the output feedback voltage and the compensation voltage. Alternatively, the duty cycle can be directly controlled based on the output feedback voltage and the reference voltage.

[0079] Specifically, when Vcs_master > Vcs_slave, the reference voltage Vref increases, which increases the duty cycle of the slave circuit, thereby increasing the load current of the slave circuit to achieve master-slave current balance. When Vcs_master < Vcs_slave, the reference voltage Vref decreases, which decreases the duty cycle of the slave circuit, thereby decreasing the load current of the slave circuit to achieve master-slave current balance.

[0080] The operating principles of the master-phase sampling circuit and the slave-phase sampling circuit are as described above and will not be repeated here. It should also be noted that in the extraction unit, the fourth transistor MOS4 forms a current mirror circuit through other transistors to replicate the current of the first transistor MOS1, and the third transistor MOS3 forms a current mirror circuit through other transistors to replicate the current of the second transistor MOS2. Such current mirror circuits are conventional techniques and will not be described in detail in this invention. Similarly, the transistors in the first and second processing units replicate current as described above.

[0081] The present invention also proposes a multiphase power supply, which includes the current sharing circuit proposed above.

[0082] It should be noted that the specific implementations and corresponding illustrations provided are merely one way of describing the implementation method of the present invention, and are not intended to limit the specific structure of the implementation scheme of the present invention. Various changes or modifications can be made to these implementation schemes without departing from the principles and essence of the present invention, but all such changes and modifications fall within the protection scope of the present invention.

[0083] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0084] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A sampling circuit for a switching power supply, wherein the connection point between the main power transistor and the freewheeling transistor in the switching power supply is a switching node, characterized in that, include: The sampling unit includes a first sampling tube and a second sampling tube connected in series. The intermediate node between the first sampling tube and the second sampling tube is connected to a switching node through a third sampling tube. A first voltage signal is obtained based on the voltage of the switching node, and a second voltage signal is obtained based on the voltage of the intermediate node. The extraction unit performs difference processing on the first voltage signal and the second voltage signal to obtain a sampled voltage that characterizes the average value of the inductor current. When the freewheeling diode is turned on, the third sampling diode controls the voltage of the intermediate node to be the voltage of the switching node, so that the on-resistance of the freewheeling diode is canceled out through difference calculation.

2. The sampling circuit as described in claim 1, characterized in that, The first voltage signal includes the load current and the on-resistance of the freewheeling diode, and the second voltage signal includes the load current and the on-resistance of the freewheeling diode. The extraction unit converts the first voltage signal and the second voltage signal into current signals respectively, and performs a difference operation on the current signals to extract the load current.

3. The sampling circuit as described in claim 2, characterized in that, The sampling voltage is proportional to the load current, and the proportionality factor includes the on-resistance of the main power transistor.

4. The sampling circuit as described in claim 1, characterized in that, The main power transistor and the freewheeling transistor are connected between the first node and the second node, and the first sampling transistor and the second sampling transistor are connected in series between the first node and the second node.

5. The sampling circuit as described in claim 1, characterized in that, The first sampling tube and the main power tube are switched on and off synchronously, as are the second sampling tube, the third sampling tube, and the freewheeling tube.

6. The sampling circuit as described in claim 2, characterized in that, The extraction unit includes: A first transistor and a second transistor, with their first terminals connected by a first resistor. The gate of the first transistor receives a first voltage signal, and the gate of the second transistor receives a second voltage signal. Equal bias currents flow into the first terminals of both transistors. The third, fourth, and fifth transistors are connected at their first terminals and at their second terminals, respectively. The third transistor replicates the current of the first transistor, the fourth transistor replicates the current of the second transistor, and the current flowing through the fifth transistor represents the load current.

7. The sampling circuit as described in claim 6, characterized in that, The extraction unit also includes a second resistor, the current flowing through the first resistor is the current flowing through the fifth transistor, and the voltage of the second resistor is the sampling voltage.

8. The sampling circuit as described in claim 1, characterized in that, The sampling unit further includes a filtering circuit, which filters the voltage of the switching node to obtain a first voltage signal and filters the voltage of the intermediate node to obtain a second voltage signal.

9. A current sharing circuit for a multiphase power supply, the multiphase power supply comprising a main phase circuit and N slave phase circuits, where N is a positive integer, characterized in that, The current sharing circuit includes N+1 sampling circuits as described in any one of claims 1-8. One of the sampling circuits is the main phase sampling circuit, which is connected to the main phase circuit and is used to obtain the main phase sampling voltage that characterizes the average inductor current of the main phase circuit. The remaining N sampling circuits are slave phase sampling circuits, which are connected to the N slave phase circuits respectively, and are used to obtain the slave phase sampling voltage that characterizes the average value of the inductor current of the slave phase circuit.

10. The current sharing circuit as described in claim 9, characterized in that, Also includes: N conversion circuits are connected to N slave phase sampling circuits respectively. The i-th conversion circuit receives the main phase sampling voltage and the slave phase sampling voltage of the i-th slave phase circuit to output a first current and a second current. N reference circuits are connected to N conversion circuits respectively. The i-th reference circuit adjusts the preset voltage according to the first current and the second current to output the reference voltage. The control circuit controls the duty cycle of the i-th slave phase circuit based on the output feedback voltage and the reference voltage of the i-th slave phase circuit, so that the inductor current of the i-th slave phase circuit follows the inductor current of the master phase circuit. Here, the first current and the second current both represent the difference between the sampling voltage of the main phase and the sampling voltage of the slave phase, and i is any integer between 1 and N.

11. The current sharing circuit as described in claim 10, characterized in that, The reference circuit includes a voltage-regulating resistor. The first current, the second current, and the voltage-regulating resistor form a current loop. The preset voltage is adjusted according to the voltage difference of the voltage-regulating resistor. The first current and the second current are equal in magnitude but opposite in direction.

12. The current sharing circuit as described in claim 11, characterized in that, The preset voltage is generated by a current source and a resistor connected in series. The potential at one end of the voltage regulating resistor is the preset voltage, and the potential at the other end is the reference voltage.

13. The current sharing circuit as described in claim 10, characterized in that, The conversion circuit includes: The conversion unit converts the main phase sampling voltage into a main phase current signal and the slave phase sampling voltage into a slave phase current signal; The first processing unit copies the main phase current signal and the slave phase current signal, and performs calculations on the copied current signal to output the first current; The second processing unit copies the main phase current signal and the slave phase current signal, and performs calculations on the copied current signal to output the second current.

14. The current sharing circuit as described in claim 13, characterized in that, The conversion unit includes: The sixth transistor and the seventh transistor are connected by a third resistor. The gate of the sixth transistor receives the main phase sampling voltage, and the gate of the seventh transistor receives the slave phase sampling voltage. Equal bias currents flow into the first terminals of the sixth transistor and the seventh transistor.

15. The current sharing circuit as described in claim 14, characterized in that, The first processing unit includes an eighth transistor, a ninth transistor, and a tenth transistor. The first terminals of the eighth and tenth transistors are connected, and the second terminals of the eighth and tenth transistors are connected to the first terminal of the ninth transistor. The eighth transistor replicates the current of the sixth transistor, and the ninth transistor replicates the current of the seventh transistor.

16. The current sharing circuit as described in claim 15, characterized in that, The second processing unit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The first terminals of the eleventh and thirteenth transistors are connected, and the second terminals of the eleventh and thirteenth transistors are connected to the first terminal of the twelfth transistor. The eleventh transistor replicates the current of the seventh transistor, and the twelfth transistor replicates the current of the sixth transistor.

17. The current sharing circuit as described in claim 10, characterized in that, When the slave phase sampling voltage corresponding to the i-th slave phase circuit is greater than the master phase sampling voltage, the reference voltage is less than the preset voltage, and the control circuit controls the duty cycle of the i-th slave phase circuit to decrease. When the sampling voltage of the i-th slave phase circuit is less than the sampling voltage of the master phase, the reference voltage is greater than the preset voltage, and the control circuit controls the duty cycle of the i-th slave phase circuit to increase.

18. The current sharing circuit as described in claim 10, characterized in that, The control circuit uses an error amplifier to obtain a compensation voltage from the output feedback voltage and the reference voltage, and controls the duty cycle of the slave phase circuit based on the compensation voltage and the output feedback voltage.

19. A multiphase power supply, characterized in that, Includes the current sharing circuit as described in any one of claims 9-18.

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