H-bridge compensation circuit, power amplifier, chip and electronic equipment

Abstract

The invention relates to an H-bridge compensation circuit, a power amplifier, a chip and electronic equipment, and relates to the technical field of H-bridges. The H-bridge compensation circuit is applied to an H-bridge driving circuit, and comprises a first digital logic module which is used for outputting a first digital compensation signal according to a power supply voltage provided by a power supply end, the on-resistance difference between a first switching tube and a second switching tube, the impedance of a load, the gain of the H-bridge driving circuit and a received digital input signal; the first digital compensation signal is used for compensating a common-mode error generated by the H-bridge driving circuit due to the on-resistance difference; and the digital output module is connected with the first digital logic module, is used for being connected with the driving module, and is used for compensating the digital input signal according to the first digital compensation signal and outputting a digital output signal so as to indicate the driving module to drive the H-bridge module. The method can improve the current detection precision.

Description

Technical Field

[0001] This application relates to the field of H-bridge technology, and in particular to an H-bridge compensation circuit, power amplifier, chip, and electronic device. Background Technology

[0002] With the continuous evolution of power electronics technology, H-bridge circuits, due to their high power output and flexible control characteristics, have been widely used in scenarios with large load current requirements, such as motor drives and power conversion. In these applications, H-bridge circuits achieve precise load control through the signals output from their two half-bridges.

[0003] To prevent circuit damage caused by abnormal overload of load current, real-time monitoring of the load current is typically performed. Since the on-resistance of the switching transistors in an H-bridge circuit is not zero, and the on-resistance of the two transistors in the same half-bridge is difficult to make perfectly identical, this leads to signal asymmetry between the first and second half-bridge outputs. Furthermore, the output common-mode error varies with the input signal, resulting in a common-mode error. This causes discrepancies between the detected load current and the actual load current, severely impacting the control accuracy and operational stability of the circuit system. Summary of the Invention

[0004] This application provides an H-bridge compensation circuit, a power amplifier, a chip, and an electronic device that can compensate for common-mode errors caused by resistance differences, thereby improving current detection accuracy.

[0005] In a first aspect, this application provides an H-bridge compensation circuit applied to an H-bridge drive circuit. The H-bridge drive circuit includes an H-bridge module and a drive module. The H-bridge module includes a first half-bridge and a second half-bridge. Both the first half-bridge and the second half-bridge include a first switch and a second switch. The control terminals of the first switch and the second switch are respectively connected to the drive module. A first terminal of the first switch is connected to a power supply terminal, and a second terminal of the second switch is connected to a ground terminal. The second terminals of the first switch and the first terminals of the second switch in the same half-bridge are connected and used for connection to a load. The on-resistances of the first switch and the second switch are different. The H-bridge compensation circuit includes:

[0006] The first digital logic module is used to output a first digital compensation signal based on the power supply voltage provided by the power supply terminal, the difference in on-resistance between the first switch and the second switch, the impedance of the load, the gain of the H-bridge drive circuit, and the received digital input signal; the first digital compensation signal is used to compensate for the common-mode error generated by the H-bridge drive circuit due to the difference in on-resistance.

[0007] A digital output module, connected to the first digital logic module, is used to connect to the driving module and to compensate the digital input signal according to the first digital compensation signal, outputting a digital output signal to instruct the driving module to drive the H-bridge module.

[0008] In one embodiment, the common-mode error is the difference between the duty cycle when both the first half-bridge and the second half-bridge output a high level and the duty cycle when both output a low level.

[0009] In one embodiment, the first digital logic module includes:

[0010] The squaring unit is used to perform squaring operations based on the digital input signal and output a squaring output signal.

[0011] A product operation unit, connected to the square operation unit, is used to perform a product operation based on the squared output signal and the product coefficients, and output a product output signal; the product coefficients are respectively related to the on-resistance difference, the impedance, and the gain;

[0012] The division unit, connected to the product unit, is used to perform a division operation on the power supply voltage based on the product output signal and output the first digital compensation signal.

[0013] In one embodiment, the first digital compensation signal is positively correlated with the digital input signal, the on-resistance difference, and the gain, respectively, and negatively correlated with the impedance and the power supply voltage, respectively.

[0014] In one embodiment, the first digital compensation signal is expressed by the formula:

[0015] V comp1 =V in ^2*(R p -R n ) / R L *Gain / PVDD

[0016] Among them, V comp1 Indicates the first digital compensation signal; V in This represents the digital input signal; (R) p -R n ) represents the difference in conduction resistance, R p R represents the on-resistance of the first switching transistor. n R represents the on-resistance of the second switching transistor; L The impedance is represented by ; Gain represents the gain; and PVDD represents the power supply voltage.

[0017] In one embodiment, the digital output module includes:

[0018] The first noise shaping unit is connected to the first digital logic module and is used to perform noise shaping on the first digital compensation signal and output the first digital shaped signal.

[0019] A first digital output unit, connected to the first noise shaping unit, is used to compensate the digital input signal according to the first digital shaping signal and output the digital output signal.

[0020] In one embodiment, the H-bridge compensation circuit further includes:

[0021] The second digital logic module is configured to output a second digital compensation signal when the H-bridge driver circuit uses odd-number pulse width modulation and the digital input signal is odd; the second digital compensation signal is used to compensate for the common-mode noise generated by the H-bridge driver circuit due to the digital input signal; wherein...

[0022] The digital output module is also connected to the second digital logic module and is used to compensate the digital input signal according to the first digital compensation signal and the second digital compensation signal, and output the digital output signal.

[0023] In one embodiment, the second digital logic module includes:

[0024] The enable submodule is used to output an enable signal when the received digital mode signal is a preset first reference value; the digital mode signal is used to represent the pulse width modulation mode of the H-bridge drive circuit.

[0025] The identification submodule is used to identify the parity of the digital input signal and output the second digital compensation signal when the digital input signal is odd.

[0026] The output submodule is connected to the enable submodule and the identification submodule respectively, and is used to output the second digital compensation signal when triggered by the enable signal.

[0027] In one embodiment, the identification submodule includes:

[0028] The modulus unit is used to perform modulus processing on the digital input signal using a preset modulus base and output a modulus output signal.

[0029] A comparison unit, connected to the modulus extraction unit, is used to compare the modulus extraction output signal with a preset second reference value, and output the second digital compensation signal if the comparison result is the same.

[0030] In one embodiment, the digital output module includes:

[0031] The superposition processing unit is connected to the first digital logic module and the second digital logic module respectively, and is used to generate a digital superposition signal by superimposing the first digital compensation signal and the second digital compensation signal.

[0032] The second noise shaping unit is connected to the superposition processing unit and is used to perform noise shaping on the digital superposition signal and output a second digital shaped signal.

[0033] The second digital output unit, connected to the second noise shaping unit, is used to compensate the digital input signal according to the second digital shaping signal and output the digital output signal.

[0034] In one embodiment, the second digital compensation signal is one-half of the least significant bit of the digital input signal.

[0035] Secondly, this application provides a power amplifier, comprising:

[0036] Such as the H-bridge compensation circuit mentioned above;

[0037] The H-bridge driver circuit includes an H-bridge module and a driver module. The H-bridge module includes a first half-bridge and a second half-bridge, each of which includes a first switch and a second switch. The control terminals of the first and second switches are respectively connected to the driver module. The first terminal of the first switch is connected to a power supply terminal, and the second terminal of the second switch is connected to a ground terminal. The second terminals of the first and second switches in the same half-bridge are connected and used to connect to a load. The on-resistances of the first and second switches are different. The driver module is connected to the digital output module of the H-bridge compensation circuit and is used to drive the H-bridge module according to the digital output signal.

[0038] In one embodiment, the driving module includes:

[0039] A digital-to-analog converter unit, connected to the digital output module, is used to perform digital-to-analog conversion on the digital output signal and output a first analog signal and a second analog signal; the first analog signal and the second analog signal have the same amplitude but opposite polarities;

[0040] A first driving unit, connected to the digital-to-analog converter, is used to drive the first half-bridge according to the first analog signal;

[0041] The second driving unit is connected to the digital-to-analog converter unit and is used to drive the second half-bridge according to the second analog signal.

[0042] In one embodiment, the H-bridge drive circuit further includes:

[0043] A current detection module is connected in series between the second terminal of the second switching transistor and the ground terminal, or in series between the first terminal of the first switching transistor and the power supply terminal. The current detection module is used to collect current signals.

[0044] Thirdly, this application also provides a chip, including the H-bridge compensation circuit as described above, or the power amplifier as described above.

[0045] Fourthly, this application also provides an electronic device, including a load and a chip as described above.

[0046] The aforementioned H-bridge compensation circuit, power amplifier, chip, and electronic device, through a first digital logic module, perform digital logic processing in the digital domain based on the on-resistance difference between the first and second switching transistors, the gain of the H-bridge drive circuit, the power supply voltage provided by the power supply terminal, the load impedance connected to the H-bridge drive circuit, and the received digital input signal, to obtain and output a first digital compensation signal. Furthermore, a digital output module uses the first digital compensation signal to compensate the digital input signal in the digital domain, obtaining and outputting a compensated digital output signal. This digital output signal can be used as the input to the drive module in the H-bridge drive circuit, enabling the drive module to drive the H-bridge module according to the analog signal corresponding to the digital output signal, thereby achieving load driving. Because the first digital compensation signal comprehensively considers the factors affecting the common-mode error generated by the H-bridge drive circuit due to the difference in conduction resistance, namely the difference in conduction resistance, gain, power supply voltage, impedance, and digital input signal, the first compensation digital signal calculated in the digital domain based on these influencing factors can compensate for the common-mode error caused by the difference in conduction resistance. Therefore, the digital output signal obtained by compensating the digital input signal with the first digital compensation signal can inversely cancel the common-mode error in the digital domain. Thus, the signal output by the H-bridge drive circuit driven by this digital output signal can tend to be symmetrical, thereby achieving error compensation between the detected current and the actual current, improving the accuracy of current detection. It can also flexibly adapt to application scenarios with different load impedances, power supply conditions, and gain configurations, making it highly applicable. Furthermore, both the first digital logic module and the digital output module of this application are digital circuit structures, meaning signal compensation is implemented in the digital domain. Compared to signal compensation in the analog domain, digital circuits have a smaller area, lower hardware design difficulty and cost, and more flexible parameter settings. This avoids introducing various non-ideal factors from analog circuits, resulting in more stable performance and improved compensation accuracy, thereby improving current detection accuracy. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the structure of the H-bridge compensation circuit and the H-bridge drive circuit in one embodiment;

[0049] Figure 2 This is a schematic diagram of the H-bridge compensation circuit and the H-bridge drive circuit in another embodiment;

[0050] Figure 3 This is a schematic diagram of the H-bridge compensation circuit and the H-bridge drive circuit in yet another embodiment;

[0051] Figure 4 This is a schematic diagram of the H-bridge compensation circuit and H-bridge drive circuit in another embodiment;

[0052] Figure 5 This is a schematic diagram of the structure of a Δ-∑ modulator in one embodiment;

[0053] Figure 6 This is a schematic diagram of the H-bridge compensation circuit and the H-bridge drive circuit in another embodiment;

[0054] Figure 7 This is a schematic diagram of the waveforms of the first pulse width modulation signal and the second pulse width modulation signal under odd and even pulse width modulation in one embodiment;

[0055] Figure 8 This is a schematic diagram of the waveforms of the first pulse width modulation signal and the second pulse width modulation signal under odd-numbered pulse width modulation in one embodiment;

[0056] Figure 9 This is a schematic diagram of the H-bridge compensation circuit and the H-bridge drive circuit in yet another embodiment;

[0057] Figure 10 This is a comparison of the simulated output signal curves of an uncompensated power amplifier in one embodiment and the power amplifier of this application.

[0058] Explanation of icon numbers:

[0059] 10. H-bridge drive circuit; 111. First half-bridge; 112. Second half-bridge; 12. Drive module; 121. First drive unit; 1211. First amplification sub-unit; 1212. First gate driver; 122. Second drive unit; 1221. Second amplification sub-unit; 1222. Second gate driver; 123. Digital-to-analog conversion unit; 20. Load; 30. H-bridge compensation circuit; 31. First digital logic module; 311. Squaring unit; 312. Multiplication unit; 313. Division unit; 32. Digital output module; 321. First noise shaping unit; 322. First digital output unit; 323. Superposition processing unit; 324. Second noise shaping unit; 325. Second digital output unit; 33. Second digital logic module; 331. Enable sub-module; 332. Recognition sub-module; 3321. Modulus extraction unit; 3322. Comparison unit; 333. Output sub-module. Detailed Implementation

[0060] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0062] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Both the first element and the second element are elements, but they are not the same element.

[0063] It is understood that in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., transmit electrical signals or data to each other. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a portion of an element" refers to part or all of an element.

[0064] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0065] The H-bridge compensation circuit 30 provided in this embodiment is applied to the H-bridge drive circuit 10. For example... Figure 1 As shown, in some exemplary embodiments, an H-bridge driving circuit 10 is provided, which includes an H-bridge module and a driving module 12.

[0066] The H-bridge module includes a first half-bridge 111 and a second half-bridge 112. Both the first half-bridge 111 and the second half-bridge 112 include a first switch M1 and a second switch M2. The control terminals of the first switch M1 and the second switch M2 are respectively connected to a drive module 12. The first switch M1 and the second switch M2 can be driven by the drive module 12. The first end of the first switch M1 is connected to a power supply terminal and can be used to receive power signals provided by the power supply terminal. The second end of the second switch M2 is connected to a ground terminal, which can be understood as a reference ground terminal. The second end of the first switch M1 and the first end of the second switch M2 are connected. The connection point between the second end of the first switch M1 and the first end of the second switch M2 is the midpoint of the bridge arm. The second end of the first switch M1 is used to connect to the load 20. That is, the second end of the first switch M1 and the first end of the second switch M2 in the first half-bridge 111 are connected, and the connection point between them is the midpoint of the first bridge arm. In the second half-bridge 112, the second terminal of the first switch M1 and the first terminal of the second switch M2 are connected, and the connection point between them is the midpoint of the second bridge arm. The midpoints of the first and second bridge arms serve as the two output terminals of the H-bridge module, respectively, and are used to connect to the load 20. The load 20 can be understood as a functional module connected to the H-bridge drive circuit 10, including but not limited to speakers, motors such as linear motors, and electric motors such as DC motors, etc., which can be determined according to the actual application scenario. The on-resistance Ron of the first switch M1 and the second switch M2 are different, meaning there is a difference in on-resistance between them. The conductivity types of the first switch M1 and the second switch M2 are different. The first switch M1 includes a P-type transistor, and the second switch M2 includes an N-type transistor. The structural types of the first switch M1 and the second switch M2 are the same, for example, including but not limited to MOS (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), or other transistor structures. In some exemplary embodiments, the first switch M1 includes a PMOS transistor, and the second switch M2 includes an NMOS transistor.

[0067] In some exemplary embodiments, the H-bridge drive circuit 10 further includes a current detection module. The current detection module is connected in series between the second terminal of the second switching transistor M2 and the ground terminal, or in series between the first terminal of the first switching transistor M1 and the power supply terminal. The current detection module is used to acquire current signals. In some exemplary embodiments, the current detection module includes two sampling resistors Rsen and a current detection unit. One sampling resistor Rsen is connected in series between the second terminal of the second switching transistor M2 of the first half-bridge 111 and the ground terminal, and the other sampling resistor Rsen is connected in series between the second terminal of the second switching transistor M2 of the first half-bridge 111 and the ground terminal. The current detection unit is connected to the connection point between the two sampling resistors Rsen and the corresponding second switching transistor M2, respectively, to detect the current signal, thereby realizing the detection of the current of the load 20, that is, the current signal detected by the current detection module is taken as the current flowing through the load 20. Similarly, the first sampling resistor Rsen and the second sampling resistor Rsen can also be connected in series between the first terminals of the two first switching transistors M1 and the power supply terminal, respectively, which will not be described in detail here. Thus, by connecting the current detection module in series with the upper or lower arm of the H-bridge, the current of the load 20 can be detected. The structure is simple and helps to achieve precise control and monitoring of the circuit and the load 20 based on the detected current signal.

[0068] However, as mentioned in the background section, the mismatch in the on-resistance of the first half-bridge 111 and the second half-bridge 112 of the H-bridge module will cause the output signal of the H-bridge module to be asymmetrical, and the output common mode will change with the signal. This will cause the current detected by the current detection module to deviate from the actual current of the load 20, thereby affecting the control accuracy and operational stability of the circuit system.

[0069] In response, this application provides an H-bridge compensation circuit 30, a power amplifier, a chip, and an electronic device that can compensate for common-mode errors caused by on-resistance mismatch, thereby helping to improve the current detection accuracy of the H-bridge drive circuit 10.

[0070] Please continue reading. Figure 1 In some exemplary embodiments, an H-bridge compensation circuit 30 is provided, which can be applied to... Figure 1 The H-bridge drive circuit 10 shown includes an H-bridge compensation circuit 30, which includes a first digital logic module 31 and a digital output module 32.

[0071] The first digital logic module 31 outputs a first digital compensation signal based on the power supply voltage PVDD provided by the power supply terminal, the difference in on-resistance between the first switch M1 and the second switch M2, the impedance of the load 20, the gain of the H-bridge drive circuit 10, and the received digital input signal. This first digital compensation signal compensates for the common-mode error generated by the H-bridge drive circuit 10 due to the difference in on-resistance. Without compensation, the signals output from the two output terminals of the H-bridge drive circuit 10 will be asymmetrical due to the difference in on-resistance, and the output common-mode will change with the digital input signal, i.e., there will be output common-mode jitter, resulting in common-mode output error and consequently, current detection error. The first digital compensation signal can be understood as the digital domain compensation amount corresponding to this common-mode error. The first digital compensation signal can be obtained by the first digital logic module 31 through digital logic operations based on the power supply voltage PVDD provided by the power supply terminal, the difference in on-resistance, the gain of the H-bridge drive circuit 10, and the received digital input signal.

[0072] The power supply voltage PVDD of the power signal can be dynamically monitored and acquired in real time. In some exemplary embodiments, the H-bridge compensation circuit 30 further includes a voltage detection module, which is connected to both the power supply terminal and the first digital logic module 31. The voltage detection module is used to detect the power supply voltage PVDD at the power supply terminal, so that the first digital logic module 31 can obtain the power supply voltage PVDD at the power supply terminal in real time through the voltage detection module to achieve signal compensation. In some exemplary embodiments, the voltage detection module includes an analog-to-digital converter (ADC), which is connected to both the power supply terminal and the first digital logic module 31. The ADC is used to acquire the power signal provided by the power supply terminal and perform analog-to-digital conversion on the power signal to obtain the power supply voltage PVDD. In other exemplary embodiments, the first digital logic module 31 can directly call the pre-stored power supply voltage PVDD. In practical applications, the method of obtaining the power supply voltage PVDD can be set according to the specific scenario, and is not limited here.

[0073] The on-resistance difference and the impedance of load 20 can be obtained in advance by measurement. In some exemplary embodiments, the first digital logic module 31 can acquire the pre-stored on-resistance difference and the impedance of load 20.

[0074] The gain of the H-bridge driver circuit 10 can be understood as the analog loop gain of the H-bridge driver circuit 10, which is the full-link gain from the input to the output of the H-bridge module.

[0075] The digital input signal can be understood as the original digital command signal that instructs the load 20 to reach the target operating state without considering common-mode error compensation; that is, it is the digital carrier that instructs the H-bridge drive circuit 10 to drive the load 20 to the desired operating state. The digital input signal is a pure digital signal, i.e., a non-analog signal, and can exist in binary form. In this application, the digital input signal can drive the load 20 to reach the target operating state after digital compensation by the H-bridge compensation circuit 30, and after digital-to-analog conversion and power amplification by the H-bridge drive circuit 10. The source of the digital input signal includes, but is not limited to, sensors, chips, host computers, etc., which can be determined according to different application scenarios. Taking the load 20 including a speaker as an example, the digital input signal is the original digital audio signal to be compensated, which is a digital data stream carrying sound information. It can be obtained by collecting physical quantities through sensors such as microphones and then converting them from analog to digital. After digital compensation by the H-bridge compensation circuit 30, and after digital-to-analog conversion and power amplification by the H-bridge drive circuit 10, the digital input signal can drive the speaker to emit sound.

[0076] The digital output module 32 is connected to both the first digital logic module 31 and the driver module 12. The digital output module 32 compensates the digital input signal according to the first digital compensation signal and outputs a digital output signal to instruct the driver module 12 to drive the H-bridge module. The compensation process of the digital output module 32 can be understood as a reverse cancellation process for common-mode error. That is, the first digital compensation signal is the opposite of the common-mode error caused by the difference in conduction resistance in the digital domain; that is, the sum of the first digital compensation signal and the common-mode error caused by the difference in conduction resistance in the digital domain is 0.

[0077] The driving module 12 is used to drive the first half-bridge 111 and the second half-bridge 112 according to the digital output signal, thereby driving the load 20 through the first half-bridge 111 and the second half-bridge 112. The driving module 12 can be used to perform digital-to-analog conversion on the digital output signal, output an analog signal, and control the opening and closing states of the first switch M1 and the second switch M2 of the first half-bridge 111 according to the analog signal, and control the opening and closing states of the first switch M1 and the second switch M2 of the second half-bridge 112 according to the analog signal, thereby driving the load 20 to work in the target working state corresponding to the digital input signal.

[0078] Ideally, the first switch M1 and the second switch M2 would have the same on-resistance, resulting in symmetrical signals output from the first half-bridge 111 and the second half-bridge 112. This would eliminate common-mode jitter in the H-bridge module due to the difference in on-resistance, meaning there would be no common-mode error. However, because the actual on-resistances of the first switch M1 and the second switch M2 are different (i.e., there is a resistance difference between them), the signals output from the first half-bridge 111 and the second half-bridge 112 become unbalanced, lacking symmetry. This leads to common-mode jitter and an error between the detected current and the actual current. From the output perspective of the first half-bridge 111 and the second half-bridge 112, ideally, the forward and reverse drive voltages would have the same amplitude and opposite polarity. This means the voltage fluctuations at the two output terminals would always be symmetrical, the common-mode voltage would remain stable and not change with the input signal, and therefore, there would be no common-mode jitter. However, in practice, due to the different on-resistances of the first half-bridge 111 and the second half-bridge 112, the outputs of the first half-bridge 111 and the second half-bridge 112 become unbalanced, meaning the voltage fluctuations at the two output terminals are asymmetrical, and the common-mode voltage changes with the input signal. This causes the detected current of the current detection module to deviate from the actual current of the load 20, resulting in current detection error, which in turn affects the control accuracy and operational stability of the circuit system.

[0079] To address this, this application provides a basic digital input signal while compensating for the digital input signal in the digital domain to compensate for the common-mode error caused by the difference in on-resistance. This makes the signals output by the first half-bridge 111 and the second half-bridge 112 more symmetrical, thereby improving the current detection accuracy. Furthermore, since the difference in on-resistance between the first switch M1 and the second switch M2 is the root cause of the common-mode error and directly determines its magnitude, the difference in on-resistance is used as the basis for compensation. Moreover, the digital input signal is the basic signal driving the load 20, and the compensation is performed in the digital domain; therefore, the digital input signal is also used as the basis for compensation. Additionally, since the signal compensation in this embodiment is implemented in the digital domain, the compensated digital output signal will undergo digital-to-analog conversion and power amplification processing by the subsequent H-bridge drive circuit 10. Therefore, when determining the first digital compensation signal, the gain of the H-bridge drive circuit 10 is also used as the basis for compensation. Furthermore, since the signal magnitudes output by the first half-bridge 111 and the second half-bridge 112 are directly affected by the power supply voltage PVDD and the impedance of the load 20, the power supply voltage PVDD and the impedance will also be used as the basis for compensation.

[0080] The H-bridge compensation circuit 30 provided in the above embodiment performs digital logic processing in the digital domain by the first digital logic module 31 based on the difference in conduction resistance between the first switch M1 and the second switch M2, the gain of the H-bridge drive circuit 10, the power supply voltage PVDD provided by the power supply terminal, the impedance of the load 20 connected to the H-bridge drive circuit 10, and the received digital input signal, to obtain and output a first digital compensation signal. The digital output module 32 then uses the first digital compensation signal to compensate the digital input signal in the digital domain to obtain and output a compensated digital output signal. This digital output signal can be used as the input of the drive module 12 in the H-bridge drive circuit 10, enabling the drive module 12 to drive the H-bridge module according to the analog signal corresponding to the digital output signal, thereby realizing the driving of the load 20. Since the first digital compensation signal comprehensively considers the factors affecting the common-mode error generated by the H-bridge drive circuit 10 due to the difference in conduction resistance, namely the difference in conduction resistance, gain, power supply voltage PVDD, impedance, and digital input signal, the first compensation digital signal calculated in the digital domain based on these influencing factors can compensate for the common-mode error caused by the difference in conduction resistance. Thus, the digital output signal obtained by compensating the digital input signal with the first digital compensation signal can inversely cancel the common-mode error in the digital domain. Therefore, the signal output by the H-bridge drive circuit 10 driven by the digital output signal can tend to be symmetrical, thereby realizing the error compensation between the detected current and the actual current, improving the accuracy of current detection, and flexibly adapting to application scenarios with different load impedances, power supply conditions, and gain configurations, making it highly applicable. Furthermore, both the first digital logic module 31 and the digital output module 32 of this application are digital circuit structures, that is, signal compensation is realized in the digital domain. Compared with signal compensation in the analog domain, digital circuits have a smaller area, lower hardware design difficulty and cost, and more flexible parameter settings. They can avoid introducing various non-ideal factors of analog circuits, resulting in more stable performance and helping to improve compensation accuracy, thereby improving current detection accuracy.

[0081] In some exemplary embodiments, the common-mode error is the difference between the duty cycle when both the first half-bridge 111 and the second half-bridge 112 output high levels and the duty cycle when both output low levels, i.e., the duty cycle error. The signals output by the first half-bridge 111 and the second half-bridge 112 may both include pulse width modulation (PWM) signals, meaning the H-bridge driver module 12 drives the H-bridge module using PWM. Therefore, the duty cycle error can be understood as the difference between the duty cycle when both the PWM signals output by the first half-bridge 111 and the second half-bridge 112 are high levels and the duty cycle when both output low levels.

[0082] Without considering compensation, the drive module 12 directly drives the H-bridge module according to the analog signal corresponding to the digital input signal. In this case, due to the difference in conduction resistance, the duty cycle when both the first half-bridge 111 and the second half-bridge 112 output high level is not equal to the duty cycle when both output low level, that is, there is a duty cycle error.

[0083] like Figure 2 As shown, the H-bridge module has three operating states. When the first switching transistor M1 of the first half-bridge 111 and the second half-bridge 112 connected to the power supply is both turned on, and the grounded second switching transistor M2 is both turned off, both the first half-bridge 111 and the second half-bridge 112 output high-level signals, and the H-bridge module is in a high-high operating state HH. When the first switching transistor M1 of one of the first half-bridge 111 and the second half-bridge 112 is turned on, and the first switching transistor M1 of the other is turned off, and simultaneously one of the first half-bridge 111 and the second half-bridge 112 outputs a high-level signal, the H-bridge module is in a high-high operating state HH. When the second switch M2 of one half-bridge is turned on and the second switch M2 of the other half-bridge is turned off, one of the first half-bridge 111 and the second half-bridge 112 outputs a high-level signal and the other outputs a low-level signal, and the H-bridge module is in a high-low operating state HL; when the first switch M1 of the first half-bridge 111 and the second half-bridge 112 connected to the power supply is turned off and the second switch M2 is turned on, the first half-bridge 111 and the second half-bridge 112 both output low-level signals, and the H-bridge drive circuit 10 is in a low-low operating state LL.

[0084] In the three operating states of the H-bridge module described above, the different on-resistances of the first switch M1 and the second switch M2 will cause the output of the H-bridge module to lose its symmetry. (See details...) Figure 3 , Figure 3 The diagram illustrates the state switching and waveforms of the H-bridge module within a single cycle in an embodiment of this application. The dashed lines represent the actual waveforms when the on-resistances of the first switch M1 and the second switch M2 are different. The solid lines represent the ideal waveforms when the first switch M1 and the second switch M2 have no on-resistance (i.e., the on-resistance difference is 0). In practical applications, the H-bridge module is controlled by a negative feedback loop, and its average output voltage within one cycle depends on the magnitude of the digital input signal and the loop gain, independent of the characteristics of the H-bridge itself. Therefore, the area enclosed by the dashed lines is equal to the area enclosed by the solid lines. However, due to the different resistances of the first switch M1 and the second switch M2, the high-level output time of the first half-bridge 111 is prolonged and the output voltage is reduced, while the high-level output time of the second half-bridge 112 is shortened and the output voltage is increased. This results in an asymmetrical output signal for the H-bridge module; the duration of the low-low operating state LL of the H-bridge module is not equal to the duration of the high-high operating state HH. Therefore, the average current detected by the detection circuit within one cycle is not equal to the average current of the load 20, causing a current detection error.

[0085] In this embodiment, the first digital compensation signal can be used to compensate for the duty cycle error caused by the difference in conduction resistance. The first digital compensation signal can be understood as the digital domain compensation amount corresponding to the duty cycle error. That is, in this embodiment, the first digital compensation signal, corresponding to the digital domain compensation amount of the duty cycle error, is output by the first digital logic module 31, and the digital input signal is compensated in the digital domain by the first digital compensation signal through the digital output module 32. The compensated digital output signal is converted into the corresponding analog signal by the digital-to-analog conversion module, and the H-bridge module is driven by the analog signal through the driving module 12, thereby realizing the driving control of the load 20 through the H-bridge module. Since the first digital compensation signal can compensate for the duty cycle error, the digital output signal output after compensating the digital input signal according to the first digital compensation signal can reversely cancel the duty cycle error, so that the actual duty cycle in a single cycle in which both the first half-bridge 111 and the second half-bridge 112 output high level is equal to the actual duty cycle in which both output low level, thereby ensuring the symmetry of the output signal of the H-bridge driving circuit 10, which is beneficial to improving the accuracy of the current detection of the H-bridge module.

[0086] Please continue reading. Figure 3 ,according to Figure 3 The difference between the solid and dashed waveforms is quantitatively analyzed, and the average value of the output voltage of the H-bridge module within one cycle can be obtained by the following formula:

[0087] D p *PVDD=D p ′*(PVDD-I coil *R p )-I coil *R n *(1-D p ′)

[0088] D n *PVDD=D n ′*(PVDD+I coil *R p )+I coil *R n *(1-D n ′)

[0089] Among them, D p The theoretical duty cycle for the high-level output of the first half-bridge 111 is D. p ′ represents the actual duty cycle of the high-level output of the first half-bridge 111; D n D is the theoretical duty cycle for the high-level output of the second half-bridge 112. n ′ represents the actual duty cycle of the high-level output of the second half-bridge 112; R pR is the on-resistance of the first switching transistor M1. n I is the on-resistance of the second switching transistor M2. coil PVDD represents the current flowing through the load 20, and PVDD represents the power supply voltage PVDD.

[0090] The current flowing through load 20 can be derived using the following formula:

[0091] I coil =PVDD / R L *D HL ′

[0092] Among them, D HL ′ represents the actual duty cycle during which one of the first half-bridge 111 and the second half-bridge 112 outputs a high level while the other outputs a low level. R L The impedance is 20Ω for the load.

[0093] Therefore, substituting the above equation, we can derive the following relationship between the actual duty cycles of both the first half-bridge 111 and the second half-bridge 112 outputting high levels and low levels within a single PWM cycle of the H-bridge module:

[0094] D p =D p ′*(1-R L -1 *D HL ′*R p )-R L -1 *D HL ′*R n *(1-D p ′)

[0095] D n =D n ′*(1+R L -1 *D HL ′*R p )+R L -1 *D HL ′*R n *(1-D n ′)

[0096] Furthermore, by transforming the above relationship, we can derive the reduction in duty cycle of the H-bridge module in its high-high operating state (HH) and low-low operating state:

[0097] △D LL =D p ′-D p =I coil / PVDD*(R n +Dp ′*(R p -R n ))>0

[0098] △D HH =D n -D n =I coil / PVDD*(R n +D n ′*(R p -R n ))>0

[0099] Among them, D p ′-D p The difference between the actual high-level output time of the first half-bridge 111 and the ideal high-level output time represents the reduction in the duty cycle ΔD of the H-bridge module in its low-low operating state. LL Similarly, D n ′-D n ′ represents the difference between the actual high-level output time of the second half-bridge 112 and the ideal high-level output time, which represents the increase in the duty cycle ΔD of the H-bridge module in the high-high operating state. HH .

[0100] It can be understood that the duty cycle can be represented by the corresponding duration and PWM period. That is, the duty cycles of the H-bridge module operating in low-low (LL) and high-high (HH) states can be expressed as follows:

[0101] D LL =T LL / T

[0102] D HH =T HH / T

[0103] Among them, T LL T represents the ideal duration of the H-bridge module's low-low operating state LL within a single cycle; HH T represents the ideal duration of the H-bridge module's high-level operating state (HH) within a single cycle; T represents the PWM cycle.

[0104] Therefore, the reduction in duty cycle of the H-bridge module in both the high-high operating state (HH) and low-low operating state can be further expressed as:

[0105] △T LL / T=(T LL ′-T LL ) / T=D p ′-D p =I coil / PVDD*(R n +Dp ′*(R p -R n ))

[0106] △T HH / T=(T HH -T HH ′) / T=D n -D n =I coil / PVDD*(R n +D n ′*(R p -R n ))

[0107] Ideally, if the on-resistance Ron of the first switch M1 and the second switch M2 is 0, then there is no on-resistance difference. In this case, the ideal duration T for both the first half-bridge 111 and the second half-bridge 112 to output a high level within one cycle is [value missing]. HH The ideal duration T for both to output a low level within one cycle LL That is, T LL =T HH Therefore, ideally, the average value of the current flowing through the second switch M2, i.e., the current sensed, is:

[0108] I sen =T LL / T*V sen_LL / R sen +T HL / T*V sen_HL / R sen +T HH / T*0

[0109] =2*T LL / T*I coil +T HL / T*I coil

[0110] =I coil *[1+(T LL -T HH ) / T]

[0111] =I coil

[0112] Among them, V sen_LL This represents the voltage across the sampling resistor Rsen when both the first half-bridge 111 and the second half-bridge 112 output a low level within one cycle; V sen_HL This represents the voltage across the sampling resistor Rsen when one of the first half-bridge 111 and the other half-bridge 112 is high and low within one cycle; T HLThis indicates the duration during which one of the first half-bridge 111 and the second half-bridge 112 outputs a high level and the other outputs a low level within one cycle; T represents the signal period of the outputs of the first half-bridge 111 and the second half-bridge 112; R sen This indicates the sampling resistor.

[0113] However, in reality, due to T LL ′≠T HH Therefore, the average value of the actual current detection is:

[0114] I sen ′=I coil *[1+(T LL ′-T HH ′) / T]=I coil *(1+D LL ′-D HH ′)<I coil

[0115] Among them, T HH ′ represents the actual duration for both the first half-bridge 111 and the second half-bridge 112 to output a high level within one cycle; T LL ′ indicates the actual duration for which both the first half-bridge 111 and the second half-bridge 112 output a low level within one cycle.

[0116] Since the relative error of current detection depends on the difference in duty cycle between the low-low operating state (LL) and the high-high operating state (HH), the relative error of current in the H-bridge module can be expressed by the following formula:

[0117] (I sen ′ / I coil ) error =D LL ′-D HH ′=(D LL -△D LL )-(D HH -△D HH )

[0118] =(D LL -D HH )+(△D HH -△D LL )

[0119] =△D HH -△D LL

[0120] By substituting the above relationships into the relationships for the reduction in duty cycle of the HH module in its high-high operating state and the reduction in duty cycle in its low-low operating state, the relative error of the deformed current can be expressed by the following relationship:

[0121] (Isen ′ / I coil ) error =△D HH -△D LL =-I coil / PVDD*(D p ′-D n ′)(R p -R n )

[0122] =-I coil / PVDD*D HL ′(R p -R n )

[0123] Substituting the current flowing through load 20 into the above equation, we can derive the following equation: The error ratio between the actual current flowing through the second switch M2 and the theoretical current within a single cycle of the H-bridge module satisfies the following relationship:

[0124] (I sen ′ / I coil ) error =-D HL ′ 2 (R p -R n ) / R L

[0125] That is, within a single PWM cycle of the H-bridge module, the error ratio between the actual current flowing through the second switching transistor M2 and the theoretical current can be expressed as:

[0126] (T LL ′-T HH ) / T=[(T LL –△T LL )-(T HH –△T HH )] / T=(△T HH –△T LL ) / T

[0127] =-I coil / PVDD*T HL ′ / T*(R p -R n )=-(T HL ′ / T) 2 (R p -R n ) / R L

[0128] Based on this, the above error needs to be converted to the input terminal of the H-bridge drive circuit 10, that is, the output terminal of the H-bridge compensation module, so as to obtain the amount of compensation that the H-bridge compensation module needs to provide for the digital input signal, which is the first digital compensation signal.

[0129] Since the signal output by the H-bridge module is a digital output signal processed by the H-bridge driver circuit 10 through digital-to-analog conversion and power amplification, the gain of the H-bridge driver module 12 needs to be inversely reduced when calculating the digital compensation for the error. Furthermore, the current flowing through the load 20 is equal to the voltage V output by the H-bridge module. out The ratio between the impedance of load 20 and the impedance of load 20, i.e., I coil =V out / R L =V in *Gain / R L Therefore, combining the above relative error formula, the first digital compensation signal corresponding to the digital domain can be obtained as:

[0130] V comp1 =V in 2 *(R p -R n ) / R L *Gain / PVDD

[0131] Among them, V comp1 Indicates the first digital compensation signal; V in Indicates a digital input signal; (R) p -R n ) represents the difference in on-resistance; R L represents the impedance of load 20; Gain represents the gain of H-bridge driver module 12; PVDD represents the power supply voltage. Based on the above formula, it can be seen that the first digital compensation signal is positively correlated with the digital input signal, the on-resistance difference, and the gain, and negatively correlated with the impedance and the power supply voltage.

[0132] It should be noted that the actual duty cycle and actual current mentioned above refer to the state parameters of the H-bridge module under actual operating conditions, while the theoretical duty cycle and theoretical current refer to the state parameters of the H-bridge module under ideal conditions (with zero on-resistance).

[0133] like Figure 4 As shown, in some exemplary embodiments, the first digital logic module 31 includes a square operation unit 311, a product operation unit 312, and a division operation unit 313.

[0134] The squaring unit 311 performs squaring operations on the digital input signal and outputs a squared output signal. That is, the squaring unit 311 calculates the square of the digital input signal, obtains and outputs the squared output signal V.in 2 In the H-bridge driver circuit 10, the common-mode error caused by the difference in on-resistance is not linearly proportional to the digital input signal, but rather proportional to the square of the input signal. This can be addressed through squaring, i.e., V... in 2 The amplitude information of the digital input signal is converted into a nonlinear quantization term that matches the error source (conduction resistance difference), providing a basis for subsequent error calculation. In applications, the squaring unit 311 can be a multiplier or other structure capable of performing squaring operations; no further restrictions are imposed here.

[0135] The product operation unit 312 is connected to the squaring operation unit 311. The product operation unit 312 performs a product operation based on the squaring output signal and the product coefficients, and outputs a product output signal. The product coefficients are related to the on-resistance difference, the impedance of the load 20, and the gain of the H-bridge drive circuit 10, respectively. Specifically, the product coefficients are positively correlated with the on-resistance difference and the gain, and negatively correlated with the impedance. The product coefficients can be (R... p -R n ) / R L *Gain. In applications, the product coefficients can be pre-calculated and stored based on the conduction resistance difference, gain, and impedance. The product operation unit 312 can directly call the product coefficients to perform the product operation. That is, the product operation unit 312 multiplies the squared output signal with the product coefficients to obtain and output the product operation result V. in 2 *(R p -R n ) / R L *Gain. In applications, the product operation unit 312 can be a multiplier or other structure capable of performing product operations, without further restrictions here.

[0136] The division unit 313 is connected to the product unit 312. The division unit 313 performs a division operation on the power supply voltage PVDD based on the product output signal, and outputs a first digital compensation signal. The division unit 313 can divide the product output signal by the power supply voltage PVDD to output the first digital compensation signal V. in 2 *(R p -R n ) / R L *Gain / PVDD. In applications, the division unit 313 can be a multiplier, a divider, or other structures capable of performing division operations; no further restrictions are imposed here.

[0137] The H-bridge compensation circuit 30 provided in the above embodiment uses the digital compensation calculation link provided by the squaring unit 311, the product unit 312, and the division unit 313 to accurately capture the nonlinear correlation between the digital input signal and the common-mode error caused by the difference in conduction resistance through squaring operation. It uses the product operation to quantify the fixed coupling effect between the error source and the impedance and gain. Then, it combines the inherent circuit parameters such as the power supply voltage PVDD to complete the calculation of the error compensation amount through division operation, and finally generates the first digital compensation signal in the digital domain. This not only realizes the accurate quantification and cancellation of the common-mode error caused by the inherent non-ideal factor of the difference in conduction resistance in the H-bridge drive circuit 10, but also effectively avoids the signal distortion caused by this type of error. It helps to reduce the harmonic distortion and noise of current detection, thereby improving the accuracy of current detection.

[0138] Please continue reading. Figure 4 In some exemplary embodiments, the digital output module 32 includes a first noise shaping unit 321 and a first digital output unit 322.

[0139] The first noise shaping unit 321 is connected to the first digital logic module 31. The first noise shaping unit 321 is used to shape the noise of the first digital compensation signal and output a first digitally shaped signal. The first noise shaping unit 321 aims to transfer the in-band quantization noise of the first digital compensation signal to the out-of-band, thereby reducing noise and improving the signal-to-noise ratio. That is, it transfers the quantization noise from the low-frequency band to the high-frequency band, thus shifting the quantization noise from the in-band to the out-of-band. In some exemplary embodiments, the first noise shaping unit 321 includes a first DSM (delta-sigma modulator, Δ-Σ modulator), which can convert the first digital compensation signal into a first digitally shaped signal without loss of accuracy, i.e., the quantization noise does not increase within the effective bandwidth; wherein the bit width of the first digitally shaped signal is smaller than the bit width of the first digital compensation signal.

[0140] like Figure 5As shown, in some exemplary embodiments, the first DSM can adopt a high-order digital Δ-Σ architecture, which includes multiple integrators T, coefficient gain units c (including c1, c2, c3, and c4), adders, and quantizers Q. After the signal in is input, it passes through the adder, integrator T, and coefficient gain unit c in a forward multi-stage integration link. Simultaneously, it is superimposed with the input signal and the previous stage signal through the feedback path (including f1 and f2) via the adder. Finally, the quantizer Q performs low-bit-width quantization on the accumulated signal and outputs the modulated signal out. The DSM achieves deep noise shaping through multi-stage integrators and sums multi-path signals through adders. Combined with the low-bit-width conversion of the quantizer, the quantization noise is transferred to the high-frequency band, thereby improving the quantization accuracy of the input signal within the effective bandwidth. Finally, it outputs a high-resolution digital modulated signal, achieving a near-high-bit-width signal processing effect with low-bit-width hardware. Figure 5 The DSM shown is a 4th-order architecture. Other suitable architectures can also be used in applications, and no further restrictions are imposed here.

[0141] The first digital output unit 322 is connected to the first noise shaping unit 321. The first digital output unit 322 is used to compensate the digital input signal according to the first digital shaping signal and output a digital output signal. This digital output signal can be used as the input of the H-bridge drive circuit 10, enabling the H-bridge drive circuit 10 to drive the load 20. In some exemplary embodiments, the first digital output unit 322 includes a PWM modulator, which is connected to the first noise shaping unit 321. The PWM modulator can perform PWM modulation according to the input first digital shaping signal and the digital input signal to output a digital output signal.

[0142] The H-bridge compensation circuit 30 provided in the above embodiment performs noise shaping on the first digital compensation signal through the first noise shaping unit 321, outputs the first digital shaped signal, and compensates the digital input signal according to the first digital shaped signal through the first digital output unit 322, outputting the digital output signal. Thus, the digital output signal can be used as the input of the H-bridge drive circuit 10, so that the H-bridge drive circuit 10 can drive the load 20. Understandably, since the common-mode error is very small, the corresponding first digital compensation signal is also very small. In response, this application can utilize the first noise shaping unit 321 to address the characteristic that small-amplitude compensation signals are susceptible to interference from quantization noise and inherent circuit noise. By employing noise shaping techniques such as Δ-Σ modulation, the quantization noise in the low-frequency band can be transferred to the high-frequency band, accurately extracting and enhancing the effective compensation information in the first digital compensation signal. This suppresses the impact of noise on the compensation effect while ensuring the accuracy of small-signal compensation. It not only achieves accurate compensation for the common-mode error but also further improves the symmetry and stability of the H-bridge output waveform, reduces current harmonic distortion during the load 20 driving process, and avoids compensation failure caused by weak compensation signals. This significantly improves the control accuracy and operational reliability of the entire H-bridge system.

[0143] like Figure 6 As shown, in some exemplary embodiments, the H-bridge compensation circuit 30 further includes a second digital logic module 33. The second digital logic module 33 is used to output a second digital compensation signal when the H-bridge driver module 12 uses odd pulse width modulation and the digital input signal is odd. The second digital compensation signal is used to compensate for the common-mode noise corresponding to the digital input signal. Here, common-mode noise refers to the output common-mode noise of the H-bridge driver module 12 caused by using odd pulse width modulation and the digital input signal being odd. The second digital compensation signal can be understood as the amount of compensation for common-mode noise in the digital domain.

[0144] The digital output module 32 is also connected to the second digital logic module 33. The digital output module 32 is used to compensate the digital input signal based on the first digital compensation signal and the second digital compensation signal, and output a digital output signal. The digital output module 32 can generate a digital output signal based on the first digital compensation signal, the second digital compensation signal, and the digital input signal. That is, based on the digital input signal, it not only uses the first digital compensation signal for compensation but also uses the second digital compensation signal for compensation, thereby achieving compensation for common-mode error and common-mode noise in the digital domain. The second digital compensation signal can be understood as the compensation amount corresponding to the common-mode noise in the digital domain.

[0145] It is understood that the H-bridge drive circuit 10 can drive the H-bridge module using pulse width modulation (PWM). That is, the drive module 12 can drive the H-bridge module by outputting a pulse width modulation signal. In other words, the drive module 12 can generate a first pulse width modulation signal PWM1 based on the analog signal to drive the first half-bridge 111 of the H-bridge module, and generate a second pulse width modulation signal PWM2 based on the analog signal to drive the second half-bridge 112 of the H-bridge module. The first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 have the same amplitude and opposite polarity.

[0146] Pulse width modulation (PWM) can include odd-numbered PWM and even-numbered PWM. Odd-numbered PWM can be understood as an asymmetric modulation method, while even-numbered PWM can be understood as a symmetric modulation method. From the perspective of the H-bridge driver circuit 10, when the PWM method is odd-numbered PWM, the first PWM signal PWM1 driving the first half-bridge 111 and the second PWM signal PWM2 driving the second half-bridge 112 are asymmetric. This asymmetry causes random jitter related to the input to the output of the H-bridge module, i.e., there is output common-mode noise. This common-mode noise will eventually be reflected in the output signal of the H-bridge module, thus affecting the current detection accuracy. In contrast, with even-numbered PWM, the first PWM signal PWM1 and the second PWM signal PWM2 are symmetrical, therefore, even-numbered PWM does not have common-mode noise.

[0147] Specifically, such as Figure 7 and Figure 8 As shown in (a), when the digital input signal is 0, regardless of whether it is odd or even pulse width modulation, the duty cycle of the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 is 50%, the differential output of the H-bridge drive circuit 10 is 0, and the common mode output is PVDD / 2.

[0148] like Figure 7 As shown in (b), for even-numbered pulse width modulation (PWM), since the two PWM signals change symmetrically, when the digital input signal is 1 (i.e., 1 LSB, the least significant bit), compared to the input being 0, both PWM signals will simultaneously adjust in the opposite direction by 1 Td. In this case, the duration of the differential output of the H-bridge driver circuit 10 is 2*Td, where Td represents the minimum time increment of the PWM signal, and the common-mode output voltage of the H-bridge driver circuit 10 is PVDD / 2. When the digital input signal is 2 (i.e., 2 LSBs), compared to the input being 0, both PWM signals will simultaneously adjust in the opposite direction by 2 Td. In this case, the duration of the differential output is 4*Td, and the common-mode output voltage is PVDD / 2. Similarly, it can be seen that the common-mode output under even-numbered PWM is fixed at PVDD / 2.

[0149] like Figure 7 (c) and Figure 8 As shown in (b), (c), and (d), for odd-numbered pulse width modulation (PWM), since the two PWM signals change asymmetrically, when the digital input signal is 1 (i.e., 1 LSB), compared to the input being 0, one of the two PWM signals will adjust by 1 Td, while the other remains unchanged. In this case, the duration corresponding to the differential output of the H-bridge driver circuit is 1*Td, and the common-mode output voltage is PVDD + 1 / 2*LSB. When the digital input signal is 2 (i.e., 2 LSB), compared to the input being 0, both PWM signals will simultaneously adjust in opposite directions by 1 Td. In this case, the duration corresponding to the differential output is 2*Td, and the common-mode output voltage is PVDD / 2. When the digital input signal is 3 LSBs (compared to the input being 0), one of the two pulse width modulation signals will adjust by 2 Td, while the other will adjust by 1 Td in the opposite direction. In this case, the duration of the differential output of the H-bridge driver circuit is 3 * Td, and the common-mode output voltage is PVDD + 1 / 2 * LSB. When the digital input signal is 4 LSBs (compared to the input being 0), both pulse width modulation signals will simultaneously adjust by 2 Td in the opposite direction. In this case, the duration of the differential output is 4 * Td, and the common-mode output voltage is PVDD / 2. Similarly, under odd-numbered pulse width modulation with an even input, the common-mode output is PVDD / 2, while under odd-numbered pulse width modulation with an odd input, the common-mode output is not PVDD / 2, but rather PVDD / 2 + 1 / 2 * LSB. The voltage offset corresponding to 1 / 2 LSB is what generates common-mode noise.

[0150] As mentioned above, the minimum time increment under even-number pulse width modulation is 2*Td, while the minimum time increment under odd-number pulse width modulation is 1*Td. Therefore, odd-number pulse width modulation offers higher accuracy. Furthermore, the common-mode output under even-number pulse width modulation is fixed at PVDD / 2, while the common-mode output under odd-number pulse width modulation is not fixed at PVDD / 2; it will offset by the voltage corresponding to 1 / 2 LSB relative to PVDD / 2 when the input is odd.

[0151] It is understandable that the common-mode output of the H-bridge driver circuit 10 is the average of the voltages output from its two output terminals. Ideally, the common-mode output of the H-bridge driver circuit 10 is stable at PVDD / 2 without any offset. However, when using odd-numbered pulse width modulation and the input is odd-numbered, the common-mode output will deviate from PVDD / 2 by 1 / 2 LSB, resulting in common-mode output fluctuations. These fluctuations constitute the common-mode noise of the H-bridge driver circuit 10. Although the H-bridge driver circuit 10 uses differential output, theoretically, differential output scenarios are not sensitive to common-mode levels. However, in actual circuits, due to load 20 or circuit non-ideals or mismatches, errors can be converted into differential output errors, ultimately affecting the output accuracy and performance of the H-bridge driver circuit 10.

[0152] Therefore, this application designs a second digital logic module 33 to output a second digital compensation signal, i.e., the compensation amount corresponding to common-mode noise in the digital domain, when the pulse width modulation is odd and the digital input signal is odd. Through the digital output signal module, in addition to compensating the digital input signal based on the first digital compensation signal, it also compensates the digital input signal based on the second digital compensation signal. This achieves compensation for common-mode error caused by the difference in on-resistance, and also compensates for common-mode noise when the pulse width modulation is odd and the digital input signal is odd, improving the signal-to-noise ratio and further enhancing the current detection accuracy. Furthermore, using odd pulse width modulation, compared to even pulse width modulation, provides higher control accuracy, meeting higher precision requirements.

[0153] In some exemplary embodiments, the second digital compensation signal is the negative half of the least significant bit of the digital input signal. Based on the above, it can be seen that in the case of odd-numbered pulse width modulation and an odd number of digital input signals, the common-mode output of the H-bridge driver circuit 10 has an offset voltage relative to PVDD / 2, corresponding to a voltage of 1 / 2 LSB. Therefore, in the digital domain, it is necessary to inversely compensate for the offset amount corresponding to this offset voltage, i.e., 1 / 2 LSB. That is, the algebraic sum of the second digital compensation signal and the offset amount is 0. Therefore, the second digital compensation signal is the negative half of the least significant bit of the digital input signal, i.e., the second digital compensation signal V... comp2 =-1 / 2LSB. In this way, common-mode noise can be eliminated when the pulse width modulation is odd and the digital input signal is odd, thereby improving the signal-to-noise ratio and helping to improve the accuracy of current detection.

[0154] like Figure 9 As shown, in some exemplary embodiments, the second digital logic module 33 includes an enable submodule 331, an identification submodule 332, and an output submodule 333.

[0155] The enable submodule 331 is used to output an enable signal when the received digital mode signal is a preset first reference value. The digital mode signal represents the pulse width modulation (PWM) mode of the H-bridge drive circuit 10, which includes either an odd-numbered PWM mode or an even-numbered PWM mode. The first reference value is preset to represent the odd-numbered PWM mode; for example, it can be set to 1. When the digital mode signal is 1, it is determined that the H-bridge drive circuit 10 uses an odd-numbered PWM mode, and an enable signal is output accordingly. The specific first reference value can be set according to the actual scenario; for example, it can be set to 0 or other suitable values, and is not limited here. In some exemplary embodiments, the enable submodule 331 may include a comparator. The two inputs of the comparator are used to receive the digital mode signal and the first reference value, respectively. When the comparison result is the same, i.e., the difference between the digital mode signal and the first reference value is 0, the output of the comparator outputs an enable signal.

[0156] The recognition submodule 332 is used to perform parity recognition on the digital input signal, and outputs a second digital compensation signal when the digital input signal is odd. That is, the recognition submodule 332 is used to identify whether the digital input signal is odd or even. If the recognition result is that the digital input signal is odd, the second digital compensation signal is output; if the recognition result is that the digital input signal is even, 0 is output.

[0157] The output submodule 333 is connected to both the enable submodule 331 and the recognition submodule 332. The output submodule 333 outputs a second digital compensation signal upon triggering by the enable signal. In some exemplary embodiments, the output submodule 333 may include a multiplier, which may be connected to both the enable submodule 331 and the recognition submodule 332. The multiplier performs a multiplication operation based on the enable signal and the signal output by the recognition submodule 332, outputting a product operation signal. Specifically, when the signal output by the recognition submodule 332 is the second digital compensation signal, the product operation signal is the second digital compensation signal, i.e., the enable signal is 1; when the signal output by the recognition submodule 332 is 0, the product operation signal is 0, i.e., a scenario without common-mode noise.

[0158] The H-bridge compensation circuit 30 provided in the above embodiment outputs an enable signal when the received digital mode signal is a preset first reference value through the enable submodule 331, performs parity identification on the digital input signal through the identification submodule 332, and outputs a second digital compensation signal when the digital input signal is odd, and outputs the second digital compensation signal when the output submodule 333 is triggered by the enable signal. This achieves effective identification of odd pulse width modulation mode and odd digital input signal, and also achieves accurate compensation for common mode noise under odd pulse width modulation, ensuring the stability of the common mode output voltage of the H-bridge drive circuit 10. It effectively avoids the common mode level offset from being converted into differential output error through the asymmetry of the load 20 or the non-ideal nature of the circuit, significantly improves the signal-to-noise ratio of the H-bridge drive circuit 10, and helps to improve the current detection accuracy.

[0159] Please continue reading. Figure 9 In some exemplary embodiments, the identification submodule 332 includes a modulus-taking unit 3321 and a comparison unit 3322. The modulus-taking unit 3321 performs modulus-taking processing on the digital input signal using a preset modulus-taking base and outputs a modulus-taking output signal. The comparison unit 3322 is connected to the modulus-taking unit 3321 and compares the modulus-taking output signal with a preset second reference value. If the comparison result is the same, it outputs a second digital compensation signal. The comparison unit 3322 can also be used to output 0 if the comparison result is different.

[0160] The modulus base and the second reference value are pre-matched and set to identify whether the digital input signal is odd. The specific values ​​can be set according to actual needs. In some exemplary embodiments, the modulus base is 2 and the second reference value is 0.5. The modulus unit 3321 divides the digital input signal by 2 and takes the remainder, outputting the modulus output signal as the remainder. The comparison unit 3322 compares this remainder with 0.5. If the comparison result is the same (remainder is 0.5), a second digital compensation signal is output; if the comparison result is different (remainder is not 0.5), 0 is output. The second digital compensation signal is -1 / 2 LSB. In other exemplary embodiments, the modulus unit 3321 can directly read and output the least significant bit of the digital input signal. The comparison unit 3322 compares whether the least significant bit is 1. If it is, the second digital compensation signal is output; otherwise, 0 is output. In practical applications, other methods can also be used to determine the parity of the digital input signal; these are only illustrative examples and are not intended to limit the application further.

[0161] The H-bridge compensation circuit 30 provided in the above embodiment performs modulus processing on the digital input signal using a preset modulus base through the identification submodule 332, outputs a modulus output signal, and compares the modulus output signal with a preset second reference value through the comparison unit 3322. If the comparison result is the same, a second digital compensation signal is output. In this way, parity recognition of the digital input signal is realized, and when the digital input signal is odd, a second digital compensation signal corresponding to common-mode noise is output. Thus, in scenarios where odd pulse width modulation is used and the input digital signal is odd, the second digital compensation signal can be used to eliminate common-mode noise, thereby avoiding the influence of common-mode noise on the H-bridge drive circuit 10, improving the signal-to-noise ratio of the H-bridge drive circuit 10, and helping to improve the current detection accuracy.

[0162] It should be noted that the above is merely an exemplary description of common-mode noise compensation in the scenario of odd-numbered pulse width modulation and odd-numbered digital input signals, as described in this application. In practical applications, any other digital logic module capable of recognizing odd-numbered pulse width modulation modes and odd-numbered digital input signals, and outputting a second digital compensation signal, can also be selected, without further limitations.

[0163] Please continue reading. Figure 9 In some exemplary embodiments, the digital output module 32 includes an overlay processing unit 323, a second noise shaping unit 324, and a second digital output unit 325.

[0164] The superposition processing unit 323 is connected to the first digital logic module 31 and the second digital logic module 33, respectively. The superposition processing unit 323 is used to generate a digital superposition signal by superimposing the first digital compensation signal and the second digital compensation signal. In some exemplary embodiments, the superposition processing unit 323 may include an adder, which can perform addition processing on the first and second digital compensation signals to output the digital superposition signal. In other exemplary embodiments, the superposition processing unit 323 may also be configured as a subtractor, and the aforementioned second digital compensation signal may be set to half of the least significant bit of the digital input signal. In practical applications, the units and signals can be flexibly configured according to actual needs, and no limitations are imposed here.

[0165] The second noise shaping unit 324 is connected to the superposition processing unit 323. The second noise shaping unit 324 is used to perform noise shaping on the digital superposition signal and output a second digitally shaped signal. The second noise shaping unit 324 aims to transfer the in-band quantization noise of the second digital compensation signal to the out-of-band, thereby reducing noise and improving the signal-to-noise ratio. That is, it transfers the quantization noise from the low-frequency band to the high-frequency band, thus shifting the quantization noise from the in-band to the out-of-band. In some exemplary embodiments, the second noise shaping unit 324 includes a second DSM, which can convert the second digital compensation signal into a second digitally shaped signal without loss of accuracy, i.e., the quantization noise does not increase within the effective bandwidth; wherein the bit width of the second digitally shaped signal is smaller than the bit width of the second digital compensation signal. It should be noted that the second DSM and the aforementioned first DSM are essentially both DSMs; the distinction between the first and second is only made in different embodiments. The second DSM can also employ... Figure 5 The structure shown is detailed in the preceding description and will not be repeated here.

[0166] The second digital output unit 325 is connected to the second noise shaping unit 324. The second digital output unit 325 is used to compensate the digital input signal according to the second digital shaping signal and output a digital output signal. In some exemplary embodiments, the second digital output unit 325 may include a PWM modulator, which can perform PWM modulation according to the second digital shaping signal and the digital input signal to output a digital output signal.

[0167] The H-bridge compensation circuit 30 provided in the above embodiment generates a digital superimposed signal by superimposing the first digital compensation signal and the second digital compensation signal by the superposition processing unit 323, performs noise shaping on the digital superimposed signal by the second noise shaping unit 324, outputs the second digital shaped signal, and compensates the digital input signal by the second digital output unit 325 based on the second digital shaped signal, outputs the digital output signal. In this way, it realizes the coordinated and accurate compensation of common-mode error and common-mode noise of the H-bridge drive circuit 10. By superimposing the dual compensation signals to cover different error sources, and then optimizing the noise characteristics of the compensation signal by noise shaping, it ensures the accuracy of the compensation action and the purity of the output signal. Understandably, the common-mode error and common-mode noise requiring compensation are very small; that is, the amplitudes of both the second and first digital compensation signals are within the small-signal range. Therefore, after calculating the total compensation amount in the digital domain, i.e., the digital superimposed signal, this application first performs noise shaping on the digital superimposed signal. This transfers the unavoidable quantization noise in the small-amplitude compensation signal to a high-frequency band outside the effective signal bandwidth, preventing the quantization noise from superimposing with the effective signal and causing a decrease in output accuracy. Simultaneously, it ensures that the quantization accuracy of the total compensation amount is not affected by small-signal processing errors. Ultimately, the compensated digital output signal enables the H-bridge driver circuit 10 to maintain a stable common-mode output level, completely canceling the differential output interference caused by common-mode noise, significantly improving the circuit's signal-to-noise ratio and long-term operational stability, and contributing to improved current detection accuracy.

[0168] Please continue reading. Figure 1 , Figure 4 , Figure 6 and Figure 9 In some exemplary embodiments, a power amplifier is provided, which includes an H-bridge drive circuit 10 and an H-bridge compensation circuit 30. The H-bridge drive circuit 10 includes an H-bridge module and a drive module 12, comprising a first half-bridge 111 and a second half-bridge 112. Both the first half-bridge 111 and the second half-bridge 112 include a first switch M1 and a second switch M2. The control terminals of the first switch M1 and the second switch M2 are respectively connected to the drive module 12. The first terminal of the first switch M1 is connected to a power supply terminal, and the second terminal of the second switch M2 is connected to a ground terminal. The second terminal of the first switch M1 and the first terminal of the second switch M2 in the same half-bridge are connected and used to connect to a load 20. The on-resistances of the first switch M1 and the second switch M2 are different. The H-bridge compensation circuit 30 can be any of the H-bridge compensation circuits provided in the foregoing embodiments, as detailed above, and will not be repeated here. The drive module 12 is connected to the digital output module 32 of the H-bridge compensation circuit 30 and is used to drive the H-bridge module according to the analog signal corresponding to the digital output signal output by the digital output module 32.

[0169] The power amplifier provided in the above embodiment addresses the non-ideal factor of the inherent on-resistance difference between the first switch M1 and the second switch M2 in the H-bridge module of the H-bridge drive circuit 10. Through the first digital logic module 31 in the H-bridge compensation circuit 30, it integrates key parameters such as the power supply voltage PVDD, on-resistance difference, load 20 impedance, gain of the H-bridge drive circuit 10, and digital input signal to accurately generate a first digital compensation signal to offset the common-mode error caused by the on-resistance difference. This signal is then compensated by the digital output module 32 in the H-bridge compensation circuit 30 and output to the drive module 12 of the H-bridge drive circuit 10. The drive module 12 drives the H-bridge sub-module based on the compensated signal. This not only achieves precise targeted compensation for the common-mode error caused by the on-resistance difference, effectively avoiding signal distortion caused by such errors and improving current detection accuracy, but also flexibly adapts to application scenarios with different load 20 impedances, power supply conditions, and gain configurations, demonstrating strong applicability. Furthermore, both the first digital logic module 31 and the digital output module 32 of this application are digital circuit structures, that is, signal compensation is realized in the digital domain. Compared with signal compensation in the analog domain, digital circuits have a smaller area, lower hardware design difficulty and cost, and more flexible parameter settings. They can avoid introducing various non-ideal factors of analog circuits, resulting in more stable performance and helping to improve compensation accuracy, thereby improving current detection accuracy.

[0170] Please continue reading. Figure 4 and Figure 9 In some exemplary embodiments, the driving module 12 includes a digital-to-analog converter (DAC) unit 123, a first driving unit 121, and a second driving unit 122. The DAC unit 123 is connected to the digital output module 32 and is used to perform digital-to-analog conversion on the digital output signal, outputting a first analog signal and a second analog signal. The first analog signal and the second analog signal have the same amplitude but opposite polarities. In some exemplary embodiments, the DAC unit 123 may include a digital-to-analog converter (DAC) and an inverter. The DAC is connected to the digital output module 32 and is used to perform digital-to-analog conversion on the digital output signal, outputting a first analog signal. The inverter is connected to the DAC and is used to invert the first analog signal, outputting a second analog signal.

[0171] The first driving unit 121 is connected to the digital-to-analog converter 123. The first driving unit 121 is used to drive the first half-bridge 111 according to the first analog signal. The second driving unit 122 is connected to the digital-to-analog converter 123, and the second driving unit 122 is used to drive the second half-bridge 112 according to the second analog signal. In some exemplary embodiments, the first driving unit 121 can be used to generate a first pulse width modulation signal PWM1 according to the first analog signal, and drive the first switch M1 and the second switch M2 of the first half-bridge 111 according to the first pulse width modulation signal PWM1; the second driving unit 122 can be used to generate a second pulse width modulation signal PWM2 according to the second analog signal, and drive the first switch M1 and the second switch M2 of the second half-bridge 112 according to the second pulse width modulation signal PWM2.

[0172] The power amplifier provided in the above embodiment accurately converts the compensated digital output signal into a first analog signal and a second analog signal with the same amplitude but opposite polarity through a digital-to-analog converter unit 123. The first drive unit 121 and the second drive unit 122 then drive the first half-bridge 111 and the second half-bridge 112 respectively. This not only perfectly matches the core requirements of differential drive in the H-bridge module, ensuring that the working states of the two half-bridges are strictly symmetrical, but also avoids problems such as H-bridge output imbalance, common-mode jitter, and common-mode noise caused by asynchronous drive from the drive source. Furthermore, it efficiently converts the common-mode error compensation effect in the digital domain into a stable output at the analog drive level, further strengthening the cancellation effect on non-ideal factors such as conduction resistance difference, and significantly improving the linearity and stability of the power amplifier output signal. Moreover, this drive method can fully adapt to the needs of high-precision drive scenarios, providing reliable drive support for power amplifiers in applications with stringent output performance requirements, such as high-precision motor control, digital-to-analog conversion, and audio amplification.

[0173] Please continue reading. Figure 4 and Figure 9 In some exemplary embodiments, the first driving unit 121 includes a first amplification subunit 1211 and a first gate driver 1212. The first amplification subunit 1211 is connected to the digital-to-analog converter unit 123. The first amplification subunit 1211 is used to generate a first pulse width modulation signal PWM1 according to the first analog signal. The first gate driver 1212 is used to drive the first half-bridge 111 according to the first pulse width modulation signal PWM1. That is, the first gate driver 1212 can control the opening and closing states of the first switch M1 and the second switch M2 of the first half-bridge 111 according to the first pulse width modulation signal PWM1, so as to provide an output for driving the load 20 and realize the driving of the load 20.

[0174] The second driving unit 122 includes a second amplification subunit 1221 and a second gate driver 1222. The second amplification subunit 1221 is connected to the digital-to-analog converter unit 123. The second amplification subunit 1221 is used to generate a second pulse width modulation signal PWM2 according to the second analog signal. The second gate driver 1222 is used to drive the second half-bridge 112 according to the second pulse width modulation signal PWM2. That is, the second gate driver 1222 can control the opening and closing states of the first switch M1 and the second switch M2 of the second half-bridge 112 according to the second pulse width modulation signal PWM2, so as to provide another output for driving the load 20 and realize the driving of the load 20.

[0175] When the first pulse width modulation signal PWM1 outputs a high level, the first gate driver 1221 drives the second switch M2 of the first half-bridge 111 to turn on and turns off the first switch M1 of the first half-bridge 111. At this time, the first half-bridge 111 outputs a low-level signal, so that the positive terminal of the load 20 receives a low voltage. Conversely, when the first half-bridge 111 outputs a high-level signal, the positive terminal of the load 20 receives a high voltage. Similarly, when the second pulse width modulation signal PWM2 outputs a high level, the second gate driver 1222 drives the second switch M2 of the second half-bridge 112 to turn on and turns off the second switch M2 of the first half-bridge 111. At this time, the second half-bridge 112 outputs a low-level signal, and the negative terminal of the load 20 receives a low voltage. Conversely, when the first half-bridge 111 outputs a high-level signal, the negative terminal of the load 20 receives a high voltage. Therefore, the H-bridge module can switch between the high-high operating state HH, the low-low operating state LL, and the high-low operating state HL through the first pulse width modulation signal PWM1.

[0176] Please continue reading. Figure 4 and Figure 9 In some exemplary embodiments, the first amplification subunit 1211 includes a first integrator D1, a second integrator D2, and a first comparator CP1. The output of the first integrator D1 is connected to the inverting input of the second integrator D2, and the inverting input of the first integrator D1 is connected to a first analog signal. The non-inverting inputs of the first integrator D1 and the second integrator D2 are grounded. The non-inverting input of the first comparator CP1 is connected to the output of the first integrator D1, and the inverting input of the first comparator CP1 is connected to the output of the second integrator D2. The output of the first comparator CP1 is connected to the first gate driver 1221.

[0177] The second amplification subunit 1221 includes a third integrator D3, a fourth integrator D4, and a second comparator CP2. The output of the third integrator D3 is connected to the inverting input of the fourth integrator D4, and the inverting input of the third integrator D3 is connected to a second analog signal. The non-inverting inputs of the third integrator D3 and the fourth integrator D4 are grounded. The non-inverting input of the second comparator CP2 is connected to the output of the third integrator D3, and the inverting input of the second comparator CP2 is connected to the output of the fourth integrator D4. The output of the second comparator CP2 is connected to the first gate driver 1222.

[0178] It should be noted that the first analog signal and the second analog signal can be square wave pulse signals. The first analog signal is converted into a sawtooth wave signal after being integrated by the first integrator D1. The sawtooth wave signal is then converted into a smoother sawtooth wave signal after being processed by the second integrator D2. The two sawtooth wave signals are then processed by the first comparator CP1 to obtain the corresponding first pulse width modulation signal PWM1. The second pulse width modulation signal PWM2 is processed similarly, and will not be elaborated here. It is understandable that the conversion of the square wave pulse signal into a pulse width modulation signal can also be achieved in other ways. For example, the sawtooth wave signal can be compared with a sine or cosine signal to generate a pulse width modulation signal. Thus, the first amplification subunit 1211 can convert the first analog signal into the first pulse width modulation signal PWM1, thereby supporting the driving of the first half-bridge 111 using pulse width modulation. Similarly, the second amplification subunit 1221 can convert the second analog signal into the second pulse width modulation signal PWM2, thereby supporting the driving of the second half-bridge 112 using pulse width modulation.

[0179] Please continue reading. Figure 4 and Figure 9 In some exemplary embodiments, both the first driving unit 121 and the second driving unit 122 further include a feedback resistor Rfb. In the first driving unit 121, the feedback resistor Rfb is connected in series between the input terminal of the first driving unit 121 and the output terminal of the first half-bridge 111, that is, the feedback resistor Rfb is connected in series between the inverting input terminal of the first integrator D1 and the midpoint of the first bridge arm. In the second driving unit 122, the feedback resistor Rfb is connected in series between the input terminal of the second driving unit 122 and the output terminal of the second half-bridge 112, that is, the feedback resistor Rfb is connected in series between the inverting input terminal of the third integrator D3 and the midpoint of the second bridge arm.

[0180] Please continue reading. Figure 9 In some exemplary embodiments, a power amplifier is provided, which includes an H-bridge compensation circuit 30 and an H-bridge drive circuit 10.

[0181] The H-bridge compensation circuit 30 includes a first digital logic module 31, a second digital logic module 33, and a digital output module 32.

[0182] The first digital logic module 31 includes a squaring unit 311, a product unit 312, and a division unit 313. The squaring unit 311 performs squaring operations based on the digital input signal and outputs a squaring output signal. The product unit 312, connected to the squaring unit 311, performs product operations based on the squaring output signal and a product coefficient, and outputs a product output signal. The division unit 313, connected to the product unit 312, performs division operations on the power supply voltage PVDD based on the product output signal, and outputs a first digital compensation signal. The first digital compensation signal is V. in 2 *(R p -R n ) / R L *Gain / PVDD.

[0183] The second digital logic module 33 includes an enable submodule 331, an identification submodule 332, and an output submodule 333. The enable submodule 331 outputs an enable signal when the received digital mode signal is a preset first reference value; the digital mode signal represents the pulse width modulation mode of the H-bridge driver circuit 10. The identification submodule 332 includes a modulus-taking unit 3321 and a comparison unit 3322. The modulus-taking unit 3321 performs modulus-taking processing on the digital input signal using a preset modulus-taking base and outputs a modulus-taking output signal. The comparison unit 3322 is connected to the modulus-taking unit 3321 and compares the modulus-taking output signal with a preset second reference value; if the comparison result is the same, it outputs a second digital compensation signal. The second digital compensation signal V... comp2 =-1 / 2LSB. The output submodule 333 is connected to the enable submodule 331 and the identification submodule 332 respectively, and is used to output the second digital compensation signal when triggered by the enable signal.

[0184] The digital output module 32 includes a superposition processing unit 323, a second noise shaping unit 324, and a second digital output unit 325. The superposition processing unit 323 is connected to both the first digital logic module 31 and the second digital logic module 33, and is used to generate a digital superposition signal by superimposing the first digital compensation signal and the second digital compensation signal. The second noise shaping unit 324 is connected to the superposition processing unit 323 and is used to perform noise shaping on the digital superposition signal, outputting a second digitally shaped signal. The second digital output unit 325 is connected to the second noise shaping unit 324 and is used to compensate the digital input signal based on the second digitally shaped signal, outputting a digital output signal. The second noise shaping unit 324 includes a second DSM (Digital Sounding Model), the structure of which can adopt… Figure 5The fourth-order structure is shown. The second digital output unit 325 includes a PWM modulator.

[0185] The H-bridge drive circuit 10 includes an H-bridge module, a drive module 12, and a current detection module. The H-bridge module includes a first half-bridge 111 and a second half-bridge 112. Both the first half-bridge 111 and the second half-bridge 112 include a first switch M1 and a second switch M2. The control terminals of the first switch M1 and the second switch M2 are respectively connected to the drive module 12. The first terminal of the first switch M1 is connected to the power supply terminal, and the second terminal of the second switch M2 is connected to the ground terminal. The second terminal of the first switch M1 and the first terminal of the second switch M2 in the same half-bridge are connected and used to connect to a load 20, such as a speaker. The on-resistances of the first switch M1 and the second switch M2 are different. Specifically, the first switch M1 includes a PMOS transistor, and the second switch M2 includes an NMOS transistor.

[0186] The driving module 12 includes a digital-to-analog converter unit 123, a first driving unit 121, and a second driving unit 122. The digital-to-analog converter unit 123 is connected to the digital output module 32 and is used to perform digital-to-analog conversion on the digital output signal, outputting a first analog signal and a second analog signal, respectively. The first analog signal and the second analog signal have the same amplitude but opposite polarities. The first driving unit 121 includes a first amplification subunit 1211, a first gate driver, and a feedback resistor Rfb. The first amplification subunit 1211 includes a first integrator, a second integrator, and a first comparator. The second driving unit 122 includes a second amplification subunit 1221, a second gate driver, and a feedback resistor Rfb. The second amplification subunit 1221 includes a third integrator D3, a fourth integrator D4, and a second comparator CP2.

[0187] The current detection module includes two sampling resistors Rsen and a current detection unit. The two sampling resistors Rsen are connected in series between the second terminals of the two second switching transistors M2 and the ground terminal. The current detection unit is connected to the connection point between the two sampling resistors Rsen and the corresponding second switching transistor M2, and is used to detect the current signal.

[0188] Based on the aforementioned power amplifier, under ideal conditions (on-resistance Ron = 0) and practical conditions (on-resistance Rp = 200mΩ for the first switch M1, on-resistance Rn = 100mΩ for the second switch M2, and sampling resistor Rsen = 20mΩ), simulation results are shown in Table 1. Here, SNR represents the signal-to-noise ratio at a 20Ω load current. Furthermore, combined with... Figure 10 The simulation curves shown are illustrated, where the dashed line represents the simulation curve of the power amplifier output signal without compensation under actual conditions, and the solid line represents the simulation curve of the power amplifier output signal of this application under actual conditions. Based on Table 1 and... Figure 10 It can be seen that after the H-bridge compensation circuit 30 provided in this application performs signal compensation in the digital domain, the signal-to-noise ratio of the power amplifier output signal is significantly improved.

[0189] Table 1

[0190]

[0191] In some exemplary embodiments, a chip is provided, including the H-bridge compensation circuit as described in any of the preceding embodiments. In applications, the H-bridge compensation circuit can be packaged as a single chip, which may be a digital chip.

[0192] In some exemplary embodiments, a chip is provided, including the power amplifier described in any of the foregoing embodiments. In applications, the H-bridge compensation circuit and the H-bridge drive circuit can be packaged into a single chip, which may be a chip integrating digital and analog circuitry.

[0193] In some exemplary embodiments, an electronic device is provided, including a load and a chip as described in any of the foregoing embodiments. The load includes, but is not limited to, a speaker, a motor such as a linear motor, a motor such as a DC motor, or other types of loads. The electronic device includes, but is not limited to, handheld devices, in-vehicle devices, wearable devices, computing devices or other processing devices, and various forms of user equipment (UE) such as mobile phones.

[0194] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0195] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An H-bridge compensation circuit, characterized in that, This invention relates to an H-bridge driver circuit, which includes an H-bridge module and a driver module. The H-bridge module includes a first half-bridge and a second half-bridge. Both the first and second half-bridges include a first switch and a second switch. The control terminals of the first and second switches are respectively connected to the driver module. The first terminal of the first switch is connected to a power supply terminal, and the second terminal of the second switch is connected to a ground terminal. The second terminals of the first and second switches in the same half-bridge are connected and used to connect to a load. The on-resistances of the first and second switches are different. The H-bridge compensation circuit includes: The first digital logic module is used to output a first digital compensation signal based on the power supply voltage provided by the power supply terminal, the difference in on-resistance between the first switch and the second switch, the impedance of the load, the gain of the H-bridge drive circuit, and the received digital input signal; the first digital compensation signal is used to compensate for the common-mode error generated by the H-bridge drive circuit due to the difference in on-resistance. A digital output module, connected to the first digital logic module, is used to connect to the driving module and to compensate the digital input signal according to the first digital compensation signal, outputting a digital output signal to instruct the driving module to drive the H-bridge module.

2. The H-bridge compensation circuit according to claim 1, characterized in that, The common-mode error is the difference between the duty cycle when both the first half-bridge and the second half-bridge output a high level and the duty cycle when both output a low level.

3. The H-bridge compensation circuit according to claim 1, characterized in that, The first digital logic module includes: The squaring unit is used to perform squaring operations based on the digital input signal and output a squaring output signal. A product operation unit, connected to the square operation unit, is used to perform a product operation based on the squared output signal and the product coefficients, and output a product output signal; the product coefficients are respectively related to the on-resistance difference, the impedance, and the gain; The division unit, connected to the product unit, is used to perform a division operation on the power supply voltage based on the product output signal and output the first digital compensation signal.

4. The H-bridge compensation circuit according to claim 1, characterized in that, The first digital compensation signal is positively correlated with the digital input signal, the on-resistance difference, and the gain, respectively, and negatively correlated with the impedance and the power supply voltage, respectively.

5. The H-bridge compensation circuit according to claim 4, characterized in that, The first digital compensation signal is expressed by the formula: V comp1 =V in ^2*(R p -R n ) / R L *Gain / PVDD Among them, V comp1 Indicates the first digital compensation signal; V in This represents the digital input signal; (R) p -R n ) represents the difference in conduction resistance, R p R represents the on-resistance of the first switching transistor. n R represents the on-resistance of the second switching transistor; L The impedance is represented by ; Gain represents the gain; and PVDD represents the power supply voltage.

6. The H-bridge compensation circuit according to claim 1, characterized in that, The digital output module includes: The first noise shaping unit is connected to the first digital logic module and is used to perform noise shaping on the first digital compensation signal and output the first digital shaped signal. A first digital output unit, connected to the first noise shaping unit, is used to compensate the digital input signal according to the first digital shaping signal and output the digital output signal.

7. The H-bridge compensation circuit according to claim 1, characterized in that, The H-bridge compensation circuit also includes: The second digital logic module is configured to output a second digital compensation signal when the H-bridge driver circuit uses odd-number pulse width modulation and the digital input signal is odd; the second digital compensation signal is used to compensate for the common-mode noise generated by the H-bridge driver circuit due to the digital input signal; wherein... The digital output module is also connected to the second digital logic module and is used to compensate the digital input signal according to the first digital compensation signal and the second digital compensation signal, and output the digital output signal.

8. The H-bridge compensation circuit according to claim 7, characterized in that, The second digital logic module includes: The enable submodule is used to output an enable signal when the received digital mode signal is a preset first reference value; the digital mode signal is used to represent the pulse width modulation mode of the H-bridge drive circuit. The identification submodule is used to identify the parity of the digital input signal and output the second digital compensation signal when the digital input signal is odd. The output submodule is connected to the enable submodule and the identification submodule respectively, and is used to output the second digital compensation signal when triggered by the enable signal.

9. The H-bridge compensation circuit according to claim 8, characterized in that, The identification submodule includes: The modulus unit is used to perform modulus processing on the digital input signal using a preset modulus base and output a modulus output signal. A comparison unit, connected to the modulus extraction unit, is used to compare the modulus extraction output signal with a preset second reference value, and output the second digital compensation signal if the comparison result is the same.

10. The H-bridge compensation circuit according to claim 7, characterized in that, The digital output module includes: The superposition processing unit is connected to the first digital logic module and the second digital logic module respectively, and is used to generate a digital superposition signal by superimposing the first digital compensation signal and the second digital compensation signal. The second noise shaping unit is connected to the superposition processing unit and is used to perform noise shaping on the digital superposition signal and output a second digital shaped signal. The second digital output unit, connected to the second noise shaping unit, is used to compensate the digital input signal according to the second digital shaping signal and output the digital output signal.

11. The H-bridge compensation circuit according to claim 7, characterized in that, The second digital compensation signal is one-half of the least significant bit of the digital input signal.

12. A power amplifier, characterized in that, include: The H-bridge compensation circuit as described in any one of claims 1-11; The H-bridge driver circuit includes an H-bridge module and a driver module. The H-bridge module includes a first half-bridge and a second half-bridge, each of which includes a first switch and a second switch. The control terminals of the first and second switches are respectively connected to the driver module. The first terminal of the first switch is connected to a power supply terminal, and the second terminal of the second switch is connected to a ground terminal. The second terminals of the first and second switches in the same half-bridge are connected and used to connect to a load. The on-resistances of the first and second switches are different. The driver module is connected to the digital output module of the H-bridge compensation circuit and is used to drive the H-bridge module according to the digital output signal.

13. The power amplifier according to claim 12, characterized in that, The driving module includes: A digital-to-analog converter unit, connected to the digital output module, is used to perform digital-to-analog conversion on the digital output signal and output a first analog signal and a second analog signal; the first analog signal and the second analog signal have the same amplitude but opposite polarities; A first driving unit, connected to the digital-to-analog converter, is used to drive the first half-bridge according to the first analog signal; The second driving unit is connected to the digital-to-analog converter unit and is used to drive the second half-bridge according to the second analog signal.

14. The power amplifier according to claim 13, characterized in that, The H-bridge drive circuit also includes: A current detection module is connected in series between the second terminal of the second switching transistor and the ground terminal, or in series between the first terminal of the first switching transistor and the power supply terminal. The current detection module is used to collect current signals.

15. A chip, characterized in that, Includes the H-bridge compensation circuit as described in any one of claims 1-11, or the power amplifier as described in any one of claims 12-14.

16. An electronic device, characterized in that, Includes the load and the chip as described in claim 15.

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