System and method for scalable modulation and coding scheme (MCS) numbering format

Abstract

The invention relates to a system and method for a scalable modulation and coding scheme (MCS) numbering format. The system may include one or more processors configured to receive a first modulation and coding scheme (MCS) number greater than or equal to 1, and determine from the first MCS number a plurality of bits representing a portion of the first MCS number and a first bit representing a difference between the portion and the first MCS number. The difference may be less than 1. The one or more processors may determine a first MCS parameter set corresponding to the portion of the first MCS number and a second MCS parameter set corresponding to the portion of the first MCS number plus a first predetermined decimal, select a third MCS parameter set from one of the first MCS parameter set or the second MCS parameter set using the first bit, and modulate data using the third set of MCS parameters.

Description

[0001] Cross-reference of related applications

[0002] This application claims the right and priority of U.S. Provisional Patent Application No. 63 / 708,351, filed October 17, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to systems and methods for improving the coding and / or modulation processes of communication systems, determining the fractional representation (or format) of the Modulation Coding Scheme (MCS) number, and / or selecting MCS parameters based on the fractional representation of the MCS number. Background Technology

[0004] The Ultra-High Reliability (UHR) research group within the IEEE 802.11 working group is dedicated to exploring PHY (Physical Layer) and MAC (Media Access Control) technologies aimed at enhancing the reliability of WLAN (Wireless Local Area Network) connectivity. As part of its initiative, UHR (802.11bn) is proposing the addition of new Modulation Codec Scheme (MCS) numbers (or MCS indices). In one approach, adding new MCS numbers involves the process of determining or designing the MCS numbering format. Summary of the Invention

[0005] One embodiment of this disclosure provides a system comprising: one or more processors. The one or more processors are configured to: receive a first modulation and coding scheme (MCS) number greater than or equal to 1; determine from the first MCS number a plurality of bits representing a first portion of the first MCS number and a first bit representing a difference between the first portion and the first MCS number, wherein the difference is less than 1; determine (1) a first MCS parameter set corresponding to the first portion of the first MCS number, and (2) a second MCS parameter set corresponding to the first portion of the first MCS number plus a first predetermined fraction; select a third MCS parameter set from either the first MCS parameter set or the second MCS parameter set using the first bit; and modulate data using the third MCS parameter set.

[0006] Another embodiment of this disclosure provides a system comprising one or more processors. The one or more processors are configured to: receive an MCS scheme whose MCS numbers are not assigned in a set of Modulation and Code Scheme (MCS) numbering schemes; identify the spectral efficiency of the MCS scheme; determine that the spectral efficiency falls between a first spectral efficiency of a first MCS number and a second spectral efficiency of a second MCS number in the set of MCS numbering; determine a fraction between the first MCS number and the second MCS number as a third MCS number; and use the set of MCS numbering and the third MCS number to modulate data.

[0007] Another embodiment of this disclosure provides a method. The method includes: receiving a first modulation and coding scheme (MCS) number greater than or equal to 1 by one or more processors; determining, by the one or more processors, a plurality of bits representing a first portion of the first MCS number and a first bit representing the difference between the first portion and the first MCS number, wherein the difference is less than 1; determining, by the one or more processors, (1) a first MCS parameter set corresponding to the first portion of the first MCS number, and (2) a second MCS parameter set corresponding to the first portion of the first MCS number plus a first predetermined decimal; selecting, by the one or more processors, a third MCS parameter set from either the first MCS parameter set or the second MCS parameter set using the first bit; and modulating data using the third MCS parameter set by the one or more processors. Attached Figure Description

[0008] The various objects, aspects, features, and advantages of this disclosure will become clearer and better understood through a detailed description taken in conjunction with the accompanying drawings, wherein like reference characters identify corresponding elements throughout. In the drawings, like reference numerals generally indicate like, functionally similar, and / or structurally similar elements.

[0009] Figure 1 It is a diagram depicting an instance communication environment having a communication system according to one or more embodiments.

[0010] Figure 2 It is a schematic block diagram of a computing system according to one or more embodiments.

[0011] Figure 3 It is a diagram depicting a transmitter including a parameter selector according to one or more embodiments.

[0012] Figure 4A and Figure 4B It is a diagram depicting the decimal representation of the Modulation Code Scheme (MCS) number according to one or more embodiments.

[0013] Figures 5A to 5CIt is a diagram depicting a first instance MCS number set according to one or more embodiments.

[0014] Figure 6 A table showing the second instance MCS number set according to one or more embodiments.

[0015] Figure 7 A table showing the instruction set of third instance MCS numbers according to one or more embodiments.

[0016] Figure 8 A table showing the fourth instance MCS number set according to one or more embodiments.

[0017] Figure 9 It is a diagram depicting an instance parameter selector that receives a 5-bit MCS number according to one or more embodiments.

[0018] Figure 10 This is a diagram depicting another instance of a parameter selector that receives a 6-bit MCS number according to one or more embodiments.

[0019] Figure 11 This is a flowchart illustrating the process of selecting MCS parameters based on the decimal representation of the MCS number, according to an embodiment.

[0020] Figure 12 This is a flowchart illustrating the process for determining the decimal representation of the MCS number according to an embodiment.

[0021] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating or communicatively coupled to a second feature may include embodiments in which the first feature directly communicates with or is directly coupled to the second feature, and may also include embodiments in which an additional feature may be located between the first and second features, such that the first feature indirectly communicates with or is indirectly coupled to the second feature. Additionally, reference numerals and / or letters may be repeated throughout the disclosure. This repetition is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] The following IEEE standards (including any draft versions of such standards) are hereby incorporated herein by reference in their entirety and are part of this disclosure for all purposes: the WiFi Alliance standards and the IEEE 802.11 standards, including but not limited to IEEE 802.11a™, IEEE 802.11b™, IEEE 802.11g™, IEEE P802.11n™; IEEE P802.11ac™; and IEEE P802.11be™ to IEEE P802.11bn™ standards. Although this disclosure may refer to aspects of these standards, this disclosure is in no way limited to these standards.

[0024] refer to Figure 1 This illustration depicts an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes a baseband circuit system 110 and a transmitter circuit system 120, and communication system 108 includes a baseband circuit system 150 and a receiver circuit system 140. In one aspect, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more than Figure 1 The components shown may be more, fewer, or different. For example, each of communication systems 105, 108 includes a transceiver circuitry to allow bidirectional communication between or with other communication systems. In some embodiments, each of communication systems 105, 108 may have, for example, more, fewer, or different components. Figure 2 The configuration shown in the image is similar to that of the computing system 2000.

[0025] The baseband circuitry system 110 of the communication system 105 is a circuitry system that generates baseband data 115 for transmission. The baseband data 115 contains information data (e.g., signals) at a baseband frequency for transmission. In one method, the baseband circuitry system 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. A parity bit (or parity data) associated with a set of bits refers to an error detection code indicating whether the total number of 1 bits in a set of bits is even or odd. In one aspect, the baseband circuitry system 110 (or encoder 130) obtains a generator matrix or a parity matrix, or uses a previously generated generator matrix or a previously generated parity matrix, and encodes the information data by applying the information data to the generator matrix or parity matrix to obtain codewords. In some embodiments, the baseband circuitry system 110 stores one or more generator matrices or one or more parity matrices conforming to any IEEE 802.11 standard for WLAN communication. The baseband circuit system 110 retrieves a stored generator matrix or a stored parity matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one method, the baseband circuit system 110 generates parity bits based on a portion of the generator matrix or using the parity matrix, and appends the parity bits to information bits to form a codeword. Information bits refer to any binary data input to an encoder to generate binary encoded data based on binary input data. The baseband circuit system 110 generates baseband data 115 containing codewords for the communication system 108 and provides the baseband data 115 to the transmitter circuit system 120.

[0026] The transmitter circuitry 120 of the communication system 105 includes or corresponds to a circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a wireless signal 125 based on the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 up-converts the baseband data 115 from the baseband circuitry 110 to a carrier signal to generate a wireless signal 125 at an RF frequency (e.g., 10 MHz to 60 GHz), and transmits the wireless signal 125 through the antenna.

[0027] The receiver circuitry 140 of communication system 108 is a circuitry that receives radio signal 125 from communication system 105 and obtains baseband data 145 from the received radio signal 125. In one configuration, receiver circuitry 140 is coupled between baseband circuitry 150 and an antenna (not shown). In this configuration, receiver circuitry 140 receives radio signal 125 through the antenna and down-converts the radio signal 125 to a carrier signal at an RF frequency to obtain baseband data 145 from the radio signal 125. Receiver circuitry 140 then provides the baseband data 145 to baseband circuitry 150.

[0028] The baseband circuitry system 150 of the communication system 108 includes or corresponds to a circuitry system that receives baseband data 145 from the receiver circuitry system 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry system 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain information data generated by the baseband circuitry system 110 of the communication system 105.

[0029] In some embodiments, each of the baseband circuit system 110 (including encoder 130), transmitter circuit system 120, receiver circuit system 140, and baseband circuit system 150 (including decoder 160) may be one or more processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof.

[0030] Figure 2 This is a schematic block diagram of a computing system according to an embodiment. The illustrated example computing system 2000 includes one or more processors 2010 that communicate directly or indirectly with memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components (e.g., input / output (“I / O”) components 2050). Typically, the processors 2010 execute instructions (or computer programs) received from memory. The illustrated processors 2010 are incorporated into or connected to cache memory 2020. In some examples, instructions are read from memory 2060 into cache memory 2020 and executed by processor 2010 from cache memory 2020. The computing system 2000 may not necessarily contain... Figure 2 All of these components are shown in the image, and may contain... Figure 2 Other components not shown in the image.

[0031] More specifically, processor 2010 may be any logic circuit system that processes instructions (e.g., instructions fetched from memory 2060 or cache memory 2020). In many embodiments, processor 2010 is a microprocessor unit or a dedicated processor. Computing device 2000 may be based on any processor or processor group capable of operating as described herein. Processor 2010 may be a single-core or multi-core processor. Processor 2010 may be multiple different processors.

[0032] Memory 2060 may be any device suitable for storing computer-readable data. Memory 2060 may be a device with fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and storage devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or Blu-ray® optical disks). Computing system 2000 may have any number of memory devices 2060.

[0033] Cache memory 2020 is typically a form of computer memory placed close to processor 2010 for fast read times. In some embodiments, cache memory 2020 is part of processor 2010 or on the same chip as processor 2010. In some embodiments, there are multiple levels of cache memory 2020, such as L2 and L3 cache memories.

[0034] Network interface controller 2030 manages data exchange via a network interface (sometimes referred to as a network interface port). Network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some of the tasks of the network interface controller are handled by one or more processors 2010. In some embodiments, network interface controller 2030 is part of processor 2010. In some embodiments, computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point of a physical network link (e.g., a Cat-5 Ethernet link). In some embodiments, network interface controller 2030 supports wireless network connectivity, and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for the IEEE 802.11 protocol, Near Field Communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, network interface controller 2030 implements one or more network protocols, such as Ethernet. Typically, computing device 2000 exchanges data with other computing devices via a network interface through a physical or wireless link. The network interface can be directly linked to another device or linked to another device via an intermediary device (e.g., a network device that connects computing device 2000 to a data network such as the Internet, such as a hub, bridge, switch, or router).

[0035] The computing system 2000 may include one or more input or output (“I / O”) devices, or provide interfaces for one or more input or output (“I / O”) devices. Input devices include, but are not limited to, keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, refreshable Braille terminals, indicator lights, MIDI devices, and 2D or 3D printers.

[0036] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, computing system 2000 may include interfaces (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., portable flash drives or external media drives). In some embodiments, computing device 2000 includes additional devices such as coprocessors; for example, a math coprocessor may assist processor 2010 in performing high-precision or complex calculations.

[0037] Component 2050 can be configured to connect to external media, display 2070, input device 2080, or any other component or combination thereof in computing system 2000. Display 2070 can be a liquid crystal display (LCD), organic light-emitting diode (OLED) display, flat panel display, solid-state display, cathode ray tube (CRT) display, projector, printer, or other known or subsequently developed display device for outputting defined information. Display 2070 can serve as an interface for a user to view the functionality of processor 2010, or specifically as an interface to software stored in memory 2060.

[0038] Input device 2080 can be configured to allow a user to interact with any component of computing system 2000. Input device 2080 can be a keypad, keyboard, cursor control device (e.g., mouse or joystick). Alternatively, input device 2080 can be a remote control, touchscreen display (which can be a combination of display 2070 and input device 2080), or any other device operable to interact with computing system 2000, such as any device operable as an interface between the user and computing system 2000.

[0039] In one area, the UHR research group within the IEEE 802.11 working group is dedicated to exploring PHY and MAC technologies aimed at enhancing the reliability of WLAN connectivity. As part of its initiative, UHR (802.11bn) is proposing the addition of new Modulation Codec Scheme (MCS) numbers (or MCS values ​​or MCS indices). Existing Wi-Fi standards (e.g., EHT-SIG (Extremely High Throughput Signaling) or Wi-Fi 7) support MCS values ​​from 0 to 15, requiring 4 bits for representation. An MCS number is a number, value, index, or identifier that identifies the modulation scheme and / or codec scheme used to transmit data from a wireless device, or identifies a set of MCS parameters containing at least one of the following: modulation type, code rate, data rate, number of spatial streams, channel width, or guard interval. The current 4-bit representation is insufficient for the new MCS numbers in upcoming Wi-Fi standards (e.g., UHR or Wi-Fi 8). In one approach, adding new MCS numbers involves the process of determining or designing a new MCS number format. The new MCS numbering format may need to be expanded from the current 4-digit MCS format in EHT-SIG to a 5-digit format. The new MCS numbering format may require promoting the modularization and gradual addition of new MCS numbers.

[0040] To address these issues, embodiments of this disclosure, according to certain aspects, relate to a technique for determining the fractional representation (or format) of a Modulation Codec (MCS) number and / or selecting MCS parameters based on the fractional representation of the MCS number. In some implementations, a 5-bit representation can be used to add four additional MCS numbers to an existing MCS number (e.g., the MCS number in an existing Wi-Fi standard). As the number of MCS numbers increases over time, a 5-bit representation can be used to add more MCS numbers to an existing MCS number.

[0041] In some implementations, an extensible MCS numbering format (e.g., UHR MCS numbering format) can be used to represent decimals (or fractional numbers). In some implementations, the MCS numbering format can be a Q numbering format or Q notation. Q notation refers to a way of specifying parameters for a binary fixed-point number format. For example, a numbering format represented by "Qm.n" indicates that the fixed-point number in this format has m bits for the integer part and n bits for the fractional part (m and n are integers).

[0042] In some implementations, the 5-bit MCS number format (or representation) allows for the incorporation of additional MCS numbers without disrupting existing designs or previous MCS numbering. In some implementations, MCS logic (e.g., an MCS parameter selector circuitry) can receive an MCS number and output a set of MCS parameters corresponding to that MCS number (e.g., code rate, quadrature amplitude modulation (QAM) size, data rate, etc.). In some implementations, a system (e.g., communication systems 105, 108) can incorporate new MCS logic (e.g., an MCS circuitry for a new 5-bit MCS number format) by copying existing MCS logic (e.g., an MCS circuitry for a previous 4-bit MCS number format) along with control logic (e.g., a control circuitry) based on the most significant bit (MSB) (e.g., the 5th bit in the 5-bit MCS number format). This method ensures that all existing MCS numbers remain unchanged. For example, in response to receiving an existing MCS number (e.g., a non-UHR or former UHR MCS number), the new MCS logic can read only the four least significant bits (LSB) of the MCS number and continue further processing. In some implementations, the new MCS logic and / or control logic may be implemented in the MCS table. In some implementations, the new MCS logic and / or control logic may be implemented in software, firmware, processor, circuit system, and / or combinations thereof.

[0043] In some implementations, the new MCS logic can be hardware-friendly, allowing existing hardware (e.g., hardware corresponding to existing MCS logic) to remain unchanged while accommodating the new MCS number with minimal modifications. In other implementations, the existing MCS logic can remain unchanged, with new MCS logic added separately for the additional MCS number. This approach enables modular design and easy integration of new MCS numbering without affecting existing hardware, making integration more efficient and cost-effective.

[0044] In some implementations, 5 bits can be used to represent the additional (new) MCS number, thus maintaining the existing four-bit structure and adding new bits for the new MCS number. In some implementations, the transition from four to five bits can be achieved by setting the new bit to 0 while retaining the existing MCS number (0 to 15), and the new MCS number can be achieved by setting the new bit to 1. In some implementations, the mapping and representation of the new MCS number can use decimal representation to indicate characteristics associated with the new MCS number (e.g., effective data rate, spectral efficiency, error vector magnitude (EVM), etc.). Effective data rate refers to the actual rate at which data can be successfully transmitted via a wireless network, taking into account various factors such as signal quality, interference, and / or network congestion. Spectral efficiency refers to the capability or characteristic of a wireless communication system, measured in bits per second per hertz (bps / Hz), to transmit data on a given bandwidth in a manner that maximizes the use of available spectrum, or to efficiently utilize the spectrum. EVM refers to a measurement representing the deviation of the received signal from the ideal constellation point or any measurement representing the difference between the ideal signal and the actual transmitted signal.

[0045] For example, as the MCS number increases, the corresponding effective data rate (or spectral efficiency or EVM) can also increase. In some implementations, the new MCS number can be represented as a fraction between existing MCS numbers. For example, an MCS number whose effective data rate falls between the effective data rate corresponding to MCS number 1 and the effective data rate corresponding to MCS number 2 can be represented as 1.5 between 1 and 2. An MCS number whose effective data rate falls between the effective data rate corresponding to MCS number 2 and the effective data rate corresponding to MCS number 3 can be represented as 2.5 between 2 and 3.

[0046] In some implementations, given an existing MCS number, a new MCS number in 5-bit MCS format may include a new bit (or control bit, fractional bit, or extra bit) and the existing 4 bits corresponding to the existing MCS number. In some implementations, the new bit of the new MCS number may be set to 1, while the existing 4 bits of the new MCS remain unchanged (e.g., the same as the existing 4 bits of the MCS number), thereby allowing a clear distinction between the existing and new MCS numbers. In this way, all existing MCS numbers (e.g., pre-UHR MCS numbers) can be represented in 5-bit MCS format as integers from 0 to 15.

[0047] In some implementations, the 5-bit MCS format may include control bits to append additional MCS numbers. In some implementations, the control bit is the most significant bit (MSB) of a plurality of bits. In some implementations, the 5-bit MCS format can add up to 16 new MCS numbers compared to the 4-bit MCS format. In some implementations, the new MCS numbers in the 5-bit MCS format may be positioned between existing MCS numbers (in the 4-bit MCS format), including the MCS number at the highest data rate (e.g., existing MCS number 13 in the pre-UHR 4-bit MCS format corresponding to a maximum data rate of 10.0 bps). In some implementations, the MCS format may extend the MCS number by including one or more decimal places (e.g., new bits, control bits, extra bits) so that the spectral efficiency (bps / Hz) can be monotonically set as the MCS number increases. In some implementations, the MCS format may provide a means for future expansion by adding extra bits to the MSB, thereby doubling the resolution with each extra bit. For example, the 6-bit MCS format can maintain an MCS resolution of 0.25, while the 5-bit MCS format offers a resolution of 0.5.

[0048] In some implementations, a new MCS number (e.g., a UHR MCS number) expands an existing MCS number (e.g., a pre-UHR MCS number) to include decimals, while all existing MCS numbers remain unchanged as integers from 0 to 15. This approach allows for the insertion of new MCS numbers (e.g., MCS values, MCS indices, MCS levels) between existing MCS numbers. For example, an MCS number “m.5” (where m is an integer in the range of 0 to 15) can produce an effective data rate between the effective data rates of the pre-UHR MCS number m and m+1.

[0049] In some implementations, using fractional mapping for new MCS numbers ensures consistency in spectral efficiency, effective data rate, and / or EVM, allowing the new MCS numbers to seamlessly align with existing MCS numbers in terms of spectral efficiency, effective data rate, and / or EVM. This fractional approach aligns well with the ordering of spectral efficiency, effective data rate, and / or EVM across MCS ranges, as is the case with existing MCS numbers (e.g., pre-UHR MCS numbers). In some implementations, equivalent integer mapping ensures that all existing MCS numbers (e.g., pre-UHR numbers) remain unchanged. In some implementations, a fractional MCS number “m.5” (where m is an integer in the range from 0 to 15) can be mapped to “16 + floor(m.5)”. For example, MCS number 1.5 can be mapped to 17.

[0050] In some implementations, the system (e.g., a communication system, a transmitter system) may include a (MCS) parameter selector, a forward error correction (FEC) manager, a modulator (MOD), and / or an orthogonal frequency division multiple access (OFDMA) manager. Each of the MCS parameter selector, FEC manager, modulator, and OFDMA manager may be implemented in software, firmware, hardware circuitry, one or more processors, or a combination thereof.

[0051] In some implementations, the parameter selector may receive an MCS number (e.g., MCS index, MCS value, MCS identifier) ​​and output an MCS parameter set (e.g., modulation type, modulation size such as QAM size, code rate, data rate, number of spatial streams, channel width, or guard interval). Modulation size refers to the QAM size or the number of different symbols that can be transmitted using a specific modulation scheme (e.g., a specific QAM scheme). In some implementations, the parameter selector may use a table (e.g., an MCS table) storing information about the relationship between MCS numbers and corresponding MCS parameter sets to identify or obtain the MCS parameter set. In some implementations, the parameter selector may provide one or more write code parameters (e.g., code rate) to the FEC manager, one or more modulation parameters (e.g., modulation size or QAM size, data rate) to the modulator, and / or one or more channel parameters (e.g., channel width) to the OFDMA manager.

[0052] In some implementations, in response to receiving a data payload, the FEC manager can encode the data payload using one or more write-code parameters to generate encoded data. In some implementations, the FEC manager can encode the data payload using low-density parity-check (LDPC) codes. In some implementations, the modulator can use one or more modulation parameters to modulate the encoded data to generate modulated data. In some implementations, the OFDMA manager can use one or more channel parameters to perform channel modulation on the modulated data to define, allocate, or configure resource units (RUs). A resource unit refers to a group of subcarriers or tones within an OFDMA channel, or any frequency bandwidth unit within the frequency bandwidth of a communication channel or communication system. In some implementations, the system (e.g., a transmitter) can use defined, allocated, or configured RUs to transmit the modulated data as one or more frames.

[0053] In some implementations, the 5-bit MCS format may treat or use the most significant bit (MSB) (e.g., bit 5 or b4) as a fractional part. In some implementations, a 5-bit MCS format with one fractional part may be represented by Q4,1 or B(4,1). This design or approach allows for a possible range of MCS numbers within the 5-bit MCS format. Furthermore, the design facilitates a potential expansion of up to 16 or more MCS numbers, providing greater flexibility and scalability for future enhancements. For example, the 5-bit MCS format may contain 5 bits represented by bi (i=0, 1, …, 4), which includes an integer part IP and a fractional part FP as follows:

[0054] ………… (Equation 1).

[0055] ………… (Equation 2).

[0056] In some implementations, the MCS number, which is in standard integer form (format) u (also represented by MCS (int) or nMCS), can be obtained or calculated from the 5-bit MCS format as follows:

[0057] ………… (Equation 3).

[0058] In some implementations, the MCS number, in floating-point form v (also represented by Q4,1, B(4,1), or MCS (float), can be obtained or calculated from the 5-bit MCS format as follows:

[0059] ………… (Equation 4).

[0060] Table 1 shows the standard integer (MCS(int)) and Q4,1 floating-point number (MCS(Q4,1)) of each of the 5-digit values ​​calculated using Equations 3 and 4.

[0061] index bit (Q4,1) MCS(int) MCS(Q4,1) 1 [0, 0, 0, 0, 0] 0 0.0 2 [0, 0, 0, 0, 1] 1 1.0 3 [0, 0, 0, 1, 0] 2 2.0 4 [0, 0, 0, 1, 1] 3 3.0 5 [0, 0, 1, 0, 0] 4 4.0 6 [0, 0, 1, 0, 1] 5 5.0 7 [0, 0, 1, 1, 0] 6 6.0 8 [0, 0, 1, 1, 1] 7 7.0 9 [0, 1, 0, 0, 0] 8 8.0 10 [0, 1, 0, 0, 1] 9 9.0 11 [0, 1, 0, 1, 0] 10 10.0 12 [0, 1, 0, 1, 1] 11 11.0 13 [0, 1, 1, 0, 0] 12 12.0 14 [0, 1, 1, 0, 1] 13 13.0 15 [0, 1, 1, 1, 0] 14 14.0 16 [0, 1, 1, 1, 1] 15 15.0 17 [1, 0, 0, 0, 0] 16 0.5 18 [1, 0, 0, 0, 1] 17 1.5 19 [1, 0, 0, 1, 0] 18 2.5 20 [1, 0, 0, 1, 1] 19 3.5 21 [1, 0, 1, 0, 0] 20 4.5 22 [1, 0, 1, 0, 1] 21 5.5 23 [1, 0, 1, 1, 0] 22 6.5 24 [1, 0, 1, 1, 1] 23 7.5 25 [1, 1, 0, 0, 0] 24 8.5 26 [1, 1, 0, 0, 1] 25 9.5 27 [1, 1, 0, 1, 0] 26 10.5 28 [1, 1, 0, 1, 1] 27 11.5 29 [1, 1, 1, 0, 0] 28 12.5 30 [1, 1, 1, 0, 1] 29 13.5 31 [1, 1, 1, 1, 0] 30 14.5 32 [1, 1, 1, 1, 1] 31 15.5

[0062] Table 1. Standard integers (MCS(int)) and Q4,1 floating-point numbers (MCS(Q4,1)) in 5-bit MCS format.

[0063] In some implementations, four MCS numbers in 5-bit MCS format can be added to existing MCS numbers (e.g., MCS numbers for EHT / 802.11be corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping (e.g., an MCS mapping for UHR). In some implementations, MCS numbers 1.5, 3.5, 4.5, and 7.5 (corresponding to indices 18, 20, 21, and 24 in Table 1) can be added to MCS numbers 0 to 15 (corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping. The new MCS mapping can be represented as an MCS table, which displays each MCS number associated with a control bit (e.g., MSB or MCS[4]), a 4-bit value (e.g., MCS[3:0]), modulation type, code rate, and / or effective data rate.

[0064] In some implementations, MCS number 1.5 (equivalent to 17 in integer form or integer representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps = 1.33); MCS number 3.5 (equivalent to 19 in integer form or integer representation) may correspond to the MCS parameter (16-QAM, R=2 / 3, bps = 2.67); MCS number 4.5 (equivalent to 20 in integer form or integer representation) may correspond to the MCS parameter (16-QAM, R=5 / 6, bps = 3.33); and MCS number 7.5 (equivalent to 23 in integer form or integer representation) may correspond to the MCS parameter (256-QAM, R=2 / 3, bps = 5.33). In some implementations, each of the added MCS numbers 1.5, 3.5, 4.5, and 7.5 can be strategically placed between two existing MCS numbers, such that the new MCS number produces a data rate between the data rates of the two existing MCS numbers. For example, MCS number 1.5 has a data rate of 1.33, which is between 1 (i.e., the data rate of MCS number 1) and 1.5 (i.e., the data rate of MCS number 2). This approach allows for a smooth transition and integration of the new MCS number within the existing MCS numbers.

[0065] In some implementations, a set of four distinct MCS numbers in a 5-digit MCS format can be added to existing MCS numbers (e.g., MCS numbers for EHT / 802.11be corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping (e.g., an MCS mapping for UHR). In some implementations, MCS numbers 0.5, 1.5, 3.5, and 7.5 (corresponding to indices 17, 18, 20, and 24 in Table 1) can be added to MCS numbers 0 to 15 (corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping. In some implementations, MCS number 0.5 (equivalent to 16 in integer form or integer representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps = 0.67); MCS number 1.5 (equivalent to 17 in integer form or integer representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps = 1.33); MCS number 3.5 (equivalent to 19 in integer form or integer representation) may correspond to the MCS parameter (16-QAM, R=2 / 3, bps = 2.67); and MCS number 7.5 (equivalent to 23 in integer form or integer representation) may correspond to the MCS parameter (256-QAM, R=2 / 3, bps = 5.33). In some implementations, each of the added MCS numbers 0.5, 1.5, 3.5, and 7.5 can be strategically placed between two existing MCS numbers, such that the new MCS number produces a data rate between the data rates of the two existing MCS numbers. This approach allows for a smooth transition and integration of the new MCS number within the existing MCS numbering system.

[0066] In some implementations, six MCS numbers in 5-digit MCS format can be added to existing MCS numbers (e.g., MCS numbers for EHT / 802.11be corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping (e.g., an MCS mapping for UHR). In some implementations, MCS numbers 0.5, 1.5, 2.5, 3.5, 4.5, and 7.5 (corresponding to indices 17, 18, 19, 20, 21, and 24 in Table 1) can be added to MCS numbers 0 to 15 (corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping. In some implementations, MCS number 0.5 (equivalent to 16 in integer form or representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps=0.67); MCS number 1.5 (equivalent to 17 in integer form or representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps = 1.33); MCS number 2.5 (equivalent to 18 in integer form or representation) may correspond to the MCS parameter (QPSK, R=5 / 6, bps=1.67); MCS number 3.5 (equivalent to 19 in integer form or representation) may correspond to the MCS parameter (16-QAM, R=2 / 3, bps = 2.67); MCS number 4.5 (equivalent to 20 in integer form or representation) may correspond to the MCS parameter (16-QAM, R=5 / 6, bps = 3.33); and MCS number 7.5 (Equivalent to 23 in integer form or representation) corresponds to the MCS parameter (256-QAM, R=2 / 3, bps=5.33). In some implementations, each of the added MCS numbers 0.5, 1.5, 2.5, 3.5, 4.5, and 7.5 can be strategically placed between two existing MCS numbers, such that the new MCS number produces a data rate between the data rates of the two existing MCS numbers. This method allows for a smooth transition and integration of the new MCS number within the existing MCS numbers.

[0067] In some implementations, eight MCS numbers in 5-digit MCS format can be added to existing MCS numbers (e.g., MCS numbers for EHT / 802.11be corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping (e.g., an MCS mapping for UHR). In some implementations, MCS numbers 0.5, 1.5, 2.5, 3.5, 4.5, 7.5, 11.5, and 13.5 (corresponding to indices 17, 18, 19, 20, 21, 24, 28, and 30 in Table 1) can be added to MCS numbers 0 to 15 (corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping. In some implementations, MCS number 0.5 (equivalent to 16 in integer form or representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps=0.67); MCS number 1.5 (equivalent to 17 in integer form or representation) may correspond to the MCS parameter (QPSK, R=2 / 3, bps = 1.33); MCS number 2.5 (equivalent to 18 in integer form or representation) may correspond to the MCS parameter (QPSK, R=5 / 6, bps=1.67); MCS number 3.5 (equivalent to 19 in integer form or representation) may correspond to the MCS parameter (16-QAM, R=2 / 3, bps = 2.67); MCS number 4.5 (equivalent to 20 in integer form or representation) may correspond to the MCS parameter (16-QAM, R=5 / 6, bps = 3.33); MCS number 7.5 (Equivalent to 23 in integer form or representation) corresponds to MCS parameters (256-QAM, R=2 / 3, bps=5.33); MCS number 11.5 (equivalent to 27 in integer form or representation) corresponds to MCS parameters (1K-QAM, R=7 / 8, bps=8.75); and MCS number 13.5 (equivalent to 29 in integer form or representation) corresponds to MCS parameters (4K-QAM, R=7 / 8, bps=10.5). In some implementations, each of the added MCS numbers 0.5, 1.5, 2.5, 3.5, 4.5, 7.5, 11.5, and 13.5 can be strategically placed between two existing MCS numbers, such that the new MCS number produces a data rate between the data rates of the two existing MCS numbers. This method allows for a smooth transition and integration of the new MCS number within the existing MCS numbers.

[0068] In some implementations, the (MCS) parameter selector may include a first parameter selector, which includes first MCS logic, second MCS logic, and a 2x1 multiplexer. In some implementations, the parameter selector may receive an MCS number bi (i=0,1,…,4) in a 5-bit MCS format, including MSB b4. In some implementations, the first MCS logic may be pre-UHR MCS logic or 4-bit MCS logic. In some implementations, the second MCS logic may be UHR additional MCS logic or 5-bit MCS logic. In some implementations, the parameter selector may provide MSB b4 to the 2x1 multiplexer and a 4-bit MCS number b to the first parameter selector. i (i=0,1,2,3). In some implementations, the first parameter selector may receive a 4-bit MCS number b. i (i=0,1,2,3), the first MCS parameter set is calculated using the first MCS logic and provided to the 2x1 multiplexer. In some implementations, the first MCS logic may use a table (e.g., having a table with...). Figure 5B The table structure shown is similar to that of a table in 4-digit MCS format. In some implementations, the parameter selector can use a second MCS logical calculation corresponding to the 4-digit MCS number b. i A second MCS parameter set (i=0,1,2,3) is provided to the 2x1 multiplexer. In some implementations, the second MCS logic can use a table (e.g., with...) Figure 5B The table shown is similar to a table in a 5-bit MCS format. In some implementations, the 2x1 multiplexer can determine whether MSB b4 is equal to 0 or 1. In response to determining that MSB b4 is equal to 0, the 2x1 multiplexer can generate a first set of MCS parameters as output. In response to determining that MSB b4 is equal to 1, the 2x1 multiplexer can generate a second set of MCS parameters as output.

[0069] The 5-bit MCS format or 5-digit fractional MCS representation offers several advantages. Existing 4-bit MCS logic prior to the UHR (e.g., the first MCS logic) can remain unchanged. New MCS logic (e.g., the second MCS logic) can be added by following the same bit-width rules. This pre-UHR MCS logic and additional (new) MCS logic can be seamlessly integrated using control logic based on the MSB of the 5-bit MCS representation. Using fractional MCS representation, MCS numbering and spectral efficiency behavior remain similar to the pre-UHR MCS logic. The 5-bit MCS format allows for modular hardware design. Given that the MCS logic is connected to many blocks in the system, modular hardware design avoids numerous design verification (DV) cycles.

[0070] In some implementations, the (MCS) parameter selector may include a first parameter selector, which includes first MCS logic, second MCS logic, third MCS logic, a first 2x1 multiplexer, and a second 2x1 multiplexer. In some implementations, the parameter selector may receive an MCS number b in 6-bit MCS format, including MSB b5 and a second MSB b4. i (i=0,1, …, 5). In some implementations, the first MCS logic may be pre-UHR MCS logic or 4-bit MCS logic. In some implementations, the second MCS logic may be UHR additional MCS logic or 5-bit MCS logic. In some implementations, the third MCS logic may be 6-bit MCS logic.

[0071] In some implementations, the parameter selector may provide MSB b5 to the second 2x1 multiplexer, the second MSB b4 to the first 2x1 multiplexer, and a 4-bit MCS number b to the first parameter selector. i (i=0,1,2,3). In some implementations, the first parameter selector may receive a 4-bit MCS number b. i (i=0,1,2,3), the first MCS parameter set is calculated using the first MCS logic and provided to the first 2x1 multiplexer. In some implementations, the first MCS logic may use a table (e.g., having a table with...). Figure 5B The table structure shown is similar to that of a table in 4-digit MCS format. In some implementations, the parameter selector can use a second MCS logical calculation corresponding to the 4-digit MCS number b. i A second MCS parameter set (i=0,1,2,3) is provided to the first 2x1 multiplexer. In some implementations, the second MCS logic may use a table (e.g., with...). Figure 5B The table shown is similar to a table in a 5-bit MCS format. In some implementations, the first 2x1 multiplexer can determine whether the second MSB b4 is equal to 0 or 1. In response to determining that the second MSB b4 is equal to 0, the first 2x1 multiplexer can generate a first MCS parameter set as output. In response to determining that the MSB b4 is equal to 1, the first 2x1 multiplexer can generate a second MCS parameter set as output.

[0072] In some implementations, the parameter selector can use a third MCS logic calculation to correspond to the 4-bit MCS number b. i The third MCS parameter set (i=0,1,2,3) is provided to the second 2x1 multiplexer. In some implementations, the third MCS logic may use a table (e.g., having a table with...) Figure 5BThe table structure shown is similar to that of a table in 6-bit MCS format. In some implementations, the second 2x1 multiplexer can determine whether MSB b5 is equal to 0 or 1. In response to determining that MSB b5 is equal to 0, the second 2x1 multiplexer can generate the output of the first 2x1 multiplexer as its output. In response to determining that MSB b5 is equal to 1, the second 2x1 multiplexer can generate a third MCS parameter set as its output.

[0073] In some implementations, a 5-digit MCS format or a 5-decimal-digit MCS designation provides design scalability for adding more MCS numbers in a 6-digit MCS format within a 5-digit MCS format design and / or implementation (e.g., a 5-digit MCS format UHR design and / or implementation). By extending to a 6-digit MCS format, the same additional control logic can be followed, facilitating the seamless integration of additional MCS numbers. This approach ensures that the system can adapt to future enhancements without requiring significant modifications to the existing framework or implementation.

[0074] The embodiments in this disclosure offer at least the following advantages and benefits. First, the embodiments in this disclosure provide a useful technique for designing or implementing a five-bit MCS format to represent additional MCS numbers while maintaining the existing four-bit MCS format. By adding new bits (e.g., control bits, extra bits) to the new MCS number, the five-bit MCS format ensures monotonicity in both spectral efficiency and error vector magnitude (EVM). This approach allows for the seamless integration of new MCS numbers without disrupting the existing framework (e.g., the four-bit MCS format).

[0075] Second, the embodiments in this disclosure provide useful techniques for implementing a hardware-friendly MCS format, thereby ensuring that existing hardware remains unchanged while accommodating new (additional) MCS numbers with minimal modifications. This approach leverages hardware advantages by allowing existing MCS logic to remain intact while incorporating new logic for additional MCS numbers. This approach preserves existing MCS logic, with new MCS logic added separately for additional MCS numbers, thereby ensuring seamless integration and minimal disruption to existing systems (e.g., pre-UHR or EHT / 802.11be systems).

[0076] Third, the embodiments in this disclosure provide useful techniques for allowing the modular and incremental addition of new MCS numbers. This modular design enables seamless integration of new MCS numbers without affecting existing hardware, thereby enhancing efficiency and cost-effectiveness.

[0077] Figure 3This is a diagram depicting a transmitter 300 including a parameter selector according to one or more embodiments. The transmitter (e.g., communication system 105, transmitter circuitry 120) may include a (MCS) parameter selector 350, an FEC manager 310, a modulator (MOD) 320, and / or an OFDMA manager 330. Each of the MCS parameter selector 350, FEC manager 310, modulator 320, and OFDMA manager 330 may be implemented in software, firmware, hardware circuitry, one or more processors, or a combination thereof.

[0078] refer to Figure 3 The parameter selector 350 can receive an MCS number (e.g., MCS index, MCS value, MCS identifier) ​​and output an MCS parameter set (e.g., modulation type, modulation size such as QAM size, code rate, data rate, number of spatial streams, channel width, or guard interval). The parameter selector 350 can use a table storing information about the relationship between MCS numbers and corresponding MCS parameter sets (e.g., ...). Figure 5B The parameter selector 350 can identify or obtain the MCS parameter set by using the MCS table 550 in the FEC manager 310. The parameter selector 350 can provide one or more write code parameters (e.g., code rate 311) to the FEC manager 310, one or more modulation parameters (e.g., modulation size or QAM size 321, data rate (bps) 323) to the modulator 320, and / or one or more channel parameters (e.g., channel width 331) to the OFDMA manager 330.

[0079] In response to receiving a data payload, FEC manager 310 can encode the data payload using one or more write coding parameters to generate encoded data. FEC manager 310 can use LDPC codes to encode the data payload. Modulator 320 can use one or more modulation parameters to modulate the encoded data to generate modulated data. OFDMA manager 330 can use one or more channel parameters to perform channel modulation on the modulated data to define, allocate, or configure RUs. The system (e.g., transmitter 300) can use the defined, allocated, or configured RUs to transmit the modulated data as one or more frames.

[0080] Figure 4A and Figure 4B Figures 400 and 450 depict the decimal representation of the MCS number according to one or more embodiments. Reference Figure 4A The 5-bit MCS format can treat or use MSB 412 (e.g., 5 bits or b4) as decimal places. The 5-bit MCS format can contain decimal places consisting of b... i (i=0, 1, …, 4) 410 represents 5 bits. The 5 bits may contain an integer part IP 420 (see Equation 1) and a fractional part FP422 (Equation 2). Figure 4B A graphical representation of the MCS numbers corresponding to the MCS numbers shown in Table 1 (e.g., MCS number 0.5 in index 17). For example, in Figure 4B In the table, reference numbers 452, 454, and 456 respectively indicate the 5-digit value ([1 0 0 0 0]), MCS (int) 16, and MCS (float) 0.5 corresponding to index 17 in Table 1.

[0081] Figures 5A to 5C Figures 500, 550, and 580 depict a first instance set of MCS numbers (e.g., 1.5, 3.5, 4.5, 7.5) according to one or more embodiments. Four MCS numbers in 5-bit MCS format can be added to existing MCS numbers (e.g., MCS numbers corresponding to indices 1 to 16 in Table 1 for EHT / 802.11be) to form a new MCS mapping (e.g., an MCS mapping for UHR). MCS numbers 1.5, 3.5, 4.5, and 7.5 (corresponding to indices 18, 20, 21, and 24 in Table 1) can be added to MCS numbers 0 to 15 (corresponding to indices 1 to 16 in Table 1) to form a new MCS mapping. Figure 5A Figure 500 shows a graphical representation of the MCS designations, which include MCS designations 1.5, 3.5, 4.5, and 7.5, respectively, represented by reference numbers 512, 514, 516, and 518. Figure 5B In this context, the new MCS mapping can be represented as an MCS table 550, which displays each MCS number 551 associated with a control bit 552 (e.g., MSB or MCS[4]), a 4-bit value 553 (e.g., MCS[3:0]), a modulation type 554, a code rate 555, and / or an effective data rate 556. The MCS table 550 contains rows 562, 564, 566, and 568 corresponding to MCS numbers 1.5, 3.5, 4.5, and 7.5.

[0082] refer to Figure 5CTable 580 shows the modulation type, code rate, data rate (bps), and integer format (nMCS) for the first instance MCS number set (e.g., 1.5, 3.5, 4.5, 7.5). For example, reference numeral 582 indicates that MCS number 1.5 (equivalent to 17 in integer form or integer representation) corresponds to the MCS parameter (QPSK, R=2 / 3, bps=1.33). Reference numeral 584 indicates that MCS number 3.5 (equivalent to 19 in integer form or integer representation) corresponds to the MCS parameter (16-QAM, R=2 / 3, bps=2.67). Reference numeral 586 indicates that MCS number 4.5 (equivalent to 20 in integer form or integer representation) corresponds to the MCS parameter (16-QAM, R=5 / 6, bps=3.33). Reference number 586 indicates that MCS number 7.5 (equivalent to 23 in integer form or integer representation) corresponds to MCS parameter (256-QAM, R=2 / 3, bps=5.33).

[0083] Figure 6 Table 600 illustrates indications of second instance MCS number sets (e.g., 0.5, 1.5, 3.5, and 7.5) according to one or more embodiments. Table 600 shows the modulation type, code rate, data rate (bps), and integer format (nMCS) of the second instance MCS number sets (e.g., 0.5, 1.5, 3.5, and 7.5). For example, reference numeral 602 indicates that MCS number 0.5 (equivalent to 16 in integer form or integer representation) may correspond to MCS parameters (QPSK, R=2 / 3, bps=0.67). Reference numeral 604 indicates that MCS number 1.5 (equivalent to 17 in integer form or integer representation) may correspond to MCS parameters (QPSK, R=2 / 3, bps=1.33). Reference numeral 606 indicates that MCS number 3.5 (equivalent to 19 in integer form or integer representation) may correspond to MCS parameters (16-QAM, R=2 / 3, bps=2.67). Reference number 608 indicates that MCS number 7.5 (equivalent to 23 in integer form or representation) corresponds to MCS parameters (256-QAM, R=2 / 3, bps=5.33).

[0084] Figure 7Table 700 illustrates a set of third instance MCS numberings (e.g., 0.5, 1.5, 2.5, 3.5, 4.5, and 7.5) according to one or more embodiments. Table 700 shows the modulation type, code rate, data rate (bps), and integer format (nMCS) of the third instance MCS numbering sets (e.g., 0.5, 1.5, 2.5, 3.5, 4.5, and 7.5). For example, reference numeral 702 indicates that MCS number 0.5 (equivalent to 16 in integer form or integer representation) may correspond to MCS parameters (QPSK, R=2 / 3, bps=0.67). Reference numeral 704 indicates that MCS number 1.5 (equivalent to 17 in integer form or integer representation) may correspond to MCS parameters (QPSK, R=2 / 3, bps=1.33). Reference number 706 indicates that MCS number 2.5 (equivalent to 18 in integer form or representation) corresponds to the MCS parameter (QPSK, R=5 / 6, bps=1.67). Reference number 708 indicates that MCS number 3.5 (equivalent to 19 in integer form or representation) corresponds to the MCS parameter (16-QAM, R=2 / 3, bps=2.67). Reference number 710 indicates that MCS number 4.5 (equivalent to 20 in integer form or representation) corresponds to the MCS parameter (16-QAM, R=5 / 6, bps=3.33). Reference number 712 indicates that MCS number 7.5 (equivalent to 23 in integer form or representation) corresponds to the MCS parameter (256-QAM, R=2 / 3, bps=5.33).

[0085] Figure 8Table 800 illustrates a fourth instance MCS number set (e.g., 0.5, 1.5, 2.5, 3.5, 4.5, 7.5, 11.5, and 13.5) according to one or more embodiments. Table 800 shows the modulation type, code rate, data rate (bps), and integer format (nMCS) of the fourth instance MCS number set (e.g., 0.5, 1.5, 2.5, 3.5, 4.5, 7.5, 11.5, and 13.5). For example, reference numeral 802 indicates that MCS number 0.5 (equivalent to 16 in integer form or integer representation) may correspond to MCS parameters (QPSK, R=2 / 3, bps=0.67). Reference numeral 804 indicates that MCS number 1.5 (equivalent to 17 in integer form or integer representation) may correspond to MCS parameters (QPSK, R=2 / 3, bps=1.33). Reference number 806 indicates that MCS number 2.5 (equivalent to 18 in integer form or representation) corresponds to the MCS parameter (QPSK, R=5 / 6, bps=1.67). Reference number 808 indicates that MCS number 3.5 (equivalent to 19 in integer form or representation) corresponds to the MCS parameter (16-QAM, R=2 / 3, bps=2.67). Reference number 810 indicates that MCS number 4.5 (equivalent to 20 in integer form or representation) corresponds to the MCS parameter (16-QAM, R=5 / 6, bps=3.33). Reference number 812 indicates that MCS number 7.5 (equivalent to 23 in integer form or representation) corresponds to the MCS parameter (256-QAM, R=2 / 3, bps=5.33). Reference number 814 indicates that MCS number 11.5 (equivalent to 27 in integer form or representation) corresponds to MCS parameters (1K-QAM, R=7 / 8, bps=8.75). Reference number 816 indicates that MCS number 13.5 (equivalent to 29 in integer form or representation) corresponds to MCS parameters (4K-QAM, R=7 / 8, bps=10.5).

[0086] Figure 9 This is a diagram depicting an instance parameter selector 900 receiving a 5-bit MCS number 910 according to one or more embodiments. The (MCS) parameter selector 900 may include a first parameter selector 920, which includes a first MCS logic 925, a second MCS logic 935, and a 2x1 multiplexer 940. The parameter selector 900 may receive a 5-bit MCS number containing MSB b4 (912). i(i=0,1, …, 4) 910. The first MCS logic 925 can be pre-UHR MCS logic or 4-bit MCS logic. The second MCS logic 935 can be UHR additional MCS logic or 5-bit MCS logic. The parameter selector 900 can provide MSB b4 to the 2x1 multiplexer 940 and a 4-bit MCS number b to the first parameter selector 920. i (i=0,1,2,3) 910. The first parameter selector 920 can receive a 4-bit MCS number b. i (i=0,1,2,3) 922, using the first MCS logic 925 to calculate the first MCS parameter set 927, and providing the first MCS parameter set 927 to the 2x1 multiplexer 940. The first MCS logic 925 can use a table (e.g., having a table with...) Figure 5B The table structure shown is similar to that of a table in 4-digit MCS format. The parameter selector 900 can use the second MCS logic 935 to calculate the value corresponding to the 4-digit MCS number b. i (i=0,1,2,3) 922's second MCS parameter set 937, and provides the second MCS parameter set 937 to the 2x1 multiplexer 940. The second MCS logic 935 can use a table (e.g., with...) Figure 5B The table shown is similar to the table for the 5-bit MCS format. The 2x1 multiplexer 940 determines whether MSB b4 is equal to 0 or 1. In response to determining that MSB b4 is equal to 0, the 2x1 multiplexer 940 generates a first MCS parameter set 927 as output 950. In response to determining that MSB b4 is equal to 1, the 2x1 multiplexer 940 generates a second MCS parameter set 937 as output 950.

[0087] Figure 10 This is a diagram depicting another instance of a parameter selector 1000 receiving a 6-bit MCS number 1010 according to one or more embodiments. The (MCS) parameter selector 1000 may include a first parameter selector 1020, which includes a first MCS logic 1025, a second MCS logic 1035, a third MCS logic 1045, a first 2x1 multiplexer 1040, and a second 2x1 multiplexer 1050. The parameter selector 1000 may receive a 6-bit MCS formatted b including MSB b5 (1012) and a second MSB b4 (1014). i (i=0,1, …, 5) 1010. The first MCS logic 1025 can be a pre-UHR MCS logic or a 4-bit MCS logic. The second MCS logic 1035 can be a UHR additional MCS logic or a 5-bit MCS logic. The third MCS logic 1045 can be a 6-bit MCS logic.

[0088] refer to Figure 10 The parameter selector 1000 can provide MSB b5 (1012) to the second 2x1 multiplexer 1050, provide the second MSB b4 (1014) to the first 2x1 multiplexer 1040, and provide a 4-bit MCS number b to the first parameter selector 1025. i (i=0,1,2,3) (1022). The first parameter selector 1020 can receive a 4-bit MCS number b. i (i=0,1,2,3)(1022), the first MCS parameter set 1027 is calculated using the first MCS logic 1025 and provided to the first 2x1 multiplexer 1040. The first MCS logic 1025 may use a table (e.g., having a table with...) Figure 5B The table structure shown is similar to that of a table in 4-digit MCS format. The parameter selector 1000 can use the second MCS logic 1035 to calculate the value corresponding to the 4-digit MCS number b. i The second MCS parameter set 1037 (i=0,1,2,3) (1022) is provided to the first 2x1 multiplexer 1040. The second MCS logic 1035 can use a table (e.g., with...) Figure 5B The table shown is similar to the table for the 5-bit MCS format. The first 2x1 multiplexer 1040 can determine whether the second MSB b4 (1014) is equal to 0 or 1. In response to determining that the second MSB b4 (1014) is equal to 0, the first 2x1 multiplexer 1040 can generate a first MCS parameter set 1027 as output 1043. In response to determining that MSB b4 is equal to 1, the first 2x1 multiplexer 1040 can generate a second MCS parameter set 1037 as output 1043.

[0089] The parameter selector 1000 can use the third MCS logic 1045 to calculate the corresponding 4-bit MCS number b. i The third MCS parameter set 1047 (i=0,1,2,3)(1022) is provided to the second 2x1 multiplexer 1050. The third MCS logic 1045 can use a table (e.g., having a table with...) Figure 5BThe table structure shown is similar to that of a table in 6-bit MCS format. The second 2x1 multiplexer 1050 can determine whether MSB b5 (1012) is equal to 0 or 1. In response to determining that MSB b5 (1012) is equal to 0, the second 2x1 multiplexer 1050 can generate the output of the first 2x1 multiplexer 1040 as output 1060. In response to determining that MSB b5 (1012) is equal to 1, the second 2x1 multiplexer can generate a third MCS parameter set 1047 as output 1060.

[0090] Figure 11 This is a flowchart illustrating a process 1100 for selecting MCS parameters based on a decimal representation of an MCS number, according to an embodiment. In some embodiments, process 1100 is performed by one or more processors of a first device (e.g., baseband circuitry 110, transmitter circuitry 120, or processor 2010 of communication system 105; processor 2010, transmitter 300, parameter selector 350, parameter selector 900, or parameter selector 1000 of communication system 108). In other embodiments, process 1100 is performed by other entities (e.g., computing systems other than communication systems 105 or 108). In some embodiments, process 1100 includes a... Figure 11 The steps shown in the text may be more, fewer, or different.

[0091] In step 1102, one or more processors may receive a first modulation and coding scheme (MCS) number greater than or equal to 1 (e.g., MCS number 301, MCS number 410, MCS number 910, MCS number 1010).

[0092] In step 1106, one or more processors may determine from a first MCS number (e.g., the integer part 922 corresponding to MCS number 1.0) a plurality of bits representing a first portion of the first MCS number (e.g., MCS number 1.5) and a first bit (e.g., MSB 912) representing the difference (e.g., 0.5) between the first portion (e.g., 1.0) and the first MCS number (e.g., 1.5). The difference may be less than 1.

[0093] In step 1108, one or more processors may determine (1) a first set of MCS parameters (e.g., parameter 927) corresponding to a first part of the first MCS number, and (2) a second set of MCS parameters (e.g., parameter 937) corresponding to the first part of the first MCS number (e.g., 1.0) plus a first predetermined decimal (e.g., 0.5).

[0094] In some embodiments, the first portion of the first MCS number (e.g., 1.0) plus a first predetermined decimal (e.g., 0.5) may correspond to one of 1.5, 3.5, 4.5, or 7.5. In some embodiments, the first portion of the MCS number may be an integer greater than or equal to 1. The first predetermined decimal portion may be 0.5. In some embodiments, the spectral efficiency of the first MCS parameter set (e.g., the spectral efficiency corresponding to the first portion of the first MCS number) may be less than the spectral efficiency of the second MCS parameter set (e.g., the spectral efficiency corresponding to the first portion of the first MCS number plus the first predetermined decimal).

[0095] In step 1110, one or more processors may use a first bit (e.g., MSB 912) to select a third MCS parameter set (e.g., parameter 950) from either a first MCS parameter set (e.g., parameter 927) or a second MCS parameter set (e.g., parameter 937). In some embodiments, the third MCS parameter set (e.g., parameter 950) may include at least one of a code rate (e.g., code rate R), a modulation size (e.g., QAM size), or a data rate (e.g., effective data rate in bps).

[0096] In step 1112, one or more processors (e.g., modulator 320) may modulate the data using a third MCS parameter set.

[0097] In some implementations, one or more processors (e.g., parameter selector 1000) may be configured to receive a first MCS number greater than or equal to (e.g., Figure 10 The second MCS number (e.g., MCS number 1010 representing the fractional MCS number 1.75) is shown in the diagram, representing the 5-bit value [b4, b3, b2, b1, b0] of the fractional MCS number 1.5. One or more processors can be configured to determine multiple bits representing the first MCS number from the second MCS number (e.g., MCS number 1010). Figure 10The five-bit value [b4, b3, b2, b1, b0] shown in the figure, and a second bit (e.g., MSB 1012) representing the difference between the first MCS number (e.g., 1.5) and the second MCS number (e.g., 1.75). The difference (e.g., 0.25) may be less than 1. One or more processors may be configured to determine (1) a third MCS parameter set (e.g., parameter 1043) corresponding to the first MCS number (e.g., 1.5), and (2) a fourth MCS parameter set (e.g., parameter 1047) corresponding to the first MCS number (e.g., 1.5) plus a second predetermined decimal (e.g., 0.25). One or more processors may be configured to use the second bit (e.g., MSB 1012) to select an MCS parameter set from either the third MCS parameter set (e.g., parameter 1043) or the fourth MCS parameter set (e.g., parameter 1047) (e.g., parameter 1060). The second predetermined decimal (e.g., 0.25) may be 0.5 times the first predetermined decimal (e.g., 0.5).

[0098] Figure 12 This is a flowchart illustrating a process 1200 for determining the decimal representation of an MCS number according to an embodiment. In some embodiments, process 1200 is executed by one or more processors of a first device (e.g., baseband circuitry 110, transmitter circuitry 120, or processor 2010 of communication system 105, or processor 2010 of communication system 108). In other embodiments, process 1200 is executed by other entities (e.g., a computing system other than communication system 105 or 108). In some embodiments, process 1200 includes a fractional representation of the MCS number. Figure 12 The steps shown in the text may be more, fewer, or different.

[0099] In step 1202, one or more processors may receive MCS schemes (e.g., such as those from the set of unassigned Modulation and Code Scheme (MCS) numbering (e.g., MCS numbers corresponding to indices 1 to 16 in Table 1) that are not assigned MCS numbers. Figure 5C The MCS scheme shown in the figure corresponds to QPSK, bit rate 2 / 3, and effective data rate 1.33 bps (582).

[0100] In step 1206, one or more processors may identify the spectral efficiency of the MCS scheme (e.g., the spectral efficiency of MCS scheme 582).

[0101] In step 1208, one or more processors may determine that the spectral efficiency falls between a first spectral efficiency (e.g., the spectral efficiency of MCS number 1.0) of a first MCS number in the set of MCS numbers (e.g., MCS numbers corresponding to indices 1 to 16 in Table 1) and a second spectral efficiency (e.g., the spectral efficiency of MCS number 2.0).

[0102] In some implementations, each of the first MCS number (e.g., 1.0) and the second MCS number (e.g., 2.0) may be an integer greater than or equal to 1. The second MCS number may be 1 greater than the first MCS number. In some implementations, the first spectral efficiency and the second spectral efficiency may be the two spectral efficiencies in the set of MCS numbers that are closest to the spectral efficiency of the MCS scheme (e.g., the two spectral efficiencies that are closest to the spectral efficiency of MCS scheme 582).

[0103] In step 1210, one or more processors may determine a fraction between the first MCS number (e.g., 1.0) and the second MCS number (e.g., 2.0) as the third MCS number (e.g., MCS number 1.5). In some embodiments, the third MCS number may be 0.5 greater than the first MCS number. The third MCS number may be 0.5 greater than the first MCS number (e.g., in the case where the first MCS number is 1.0, the second MCS number is 2.0, and the third MCS number is 1.5), or 0.25 greater than the first MCS number (e.g., in the case where the first MCS number is 1.5, the second MCS number is 2.0, and the third MCS number is 1.75). In some embodiments, the minimum number of bits (e.g., 4 bits) representing the set of MCS numbers (e.g., corresponding to the MCS numbers at indices 1 to 16 in Table 1) may be 1 less than the minimum number of bits (e.g., 5 bits) representing the set of MCS numbers and the third MCS number (e.g., corresponding to the MCS numbers at indices 1 to 16 and 18 in Table 1). In some implementations, the third MCS number is one of 1.5, 3.5, 4.5, or 7.5 (see [link to implementation details]). Figures 5A to 5C ).

[0104] In step 1212, one or more processors (e.g., modulator 320) may use the MCS number set and a third MCS number (e.g., MCS numbers corresponding to indices 1 to 16 and 18 in Table 1) to modulate data.

[0105] A reference to "or" can be interpreted as inclusive, such that any term described using "or" can refer to a single, more than one, or any of the described terms. A reference to at least one of a list of conjunctions for a term can be interpreted as inclusive or to refer to a single, more than one, or any of the described terms. For example, a reference to "at least one of 'A' and 'B'" can include only 'A', only 'B', or both 'A' and 'B'. Such references used in conjunction with "include" or other open terms can include additional items.

[0106] It should be noted that certain paragraphs of this disclosure may refer to terms (e.g., "first" and "second") related to subsets of transmit space streams, probe frames, responses, and devices for the purpose of identifying or distinguishing them from each other or for other purposes. These terms are not intended to relate entities (e.g., first device and second device) merely in time or sequentially, although in some cases these entities may include such relationships. These terms also do not limit the number of possible entities (e.g., STA, AP, beamformer and / or beamformee) that can operate within a system or environment. It should be understood that the systems described above may provide any or multiple of the components, and these components may be located on a standalone machine, or, in some embodiments, on multiple machines in a distributed system. Furthermore, the bit field positions may be varied, and multiple bit words may be used. Additionally, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or magnetic tape). The program can be implemented in any programming language (e.g., LISP, PERI, C, C++, C#) or in any bytecode language (e.g., JAVA). The software program or executable instructions can be stored as object code on or in one or more artifacts.

[0107] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art should understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples described herein. Therefore, the methods and systems should not be limited to the foregoing embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. A system comprising: One or more processors, configured to: Receive the first modulation and coding scheme MCS number that is greater than or equal to 1; From the first MCS number, determine a plurality of bits representing a first part of the first MCS number and a first bit representing the difference between the first part and the first MCS number, wherein the difference is less than 1; Determine (1) a first set of MCS parameters corresponding to the first part of the first MCS number, and (2) a second set of MCS parameters corresponding to the first part of the first MCS number plus a first predetermined decimal. The first bit is used to select a third MCS parameter set from either the first MCS parameter set or the second MCS parameter set; and The data is modulated using the third MCS parameter set.

2. The system according to claim 1, wherein The third MCS parameter set includes at least one of bit rate, modulation size, or data rate.

3. The system according to claim 1, wherein The first part of the MCS number is an integer greater than or equal to 1.

4. The system according to claim 3, wherein the first predetermined decimal is 0.

5.

5. The system according to claim 1, wherein The spectral efficiency of the first MCS parameter set is less than that of the second MCS parameter set.

6. The system of claim 1, wherein the one or more processors are further configured to: Receive a second MCS number that is greater than or equal to the first MCS number; From the second MCS number, determine a plurality of bits representing the first MCS number and a second bit representing the difference between the first MCS number and the second MCS number, wherein the difference is less than 1; Determine (1) the third MCS parameter set corresponding to the first MCS number, and (2) the fourth MCS parameter set corresponding to the first MCS number plus a second predetermined decimal; and Use the second bit to select an MCS parameter set from either the third or the fourth MCS parameter set.

7. The system according to claim 6, wherein the second predetermined decimal is 0.5 times the first predetermined decimal.

8. The system of claim 1, wherein the first portion of the first MCS number plus the first predetermined decimal corresponds to one of 1.5, 3.5, 4.5 or 7.

5.

9. A system comprising: One or more processors, configured to: MCS schemes that receive MCS numbers from the MCS number set that have not been assigned a modulation and coding scheme; Indicate the spectral efficiency of the MCS scheme; Determine that the spectral efficiency falls between the first spectral efficiency of the first MCS number and the second spectral efficiency of the second MCS number in the MCS number set; The fractional number between the first MCS number and the second MCS number is determined as the third MCS number; and The data is modulated using the MCS number set and the third MCS number.

10. The system according to claim 9, wherein Each of the first MCS number and the second MCS number is an integer greater than or equal to 1, and The second MCS number is 1 greater than the first MCS number.

11. The system of claim 10, wherein the third MCS number is 0.5 greater than the first MCS number.

12. The system according to claim 9, wherein The first spectral efficiency and the second spectral efficiency are the two spectral efficiencies in the MCS number set that are closest to the spectral efficiency of the MCS scheme.

13. The system of claim 12, wherein the third MCS number is 0.5 greater than the first MCS number or 0.25 greater than the first MCS number.

14. The system according to claim 9, wherein The minimum number of digits in the MCS number set is 1 less than the minimum number of digits in both the MCS number set and the third MCS number.

15. The system of claim 9, wherein the third MCS number is one of 1.5, 3.5, 4.5 or 7.

5.

16. The system of claim 9, wherein the third MCS number corresponds to one of 17, 19, 20 or 23 in integer form.

17. A method comprising: The first modulation and coding scheme (MCS) number, which is greater than or equal to 1, is received by one or more processors. The one or more processors determine, from the first MCS number, a plurality of bits representing a first portion of the first MCS number and a first bit representing the difference between the first portion and the first MCS number, wherein the difference is less than 1; The one or more processors determine (1) a first set of MCS parameters corresponding to the first part of the first MCS number, and (2) a second set of MCS parameters corresponding to the first part of the first MCS number plus a first predetermined decimal. The one or more processors use the first bit to select a third MCS parameter set from either the first MCS parameter set or the second MCS parameter set; and The data is modulated by the one or more processors using the third MCS parameter set.

18. The method of claim 17, wherein The third MCS parameter set includes at least one of bit rate, modulation size, or data rate.

19. The method of claim 17, wherein The spectral efficiency of the first MCS parameter set is less than that of the second MCS parameter set.

20. The method of claim 17, further comprising: Receive a second MCS number that is greater than or equal to the first MCS number; From the second MCS number, determine a plurality of bits representing the first MCS number and a second bit representing the difference between the first MCS number and the second MCS number, wherein the difference is less than 1; Determine (1) the third MCS parameter set corresponding to the first MCS number, and (2) the fourth MCS parameter set corresponding to the first MCS number plus a second predetermined decimal; and Use the second bit to select an MCS parameter set from either the third or the fourth MCS parameter set.

Images