10-gigabit TCP / IP hardware unloading method for pipeline architecture

Abstract

The invention discloses a 10-gigabit TCP / IP (Transmission Control Protocol / Internet Protocol) hardware unloading method of a pipeline architecture, and relates to the technical field of high-speed network communication. A TCP / IP protocol stack is unloaded to hardware, modular design is adopted, AXIS standard interfaces are uniformly used for connecting all functional modules, and the functional modules comprise a TCP engine, a UDP engine and a 10G MAC layer. The core is that an optimization design combining a pipeline and pre-calculation is adopted for UDP and TCP engines; in a data packet processing idle period, pre-calculation is performed on a fixed data packet header field and a result is temporarily stored; in a real-time processing stage, incremental calculation is performed by combining a pre-calculation result and a real-time variable field, so that the delay of a critical path is reduced. And meanwhile, the processes of data encapsulation, check and calculation, frame assembly and the like are decomposed into parallel execution stages through a multi-stage assembly line, so that the data processing throughput and the transmission bandwidth of a small data packet are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of high-speed network communication technology, and more specifically to a pipelined architecture method for 10 Gigabit TCP / IP hardware offloading. Background Technology

[0002] With the development of artificial intelligence, cloud computing, and 5G networks, data center network communication systems need to handle massive amounts of data. Traditional 1G networks can no longer meet bandwidth demands, and 10G networks are becoming increasingly prevalent. In 10G networks, the Transmission Control Protocol (TCP) is used to ensure the correctness of data transmission, but its handshake and retransmission mechanisms cause bandwidth loss. The traditional TCP / IP protocol stack relies on CPU software implementation, which consumes a large amount of CPU resources and becomes a bottleneck for data exchange.

[0003] Existing solutions include using dedicated high-speed network interface cards (NICs) or dedicated chips. Dedicated 10G Ethernet NICs only implement the physical layer (PHY) and media access control layer (MAC), while network and transport layer processing still relies on the CPU, increasing CPU load. High-performance smart NICs have TCP / IP protocol stack offloading capabilities, reducing CPU overhead, but require the development of independent drivers and have higher power consumption. Dedicated network processing chips, while reducing power consumption, suffer from high R&D costs, long development cycles, and lack of programmability, making them difficult to adapt to complex and ever-changing application scenarios.

[0004] Especially in the data center access layer, in scenarios involving high-frequency, small data packet interactions, insufficient bandwidth for small data packet transmission can lead to significant packet loss. Existing FPGA-based TCP / IP implementations perform reasonably well in large data packet transmission, but generally suffer from high logic resource consumption and low efficiency in small data packet transmission.

[0005] Therefore, how to generate a TCP / IP hardware offloading scheme that can both efficiently utilize hardware resources and significantly improve the bandwidth of small data packet transmission is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above problems, the present invention is proposed to provide a pipelined architecture for 10 Gigabit TCP / IP hardware offloading method that overcomes or at least partially solves the above problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution, the method of which is based on FPGA hardware and includes the following steps: S1. Establish a TCP / IP hardware offloading module, which includes an ARP module, a MAC resolution module, a UDP engine module, a TCP engine module, a routing module, and an AXIS interconnection module; The S2 and SFP+ interfaces receive external network data, which is then transmitted to the 10G MAC layer via the AXIS interface. The 10G MAC layer outputs the external network data to the MAC resolution module or ARP module through the AXIS interconnect module. S3. External network data output to the ARP module is processed by the ARP module to generate ARP response data. The ARP response data is directly returned to the 10G MAC layer through the AXIS interconnect module. External network data output to the MAC resolution module is processed by the MAC resolution module to extract IP packets and is selectively distributed to the UDP engine module or TCP engine module according to the protocol field of the IP packet header. S4, the UDP engine module or the TCP engine module processes the IP packet header. The UDP engine module performs address resolution, checksum calculation, and extraction of the UDP data packet based on the UDP packet format, and outputs the UDP data packet to the application layer through the AXIS interface. The TCP engine module performs address resolution, checksum calculation, and extraction of the TCP data packet based on the TCP packet format, and outputs the TCP data packet to the application layer through the AXIS interface. S5. The application layer, based on the received UDP or TCP data packets, sends a response data packet back to the TCP / IP hardware offload module via the AXIS interface. The UDP engine module in the TCP / IP hardware offload module performs protocol encapsulation, verification, and calculation on the response data packet in a three-stage pipeline. The TCP engine module performs protocol encapsulation, verification, and calculation on the response data packet, as well as connection management based on a finite state machine, in a four-stage pipeline. After processing the response data packet, the UDP engine or TCP engine module obtains the response message and sends it to the 10G MAC layer through the AXIS interface module.

[0008] Preferably, the TCP / IP hardware offloading module also includes a routing module. The routing module is used to perform routing queries. When the application layer needs to send data, the routing module receives IP queries initiated by the UDP engine module and the TCP engine module. The routing module provides physical address information to the UDP engine module and the TCP engine module, and generates a response MAC address and outputs it to the UDP engine module or the TCP engine module. If the routing module fails to query, it re-initiates an ARP request through the ARP module to obtain a new MAC address and outputs it to the UDP engine module or the TCP engine module.

[0009] Preferably, the UDP engine module also includes a data receiving function, the specific implementation process of which includes: receiving IP data from the 10G MAC layer through the AXIS interface; sequentially performing IP protocol identification, IP address matching, port information detection, and data verification; when all verifications pass, extracting payload data from the IP packet and outputting the payload data to the application layer through the AXIS interface; when verification fails, re-obtaining IP data from the 10G MAC layer.

[0010] Preferably, the process by which the UDP engine in S5 processes response packets in a three-stage pipeline to obtain response messages and sends them to the 10G MAC layer includes: Level 1: Buffer the response data packet into the AXIS FIFO interface, pre-calculate the data checksum, and output the mapped port information, IP address information, and MAC header information; Level 2: Based on port information, IP header information, and data checksum, calculate the IP checksum and UDP checksum, assemble the packet, and output the IP header to the AXIS FIFO interface; Level 3: Based on the UDP checksum, UDP data, and UDP data length information calculated from the IP header, UDP header packets and UDP data packets are assembled. Finally, a UDP format response packet is output to the AXIS FIFO interface via the AXIS interface, and finally output to the 10G MAC layer.

[0011] Preferably, the process by which the TCP engine in S5 processes response packets in a four-stage pipeline to obtain response messages and sends them to the 10G MAC layer includes: Level 1: Receive response data packets, cache the data in RAM, segment the application data according to the window size and maximum segment size, pre-calculate the data checksum, and output the data transmission length; Level 2: Read the pre-configured IP address, port information, and MAC information, perform IP checksum calculation based on the data length, and prepare the MAC header to output to the AXIS FIFO interface; Level 3: Generate a TCP pseudo header based on the data length and IP information, perform TCP checksum calculation in conjunction with the pre-calculated data checksum, and prepare the IP header; Level 4: Based on the calculated TCP checksum and data length information, output the TCP header and TCP packet data, and finally output a complete TCP / IP format response packet in the form of AXIS interface.

[0012] Preferably, the TCP engine module includes a TCP connection module, which manages the communication connection between the client and the server. In S5, the TCP engine is connected to a finite state machine to control the establishment and termination of TCP connections. The finite state machine includes at least the following states: State 0: Initialize the finite state machine, wait for the client to send a SYN signal, and transition to state 0; if a reset signal is received, transition to state 0. State 1: Send a SYN+ACK signal to the client and transition to State 0; if a reset signal is received, transition to State 0. State 2: Waiting for the client to return ACK and SEQ signals to complete the three-way handshake; State 3: After the third handshake is completed, a connection is established between the server and the client, and data transmission is carried out based on the TCP protocol. In State 3, if the keep-alive function fails, the server starts the connection termination procedure and transitions to State 6. If the FIN signal is received from the client, the server sends an ACK signal to the client and transitions to State 4. State 4: Send ACK+FIN signal to the client, transition to State 5; State 5: Receive the client's ACK response signal, complete the four-way handshake, close the connection between the server and the client, and transition to state 0; State 6: Connection reset or keep-alive failed, actively closed the connection, the server sends a FIN signal to the client, waits for the ACK+FIN signal, and then transitions to State 7; State 7: After the client receives the server's FIN signal, the server sends an ACK signal to the client, transitioning to State 8; if a reset signal is received, the server transitions to State 0. Status 8: The server is shut down, returning status 0.

[0013] Preferably, the data interfaces between the UDP engine, TCP engine, MAC resolution module, ARP module, and AXIS interconnect module within the TCP / IP hardware offloading module all adopt the AXIS standard interface.

[0014] Preferably, in S5, if the response data packet is in UDP packet format, the UDP engine module encapsulates the response data packet to obtain the response packet, connects to the AXIS interconnect module through the AXIS interface, and sends the response packet to the 10G MAC layer; if the response data packet is in TCP packet format, the TCP engine module initiates a connection with the application layer. After the connection is established, the TCP engine module encapsulates the response data packet to obtain the response packet, connects to the AXIS interconnect module through the AXIS interface, and sends the response packet to the 10G MAC layer. The TCP engine module completes the transmission of the response data packet and disconnects from the application layer.

[0015] As can be seen from the above technical solutions, compared with the prior art, the present invention discloses a pipelined architecture method for 10 Gigabit TCP / IP hardware offloading. The beneficial effects of the above technical solutions provided by the embodiments of the present invention include at least the following: 1. Achieve near-line-speed high-bandwidth transmission and small packet throughput optimization: Through FPGA hardware offloading, pre-computation, and multi-stage pipeline parallel processing technology, significantly improve network data processing bandwidth, especially in high-frequency small data packet interaction scenarios, effectively reducing packet loss and transmission delay.

[0016] 2. Reduce system resource consumption and enhance design flexibility: Offloading the complete TCP / IP protocol stack from the CPU to the FPGA hardware greatly reduces the host CPU load; adopting modular design and a unified AXIS standard interface improves the portability, scalability and functional reconfigurability of the design, and reduces development costs and cycle time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a diagram of the TCP / IP hardware offloading architecture provided in this embodiment of the invention; Figure 2 This is the TCP three-way handshake and four-way handshake principle provided in the embodiments of the present invention; Figure 3 This is a hardware offloading architecture diagram of the transaction layer verification and structure provided in this embodiment of the invention; Figure 4 This is the server-side TCP engine architecture design provided in the embodiments of the present invention; Figure 5 This is a finite state machine implementation for server-side TCP connection management provided in this embodiment of the invention; Figure 6 This is the three-stage pipeline design for the UDP engine provided in this embodiment of the invention; Figure 7 This is a four-stage pipeline implementation of the TCP engine provided in this embodiment of the invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] like Figure 1 As shown in the figure, this invention discloses a pipelined architecture method for 10 Gigabit TCP / IP hardware offloading.

[0021] The method is implemented based on FPGA hardware and includes the following steps: S1. Establish a TCP / IP hardware offloading module, which includes an ARP module, a MAC resolution module, a UDP engine module, a TCP engine module, a routing module, and an AXIS interconnection module; The S2 and SFP+ interfaces receive external network data, which is then transmitted to the 10G MAC layer via the AXIS interface. The 10G MAC layer outputs the external network data to the MAC resolution module or ARP module through the AXIS interconnect module. S3. External network data output to the ARP module is processed by the ARP module to generate ARP response data. The ARP response data is directly returned to the 10G MAC layer through the AXIS interconnect module. External network data output to the MAC resolution module is processed by the MAC resolution module to extract IP packets and is selectively distributed to the UDP engine module or TCP engine module according to the protocol field of the IP packet header. S4, the UDP engine module or the TCP engine module processes the IP packet header. The UDP engine module performs address resolution, checksum calculation, and extraction of the UDP data packet based on the UDP packet format, and outputs the UDP data packet to the application layer through the AXIS interface. The TCP engine module performs address resolution, checksum calculation, and extraction of the TCP data packet based on the TCP packet format, and outputs the TCP data packet to the application layer through the AXIS interface. S5. The application layer, based on the received UDP or TCP data packets, sends a response data packet back to the TCP / IP hardware offload module via the AXIS interface. The UDP engine module in the TCP / IP hardware offload module performs protocol encapsulation, verification, and calculation on the response data packet in a three-stage pipeline. The TCP engine module performs protocol encapsulation, verification, and calculation on the response data packet, as well as connection management based on a finite state machine, in a four-stage pipeline. After processing the response data packet, the UDP engine or TCP engine module obtains the response message and sends it to the 10G MAC layer through the AXIS interface module.

[0022] Specifically, the routing module primarily implements route lookups. When the application layer needs to send data, it provides physical address information to the TCP and UDP engine modules. Internally, the routing module utilizes RAM to store resources, caching a high-speed cache of 1024 MAC address routing tables. The module receives IP queries from the UDP and TCP engine modules, queries its internal routing table, generates corresponding responses and MAC addresses, and outputs them to the UDP or TCP engine modules. If a query fails, it re-initiates an ARP request through the ARP module to obtain a new MAC address.

[0023] Specifically, the UDP engine is a key component in the entire TCP / IP hardware offloading process, enabling connectionless data transmission. Data input from the application layer is then processed by the UDP engine, which performs protocol encapsulation by adding frame headers, checksums, and other information according to the UDP physical layer packet format. To improve data transmission throughput, we propose a pipelining-based approach to control the UDP data flow, eliminating the delay between the completion of one packet transmission and the start of the next. Simultaneously, we propose a pre-computation method to reduce data latency, which helps reduce the number of pipelining stages and improve packet assembly efficiency. Finally, the new data packet is output to the 10G MAC layer via the AXIS interface.

[0024] The UDP engine receives IP layer packet data from the MAC parsing module. It parses the packets using a parallel processing method, allowing for non-blocking reception of input data. It extracts information such as IP address, port information, and checksum from the IP packets, then performs IP address matching and pre-calculated checksum analysis to extract valid data from correct packets. Finally, the valid data is output to the application layer via the AXIS interface.

[0025] Specifically, the TCP protocol supports reliable transmission and is a key module in the entire TCP / IP protocol stack for achieving secure data transmission. A connection must be established before communication can begin, and the TCP three-way handshake is the basic process for establishing a reliable connection between the server and the client.

[0026] like Figure 2 As shown in (a), the TCP engine uses a three-way handshake mechanism to establish a connection. The first handshake: When the client and server need to transmit data, the client actively initiates a connection establishment request to the server. The IP packet sets SYN to 1 and assigns the sequence number seq value x, indicating that the sequence number of the first data byte transmitted is x. The client enters the SYN_SEND state and prepares to receive the second handshake packet returned by the server. During this process, the TCP engine module of the server's TCP / IP hardware offloading module receives the request frame sent by the client.

[0027] Second handshake: After the server receives the client's request, such as... Figure 4 As shown, the TCP connection module provides connection management and performs frame inspection on the received synchronization messages. When the synchronization message format is correctly detected, an acknowledgment segment is sent back, setting SYN to 1 and ACK to 1 in the acknowledgment segment, indicating that a valid acknowledgment message has been initiated. Simultaneously, the segment sequence number seq equals y, ack equals x plus 1, and the acknowledgment message is output to the 10GMAC module through the AXIS interface. The server then transitions from LISTEN to SYN_RCVD state.

[0028] The third handshake: After receiving the acknowledgment message from the server, the client also needs to send an acknowledgment message to the server. For a valid acknowledgment sequence number field, ACK is 1, seq equals x+1, ack equals y+1, and the client enters the ESTABLISHED state. After receiving the client's request, the server's TCP connection module performs frame inspection on the received response message. If the message format is correct, the server also enters the ESTABLISHED state. The TCP connection module outputs the connection establishment standard to the TCP sending module, and the server can also initiate data communication with the client.

[0029] Once the transmission between the client and server is complete, the connection must be terminated, which requires a four-way handshake. The handshake protocol ensures a reliable two-way shutdown.

[0030] like Figure 2 As shown in (b), the four-way handshake process for terminating a TCP connection is illustrated.

[0031] First handshake: When the client does not need to send or receive data, the client initiates a connection disconnection request to the server. The IP packet sets FIN=1 and ACK=1 to request the connection to be disconnected. The client enters the IN-WAIT-1 termination wait 1 state, stops sending and receiving data at the transport layer, and waits for the server to send a response packet for confirmation.

[0032] The second handshake: After the server-side TCP connection module receives the client's connection termination request and the request packet passes inspection, the TCP sending module initiates an acknowledgment packet. The IP packet sets ACK to 1, the seq equals the received ack, and the ack equals the seq of the first handshake plus 1. The TCP sending module sends the acknowledgment packet to the 10G MAC layer, and the server enters the CLSOSE-WAIT closing and waiting state.

[0033] The third handshake: The server's TCP sending module confirms that it will no longer send data to the client, so it sends a FIN=1 packet and then enters the LAST-ACK state. The client receives the seq and ack packets from the server, prepares to return an acknowledgment packet, and enters the FIN-WAIT-2 termination wait state.

[0034] The fourth handshake: After the TCP connection module receives the FIN sent by the client, the TCP sending module sends an ACK confirmation, Seq equals u plus 1, ack equals w plus 1, and after waiting for a period of time, it completely closes the connection. The client receives the ACK confirmation and closes the connection directly.

[0035] The TCP engine and application layer share a unified AXIS interface, which facilitates pipelined design. Data from SFP+ is forwarded and processed by MAC, then processed by the TCP engine and finally sent to the application layer; at the same time, the TCP engine can also receive data from the application layer, process it according to the protocol, and then transmit it to the MAC layer.

[0036] like Figure 3 The diagram shows the TCP checksum pre-calculation process. The TCP / IP checksum process implemented through pre-calculation is as follows: Upon detecting application-layer data input, the module calculates the input data checksum, calculates the input data length, stores the checksum in a register, and forwards it to the next stage, thereby eliminating critical path latency caused by real-time checksum calculation. The module can also receive MAC data from the MAC parsing module for checksum calculation, and extract IP header, UDP header, and TCP header information for checksum verification.

[0037] The system reads the pre-calculated data checksum, data length, IP header information, UDP header information, and TCP header information from the registers and performs checksum calculation. The UDP and TCP checksums are used to obtain the length information for incremental calculation, and then the IP checksum, UDP checksum, and TCP checksum are generated. Checksum calculation is completed within one clock cycle, which significantly reduces the latency of receiving MAC layer messages and generating UDP and TCP / IP protocol frames.

[0038] The IP checksum, UDP checksum, and TCP checksum sent by the MAC parsing module are returned to the MAC parsing module. The IP checksum, UDP checksum, and TCP checksum sent by UDP and TCP are returned to the UDP engine and TCP engine for MAC packet assembly. Finally, the UDP engine and TCP engine output the MAC packet to the 10G MAC layer.

[0039] This invention provides a specific embodiment for implementing the unloading logic of the UCP engine.

[0040] The UDP engine implements the UDP network protocol at the transport layer and has two core functions: UDP data reception and data transmission. Regarding UDP data reception, this module supports non-blocking data reception with a maximum data bandwidth of 10Gbps. Specifically, UDP protocol data is input through the AXIS interface of the MAC resolution module and undergoes four verification steps: IP protocol identification, IP address matching, port information detection, and data checksum verification. Only data that passes all verifications is considered valid UDP data and is finally output to the application layer through the UDP engine's AXIS interface.

[0041] The implementation flow of UDP data reception logic is as follows: IP data is received from the MAC resolution module via the AXIS interface, and source port information, destination port information, and length information are latched. The IP data was detected to have a protocol (IP_PROTOCOL) of 17, and the destination port information matched the local port information. When the tlast signal of the AXIS interface is 1, it indicates the end of the input data packet. If the UDP checksum verification signal (UDP_CHECKSUM) is high, it indicates that the UDP checksum is correct, and the signal (FRAM memory E_VALID) is set to 1, indicating that the input UDP data packet is valid. Valid data packets are output through the AXIS interface of the UDP engine for use by the application layer; otherwise, these packets are discarded.

[0042] For UDP data transmission, the UDP engine receives data from the application layer. It then transmits the data to the AXIS interconnect module according to the MAC layer format, and finally sends it to the 10GMAC. However, this process is prone to blocking. To improve the bandwidth of UDP data transmission, this paper proposes a UDP pipelining design as a key optimization method.

[0043] like Figure 6 The diagram shows the data transmission process of a UDP three-stage pipeline.

[0044] Level 1: This module receives 64-bit data from the application layer AXIS interface, stores the data in the AXIS FIFO interface for data buffering. The AXIS FIFO interface is a FIFO core in the form of an AXIS interface, specifically designed for streaming data buffering. It counts the input length, pre-calculates the data checksum, and outputs the mapped port information, IP address information, and MAC header information.

[0045] The second level receives IP address and port information, data checksum, and data length from the previous level. It then outputs this information to the pre-calculation checksum module for IP checksum calculation, generates a UDP pseudo-header, and outputs it to the pre-calculation checksum module for UDP checksum calculation. Simultaneously, it assembles the packet and outputs the IP header to the AXIS FIFO interface.

[0046] Level 3: Receives the UDP checksum, UDP data, and data length information from the upper level, performs UDP header packet assembly and UDP data packet assembly, and finally outputs UDP formatted packets to the AXIS FIFO interface in the form of an AXIS interface, and outputs them to the 10G MAC layer.

[0047] This invention provides a specific embodiment for implementing the TCP engine's offload logic.

[0048] like Figure 5 As shown, to implement TCP connection management, once a connection is established between the TCP server and the client, the TCP engine module receives data input from the MAC parsing module. First, it outputs the IP address, IP protocol, and port information to the pre-calculated checksum. After the checksum is verified to be correct, it extracts the payload data from the IP packet, outputs the data to the TCP receive buffer, and finally sends it to the application layer via the AXIS interface.

[0049] The TCP send buffer is responsible for buffering application data, calculating data length, and performing checksum calculations. After receiving data from the TCP send buffer module, the TCP send module initiates MAC frame encapsulation. This module performs IP checksum and TCP header checksum calculations. To improve TCP transmission efficiency and support TCP pipeline implementation, a method combining pre-calculation and real-time calculation is proposed.

[0050] The TCP connection module in the TCP engine is responsible for managing network communication connections between the client and the server. Its logic implementation uses a finite state machine design. Figure 5 The left-hand module illustrates the state transitions during the connection establishment process, from state 0 to state 3, while the right-hand module illustrates the state transitions during the connection termination process, from state 3 to state 8. State 3 indicates that a connection has been successfully established between the server and client, enabling the sending and receiving of TCP data. A detailed explanation of the finite state machine transitions is as follows: State 0: Initialize the finite state machine, wait for the client to send a SYN signal, and transition to state 0; if a reset signal is received, transition to state 0. State 1: Send a SYN+ACK signal to the client and transition to State 0; if a reset signal is received, transition to State 0. State 2: Waiting for the client to return ACK and SEQ signals to complete the three-way handshake; State 3: After the third handshake is completed, a connection is established between the server and the client, and data transmission is carried out based on the TCP protocol. If keep-alive fails in state 3, the server transitions to state 6. If the server receives the client's FIN signal, it sends an ACK signal to the client and transitions to state 4. State 4: Send ACK+FIN signal to the client, transition to State 5; State 5: Receive the client's ACK response signal, complete the four-way handshake, close the connection between the server and the client, and transition to state 0; State 6: Connection reset or keep-alive failed, actively closed the connection, the server sends a FIN signal to the client, waits for the ACK+FIN signal, and then transitions to State 7; State 7: After the client receives the server's FIN signal, the server sends an ACK signal to the client, transitioning to State 8; if a reset signal is received, the server transitions to State 0. Status 8: The server is shut down, returning status 0.

[0051] During TCP data transmission, the TCP engine detects that the LINK_START signal is high and initiates connection establishment. After the connection is established, TCP can send and receive data. For data transmission, the logic receives data from the application layer's S_AXIS interface, buffers the input data in RAM, and then sends a transmission request to TCP_TX. TCP_TX sends the encapsulated MAC data packet to the 10GMAC kernel through the AXIS interface. To improve TCP data transmission bandwidth, this study focuses on TCP pipeline design. The TCP four-stage pipeline process is as follows: Figure 7 As shown.

[0052] The system receives 64-bit AXIS data from the application layer. A connection needs to be established for the first data transmission, but not for subsequent transmissions. The received data is stored in a dual-port RAM. The application data is segmented based on the detected window size and maximum segment size (MSS), the data checksum is pre-calculated, the data transmission length is output, and the corresponding data is output to the AXISFIFO interface. Read the initialized IP address, port information, MAC information, and data length from the FPGA, output them to the pre-calculation checksum module to start IP checksum calculation, prepare to output MAC packets, update the window size, and output the MAC packet header to the AXISFIFO interface. Obtain information such as data length and IP address, and generate a TCP pseudo-header. Output the pseudo-header, data length, and data checksum to the pre-calculated checksum for TCP checksum calculation, and simultaneously prepare to output the IP header information to the AXISFIFO interface; Receive the pre-calculated TCP checksum and data length information, start outputting the TCP header, and after the TCP header is output, further output the TCP packet data part, and finally output it to the MAC layer in the AXIS interface mode.

[0053] like Figure 7 The diagram shows the process of a TCP four-level pipeline.

[0054] During TCP data transmission, the TCP engine detects that the LINK_START signal is high and initiates connection establishment. After the connection is established, TCP can send and receive data. For data transmission, the logic receives data from the application layer's S_AXIS interface, buffers the input data in RAM, and then sends a transmission request to TCP_TX. TCP_TX sends the encapsulated MAC data packet to the 10G MAC layer kernel through the AXIS interface. To improve TCP data transmission bandwidth, this study focuses on TCP pipeline design. The specific implementation process of the TCP four-stage pipeline is as follows: Level 1: Receives 64-bit AXIS data from the application layer. A connection needs to be established for the first data transmission, but not for subsequent transmissions. The received data is stored in a dual-port RAM. The application data is segmented according to the detected window size and maximum segment size. The data checksum is pre-calculated, the data transmission length is output, and the corresponding data is output to the AXIS FIFO interface.

[0055] The second stage reads the initialized IP address, port information, MAC information, and data length from the FPGA, outputs them to the pre-calculation checksum module to start IP checksum calculation, prepares to output MAC packets, updates the window size, and outputs the MAC packet header to the AXIS FIFO interface.

[0056] Level 3: Obtain data length, IP address, and other information, and generate a TCP pseudo-header. Output the pseudo-header, data length, data checksum, and other information to the pre-calculated checksum for TCP checksum calculation. Simultaneously, prepare to output the IP header information to the AXISFIFO interface.

[0057] Level 4: Receives pre-calculated TCP checksum and data length information, begins outputting the TCP header, and after the TCP header is output, further outputs the TCP packet data portion, and finally outputs it to the 10G MAC layer via the AXIS interface.

[0058] This architecture uses the AXIS standard interface to unify communication between modules, simplifying integration and enhancing compatibility. Board-level verification shows that this method achieves maximum UDP / TCP bandwidths of 10Gbps and 9.49Gbps ​​respectively, consuming only 12% of the FPGA lookup table. This method effectively improves transmission bandwidth, enabling its application in high-speed transmission systems.

[0059] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pipelined architecture method for 10 Gigabit TCP / IP hardware offloading, characterized in that, The method is implemented based on FPGA hardware and includes the following steps: S1. Establish a TCP / IP hardware offloading module, which includes an ARP module, a MAC resolution module, a UDP engine module, a TCP engine module, a routing module, and an AXIS interconnection module; The S2 and SFP+ interfaces receive external network data, which is then transmitted to the 10G MAC layer via the AXIS interface. The 10G MAC layer outputs the external network data to the MAC resolution module or ARP module through the AXIS interconnect module. S3. External network data output to the ARP module is processed by the ARP module to generate ARP response data. The ARP response data is directly returned to the 10G MAC layer through the AXIS interconnect module. External network data output to the MAC resolution module is processed by the MAC resolution module to extract IP packets and is selectively distributed to the UDP engine module or TCP engine module according to the protocol field of the IP packet header. S4, the UDP engine module or the TCP engine module processes the IP packet header. The UDP engine module performs address resolution, checksum calculation, and extraction of the UDP data packet based on the UDP packet format, and outputs the UDP data packet to the application layer through the AXIS interface. The TCP engine module performs address resolution, checksum calculation, and extraction of the TCP data packet based on the TCP packet format, and outputs the TCP data packet to the application layer through the AXIS interface. S5. The application layer, based on the received UDP or TCP data packets, sends a response data packet back to the TCP / IP hardware offload module via the AXIS interface. The UDP engine module in the TCP / IP hardware offload module performs protocol encapsulation, verification, and calculation on the response data packet in a three-stage pipeline. The TCP engine module performs protocol encapsulation, verification, and calculation on the response data packet, as well as connection management based on a finite state machine, in a four-stage pipeline. After processing the response data packet, the UDP engine or TCP engine module obtains the response message and sends it to the 10G MAC layer through the AXIS interface module.

2. A pipelined architecture method for 10 Gigabit TCP / IP hardware offloading according to claim 1, characterized in that, The TCP / IP hardware offloading module also includes a routing module, which is used to perform routing queries. When the application layer needs to send data, the routing module receives IP queries initiated by the UDP engine module and the TCP engine module. The routing module provides physical address information to the UDP engine module and the TCP engine module, and the routing module generates the MAC address of the response and outputs it to the UDP engine module or the TCP engine module. If the routing module fails to query, the ARP module will re-initiate the ARP request to obtain the new MAC address and output it to the UDP engine module or TCP engine module.

3. A pipelined architecture method for 10 Gigabit TCP / IP hardware offloading according to claim 1, characterized in that, The UDP engine module also includes a data receiving function. The specific implementation process includes: receiving IP data from the 10G MAC layer through the AXIS interface; sequentially performing IP protocol identification, IP address matching, port information detection, and data verification; when all verifications pass, extracting payload data from the IP packet and outputting the payload data to the application layer through the AXIS interface; when verification fails, re-obtaining IP data from the 10G MAC layer.

4. A pipelined architecture method for 10 Gigabit TCP / IP hardware offloading according to claim 1, characterized in that, In S5, the UDP engine processes response packets in a three-stage pipeline to obtain response messages and send them to the 10G MAC layer. The process includes: Level 1: Buffer the response data packet into the AXIS FIFO interface, pre-calculate the data checksum, and output the mapped port information, IP address information, and MAC header information; Level 2: Based on port information, IP header information, and data checksum, calculate the IP checksum and UDP checksum, assemble the packet, and output the IP header to the AXIS FIFO interface; Level 3: Based on the UDP checksum, UDP data, and UDP data length information calculated from the IP packet header, UDP header packets and UDP data packets are assembled. Finally, a UDP format response packet is output to the AXIS FIFO interface via the AXIS interface module and then output to the 10G MAC layer.

5. A method for offloading 10 Gigabit TCP / IP hardware with a pipelined architecture according to claim 1, characterized in that, In S5, the TCP engine processes response packets in a four-stage pipeline to obtain response messages and send them to the 10G MAC layer. The process includes: Level 1: Receive response data packets, cache the data in RAM, segment the application data according to the window size and maximum segment size, pre-calculate the data checksum, and output the data transmission length; Level 2: Read the pre-configured IP address, port information, and MAC information, perform IP checksum calculation based on the data length, and prepare the MAC header to output to the AXIS FIFO interface; Level 3: Generate a TCP pseudo header based on the data length and IP information, perform TCP checksum calculation in conjunction with the pre-calculated data checksum, and prepare the IP header; Level 4: Based on the calculated TCP checksum and data length information, output the TCP header and TCP packet data, and finally output the complete TCP data packet in the form of AXIS interface, and output it to the 10G MAC layer through the AXIS interface module.

6. A method for hardware offloading of 10 Gigabit TCP / IP with a pipelined architecture according to claim 1, characterized in that, The TCP engine module includes a TCP connection module, which manages the communication connection between the client and the server. In S5, the TCP engine connects to a finite state machine to control the establishment and termination of TCP connections; the finite state machine includes at least the following states: State 0: Initialize the finite state machine, wait for the client to send a SYN signal, and transition to state 0; if a reset signal is received, transition to state 0. State 1: Send a SYN+ACK signal to the client and transition to State 0; if a reset signal is received, transition to State 0. State 2: Waiting for the client to return ACK and SEQ signals to complete the three-way handshake; State 3: After the third handshake is completed, a connection is established between the server and the client, and data transmission is carried out based on the TCP protocol; In state 3, if the keep-alive function fails, the server initiates the connection termination procedure and transitions to state 6; if it receives the client's FIN signal, it sends an ACK signal to the client and transitions to state 4. State 4: Send ACK+FIN signal to the client, transition to State 5; State 5: Receive the client's ACK response signal, complete the four-way handshake, close the connection between the server and the client, and transition to state 0; State 6: Connection reset or keep-alive failed, actively closed the connection, the server sends a FIN signal to the client, waits for the ACK+FIN signal, and then transitions to State 7; State 7: After the client receives the server's FIN signal, the server sends an ACK signal to the client, transitioning to State 8; if a reset signal is received, the server transitions to State 0. Status 8: The server is shut down, returning status 0.

7. A method for offloading 10 Gigabit TCP / IP hardware with a pipelined architecture according to claim 1, characterized in that, The data interfaces between the UDP engine, TCP engine, MAC parsing module, ARP module, and AXIS interconnect module within the TCP / IP hardware offloading module all adopt the AXIS standard interface.

8. A method for offloading 10 Gigabit TCP / IP hardware with a pipelined architecture according to claim 1, characterized in that, In S5, if the response data packet is in UDP packet format, the UDP engine module encapsulates the response data packet to obtain the response packet, connects to the AXIS interconnect module through the AXIS interface, and sends the response packet to the 10G MAC layer. If the response data packet is in TCP packet format, the TCP engine module initiates a connection with the application layer. After the connection is established, the TCP engine module encapsulates the response data packet to obtain the response packet, connects to the AXIS interconnect module through the AXIS interface, and sends the response packet to the 10G MAC layer. The TCP engine module then completes the transmission of the response data packet and disconnects from the application layer.

Images