Link state detection method, physical layer chip, electronic equipment and storage medium

Abstract

The invention discloses a link state detection method based on a physical layer chip, and the physical layer chip comprises an analog front-end signal detection register, a digital rear-end signal detection register and a basic control register. The method comprises the following steps: acquiring a first flag bit value of an analog front-end signal detection register, a second flag bit value of a digital rear-end signal detection register and a third flag bit value of a basic control register; and determining a link connection state according to the first flag bit value, the second flag bit value, the third flag bit value and a preset link state judgment strategy. Thus, link state judgment is carried out by collecting link state information of three different dimensions and combining the preset strategy, the real situation of the link can be reflected more comprehensively, link state judgment deviation caused by single judgment basis is effectively avoided, the accuracy of link state judgment is ensured to a certain extent, and the link state judgment efficiency is improved. The adaptive capacity of the network equipment is improved, and the stability and reliability of the network equipment are enhanced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a link state detection method based on a physical layer chip, a physical layer chip, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In related technologies, the link connection status is usually determined by reading the value of the digital back-end detection register of the physical layer chip. However, the detection result of this single signal often cannot fully reflect the actual link situation, resulting in deviations in the link connection status judgment and affecting the stability and reliability of network devices. Summary of the Invention

[0003] This application provides a link state detection method based on a physical layer chip, a physical layer chip, an electronic device, a computer-readable storage medium, and a computer program product.

[0004] This application provides a link state detection method based on a physical layer chip. The physical layer chip includes an analog front-end signal detection register, a digital back-end signal detection register, and a basic control register. The method includes: The first flag value of the analog front-end signal detection register, the second flag value of the digital back-end signal detection register, and the third flag value of the basic control register are obtained. The first flag value is used to indicate whether an electrical signal is detected, the second flag value is used to indicate whether the average amplitude of the sampled signal is greater than or equal to a first preset signal amplitude, and the third flag value is used to indicate the working mode of the physical layer chip. The link connection status is determined based on the first flag value, the second flag value, and the third flag value, along with a preset link status judgment strategy.

[0005] In this way, by collecting link status information from three different dimensions and combining it with preset strategies to determine link status, the traditional mode of relying solely on digital backend detection results is changed. This can more comprehensively reflect the real situation of the link, effectively avoid the link status judgment deviation caused by a single judgment basis, and thus ensure the accuracy of link status determination to a certain extent, improve the adaptability of network devices to complex network environments, and enhance the stability and reliability of network devices.

[0006] In some implementations, the first flag bit is set to 1 when the electrical signal is detected, and to 0 when the electrical signal is not detected. The second flag bit is set to 1 when the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, and to 0 when the average amplitude of the sampled signal is less than the first preset signal amplitude. The third flag bit is set to 00 when the physical layer chip is in a state of unsuccessful negotiation.

[0007] In this way, by clarifying the specific value rules for the three flag bits, a standardized and consistent input basis is provided for link status determination. The unified value rules enable the accurate quantification of electrical signal detection results, sampling signal amplitude status, and chip operating modes in different scenarios. To a certain extent, this avoids the confusion caused by inconsistent value standards and improves the accuracy and reliability of the determination results. At the same time, the binary assignment rules reduce the technical implementation difficulty, making it easier for developers to understand and apply, which is conducive to the promotion and implementation of the solution and improves the practicality and operability of the entire technical solution to a certain extent.

[0008] In some implementations, determining the link connection status based on the first flag value, the second flag value, and the third flag value, and a preset link status determination strategy, includes: If the first flag value and the second flag value are both 0 and the third flag value is 00, the link connection state is determined to be idle.

[0009] In this way, by clearly defining the correspondence between specific flag bit values ​​and idle status, the system can quickly and accurately identify the idle status of the link to a certain extent, providing a reliable basis for resource allocation and task scheduling at the upper layer of the system. At the same time, accurate idle status identification helps maintenance personnel understand the usage of network links, providing a reference for network optimization and expansion, and improving the operating efficiency and management convenience of the network system to a certain extent.

[0010] In some implementations, determining the link connection status based on the first flag value, the second flag value, and the third flag value, and a preset link status determination strategy, includes: If both the first and second flag values ​​are 1 and the third flag value is not 00, the link connection status is determined to be busy.

[0011] In this way, by clearly defining the correspondence between specific flag bit value combinations and busy status, the system can accurately identify the normal communication status of the link, enabling the upper layer of the system to quickly decide on the sending and receiving of data packets based on the judgment results. This improves the efficiency of network communication to a certain extent. Furthermore, this judgment rule is based on multi-dimensional cross-validation, avoiding misjudgments caused by single-dimensional judgment, and improving the accuracy of busy status judgment. This provides a strong guarantee for the stable and efficient operation of network devices to a certain extent.

[0012] In some implementations, determining the link connection status based on the first flag value, the second flag value, and the third flag value, and a preset link status determination strategy, includes: If the first flag value and the second flag value are different, obtain the first flag value, the second flag value and the third flag value a preset number of times; If the first flag value and the second flag value are different each time they are obtained, the link connection status is determined to be abnormal. If the first flag value and the second flag value are the same at least once in the preset number of times, the link connection status is determined according to the first flag value, the second flag value, the third flag value, and the preset link status judgment strategy.

[0013] Thus, a multi-round verification judgment mechanism was established for special scenarios where the first and second flag values ​​are different. This enables the detection scheme to cover various link scenarios, including normal and abnormal ones. To a certain extent, it effectively filters out false differences caused by factors such as instantaneous interruption of external links and accidental interference, avoids misjudgment caused by single detection, improves the accuracy and reliability of abnormal state judgment, enhances the stability and adaptability of network devices, and reduces the risk of communication failures caused by link misjudgment.

[0014] In some implementations, the physical layer chip further includes a digital back-end signal quality register. The fourth flag bit of the digital back-end signal quality register is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fourth flag bit is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fourth flag bit is 0. The second preset signal amplitude is less than the first preset signal amplitude. Determining the link connection status as abnormal when the first flag bit value and the second flag bit value are different each time includes: When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, a renegotiation process is performed for a preset number of times. After completing the renegotiation process for the preset number of negotiation times, the first flag value, the second flag value, and the third flag value are obtained again. The link connection status is determined based on the first flag value, the second flag value, and the third flag value obtained again, and the preset link status judgment strategy. If the link connection status is in the abnormal state, the physical layer chip is reset.

[0015] Thus, by adding a digital back-end signal quality register, precise segmentation of signal quality under abnormal scenarios is achieved. This enables the differentiation of anomalies caused by different reasons, and the hierarchical recovery mechanism corresponding to specific flag bit value combinations prioritizes link recovery attempts through renegotiation, fully utilizing the basic communication potential of the signal, reducing unnecessary reset operations, and lowering system overhead. Simultaneously, by handling abnormal link states hierarchically, the link state detection and recovery mechanism becomes more targeted and flexible, improving the efficiency and success rate of link anomaly recovery to a certain extent. This enhances the self-diagnosis and repair capabilities of the physical layer chip, improves the stability and reliability of network devices, and is suitable for complex communication scenarios such as poor network cable quality and strong interference.

[0016] In some implementations, the renegotiation process, performed a preset number of times, when the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1, and the third flag bit is 00, includes: When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, the renegotiation process is performed for the preset number of negotiation times based on the speed reduction adaptive mechanism of the physical layer chip.

[0017] Thus, by introducing a rate-reduction adaptive mechanism during the renegotiation process, the physical layer chip can flexibly adjust the negotiation rate according to the link signal quality, increasing the probability of successful renegotiation and avoiding negotiation failures and link interruptions caused by rate mismatch. This enhances the self-repair capability of the physical layer chip to a certain extent, effectively reduces the duration of link anomalies, lowers maintenance costs, and improves the stability and reliability of network devices. It is suitable for complex communication scenarios such as poor network cable quality and strong interference.

[0018] In some embodiments, the method further includes: If the first flag bit value is 0, the second flag bit value is 1, the fourth flag bit value is 0, or the third flag bit value is not 00, the link connection status is determined to be the abnormal status. If the link connection status is in the abnormal state, the physical layer chip is reset.

[0019] In this way, by clearly defining the anomaly judgment rules corresponding to multiple flag bit value combinations, comprehensive coverage of link anomaly scenarios is achieved, avoiding the problem of unmanageable issues due to omissions of anomaly scenarios. Furthermore, the multi-dimensional anomaly judgment conditions can accurately identify different types of link anomalies, to a certain extent preventing the omission of some abnormal states and improving the comprehensiveness and accuracy of link status detection. Simultaneously, directly triggering a reset process for abnormal states can quickly clear abnormal states and fault logic within the chip, preventing anomalies from continuously affecting network communication. This, to a certain extent, improves the efficiency of link fault handling, enabling the physical layer chip to have self-diagnosis and repair capabilities, effectively reducing the duration of abnormal situations such as false connections and link jams, lowering maintenance costs, and enhancing the stability and reliability of network equipment.

[0020] In some implementations, resetting the physical layer chip when the link connection state is in the abnormal state includes: Read and store the configuration parameters of the basic control register; The physical layer chip is reset. After completing the reset process of the physical layer chip, the configuration parameters are rewritten into the basic control register; The physical layer chip is powered on. After the physical layer chip is powered on, a renegotiation process is performed.

[0021] In this way, the standardized closed-loop reset process effectively solves the problems of parameter loss and incomplete recovery caused by traditional chip reset. To a certain extent, it ensures that the physical layer chip can be restored to its working state before the abnormality after reset, reducing the probability of abnormal state recurrence. Moreover, after the link is determined to be in an abnormal state, the closed-loop reset process is automatically executed, enabling the physical layer chip to have the ability to self-diagnose and self-recover. This reduces the link interruption time to a certain extent, improves the stability and reliability of network devices, and provides a strong guarantee for the continuous and smooth network communication.

[0022] This application provides a physical layer chip, which includes an analog front-end signal detection register, a digital back-end signal detection register, a basic control register, a status detection module, and a logic determination module. The state detection module is configured to acquire the first flag value of the analog front-end signal detection register, the second flag value of the digital back-end signal detection register, and the third flag value of the basic control register. The first flag value is used to indicate whether an electrical signal is detected, the second flag value is used to indicate whether the average amplitude of the sampled signal is greater than or equal to a first preset signal amplitude, and the third flag value is used to indicate the working mode of the physical layer chip. The logic determination module is configured to determine the link connection status based on the first flag value, the second flag value, and the third flag value, and a preset link status determination strategy.

[0023] In this way, by collecting link status information from three different dimensions and combining it with preset strategies to determine link status, the traditional mode of relying solely on digital backend detection results is changed. This can more comprehensively reflect the real situation of the link, effectively avoid the link status judgment deviation caused by a single judgment basis, and thus ensure the accuracy of link status determination to a certain extent, improve the adaptability of network devices to complex network environments, and enhance the stability and reliability of network devices.

[0024] In some implementations, the analog front-end signal detection register is configured such that when the physical layer chip detects the electrical signal, the first flag bit is set to 1, and when the electrical signal is not detected, the first flag bit is set to 0. The digital back-end signal detection register is configured such that when the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, the second flag bit is 1, and when the average amplitude of the sampled signal is less than the first preset signal amplitude, the second flag bit is 0. The basic control register is configured such that, when the physical layer chip is in a state of unsuccessful negotiation, the third flag bit is set to 00.

[0025] In this way, by clarifying the specific value rules for the three flag bits, a standardized and consistent input basis is provided for link status determination. The unified value rules enable the accurate quantification of electrical signal detection results, sampling signal amplitude status, and chip operating modes in different scenarios. To a certain extent, this avoids the confusion caused by inconsistent value standards and improves the accuracy and reliability of the determination results. At the same time, the binary assignment rules reduce the technical implementation difficulty, making it easier for developers to understand and apply, which is conducive to the promotion and implementation of the solution and improves the practicality and operability of the entire technical solution to a certain extent.

[0026] In some implementations, the state detection module is configured to acquire the first flag value, the second flag value, and the third flag value a preset number of times when the first flag value and the second flag value are different. The logic determination module is configured to determine that the link connection status is abnormal when the first flag value and the second flag value are different each time. If the first flag value and the second flag value are the same at least once in the preset number of times, the link connection status is determined according to the first flag value, the second flag value, the third flag value, and the preset link status judgment strategy.

[0027] Thus, a multi-round verification judgment mechanism was established for special scenarios where the first and second flag values ​​are different. This enables the detection scheme to cover various link scenarios, including normal and abnormal ones. To a certain extent, it effectively filters out false differences caused by factors such as instantaneous interruption of external links and accidental interference, avoids misjudgment caused by single detection, improves the accuracy and reliability of abnormal state judgment, enhances the stability and adaptability of network devices, and reduces the risk of communication failures caused by link misjudgment.

[0028] In some embodiments, the physical layer chip further includes a digital back-end signal quality register and a recovery execution module. The fourth flag bit of the digital back-end signal quality register is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fourth flag bit is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fourth flag bit is 0. The second preset signal amplitude is less than the first preset signal amplitude. The recovery execution module is configured to perform a preset number of renegotiation processes when the first flag bit value is 1, the second flag bit value is 0, the fourth flag bit value is 1 and the third flag bit value is 00. The state detection module is configured to, after completing the renegotiation process for the preset number of negotiation times, obtain the first flag value, the second flag value, and the third flag value again; The logic determination module is configured to determine the link connection status based on the first flag value, the second flag value, and the third flag value obtained again and the preset link status determination strategy. The recovery execution module is configured to reset the physical layer chip when the link connection status is in the abnormal state.

[0029] Thus, by adding a digital back-end signal quality register, precise segmentation of signal quality under abnormal scenarios is achieved. This enables the differentiation of anomalies caused by different reasons, and the hierarchical recovery mechanism corresponding to specific flag bit value combinations prioritizes link recovery attempts through renegotiation, fully utilizing the basic communication potential of the signal, reducing unnecessary reset operations, and lowering system overhead. Simultaneously, by handling abnormal link states hierarchically, the link state detection and recovery mechanism becomes more targeted and flexible, improving the efficiency and success rate of link anomaly recovery to a certain extent. This enhances the self-diagnosis and repair capabilities of the physical layer chip, improves the stability and reliability of network devices, and is suitable for complex communication scenarios such as poor network cable quality and strong interference.

[0030] In some implementations, the logic determination module is configured to determine the link connection status as the abnormal state when the first flag bit value is 0, the second flag bit value is 1, the fourth flag bit value is 0, or the third flag bit value is not 00. The recovery execution module is configured to reset the physical layer chip when the link connection status is in the abnormal state.

[0031] In this way, by clearly defining the anomaly judgment rules corresponding to multiple flag bit value combinations, comprehensive coverage of link anomaly scenarios is achieved, avoiding the problem of unmanageable issues due to omissions of anomaly scenarios. Furthermore, the multi-dimensional anomaly judgment conditions can accurately identify different types of link anomalies, to a certain extent preventing the omission of some abnormal states and improving the comprehensiveness and accuracy of link status detection. Simultaneously, directly triggering a reset process for abnormal states can quickly clear abnormal states and fault logic within the chip, preventing anomalies from continuously affecting network communication. This, to a certain extent, improves the efficiency of link fault handling, enabling the physical layer chip to have self-diagnosis and repair capabilities, effectively reducing the duration of abnormal situations such as false connections and link jams, lowering maintenance costs, and enhancing the stability and reliability of network equipment.

[0032] In some implementations, the recovery execution module is configured to read and store the configuration parameters of the basic control register; The physical layer chip is reset. After completing the reset process of the physical layer chip, the configuration parameters are rewritten into the basic control register; The physical layer chip is powered on. After the physical layer chip is powered on, a renegotiation process is performed.

[0033] In this way, the standardized closed-loop reset process effectively solves the problems of parameter loss and incomplete recovery caused by traditional chip reset. To a certain extent, it ensures that the physical layer chip can be restored to its working state before the abnormality after reset, reducing the probability of abnormal state recurrence. Moreover, after the link is determined to be in an abnormal state, the closed-loop reset process is automatically executed, enabling the physical layer chip to have the ability to self-diagnose and self-recover. This reduces the link interruption time to a certain extent, improves the stability and reliability of network devices, and provides a strong guarantee for the continuous and smooth network communication.

[0034] This application also provides an electronic device including the physical layer chip described in some of the above embodiments.

[0035] This application also provides a computer-readable storage medium storing a computer program that, when executed by one or more processors, implements the methods described in some of the above embodiments.

[0036] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the methods described in some of the above embodiments.

[0037] The electronic device, computer-readable storage medium, and computer program product provided in this application, when implementing the above method, first acquire the first flag value of the analog front-end signal detection register, the second flag value of the digital back-end signal detection register, and the third flag value of the basic control register. The first flag value indicates whether an electrical signal is detected, the second flag value indicates whether the average amplitude of the sampled signal is greater than or equal to a first preset signal amplitude, and the third flag value indicates the operating mode of the physical layer chip. Finally, based on the first flag value, the second flag value, and the third flag value, and a preset link status judgment strategy, the link connection status is determined. In this way, by collecting link status information from three different dimensions and combining it with a preset strategy for link status judgment, the traditional mode of relying solely on digital back-end detection results is changed. This allows for a more comprehensive reflection of the true link situation, effectively avoiding link status judgment bias caused by a single judgment criterion. This, to a certain extent, ensures the accuracy of link status judgment, improves the adaptability of network devices to complex network environments, and enhances the stability and reliability of network devices.

[0038] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0039] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein: Figure 1 This is one of the flowcharts illustrating a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 2 This is one of the schematic diagrams of the physical layer chip structure in certain embodiments of this application; Figure 3 This is a second flowchart illustrating a link state detection method based on a physical layer chip according to certain embodiments of this application. Figure 4 This is the third flowchart illustrating a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 5 This is the fourth flowchart of a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 6 This is the fifth flowchart illustrating a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 7 This is a second schematic diagram of the physical layer chip structure of certain embodiments of this application; Figure 8 This is the sixth flowchart of a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 9 This is the seventh flowchart of a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 10 This is the eighth flowchart of a link state detection method based on a physical layer chip according to certain embodiments of this application; Figure 11 This is a schematic diagram of the process flow of a link state detection method based on a physical layer chip according to certain embodiments of this application. Detailed Implementation

[0040] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application.

[0041] In wired connection scenarios, plugging and unplugging switch ports is the most common operation in network maintenance and personal user use. However, during the plugging and unplugging process, the difference in the quality of the network cable used for connection, the uncertainty of the performance and compatibility of the other end device, and the fluctuation of factors such as temperature, humidity and electromagnetic interference in the connection environment may all affect the stability of the link.

[0042] Switches primarily rely on PHY chips (Physical Layer Chips) to achieve external connectivity. Internally, they can be divided into two parts: Analog Front-End (AFE) and Digital Back-End (DBE). The Analog Front-End focuses on the processing and conversion of analog signals, while the Digital Back-End is responsible for digital signal processing and interface control with the MAC layer. Furthermore, the Digital Back-End integrates an Auto-Negotiation (AN) module for negotiating communication rates, duplex modes, and other parameters with the link partner, laying the foundation for stable link establishment.

[0043] In wired data communication and transmission, accurate determination of link connection status (Link Up / Link Down) is crucial for decisions made by upper-layer drivers. Related technologies commonly employ the signal detection function of the PHY chip's digital backend to determine the link status. Its core principle is: by detecting whether the digital signal energy is greater than or equal to a preset digital threshold, a signal detection status register is set. The system then periodically queries the status of this register through management interfaces such as MDIO to determine the link connection status.

[0044] However, since the signal detection register reads based on digital samples converted by the analog-to-digital converter (ADC), rather than the physical signal directly acquired by the analog front-end, PHY chip malfunctions or external interference can lead to abnormal reads or state machine freezes in the signal detection register. For example, frequent port plugging and unplugging can cause high-frequency changes in link status, potentially causing the PHY chip's Link-Up logic state machine to freeze. Furthermore, electrostatic discharge in the external environment can interfere with the chip's internal circuit modules, resulting in abnormal reads from the signal detection status register.

[0045] Secondly, in the high-speed digital circuit design of PHY chips, the physical layout of the transmitting and receiving channels is sometimes quite close. When the transmitting channel operates under continuous high load, the generated digital signal may leak to the adjacent receiving channel through power supply or electromagnetic coupling, causing crosstalk interference. Furthermore, if the network cable is suddenly disconnected while the PHY chip is normally connected to the link partner and transmitting and receiving data at line speed, the high-frequency signal emitted by the analog front-end of the PHY chip will be reflected at the disconnected end of the network cable due to impedance mismatch. This reflected signal may re-enter the receiving channel, causing the detection result of the digital side energy detector to be greater than or equal to the preset digital threshold, resulting in the signal detection status register being set. When the signal detection register is set, the MAC layer will continuously receive the Link Up signal, continuously forwarding or flooding data packets to that port to maintain the signal transmission of the transmitting link. This, in turn, further exacerbates the intensity of the leaked interference signal, causing the system to enter an abnormal state without automatic recovery, even without any hardware module failure.

[0046] Furthermore, when faults such as "false connections" occur, the PHY chip itself lacks effective self-awareness and automatic recovery capabilities. It typically continues to report error messages indicating that the link is normal, even though normal communication is no longer possible. Since the port indicator lights and the Link-Up status displayed on the web control page are controlled by the MAC layer, users may see the port link status light constantly on and the port link up status displayed as "on," easily leading to misjudgments. This abnormal state will persist until the system administrator manually restarts the port or resets the PHY chip. For basic switches lacking management functions such as reset, even a hardware power-off restart is required to restore functionality, reducing network system maintainability and increasing the manpower and time costs of network maintenance.

[0047] In summary, the link connection status determination in related technologies only focuses on the output of a single module in the PHY chip's signal processing flow, ignoring the health status of each link in the entire transmission path from the physical medium into the digital system. This leads to frequent anomalies such as "false connections," affecting the stability and reliability of network communication.

[0048] Based on the above issues, please refer to Figure 1 This application provides a link state detection method based on a physical layer chip 100. The physical layer chip 100 includes an analog front-end signal detection register 101, a digital back-end signal detection register 102, and a basic control register 103. The method includes: 01: Obtain the first flag value of the analog front-end signal detection register 101, the second flag value of the digital back-end signal detection register 102, and the third flag value of the basic control register 103. The first flag value is used to indicate whether an electrical signal is detected, the second flag value is used to indicate whether the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, and the third flag value is used to indicate the working mode of the physical layer chip 100. 02: Determine the link connection status based on the first flag value, the second flag value, and the third flag value and the preset link status judgment strategy.

[0049] Please see Figure 2 This application provides a physical layer chip 100, which includes an analog front-end signal detection register 101, a digital back-end signal detection register 102, a basic control register 103, a status detection module 104, and a logic determination module 105. The status detection module 104 is configured to acquire the first flag value of the analog front-end signal detection register 101, the second flag value of the digital back-end signal detection register 102, and the third flag value of the basic control register 103. The first flag value is used to indicate whether an electrical signal is detected, the second flag value is used to indicate whether the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, and the third flag value is used to indicate the working mode of the physical layer chip 100. The logic determination module 105 is configured to determine the link connection status based on the first flag value, the second flag value, and the third flag value and a preset link status determination strategy.

[0050] Specifically, the physical layer chip 100 is the hardware that implements the physical layer functions of the network. It is responsible for processing the transmission, reception and conversion of electrical signals and is a key component for devices to access the network.

[0051] The analog front-end signal detection register 101 is a register inside the physical layer chip 100 used to store analog signal detection data, recording the transmission status and characteristic parameters of the analog signal.

[0052] The digital back-end signal detection register 102 is a register inside the physical layer chip 100 used to store digital signal detection data and record information such as the quality and integrity of the digital signal.

[0053] The basic control register 103 is the core control register of the physical layer chip 100. It is used to store and configure the chip's operating mode, parameter thresholds and other configuration information, and is the basis for the normal operation of the chip.

[0054] The status detection module 104 is a functional unit responsible for collecting the status information of the physical layer chip 100 port. It can actively acquire various register data and perform preliminary processing.

[0055] The logic judgment module 105 is a functional unit that analyzes and processes the collected status data and judges the fault type, and outputs the judgment result through preset judgment rules.

[0056] The first flag value is a specific bit value in the analog front-end signal detection register 101 used to determine whether the physical layer chip 100 has detected an electrical signal. It is an indicator for determining whether the analog front-end signal exists.

[0057] The second flag bit value is a specific bit value in the digital back-end signal detection register 102 used to characterize whether the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, and is the basis for evaluating the digital back-end signal status.

[0058] The third flag value is a specific bit value in the basic control register 103 used to reflect the working mode of the physical layer chip 100, which can help determine the overall status of the link connection.

[0059] Electrical signals are physical electrical signals that are transmitted through physical media and can be captured by the analog front-end signal detection register 101. They are the basic signal carriers for link connections.

[0060] The average amplitude of the sampled signal is the average value of the signal amplitude calculated by the digital back-end after sampling the received signal. It can reflect the strength and stability of the signal.

[0061] The first preset signal amplitude is a signal amplitude standard pre-set according to the normal communication requirements of the link. It is used to judge the validity of the sampled signal. When the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, it indicates that the signal strength meets the requirements of subsequent processing. For example, the average amplitude of the sampled signal is converted into a range of 0 to 256 steps. Usually, the physical layer chip 100 will divide this step into a "health waterline", i.e., the first preset signal amplitude, according to the normal communication requirements of the link. The sampled signal strength corresponding to the average amplitude of the sampled signal that is greater than or equal to the "health waterline" meets the communication requirements. For example, if the first preset signal amplitude is set to 80, when the average amplitude of the sampled signal is greater than 80, it indicates that the signal strength of the current link is sufficient and the quality is stable. The electrical signal detected by the analog front end can be accurately processed by the digital back end after analog-to-digital conversion, and it is not easy to have problems such as signal distortion and increased bit error rate due to external interference or channel loss.

[0062] The preset link status judgment strategy is a pre-constructed rule system based on the first flag value of the analog front-end signal detection register 101, the second flag value of the digital back-end signal detection register 102, and the third flag value of the basic control register 103. This strategy systematically integrates and analyzes the link-related status information represented by the three flag values, providing a unified and standardized judgment standard for accurate link connection status determination. In practical applications, specific judgment rules can be flexibly formulated based on the electrical signal detection status recorded by the analog front-end signal detection register 101, the average amplitude of the sampled signal recorded by the digital back-end signal detection register 102, and the operating mode of the physical layer chip 100 recorded by the basic control register 103, combined with specific application scenarios or actual business needs. This ensures that the link connection status judgment results are highly adapted to actual application requirements, thereby effectively supporting the stable operation of network equipment.

[0063] The link connection status is the working status of the physical layer chip 100, including normal connection, abnormal status and other situations.

[0064] The physical layer chip 100 integrates an analog front-end signal detection register 101, a digital back-end signal detection register 102, and a basic control register 103. When performing link status detection, the status detection module 104 first obtains the first flag value of the analog front-end signal detection register 101, the second flag value of the digital back-end signal detection register 102, and the third flag value of the basic control register 103.

[0065] After obtaining the three flag values, they are transmitted to the logic determination module 105. The logic determination module 105 performs comprehensive analysis and judgment on the three flag values ​​according to the preset link status judgment strategy, and finally determines the link connection status.

[0066] In this way, by collecting link status information from three different dimensions and combining it with preset strategies to determine link status, the traditional mode of relying solely on digital backend detection results is changed. This can more comprehensively reflect the real situation of the link, effectively avoid the link status judgment deviation caused by a single judgment basis, and thus ensure the accuracy of link status determination to a certain extent, improve the adaptability of network devices to complex network environments, and enhance the stability and reliability of network devices.

[0067] In some implementations, when an electrical signal is detected, the first flag bit is 1; when no electrical signal is detected, the first flag bit is 0; when the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, the second flag bit is 1; when the average amplitude of the sampled signal is less than the first preset signal amplitude, the second flag bit is 0; and when the physical layer chip 100 is in a state of unsuccessful negotiation, the third flag bit is 00.

[0068] Please see Figure 2 In some implementations, the analog front-end signal detection register 101 is configured such that when the physical layer chip 100 detects an electrical signal, the first flag bit is set to 1, and when no electrical signal is detected, the first flag bit is set to 0. The digital back-end signal detection register 102 is configured such that when the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, the second flag bit is set to 1, and when the average amplitude of the sampled signal is less than the first preset signal amplitude, the second flag bit is set to 0. The basic control register 103 is configured such that when the physical layer chip 100 is in the unsuccessful negotiation state, the third flag bit is 00.

[0069] Specifically, the unsuccessful negotiation state is the working state in which the physical layer chip 100 and the peer device of the link fail to reach an agreement on parameters such as communication rate and duplex mode. At this time, the link cannot transmit data normally.

[0070] In practical applications, it is necessary to quantify the signal status of the link and the chip operating mode, and set a unified judgment standard for different links in order to achieve accurate link determination.

[0071] In this embodiment, the first flag value is assigned based on whether an electrical signal is detected. The electrical signal is transmitted to the analog front-end of the physical layer chip 100 through a physical medium such as twisted pair or optical fiber. Components such as the receiving amplifier of the analog front-end detect external signals. When the electrical signal is detected, it indicates that there may be signal transmission in the link, and the first flag value is set to 1. When no electrical signal is detected, it indicates that there may be no signal input in the link, and the first flag value is set to 0. This binary assignment method can quickly characterize the presence and state of the electrical signal.

[0072] The second flag value is assigned based on a comparison between the average amplitude of the sampled signal and the amplitude of the first preset signal. The sampled signal is a digital signal obtained by an analog-to-digital converter after being processed by the analog front-end of the physical layer chip 100. The average amplitude of the sampled signal is the average calculation result of the amplitude of the sampled signal over a certain period of time, which can reflect the overall strength of the signal. When the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, it indicates that the signal strength meets the requirements, and the second flag value is set to 1; when the average amplitude of the sampled signal is less than the first preset signal amplitude, it indicates that the signal strength is insufficient, and the second flag value is set to 0.

[0073] The value of the third flag bit is related to the operating mode of the physical layer chip 100, which includes various operating modes such as unsuccessful negotiation and successful negotiation. To facilitate the identification of the operating mode of the physical layer chip 100, the third flag bit is set to 00. This combination of values ​​can clearly distinguish the unsuccessful negotiation state from other operating modes, providing a clear reference for link status judgment.

[0074] In this way, by clarifying the specific value rules for the three flag bits, a standardized and consistent input basis is provided for link status determination. The unified value rules enable the accurate quantification of electrical signal detection results, sampling signal amplitude status, and chip operating modes in different scenarios. To a certain extent, this avoids the confusion caused by inconsistent value standards and improves the accuracy and reliability of the determination results. At the same time, the binary assignment rules reduce the technical implementation difficulty, making it easier for developers to understand and apply, which is conducive to the promotion and implementation of the solution and improves the practicality and operability of the entire technical solution to a certain extent.

[0075] Please see Figure 3 In some implementations, step 02 includes: 021: If the first flag value and the second flag value are both 0 and the third flag value is 00, the link connection status is determined to be idle.

[0076] Specifically, the idle state is a link state in which no effective connection has been established, no effective electrical signal is transmitted in the physical medium, the physical layer chip 100 has not reached a negotiation with the peer device, and data transmission and reception are impossible.

[0077] The first flag value is 0, indicating that the analog front end of the physical layer chip 100 has not detected an external electrical signal, and the current link may not have an external signal input, and there is no basic condition for signal transmission.

[0078] The second flag value being 0 indicates that the average amplitude of the sampled signal is less than the first preset signal amplitude. Considering the workflow of the physical layer chip 100, when the analog front-end does not detect an electrical signal, it cannot generate a sampling signal that meets the requirements. Therefore, the combination of the second flag value being 0 and the first flag value being 0 further confirms that the link has no effective signal transmission.

[0079] The third flag value is 00, which corresponds to the physical layer chip 100 operating mode being in a failed negotiation state. When there is no valid signal transmission on the link, the physical layer chip 100 cannot negotiate communication parameters with the peer device and is in a failed negotiation state, corresponding to the states represented by the first flag value being 0 and the second flag value being 0.

[0080] The preset link status judgment strategy associates the combination of the above three flag values ​​with the idle state. When the above three conditions are met at the same time, the link connection status can be determined to be idle. At this time, the upper layer of the system does not need to send and receive data packets, and network resources can be allocated reasonably to avoid resource waste.

[0081] When actually determining the link connection status, the status detection module 104 obtains the first flag value, the second flag value, and the third flag value of the three registers respectively, and the logic determination module 105 compares them according to the above conditions. Only when the three flag values ​​simultaneously meet the above three conditions will it be determined to be in an idle state, ensuring the accuracy of the determination result and avoiding misjudgment due to the satisfaction of a single condition.

[0082] In this way, by clearly defining the correspondence between specific flag bit values ​​and idle status, the system can quickly and accurately identify the idle status of the link to a certain extent, providing a reliable basis for resource allocation and task scheduling at the upper layer of the system. At the same time, accurate idle status identification helps maintenance personnel understand the usage of network links, providing a reference for network optimization and expansion, and improving the operating efficiency and management convenience of the network system to a certain extent.

[0083] Please see Figure 4 In some implementations, step 02 includes: 022: If the first and second flag values ​​are both 1 and the third flag value is not 00, the link connection status is determined to be busy.

[0084] Specifically, the busy state is a link state in which a valid connection has been established, there is stable electrical signal transmission in the physical medium, and the physical layer chip 100 has successfully negotiated with the peer device and is in the data transmission and reception state.

[0085] The first flag value is 1, indicating that the analog front end of the physical layer chip 100 has successfully detected the external electrical signal, and the peer device may be sending a signal or has established a signal connection.

[0086] The second flag value is 1, indicating that the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude. After analog-to-digital conversion, the strength of the electrical signal detected by the analog front end meets the requirements of subsequent digital processing. The signal is valid and available and can support normal data transmission.

[0087] A non-zero value for the third flag indicates that the physical layer chip 100 is in a successful negotiation state. A successful negotiation state means that the physical layer chip 100 and the peer device have completed communication parameter negotiation through the automatic negotiation module, determining the maximum communication rate, duplex mode, and other parameters supported by both parties, thus preparing for data transmission. Furthermore, different combinations of non-zero flag values ​​correspond to different successful negotiation modes. For example, a third flag value of 01 indicates that the physical layer chip 100 is in a 100 Mbps full-duplex mode; a third flag value of 10 indicates that the physical layer chip 100 is in a 10 Mbps half-duplex mode; and a third flag value of 11 indicates that the physical layer chip 100 is in a gigabit full-duplex mode. All of these indicate that the physical layer chip 100 is in a normal communication working state.

[0088] The preset link status judgment strategy associates the combination of the above three flag values ​​with the busy state. When the above three conditions are met at the same time, the link connection status can be determined to be busy.

[0089] When actually determining the link connection status, the status detection module 104 obtains the first flag value, the second flag value, and the third flag value of the three registers respectively, and the logic determination module 105 compares them according to the above conditions. Only when all three flag values ​​meet the requirements will the system be determined to be in a busy state, ensuring the accuracy of the determination result and avoiding misjudgments caused by factors such as signal interference.

[0090] In this way, by clearly defining the correspondence between specific flag bit value combinations and busy status, the system can accurately identify the normal communication status of the link, enabling the upper layer of the system to quickly decide on the sending and receiving of data packets based on the judgment results. This improves the efficiency of network communication to a certain extent. Furthermore, this judgment rule is based on multi-dimensional cross-validation, avoiding misjudgments caused by single-dimensional judgment, and improving the accuracy of busy status judgment. This provides a strong guarantee for the stable and efficient operation of network devices to a certain extent.

[0091] Please see Figure 5 In some implementations, step 02 includes: 023: If the first flag value and the second flag value are different, obtain the first flag value, the second flag value and the third flag value a preset number of times; 024: If the first flag value and the second flag value are different each time they are obtained, the link connection status is determined to be abnormal. 025: If the first flag value and the second flag value are the same at least once in the preset number of times, determine the link connection status according to the first flag value, the second flag value and the third flag value and the preset link status judgment strategy.

[0092] Please see Figure 2 In some implementations, the state detection module 104 is configured to acquire the first flag bit value, the second flag bit value, and the third flag bit value a preset number of times when the first flag bit value and the second flag bit value are different. The logic determination module 105 is configured to determine that the link connection status is abnormal when the first flag value and the second flag value are different each time. If the first flag value and the second flag value are the same at least once in a preset number of attempts, the link connection status is determined based on the first flag value, the second flag value, the third flag value, and the preset link status judgment strategy.

[0093] Specifically, an abnormal state is a link state where there is a fault or interference, resulting in inconsistent signal detection results between the analog front end and the digital back end, and data transmission cannot be carried out normally.

[0094] The preset number of times is the number of times the flag value is collected based on actual needs such as network environment stability and device response speed. It is used to ensure the stability and reliability of the test results, and is usually 3 times.

[0095] The status detection module 104 periodically collects the first flag bit value, the second flag bit value, and the third flag bit value of three registers for link connection status determination.

[0096] During data processing, the logic determination module 105 first determines whether the first flag value and the second flag value are the same. The first flag value indicates whether the analog front end has detected an electrical signal, and the second flag value indicates whether the average amplitude of the sampled signal meets the standard. Under normal circumstances, the two should be consistent.

[0097] When the two flags differ, there could be several reasons. For example, the difference could be a momentary anomaly caused by a sudden interruption of the external link, or it could be a genuine abnormal state caused by hardware failure or continuous interference. To distinguish the specific reasons for the difference between the first and second flag values, multiple verifications are required.

[0098] The status detection module 104 repeatedly collects three flag values ​​a preset number of times. During each acquisition interval, the system waits for a preset time to ensure that the flag values ​​acquired each time can reflect the true status of the link and avoid data duplication or inaccuracy caused by continuous and rapid acquisition.

[0099] The logic judgment module 105 verifies the results of each acquisition one by one. If the first flag value and the second flag value obtained each time are different, it indicates that the difference is not caused by instantaneous interference, but that there is a continuous abnormality in the link. At this time, the link connection status is determined to be abnormal.

[0100] If the first flag value and the second flag value are the same at least once in the preset number of times, it indicates that the previous difference may have been caused by transient interference, and the link has returned to normal or there is normal state fluctuation. At this time, the link connection status needs to be determined based on the same first flag value, second flag value and third flag value, combined with the preset link status judgment strategy.

[0101] Thus, a multi-round verification judgment mechanism was established for special scenarios where the first and second flag values ​​are different. This enables the detection scheme to cover various link scenarios, including normal and abnormal ones. To a certain extent, it effectively filters out false differences caused by factors such as instantaneous interruption of external links and accidental interference, avoids misjudgment caused by single detection, improves the accuracy and reliability of abnormal state judgment, enhances the stability and adaptability of network devices, and reduces the risk of communication failures caused by link misjudgment.

[0102] Please see Figure 6 In some embodiments, the physical layer chip 100 further includes a digital back-end signal quality register 106. The fourth flag bit of the digital back-end signal quality register 106 is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fourth flag bit is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fourth flag bit is 0. The second preset signal amplitude is less than the first preset signal amplitude. Step 024 includes: 0241: When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, perform renegotiation processing for a preset number of negotiation times; 0242: After completing the renegotiation process for the preset number of negotiation cycles, obtain the first flag value, the second flag value, and the third flag value again; 0243: Determine the link connection status based on the first flag value, second flag value, and third flag value obtained again and the preset link status judgment strategy; 0244: When the link connection status is abnormal, the physical layer chip 100 is reset.

[0103] Please see Figure 7 In some embodiments, the physical layer chip 100 further includes a digital back-end signal quality register 106 and a recovery execution module 107. The fourth flag bit of the digital back-end signal quality register 106 is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fourth flag bit is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fourth flag bit is 0. The second preset signal amplitude is less than the first preset signal amplitude. The execution recovery module 107 is configured to perform a preset number of renegotiation processes when the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00. The status detection module 104 is configured to acquire the first flag value, the second flag value, and the third flag value again after completing the renegotiation process for a preset number of negotiation times. The logic determination module 105 is configured to determine the link connection status based on the first flag value, the second flag value, and the third flag value obtained again and the preset link status determination strategy. The recovery execution module 107 is configured to reset the physical layer chip 100 when the link connection status is abnormal.

[0104] Specifically, the digital back-end signal quality register 106 is a newly added register in the physical layer chip 100 used to evaluate the quality of the sampled signal. The fourth flag bit value reflects whether the sampled signal meets the basic communication requirements, providing a basis for the subdivision of abnormal scenarios.

[0105] The fourth flag bit value is a specific bit value in the digital back-end signal quality register 106 used to characterize whether the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, and is an indicator for distinguishing signal quality levels.

[0106] The second preset signal amplitude is a pre-set standard signal amplitude lower than the first preset signal amplitude. It is used to judge the severity of the sampled signal quality, determine whether the sampled signal has basic communication potential, and provide a judgment benchmark for graded recovery. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, it indicates that the signal quality is basically qualified and has basic communication potential, and the fourth flag bit is set to 1. When the average amplitude of the sampled signal is less than the second preset signal amplitude, it indicates that the signal quality is poor, does not have basic communication potential, and cannot meet normal communication requirements, and the fourth flag bit is set to 0.

[0107] For example, the average amplitude of the sampled signal is converted into a range of 0 to 256 steps. Typically, the physical layer chip 100 divides this step into a "severe threshold," i.e., a second preset signal amplitude, based on the basic communication requirements of the link. The sampled signal strength corresponding to the average amplitude of the sampled signal that is greater than or equal to this "severe threshold" can basically meet the communication requirements and has basic communication potential. For example, if the first preset signal amplitude is set to 80 and the second preset signal amplitude is set to 30, when the average amplitude of the sampled signal is greater than or equal to 30 and less than 80, it indicates that the current sampled signal strength can basically meet the communication requirements and has basic communication potential. The physical layer chip 100 and the link peer device have the conditions to establish a negotiated link connection. However, due to the poor quality of the negotiated link, the signal transmission between the two ends is easily interfered with, and the signal carrying capacity is limited, resulting in poor communication performance. Therefore, the negotiated link parameters need to be adjusted.

[0108] The preset number of negotiation attempts is the number of renegotiations that are pre-set based on the performance of the physical layer chip 100 and the network environment, ensuring that the physical layer chip 100 has sufficient opportunities to establish a valid link. It can usually be set to 2 times.

[0109] Renegotiation is the process by which the physical layer chip 100 renegotiates parameters such as communication rate and duplex mode with the peer device in an attempt to establish a link connection that is adapted to the current signal quality.

[0110] The reset process is an initialization operation performed on the physical layer chip 100, which can clear the abnormal state and temporary configuration inside the physical layer chip 100 and restore the initial working state to resolve the fault.

[0111] When the logic determination module 105 detects that the first flag value and the second flag value are different each time they are acquired, it needs to combine the fourth flag value and the third flag value to further determine the abnormal state type.

[0112] When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, it indicates that the analog front end has detected an electrical signal, but the average amplitude of the sampled signal has not reached the first preset signal amplitude but is greater than or equal to the second preset signal amplitude, and the physical layer chip 100 is in a state of unsuccessful negotiation. This situation is usually caused by poor external link signal quality. At this time, the renegotiation process of the preset number of negotiations can be performed by the recovery execution module 107.

[0113] After completing the renegotiation process for the preset number of negotiation cycles, the status detection module 104 acquires three flag values ​​again, and the logic determination module 105 redetermines the link connection status based on the new flag values ​​and the preset link status judgment strategy.

[0114] If the link status returns to normal after renegotiation, the process ends. If the link is still in an abnormal state after completing the preset number of negotiations, it indicates that the renegotiation process cannot solve the problem and there may be more serious situations such as hardware failure. At this time, the recovery execution module 107 performs a reset process on the physical layer chip 100, clears the abnormal state and reinitializes it, attempts to establish a normal link connection, and restores the normal operation of the chip.

[0115] Understandably, for anomalies caused by poor signal quality, the system attempts to restore the normal link connection by renegotiation after a preset number of negotiations, which improves the success rate of anomaly recovery. Furthermore, when renegotiation fails, a reset is performed, which effectively ensures the complete elimination of the abnormal state. This approach avoids the impact of blind resets on normal communication to a certain extent, while also ensuring that the abnormal state can be effectively handled.

[0116] Furthermore, the automatic recovery mechanism that executes the corresponding link recovery operation based on the judgment result of the logic judgment module 105 reduces the need for manual intervention, lowers operation and maintenance costs, and improves the stability and availability of the network system.

[0117] Thus, by adding a digital back-end signal quality register, precise segmentation of signal quality under abnormal scenarios is achieved. This enables the differentiation of anomalies caused by different reasons, and the hierarchical recovery mechanism corresponding to specific flag bit value combinations prioritizes link recovery attempts through renegotiation, fully utilizing the basic communication potential of the signal, reducing unnecessary reset operations, and lowering system overhead. Simultaneously, by handling abnormal link states hierarchically, the link state detection and recovery mechanism becomes more targeted and flexible, improving the efficiency and success rate of link anomaly recovery to a certain extent. This enhances the self-diagnosis and repair capabilities of the physical layer chip 100, improves the stability and reliability of network devices, and is suitable for complex communication scenarios such as poor network cable quality and strong interference.

[0118] In some implementations, the fifth flag bit value of the digital back-end signal detection register 102 is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fifth flag bit value is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fifth flag bit value is 0. The second preset signal amplitude is less than the first preset signal amplitude. If the first flag bit value and the second flag bit value are different each time they are obtained, the link connection status is determined to be abnormal, including: If the first flag bit is 1, the second flag bit is 0, the fifth flag bit is 1 and the third flag bit is 00, perform a renegotiation process for a preset number of negotiation times; After completing the renegotiation process for the preset number of negotiation attempts, the first flag value, the second flag value, and the third flag value are obtained again. Based on the newly acquired first flag value, second flag value, and third flag value and the preset link status judgment strategy, determine the link connection status; If the link connection is in an abnormal state, the physical layer chip 100 is reset.

[0119] Specifically, the fifth flag bit value is a specific bit value in the digital back-end signal detection register 102 used to characterize whether the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude. It is an indicator for evaluating whether the quality of the sampled signal meets the basic communication requirements.

[0120] The status detection module 104 periodically collects the first flag bit value, the second flag bit value, and the third flag bit value of three registers according to preset rules to determine the link connection status.

[0121] When the logic determination module 105 detects that the first flag value and the second flag value are different each time, it further determines whether the conditions of the first flag value being 1, the second flag value being 0, the fifth flag value being 1, and the third flag value being 00 are met.

[0122] If the condition is met, the recovery execution module 107 starts the renegotiation process and renegoties the communication parameters with the peer device according to the preset number of negotiations.

[0123] After each renegotiation is completed, the status detection module 104 collects the values ​​of the three core flag bits again, and the logic judgment module 105 determines the link status according to the preset link status judgment strategy.

[0124] If the link status returns to normal after renegotiation, the process ends. If the link is still in an abnormal state after the preset number of negotiations, the recovery execution module 107 performs a reset process on the physical layer chip 100, clears the abnormal state and reinitializes it, and attempts to establish a normal link connection.

[0125] In this way, by adding a fifth flag value, the quality of the sampled signal can be subdivided and evaluated, and specific abnormal scenarios that can be recovered through renegotiation can be accurately identified. To a certain extent, this avoids directly including all inconsistent signal detection results into the reset process, reducing unnecessary system overhead. Furthermore, renegotiation is performed preferentially for specific flag value combinations, making full use of the low-speed communication potential still possessed by the signal. This improves the success rate and efficiency of link anomaly recovery to a certain extent and reduces link interruption time.

[0126] Furthermore, the fallback mechanism that triggers a reset after a renegotiation failure ensures that abnormal states can be completely resolved, preventing the fault from continuing to affect network communication. This makes the link state detection and recovery mechanism more targeted and flexible, thereby enhancing the self-diagnosis and repair capabilities of the physical layer chip 100 to a certain extent, improving the stability and reliability of network devices, and making it suitable for complex communication scenarios such as poor network cable quality and strong interference.

[0127] Please see Figure 8 In some embodiments, step 0241 includes: 02411: When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, the renegotiation process is performed for a preset number of times based on the speed reduction adaptive mechanism of the physical layer chip 100.

[0128] Specifically, the downspeed adaptive mechanism is a function of the physical layer chip 100 that automatically adjusts the communication rate based on the link signal quality. When the signal quality is poor, the physical layer chip 100 will lower the negotiated rate standard, shifting from a high-speed mode to a lower-speed mode, such as from gigabit mode to 100 Mbps or 10 Mbps mode. Lower-speed communication has relatively lower requirements for signal quality, making it easier to establish a stable connection in link environments with poor signal quality.

[0129] The status detection module 104 periodically collects the flag bit values ​​corresponding to the four registers to determine the link connection status. When the logic determination module 105 detects that the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1, and the third flag bit is 00, it indicates that there is an electrical signal in the current link, but the signal quality is poor. The average amplitude of the sampled signal does not reach the first preset signal amplitude but is higher than the second preset signal amplitude, and the chip has failed to negotiate, triggering the renegotiation process.

[0130] If renegotiation is performed directly at this point, negotiating at the original rate may not be compatible with the current signal quality, leading to negotiation failure.

[0131] Therefore, during the renegotiation process, the autonegotiation module of the physical layer chip 100 will combine a rate reduction adaptive mechanism to send negotiation frames including lower rate options to the peer device.

[0132] After receiving the negotiation frame, the peer device will respond according to its own supported rate range. The two parties will eventually determine a lower rate that they both support and that is suitable for the current signal quality as the communication rate.

[0133] The preset number of negotiations is usually 2. During each renegotiation process, a speed reduction adaptive mechanism is enabled to ensure that different rate combinations are fully tried, thereby increasing the probability of successful renegotiation. After each renegotiation is completed, the flag value is retrieved again for judgment, and the renegotiation effect is re-examined.

[0134] Thus, by introducing a speed reduction adaptive mechanism during the renegotiation process, the physical layer chip 100 can flexibly adjust the negotiation rate according to the link signal quality, which increases the probability of successful renegotiation and avoids negotiation failure and link interruption caused by rate mismatch. This enhances the self-repair capability of the physical layer chip 100 to a certain extent, effectively reduces the duration of link anomalies, lowers maintenance costs, and improves the stability and reliability of network devices. It is suitable for complex communication scenarios such as poor network cable quality and strong interference.

[0135] Please see Figure 9 In some implementations, the method includes: 03: If the first flag bit is 0, the second flag bit is 1, the fourth flag bit is 0, or the third flag bit is not 00, the link connection status is determined to be abnormal. 04: If the link connection is in an abnormal state, the physical layer chip 100 will be reset.

[0136] Please see Figure 7 In some implementations, the logic determination module 105 is configured to determine that the link connection status is abnormal when the first flag bit value is 0, the second flag bit value is 1, the fourth flag bit value is 0, or the third flag bit value is not 00. The recovery execution module 107 is configured to reset the physical layer chip 100 when the link connection status is abnormal.

[0137] Specifically, a first flag value of 0 indicates that the analog front end has not detected an electrical signal. If other flag values ​​show a valid signal or a successful negotiation status, it indicates that the detection results are contradictory and the link is abnormal.

[0138] The second flag value of 1 indicates that the average amplitude of the sampled signal meets the standard. If it presents an unreasonable state in combination with other flag values, such as no electrical signal is detected but there is a valid sampled signal, it indicates that there is an abnormality in the link.

[0139] A value of 0 for the fourth flag indicates that the average amplitude of the sampled signal is less than the second preset signal amplitude, the signal quality is poor and cannot meet the basic communication requirements, which is an abnormal state.

[0140] A value other than 00 for the third flag indicates that the chip is in a successful negotiation state. If the combination with other flag values ​​does not conform to normal communication logic, for example, if no electrical signal is detected but the negotiation has been successful, it also indicates that there is an abnormality in the link.

[0141] When determining the link connection status, the status detection module 104 periodically collects the first flag bit value, the second flag bit value, the third flag bit value and the fourth flag bit value corresponding to the four registers according to preset rules.

[0142] During data processing, the logic judgment module 105 performs combined verification on the four collected flag bit values ​​to determine whether any of the following conditions are met: the first flag bit value is 0, the second flag bit value is 1, the fourth flag bit value is 0, or the third flag bit value is not 00.

[0143] When any one of the above conditions is met by the four flag values, the logic determination module 105 directly determines that the link connection status is abnormal. These abnormalities may be caused by hardware failure, continuous severe signal interference, abnormal register read values, etc. Simple renegotiation processing often cannot solve the problem, and a more thorough reset processing method is required.

[0144] During the reset process, the logic determination module 105 first sends a reset trigger signal to the recovery execution module 107. After receiving the signal, the recovery execution module 107 performs a reset process on the physical layer chip 100, clears the abnormal state and fault logic inside the physical layer chip 100, and restarts the physical layer chip 100 to attempt to establish a normal link connection, thus completing the abnormal handling process.

[0145] In practical applications, the system monitors the values ​​of each flag bit in real time. Once the above abnormal conditions are detected, the system immediately triggers the reset process to ensure that the abnormality can be cleared in time and to avoid the abnormal state from continuing to affect network communication.

[0146] In this way, by clearly defining the anomaly judgment rules corresponding to multiple flag bit value combinations, comprehensive coverage of link anomaly scenarios is achieved, avoiding the problem of unmanageable issues due to omissions of anomaly scenarios. Furthermore, the multi-dimensional anomaly judgment conditions can accurately identify different types of link anomalies, to a certain extent preventing the omission of some abnormal states and improving the comprehensiveness and accuracy of link status detection. Simultaneously, directly triggering a reset process for abnormal states can quickly clear the abnormal states and fault logic inside the chip, preventing anomalies from continuously affecting network communication. This, to a certain extent, improves the efficiency of link fault handling, enabling the physical layer chip 100 to have self-diagnosis and repair capabilities. This effectively reduces the duration of abnormal situations such as false connections and link jams, lowers maintenance costs, and enhances the stability and reliability of network equipment.

[0147] Please see Figure 10 In some embodiments, steps 0244 and 04 include: 02441: Read and store the configuration parameters of the basic control register 103; 02442: Perform a reset on physical layer chip 100; 02443: After completing the reset process of the physical layer chip 100, the configuration parameters are rewritten into the basic control register 103; 02444: Power-on process for physical layer chip 100; 02445: After completing the power-on process of the physical layer chip 100, a renegotiation process is performed.

[0148] Please see Figure 7 In some implementations, the recovery execution module 107 is configured to read and store the configuration parameters of the base control register 103; Perform a reset on the physical layer chip 100; After completing the reset process of the physical layer chip 100, the configuration parameters are rewritten into the basic control register 103; Power on the physical layer chip 100; After the power-on process of the physical layer chip 100 is completed, a renegotiation process is performed.

[0149] Specifically, the configuration parameters, such as the flow control switch status, negotiation results, duplex mode, and power saving mode, stored in the basic control register 103, determine the working mode and performance of the physical layer chip 100.

[0150] Power-on processing is the operation of providing operating power to physical layer chip 100 after it is reset, so that it enters normal operating state from power-off or low-power state.

[0151] When the logic determination module 105 determines that the link connection status is abnormal, it triggers a reset process. First, the system reads all configuration parameters stored in the basic control register 103 in the physical layer chip 100 and stores these configuration parameters in a temporary cache area to ensure that the parameters are not lost.

[0152] Subsequently, the system performs a reset process on the physical layer chip 100, clearing the abnormal state, temporary data and fault logic inside the physical layer chip 100, and restoring all status registers to their initial default state. At this time, the physical layer chip 100 enters a low-power or power-off state.

[0153] In addition, in some implementations, the reset operation can be achieved by writing a control signal to a specific reset bit of the basic control register 103. After the reset signal is written, the physical layer chip 100 enters the reset mode, and the reset bit will automatically be restored to the default value after the reset is completed.

[0154] After the reset process is completed, the system retrieves the previously stored configuration parameters from the temporary cache and rewrites them into the basic control register 103, so that the physical layer chip 100 is restored to its working configuration before the abnormality, thus avoiding configuration loss and functional abnormality caused by the reset.

[0155] After the configuration parameters are written, the system powers on the physical layer chip 100, enabling it to start from the initial state and enter the normal operating ready state. In some implementations, the reset operation usually defaults to powering down the physical layer chip 100. Therefore, it is necessary to write a signal to the power-on control bit of the basic control register 103 to power on the physical layer chip 100 and enable it to enter the normal operating mode.

[0156] After powering on, the physical layer chip 100 automatically renegotiates communication parameters with the peer device to establish a new valid link connection, completing the entire anomaly recovery process. Furthermore, since the physical layer chip 100 has restored its previous configuration parameters, the renegotiation process is based on these parameters, enabling the rapid establishment of a communication connection consistent with the pre-anomaly state. This improves the link's recovery efficiency from anomaly to normal, shortens network communication interruption time, and ensures the continuous availability of network devices.

[0157] Understandably, the backup and restoration of configuration parameters effectively ensures that the physical layer chip 100 can quickly restore its original working state after a reset, without the need for manual reconfiguration, reducing maintenance costs and improving the fault recovery efficiency of network devices. Furthermore, the reset process can clear abnormal states, logical disorder, and other faults inside the physical layer chip 100. Combined with the subsequent power-on and renegotiation process, it can, to a certain extent, ensure that the link can re-establish a valid connection and reduce the probability of abnormal state recurrence.

[0158] In this way, the standardized closed-loop reset process effectively solves the problems of parameter loss and incomplete recovery caused by traditional chip reset. To a certain extent, it ensures that the physical layer chip 100 can be restored to its working state before the abnormality after reset, reducing the probability of abnormal state recurrence. Moreover, after the link is determined to be in an abnormal state, the closed-loop reset process is automatically executed, enabling the physical layer chip 100 to have the ability to self-diagnose and self-recover. This reduces the link interruption time to a certain extent, improves the stability and reliability of network devices, and provides a strong guarantee for the continuous and smooth network communication.

[0159] In some implementations, the link state detection method based on the physical layer chip 100 can be integrated into the driver program of the physical layer chip 100 and continuously executed through a loop polling mechanism in the main program. The polling cycle is consistent with the execution cycle of the driver program, ensuring that the detection method can be accurately invoked each time the main task is scheduled, thus guaranteeing the continuity of link state monitoring.

[0160] Taking a switch as an example, its internal switching chip or media access control chip periodically queries the port status of the downstream physical layer chip. This query function can be implemented through the PHY_getPortStatus function. This function itself has the core capability to read the working status of the physical layer chip. The link status detection method of this application can be integrated into this function. With the help of its existing status reading channel and polling scheduling mechanism, it can efficiently complete a series of operations such as multi-dimensional register data acquisition, link status determination and anomaly recovery without the need for additional independent scheduling logic, thus achieving seamless compatibility with existing systems.

[0161] Please see Figure 11 The following explanation uses a commercial physical layer chip supporting Gigabit Ethernet as the core, and an enterprise-level switch as the basis for building a link detection system, to illustrate the link state detection method based on the physical layer chip in this application: This physical layer chip integrates the analog front-end signal detection register ANA_SG_DET, the digital back-end signal detection register DIG_SQ_DET, the basic control register MCR, the digital back-end signal quality register DIG_SQ_BADREAD, and the linkstatus register. The link status register is 16 bits; bit 2 indicates whether the port is linked up. It is set to 1 if linked up, and 0 otherwise. The system has built-in status detection, logic determination, and recovery execution modules. All detection logic is embedded in the switch driver through the PHY_getPortStatus function, enabling periodic polling monitoring of each PHY port.

[0162] During actual operation, the PHY_getPortStatus function continuously performs polling operations on each PHY port of the switch according to the period set by the driver. Whenever polling is triggered, the status detection module synchronously reads the bit0 value of ANA_SG_DET, the bit15 value of DIG_SQ_DET, the bit4 / 5 values ​​of MCR, the flag value of DIG_SQ_BADREAD, and the current status of the link status register through the MDIO management interface. This status data collected from different dimensions is transmitted to the logic determination module in real time, providing comprehensive raw evidence for accurate determination of link status.

[0163] After receiving the data, the logic judgment module immediately starts the consistency logic judgment program and analyzes the scenario according to the preset link status judgment strategy.

[0164] When ANA_SG_DET==0, DIG_SQ_DET==0 and MCR[4:5]==00 are detected, it is determined that there is no signal input on the PHY port and it is in a normal idle state. At this time, bit 2 of the link status register is set to 0, and then the current program is exited to wait for the next round of polling to be triggered.

[0165] When ANA_SG_DET==1, DIG_SQ_DET==1 and MCR[4:5]≠00 are detected, it indicates that both the analog front-end and digital back-end of the PHY have detected valid signals and have successfully negotiated with the peer device. The port is determined to be in a normal busy state. At this time, bit 2 of the link status register is set to 1, and the program is exited to enter the next loop.

[0166] If the logic determination module detects that ANA_SG_DET ≠ DIG_SQ_DET, meaning the signal identifiers of the analog and digital modules before and after the receiving channel are inconsistent, the system will activate a read value accuracy guarantee mechanism to avoid misjudgment caused by occasional anomalies such as momentary interruptions in the external link. The status detection module 104 will reread the above register values ​​three times. If all three reads result in ANA_SG_DET ≠ DIG_SQ_DET, it is determined that there is a link establishment anomaly in the PHY. The logic determination module will then send an anomaly trigger signal to the recovery execution module to initiate the subsequent recovery process.

[0167] After the execution module response is restored, the anomaly type is further determined. If ANA_SG_DET==1, DIG_SQ_DET==0, DIG_SQ_BADREAD==1 and MCR[4:5]==00 are detected, it indicates that the analog front-end detected an electrical signal, but the digital back-end cannot process it normally because the signal quality is less than the "healthy waterline" or greater than or equal to the "poor waterline", and it has not successfully negotiated with the peer device. This is determined to be an abnormal situation of poor link quality. At this time, bit2 of the link status register remains unchanged.

[0168] The recovery execution module will initiate the Re-AN renegotiation process. Based on the physical layer chip's speed reduction adaptive mechanism, it will renegotiate the communication rate and duplex mode with the Link partner. After the negotiation is completed, it will read the register value again to determine consistency. This renegotiation process will loop twice.

[0169] If ANA_SG_DET and DIG_SQ_DET are still inconsistent after two renegotiations, or if the exception type is any other case, it is determined that a false link failure has occurred in the PHY. At this time, the recovery execution module will first read and store the current configuration parameters of the MCR register, including key information such as flow control settings and negotiation mode.

[0170] Then, a reset operation is performed on the PHY chip to clear all abnormal states and temporary configurations. During the reset process, the port will automatically perform a power-down. During this process, bit 2 of the link status register will be restored to its initial state along with the reset operation.

[0171] After the reset is complete, the system will rewrite the previously stored configuration parameters into the MCR register, and then perform a power-up operation on the PHY chip. After successful power-up, the PHY will automatically re-handshake with the link partner and attempt to establish a link up. Once the link is back to normal, bit 2 of the link status register will be assigned a value based on the final determination result. If the link is determined to be up, the bit will be set to 1; otherwise, it will be set to 0. After that, the program will exit the recovery process and enter the next polling loop.

[0172] Understandably, from periodic polling to collect data, to the logic judgment module analyzing the status and synchronously updating the linkstatus register status, to the hierarchical recovery in case of anomalies, a complete closed-loop control system is formed. Through cross-validation of multi-dimensional register data, accurate status feedback from the link status register, and hierarchical recovery strategies, it effectively filters out misjudgments caused by occasional interference and can accurately address different types of anomalies, improving the accuracy of link status determination and the robustness of the system, reducing network operation and maintenance costs, and is suitable for scenarios with high requirements for link reliability, such as data centers and industrial IoT.

[0173] Understandably, some of the above implementation methods determine the link connection status by collecting the relevant flag bit values ​​of the analog front-end signal detection register 101, digital back-end signal detection register 102, and basic control register 103 inside the physical layer chip 100, and combining them with a preset link status judgment strategy.

[0174] Meanwhile, some of the above-described implementations use binary identifiers such as 0, 1, or 00 to identify the specific status of the link connection. However, these identifiers are merely exemplary rules set for the convenience of technical description and understanding, and are not a limitation on the identifier method. In fact, the implementation of the link status detection method based on the physical layer chip 100 does not depend on a specific identifier form. Other identifier methods such as multi-level numerical values ​​and combined encoding can be used according to the needs of the actual application scenario.

[0175] Binary identification and other identification methods are set based on the gradient differences or diverse states of physical characteristics such as electrical signal strength, sampling signal amplitude, and chip operating mode. The corresponding judgment rules are also adjusted in a targeted manner according to the changes in the identification method, and the link judgment logic of cross-validation of multi-dimensional state information is always maintained to ensure the accuracy and reliability of link state determination.

[0176] This application also provides an electronic device including a physical layer chip 100 of some of the above embodiments.

[0177] This application also provides a computer-readable storage medium storing a computer program that, when executed by one or more processors, implements the methods of some of the above-described embodiments.

[0178] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the methods of some of the above-described embodiments.

[0179] It is understood that a computer program includes computer program code. Computer program code can be in the form of source code, object code, executable files, or some intermediate form. Computer-readable storage media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution media, etc.

[0180] In this specification, the terms "specifically," "furthermore," "particularly," "understandably," etc., refer to specific features, structures, materials, or characteristics described in connection with embodiments or examples that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0181] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of executable request code comprising one or more steps for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0182] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A link state detection method based on a physical layer chip, characterized in that, The physical layer chip includes an analog front-end signal detection register, a digital back-end signal detection register, and a basic control register. The method includes: The first flag value of the analog front-end signal detection register, the second flag value of the digital back-end signal detection register, and the third flag value of the basic control register are obtained. The first flag value is used to indicate whether an electrical signal is detected, the second flag value is used to indicate whether the average amplitude of the sampled signal is greater than or equal to a first preset signal amplitude, and the third flag value is used to indicate the working mode of the physical layer chip. The link connection status is determined based on the first flag value, the second flag value, and the third flag value, along with a preset link status judgment strategy.

2. The method according to claim 1, characterized in that, When the electrical signal is detected, the first flag bit is 1; when the electrical signal is not detected, the first flag bit is 0; when the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, the second flag bit is 1; when the average amplitude of the sampled signal is less than the first preset signal amplitude, the second flag bit is 0; and when the physical layer chip is in a state of unsuccessful negotiation, the third flag bit is 00.

3. The method according to claim 2, characterized in that, The step of determining the link connection status based on the first flag value, the second flag value, and the third flag value and a preset link status judgment strategy includes: If the first flag value and the second flag value are both 0 and the third flag value is 00, the link connection state is determined to be idle.

4. The method according to claim 2, characterized in that, The step of determining the link connection status based on the first flag value, the second flag value, and the third flag value and a preset link status judgment strategy includes: If both the first and second flag values ​​are 1 and the third flag value is not 00, the link connection status is determined to be busy.

5. The method according to claim 2, characterized in that, The step of determining the link connection status based on the first flag value, the second flag value, and the third flag value and a preset link status judgment strategy includes: If the first flag value and the second flag value are different, obtain the first flag value, the second flag value and the third flag value a preset number of times; If the first flag value and the second flag value are different each time they are obtained, the link connection status is determined to be abnormal. If the first flag value and the second flag value are the same at least once in the preset number of times, the link connection status is determined according to the first flag value, the second flag value, the third flag value, and the preset link status judgment strategy.

6. The method according to claim 5, characterized in that, The physical layer chip also includes a digital back-end signal quality register. The fourth flag bit of the digital back-end signal quality register is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fourth flag bit is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fourth flag bit is 0. The second preset signal amplitude is less than the first preset signal amplitude. Determining the link connection status as abnormal when the first flag bit value and the second flag bit value are different each time includes: When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, a renegotiation process is performed for a preset number of times. After completing the renegotiation process for the preset number of negotiation times, the first flag value, the second flag value, and the third flag value are obtained again. The link connection status is determined based on the first flag value, the second flag value, and the third flag value obtained again, and the preset link status judgment strategy. If the link connection status is in the abnormal state, the physical layer chip is reset.

7. The method according to claim 6, characterized in that, The renegotiation process, performed a preset number of times, when the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1, and the third flag bit is 00, includes: When the first flag bit is 1, the second flag bit is 0, the fourth flag bit is 1 and the third flag bit is 00, the renegotiation process is performed for the preset number of negotiation times based on the speed reduction adaptive mechanism of the physical layer chip.

8. The method according to claim 6, characterized in that, The method further includes: If the first flag bit value is 0, the second flag bit value is 1, the fourth flag bit value is 0, or the third flag bit value is not 00, the link connection status is determined to be the abnormal status. If the link connection status is in the abnormal state, the physical layer chip is reset.

9. The method according to any one of claims 6-8, characterized in that, When the link connection status is in the abnormal state, the physical layer chip is reset, including: Read and store the configuration parameters of the basic control register; The physical layer chip is reset. After completing the reset process of the physical layer chip, the configuration parameters are rewritten into the basic control register; The physical layer chip is powered on. After the physical layer chip is powered on, a renegotiation process is performed.

10. A physical layer chip, characterized in that, The physical layer chip includes an analog front-end signal detection register, a digital back-end signal detection register, a basic control register, a status detection module, and a logic determination module. The state detection module is configured to acquire the first flag value of the analog front-end signal detection register, the second flag value of the digital back-end signal detection register, and the third flag value of the basic control register. The first flag value is used to indicate whether an electrical signal is detected, the second flag value is used to indicate whether the average amplitude of the sampled signal is greater than or equal to a first preset signal amplitude, and the third flag value is used to indicate the working mode of the physical layer chip. The logic determination module is configured to determine the link connection status based on the first flag value, the second flag value, and the third flag value, and a preset link status determination strategy.

11. The physical layer chip according to claim 10, characterized in that, The analog front-end signal detection register is configured such that when the physical layer chip detects the electrical signal, the first flag bit is set to 1, and when the electrical signal is not detected, the first flag bit is set to 0. The digital back-end signal detection register is configured such that when the average amplitude of the sampled signal is greater than or equal to the first preset signal amplitude, the second flag bit is 1, and when the average amplitude of the sampled signal is less than the first preset signal amplitude, the second flag bit is 0. The basic control register is configured such that, when the physical layer chip is in a state of unsuccessful negotiation, the third flag bit is set to 00.

12. The physical layer chip according to claim 11, characterized in that, The state detection module is configured to acquire the first flag value, the second flag value, and the third flag value a preset number of times when the first flag value and the second flag value are different. The logic determination module is configured to determine that the link connection status is abnormal when the first flag value and the second flag value are different each time. If the first flag value and the second flag value are the same at least once in the preset number of times, the link connection status is determined according to the first flag value, the second flag value, the third flag value, and the preset link status judgment strategy.

13. The physical layer chip according to claim 12, characterized in that, The physical layer chip also includes a digital back-end signal quality register and a recovery execution module. The fourth flag bit of the digital back-end signal quality register is used to characterize whether the average amplitude of the sampled signal is greater than or equal to a second preset signal amplitude. When the average amplitude of the sampled signal is greater than or equal to the second preset signal amplitude, the fourth flag bit is 1; when the average amplitude of the sampled signal is less than the second preset signal amplitude, the fourth flag bit is 0, indicating that the second preset signal amplitude is less than the first preset signal amplitude. The recovery execution module is configured to perform a preset number of renegotiation processes when the first flag bit value is 1, the second flag bit value is 0, the fourth flag bit value is 1 and the third flag bit value is 00. The state detection module is configured to, after completing the renegotiation process for the preset number of negotiation times, obtain the first flag value, the second flag value, and the third flag value again; The logic determination module is configured to determine the link connection status based on the first flag value, the second flag value, and the third flag value obtained again and the preset link status determination strategy. The recovery execution module is configured to reset the physical layer chip when the link connection status is in the abnormal state.

14. The physical layer chip according to claim 13, characterized in that, The logic determination module is configured to determine the link connection status as the abnormal state when the first flag bit value is 0, the second flag bit value is 1, the fourth flag bit value is 0, or the third flag bit value is not 00. The recovery execution module is configured to reset the physical layer chip when the link connection status is in the abnormal state.

15. The physical layer chip according to claim 13 or 14, characterized in that, The recovery execution module is configured to read and store the configuration parameters of the basic control register; The physical layer chip is reset. After completing the reset process of the physical layer chip, the configuration parameters are rewritten into the basic control register; The physical layer chip is powered on. After the physical layer chip is powered on, a renegotiation process is performed.

16. An electronic device, characterized in that, Includes the physical layer chip as described in any one of claims 10-15.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by one or more processors, implements the method according to any one of claims 1-9.

18. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the method described in any one of claims 1-9.

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