Bus signal for vehicle-gauge-level MCU chip adaptation evaluation, and generation method and device of bus signal for vehicle-gauge-level MCU chip adaptation evaluation

Abstract

The invention relates to the technical field of data transmission, and discloses a bus signal for vehicle gauge level MCU chip adaptation evaluation, a generation method and a device, the bus signal is composed of a start frame, a 6-bit racing frame, a variable length control frame, a data frame, a 16-bit CRC check frame, a response frame and an end frame in sequence; 3-bit priorities and 3-bit data type identifiers are built in the race frame, the length of the control frame is dynamically expanded by multiplying the number of data type identifiers in the race frame as 0 by 4 bits, and the byte length of integer and single / double-precision floating point type data is sequentially defined 4 bits by 4 bits, so that the self-description of a protocol layer is realized. The generating device automatically completes frame coding, data filling, periodic sending and response backward reading after parameters are configured on the upper computer, a test vector can be switched in a zero script mode within the range of 1-200 ms, and a single frame bears 192-byte mixed data to the maximum extent, so that real-time blind decoding can be achieved without preset analysis of an MCU chip. According to the invention, the adaptation verification period of the vehicle-gauge-level MCU chip is obviously shortened, the test coverage rate is improved, and the manual coding error risk is reduced.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a bus signal, generation method, and apparatus for automotive-grade MCU chip adaptation evaluation. Background Technology

[0002] As automotive electronic and electrical architectures rapidly evolve from distributed to domain-centralized systems, the number of ECUs per vehicle has decreased to less than ten. However, the algorithmic complexity and data throughput of a single ECU have increased exponentially. As the heart of the domain controller, the automotive-grade MCU's CPU core, storage bandwidth, peripheral interfaces, and real-time response capabilities must undergo deep matching and verification with the vehicle's data load before installation. Traditional verification methods utilize hardware-in-the-loop test benches to inject periodic messages into the MCU under test via CAN / CAN-FD bus to evaluate its resource consumption, interrupt latency, and computing power margin under different data scenarios. However, the CAN protocol itself only provides a rough definition of the data field length (0-8 bytes or CAN-FD 0-64 bytes), and is completely "transparent" regarding data types, bit width, and combination ratios. Test engineers have to manually code at the application layer, serializing mixed data such as integers and single / double precision floating-point numbers before filling them into 8-byte slices, which is both time-consuming and error-prone. Once the data type ratio or bit width needs to be adjusted, the parsing code on both the host computer and the MCU must be recompiled, resulting in long evaluation cycles and limited coverage of scenarios, making it difficult to meet the current requirements of "software-defined vehicles" for chip selection iteration speed.

[0003] On the other hand, other bus protocols for automotive applications—such as FlexRay, LIN, and 10BASE-T1S—also treat the data field as pure payload, carrying no type or length semantics at the link layer, and therefore cannot be directly used to quickly generate diverse test vectors. Some manufacturers have attempted to customize application layer protocols on top of CAN, but these protocols primarily serve calibration or diagnostics, have fixed frame formats, high overhead, and require pre-programmed description files, making them unsuitable for on-demand modification. Therefore, the industry urgently needs a "plug-and-play" bus signal format that allows HIL / RCP benchtops to dynamically change the type, bit width, and mixing ratio of transmitted data within milliseconds, while the MCU chip can directly recognize and run the evaluation algorithm without pre-installed parsing scripts, thereby significantly shortening the adaptation and verification cycle of automotive-grade MCU chips and improving test coverage. Summary of the Invention

[0004] The purpose of this invention is to provide a bus signal, generation method and apparatus for automotive-grade MCU chip adaptation evaluation, so as to overcome the defects of the prior art where the protocol layer cannot describe the data type and length, resulting in test vectors needing to be manually encoded, slow to adjust and limited in coverage.

[0005] To achieve the above technical objectives and effects, this invention discloses a bus signal for automotive-grade MCU chip adaptation evaluation, wherein the bus signal consists of a start frame, a race frame, a control frame, a data frame, a check frame, an acknowledge frame, and an end frame arranged in sequence. The race frame is 6 bits, with the first 3 bits being a priority field and the last 3 bits being a data type identifier field. Each bit of the data type identifier field corresponds to the existence status of integer, single-precision floating-point, and double-precision floating-point data, respectively. The control frame has a variable length, which is 4 × (the number of data type identifier bits that are "0" in the race frame), with each 4 bits sequentially describing the byte length of the corresponding data type; The number of bytes and the internal arrangement order of the data frame are determined by the length and order defined by each 4-bit field of the control frame, realizing the self-description of the protocol layer.

[0006] In the competition frame, the data type identifier field adopts an encoding rule where "0" indicates presence and "1" indicates absence, and the 3-bit field corresponds to integer, single-precision floating-point, and double-precision floating-point types respectively from the high bit to the low bit.

[0007] In this control frame, each 4-bit length descriptor field uses binary encoding 0000-1000, which maps to data lengths of 0-8 bytes respectively.

[0008] The verification frame is a 16-bit CRC, and the verification range covers the entire bit stream of the race frame, control frame, and data frame.

[0009] The bus signal evaluation period dynamically switches between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms, and the receiving automotive-grade MCU chip can complete the real-time parsing of data frames based on the race frame and control frame without the need for a pre-set parsing script.

[0010] This invention also discloses a method for generating bus signals for automotive-grade MCU chip adaptation evaluation. The generation method is based on the aforementioned bus signals and is executed sequentially: S1: Receive evaluation parameters configured by the user, the evaluation parameters including at least the priority level, the combination of data types to be enabled, the byte length of each data type, and the signal transmission period; S2: Generate a 6-bit race frame based on the data type combination, wherein the priority field is written with the priority level, and in the data type identifier field, the corresponding bit is set to 0 if the data type exists, and set to 1 if it does not exist; S3: Based on the number of data type identifier bits that are "0" in the competition frame, generate 4 × (number of data type identifier bits that are "0" in the competition frame) bit control frames sequentially. Each 4-bit subfield is written in binary 0000-1000 to the corresponding data type byte length. S4: Generate data frames filled with test values ​​according to the order and length defined in the control frames; S5: Calculate the bit stream CRC of the race frame, control frame, and data frame to form a 16-bit check frame. S6: Assemble the start frame, race frame, control frame, data frame, check frame, response frame, and end frame to obtain the complete bus signal, and periodically send it to the automotive-grade MCU chip under test according to the stated sending cycle.

[0011] Preferably, the test values ​​in S4 are pseudo-random sequences, linearly increasing sequences, or user-defined patterns to simulate real vehicle data load.

[0012] Preferably, the transmission period is dynamically switched between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms, and the switching process does not require recompiling the host computer or MCU parsing code.

[0013] Preferred options also include: S7: After the bus verification frame signal is sent, receive the response frame returned by the MCU chip under test. If the response frame indicates a CRC error or a frame format error, immediately retransmit the current bus signal and record the error event for evaluation and statistics.

[0014] This invention also discloses a bus signal generation device for automotive-grade MCU chip adaptation evaluation. The generation device, based on the above-described generation method, includes at least: The parameter configuration module is used to receive and store user input, including priority level, data type combination, byte length of each type, and transmission period. The frame encoding module, connected to the parameter configuration module, is used to sequentially generate the start frame, race frame, control frame, data frame, check frame, response frame, and end frame. The data filling module is used to generate test values ​​and write them into the data frame according to the order and length defined in the control frame. The periodic transmission module is used to periodically send the assembled bus signals to the automotive-grade MCU chip under test via the physical bus interface at a configurable period. The error readback module is used to receive the response frames returned by the MCU chip under test, and to trigger retransmission and log recording when a CRC error or frame format error is detected.

[0015] The present invention has the following beneficial effects: 1. The built-in race frames and control frames in the protocol layer make data type, bit width and priority information part of the frame structure itself. The evaluation platform only needs to modify the parameters to generate new test vectors in real time at any period in the range of 1ms-200ms. There is no need to recompile the host computer or MCU parsing code. The single-vehicle-grade MCU adaptation verification cycle is shortened from several weeks to several days, and the risk of errors caused by manual coding is completely eliminated.

[0016] 2. A single frame can carry up to 192 bytes of mixed data, with integer and single / double precision floating-point combinations as needed. A single message can cover all the data density that may occur in real vehicle control algorithms. With 16-bit CRC check and optional response retransmission mechanism, high reliability is ensured while significantly expanding the coverage of test scenarios, reducing the probability of missed tests during the chip selection stage, and providing sufficient data support for subsequent functional safety certification. Attached Figure Description

[0017] Figure 1 This is a structural diagram of Embodiment 1 of the present invention.

[0018] Figure 2 This is a flowchart of the signal generation and transmission process in Embodiment 2 of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. Example 1

[0020] like Figure 1 As shown, this embodiment discloses a bus signal for automotive-grade MCU chip adaptation evaluation. The bus signal consists of a start frame, a race frame, a control frame, a data frame, a check frame, and an end frame arranged in sequence. The race frame is 6 bits, with the first 3 bits being a priority field and the last 3 bits being a data type identifier field. Each bit of the data type identifier field corresponds to the existence status of integer, single-precision floating-point, and double-precision floating-point data, respectively. The control frame has a variable length, which is 4 × (the number of data type identifier bits that are "0" in the race frame), with each 4 bits sequentially describing the byte length of the corresponding data type; The number of bytes and the internal arrangement order of the data frame are determined by the length and order defined by each 4-bit field of the control frame, realizing the self-description of the protocol layer.

[0021] In the competition frame, the data type identifier field adopts an encoding rule where "0" indicates presence and "1" indicates absence, and the 3-bit field corresponds to integer, single-precision floating-point, and double-precision floating-point types respectively from the high bit to the low bit.

[0022] In this control frame, each 4-bit length descriptor field uses binary encoding 0000-1000, which maps to data lengths of 0-8 bytes respectively.

[0023] The verification frame is a 16-bit CRC, and the verification range covers the entire bit stream of the race frame, control frame, and data frame.

[0024] The bus signal evaluation period dynamically switches between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms, and the receiving automotive-grade MCU chip can complete the real-time parsing of data frames based on the race frame and control frame without the need for a pre-set parsing script.

[0025] This embodiment achieves high efficiency and flexibility in automotive-grade MCU chip adaptation evaluation through a meticulously designed bus signal structure. First, the 6-bit design of the contention frame cleverly integrates priority and data type identification, using only 3 bits to clearly identify the presence of integer, single-precision floating-point, and double-precision floating-point data, greatly simplifying the data type identification process. The dynamic length design of the control frame allocates 4-bit sub-fields as needed to describe the byte length of the corresponding data type based on the number of "0" bits in the contention frame. This self-describing mechanism allows data frames to flexibly organize data according to the control frame definition, enabling dynamic configuration of the protocol layer. The number of bytes and the internal arrangement order of the data frame are entirely defined by each 4-bit field of the control frame. This design not only improves the flexibility of data transmission but also enhances data readability and parsing. The introduction of a 16-bit CRC check frame ensures the integrity and reliability of data transmission, covering the entire bit stream of the contention frame, control frame, and data frame, providing strong support for accurate data transmission. Furthermore, the ability to dynamically switch the bus signal evaluation period between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms allows the evaluation system to quickly adjust the signal transmission frequency according to different test requirements without recompiling the host computer or MCU-side parsing code, greatly improving evaluation efficiency. The receiving automotive-grade MCU chip can complete real-time parsing of data frames based on the race frame and control frame without requiring a pre-built parsing script, further reducing the complexity and cost of adaptation verification. Example 2

[0026] like Figure 2 As shown, this embodiment, based on the design foundation of Embodiment 1, proposes a method for generating bus signals for automotive-grade MCU chip adaptation evaluation, comprising: S1: Receive evaluation parameters configured by the user, the evaluation parameters including at least the priority level, the combination of data types to be enabled, the byte length of each data type, and the signal transmission period; S2: Generate a 6-bit race frame based on the data type combination, wherein the priority field is written with the priority level, and in the data type identifier field, the corresponding bit is set to 0 if the data type exists, and set to 1 if it does not exist; S3: Based on the number of data type identifier bits that are "0" in the competition frame, generate 4 × (number of data type identifier bits that are "0" in the competition frame) bit control frames sequentially. Each 4-bit subfield is written in binary 0000-1000 to the corresponding data type byte length. S4: Generate data frames filled with test values ​​according to the order and length defined in the control frames; S5: Calculate the bit stream CRC of the race frame, control frame, and data frame to form a 16-bit check frame. S6: Assemble the start frame, race frame, control frame, data frame, verification frame and end frame to obtain the complete bus signal, and periodically send it to the automotive-grade MCU chip under test according to the said sending cycle; S7: After the bus verification frame signal is sent, receive the response frame returned by the MCU chip under test. If the response frame indicates a CRC error or a frame format error, immediately retransmit the current bus signal and record the error event for evaluation and statistics.

[0027] In S4, the test values ​​are pseudo-random sequences, linearly increasing sequences, or user-defined patterns to simulate real vehicle data load.

[0028] The transmission period dynamically switches between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms, and the switching process does not require recompiling the host computer or MCU parsing code.

[0029] This embodiment, based on the frame structure of Embodiment 1, transforms protocol features into an executable generation process: through pipelined encapsulation of S1-S6, evaluators only need to specify priority, data type combination, and byte length in a single configuration. The device can automatically assemble the race frame, control frame, data frame, and CRC within milliseconds and immediately send them out cyclically at the selected period. The 2-bit acknowledgment frame readback and instant retransmission mechanism introduced in S7 enables the transmission reliability statistics and evaluation process to be completed simultaneously. Packet loss or bit error events can be recorded without additional test scripts, significantly shortening fault location time. The overall method can achieve dynamic switching of test vectors without modifying the MCU-side code, reducing the single-vehicle-grade MCU adaptation verification cycle from several weeks to several days, and greatly reducing the risk of errors introduced by manual coding. Example 3

[0030] This embodiment proposes a bus signal generation device for automotive-grade MCU chip adaptation evaluation based on embodiments 1 and 2. The generation device is based on the above-mentioned generation method and includes: The parameter configuration module is used to receive and store user input, including priority level, data type combination, byte length of each type, and transmission period. The frame encoding module, connected to the parameter configuration module, is used to generate the start frame, race frame, control frame, data frame, check frame and end frame in sequence. The data filling module is used to generate test values ​​and write them into the data frame according to the order and length defined in the control frame. The periodic transmission module is used to periodically send the assembled bus signals to the automotive-grade MCU chip under test via the physical bus interface at a configurable period. The error readback module is used to receive the response frames returned by the MCU chip under test, and to trigger retransmission and log recording when a CRC error or frame format error is detected.

[0031] After receiving user input once through the parameter configuration module, the frame encoding module and data filling module assemble a 6-bit contention frame, a variable control frame, and a 192-byte mixed data frame in millisecond-level pipeline, achieving "zero-compilation" dynamic load switching. The periodic transmission module sends data cyclically through the standard physical bus interface at a programmable period of 1 ms to 200 ms, ensuring seamless alignment between the HIL bench and the actual vehicle timing. The error readback module synchronously collects the 2-bit response frame returned by the MCU, immediately triggers retransmission, and records and counts the data. Evaluation and reliability verification are completed in one go, thereby compressing the traditional automotive-grade MCU adaptation cycle, which requires repeated script iterations and manual analysis, into a single test, significantly reducing labor costs and the risk of missed tests.

[0032] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bus signal for automotive-grade MCU chip adaptation evaluation, characterized in that, The bus signals consist of a start frame, a race frame, a control frame, a data frame, a check frame, an acknowledge frame, and an end frame arranged in sequence. The race frame is 6 bits, with the first 3 bits being a priority field and the last 3 bits being a data type identifier field. Each bit of the data type identifier field corresponds to the existence status of integer, single-precision floating-point, and double-precision floating-point data, respectively. The control frame has a variable length, which is 4 × (the number of data type identifier bits that are "0" in the race frame), with each 4 bits sequentially describing the byte length of the corresponding data type; The number of bytes and the internal arrangement order of the data frame are determined by the length and order defined by each 4-bit field of the control frame, realizing the self-description of the protocol layer.

2. The automotive-grade MCU chip adaptation evaluation bus signal as described in claim 1, characterized in that, The data type identifier field in the competition frame adopts an encoding rule where "0" indicates presence and "1" indicates absence, and the 3-bit field corresponds to integer, single-precision floating-point, and double-precision floating-point data types respectively from the high bit to the low bit.

3. A bus signal for automotive-grade MCU chip adaptation evaluation as described in claim 1 or 2, characterized in that, Each 4-bit length descriptor field of the control frame uses binary encoding 0000-1000, which maps to data lengths of 0-8 bytes respectively.

4. The automotive-grade MCU chip adaptation evaluation bus signal as described in claim 1, characterized in that, The verification frame is a 16-bit CRC, and the verification range covers the entire bit stream of the race frame, control frame, and data frame.

5. The automotive-grade MCU chip adaptation evaluation bus signal as described in claim 1, characterized in that, The bus signal evaluation period dynamically switches between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms, and the receiving automotive-grade MCU chip can complete the real-time parsing of data frames based on the race frame and control frame without the need for a pre-set parsing script.

6. A method for generating bus signals for automotive-grade MCU chip adaptation evaluation, characterized in that, The generation method is based on the bus signal described in any one of claims 1-5, and is executed sequentially: S1: Receive evaluation parameters configured by the user, the evaluation parameters including at least the priority level, the combination of data types to be enabled, the byte length of each data type, and the signal transmission period; S2: Generate a 6-bit race frame based on the data type combination, wherein the priority field is written with the priority level, and in the data type identifier field, the corresponding bit is set to 0 if the data type exists, and set to 1 if it does not exist; S3: Based on the number of data type identifier bits that are "0" in the competition frame, generate 4 × (number of data type identifier bits that are "0" in the competition frame) bit control frames sequentially. Each 4-bit subfield is written in binary 0000-1000 to the corresponding data type byte length. S4: Generate data frames filled with test values ​​according to the order and length defined in the control frames; S5: Calculate the bit stream CRC of the race frame, control frame, and data frame to form a 16-bit check frame. S6: Assemble the start frame, race frame, control frame, data frame, check frame, response frame and end frame to obtain the complete bus signal, and periodically send it to the automotive-grade MCU chip under test according to the said sending cycle.

7. The method for operating bus signals for automotive-grade MCU chip adaptation evaluation as described in claim 6, characterized in that: The test values ​​in S4 are pseudo-random sequences, linearly increasing sequences, or user-defined patterns to simulate real vehicle data load.

8. The method for operating bus signals for automotive-grade MCU chip adaptation evaluation as described in claim 6, characterized in that: The transmission period dynamically switches between 1ms, 5ms, 10ms, 50ms, 100ms, and 200ms, and the switching process does not require recompiling the parsing code on the host computer or MCU chip.

9. The method for operating bus signals for automotive-grade MCU chip adaptation evaluation as described in claim 6, characterized in that: Also includes: S7: After the bus verification frame signal is sent, the MCU chip under test returns an acknowledgment frame. If the acknowledgment frame indicates a CRC error or a frame format error, the current bus signal is immediately retransmitted, and the error event is recorded for evaluation and statistics.

10. A bus signal generation device for automotive-grade MCU chip adaptation evaluation, characterized in that: The generating apparatus, based on the generating method according to any one of claims 6-9, comprises at least: The parameter configuration module is used to receive and store user input, including priority level, data type combination, byte length of each type, and transmission period. The frame encoding module, connected to the parameter configuration module, is used to sequentially generate the start frame, race frame, control frame, data frame, check frame, response frame, and end frame. The data filling module is used to generate test values ​​and write them into the data frame according to the order and length defined in the control frame. The periodic transmission module is used to periodically send the assembled bus signals to the automotive-grade MCU chip under test via the physical bus interface at a configurable period. The error readback module is used to receive the response frames returned by the MCU chip under test, and to trigger retransmission and log recording when a CRC error or frame format error is detected.

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