Chip system, data processing method and computer system

Abstract

The invention relates to a chip system, a data processing method and a computer system. The chip comprises a first bare chip and a second bare chip, and a cache region is arranged in the second bare chip; the first bare chip is used for receiving the cache pointer periodically sent by the second bare chip and determining the current residual available space of the cache region according to the newly received cache pointer; according to the residual available space, sending a plurality of first data packets corresponding to the target message to a second bare chip; wherein the cache pointer is used for indicating the latest cache space condition of the cache region; and the second bare chip is used for storing the received first data packets in the cache region, and sequentially taking out the stored first data packets from the first first data packet and sending the stored first data packets to other chips under the condition that the (K + 1) th first data packet is received. According to the chip, long message transmission can be carried out under the condition that the bare chip area is not increased.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip system, a data processing method, and a computer system. Background Technology

[0002] As chips become increasingly larger, to improve yield, they are often broken down into multiple functional modules for separate manufacturing and testing. Therefore, multi-die structures exist in large-scale chips, where multiple dies with different functions are incorporated. In networking, multi-die chips include buffer space within the die to store received data. Currently, due to the large length of messages transmitted between dies, sufficient buffer space needs to be reserved within the die, thus increasing the die area. Summary of the Invention

[0003] Based on this, a chip system, a data processing method, and a computer system that can transmit long messages without increasing the die area are provided.

[0004] In a first aspect, this application provides a chip system. The chip system includes a first die and a second die, with a buffer area configured in the second die. The first die is used to receive a buffer pointer periodically sent by the second die, and to determine the current remaining available space in the buffer area based on the latest received buffer pointer. Based on the remaining available space, it sends multiple first data packets corresponding to a target message to the second die. The buffer pointer indicates the latest buffer space status of the buffer area. The second die is used to store each received first data packet in the buffer area, and, upon receiving the (K+1)th first data packet, to sequentially retrieve each stored first data packet starting from the first first data packet and send them to other chips.

[0005] In one embodiment, the first die is specifically used for: validating the received cache pointer; and determining the remaining available space based on the latest received valid cache pointer that has passed the verification.

[0006] In one embodiment, the first bare die is specifically used for: performing cyclic redundancy check on the received cache pointer; determining the remaining available space based on the latest received valid cache pointer that has passed the cyclic redundancy check and the local pointer maintained in the first bare die; wherein the local pointer is determined based on the cumulative length of the data packets output by the first bare die.

[0007] In one embodiment, the first bare die is further configured to: repeatedly execute the step of outputting multiple second data packets corresponding to the target message to the second bare die based on the latest determined remaining available space of the buffer, until the data packets corresponding to the target message are sent; the multiple second data packets are other data packets corresponding to the target message besides the multiple first data packets.

[0008] In one embodiment, the first die is specifically used to generate an error correction check code for the first data packet and send the first data packet carrying the error correction check code to the second die; the second die is specifically used to correct the error correction check code in the received first data packet and store the corrected first data packet in the buffer.

[0009] In one embodiment, K is determined based on the frequency difference between the data transmitted by the first die and the second die.

[0010] In one embodiment, a first die and a second die are respectively provided with D2D interfaces; the first die is used to output a first data packet through the D2D interface in the first die; the second die is used to receive the first data packet through the D2D interface in the second die.

[0011] In one embodiment, the maximum available space size of the buffer is determined based on the bit width and interface latency of the D2D interface.

[0012] Secondly, this application also provides a data processing method for use in a chip system, the chip system including a first die and a second die, wherein a buffer area is provided in the second die; the method includes:

[0013] The first die receives the buffer pointer periodically sent by the second die. Based on the latest received buffer pointer, the remaining available space in the buffer is determined. Based on the remaining available space, multiple first data packets corresponding to the target message are sent to the second die. The buffer pointer is used to indicate the latest buffer space status of the buffer. The second die stores each received first data packet in the buffer. When the (K+1)th first data packet is received, each stored first data packet is retrieved sequentially from the first first data packet and sent to other chips.

[0014] Thirdly, this application also provides a computer system that integrates the chip system described in any one of the first aspects.

[0015] The aforementioned chip system, data processing method, and computer system include a first die and a second die, with a buffer in the second die. The first die receives a buffer pointer periodically sent by the second die and determines the remaining available space in the buffer based on the latest received pointer. Based on the remaining available space, it sends multiple first data packets corresponding to the target message to the second die. The buffer pointer indicates the latest buffer space status. The second die stores each received first data packet in the buffer and, upon receiving the (K+1)th first data packet, sequentially retrieves and sends each stored first data packet, starting from the first first data packet, to other chips. Thus, during the transmission of the target message, the second die only needs to store K data packets in the buffer to receive the target message data packets sent by the first die and continuously send them to other chips at a remote location. Transmission of the target message can be achieved regardless of its length. That is, it ensures the transmission of long messages without excessively consuming buffer resources. Therefore, the buffer size does not need to be excessive, and the area of ​​the raw chip will not increase, achieving the goal of long message transmission without increasing the raw chip area. Furthermore, since the remaining available space of the buffer is determined based on the buffer pointer periodically sent by the second raw chip, the current remaining available space can be accurately determined. Based on this, multiple first data packets are sent, ensuring that the buffer of the second raw chip does not overflow. Because the first raw chip can periodically receive the buffer pointer, the latest remaining available space of the buffer can be accurately determined based on the latest received buffer pointer under any circumstances, ensuring the reliability and correctness of buffer management for data packet transmission between raw chips. Moreover, since data packets are corrected using error correction codes, even if occasional errors occur, they can be corrected to ensure the reliability of data packet transmission.

[0016] Other beneficial effects of this application will be further explained and illustrated in detail when combined with the accompanying drawings and specific embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the CPU chip structure in one embodiment;

[0019] Figure 2This is a schematic diagram of the structure of another CPU chip in one embodiment;

[0020] Figure 3 This is a schematic diagram of the structure of a network switching chip in one embodiment;

[0021] Figure 4 This is a schematic diagram of the structure of another network switching chip in one embodiment;

[0022] Figure 5 This is a flowchart illustrating the process of determining the remaining available space in one embodiment;

[0023] Figure 6 This is a schematic diagram of the interaction between two chips in one embodiment;

[0024] Figure 7 This is a flowchart illustrating a data processing method in one embodiment. Detailed Implementation

[0025] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0027] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0028] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0029] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0030] As chips become increasingly larger, the area of ​​a single chip also gradually increases, even reaching the physical limits of photomasks. Furthermore, the yield rate of large chips tends to be lower, leading to increased chip costs. Breaking large chips down into multiple functional modules, manufacturing and testing each module separately, has become a common practice for large chip manufacturers. This avoids the risk of entire chips being scrapped due to defects in a single large chip, significantly improving yield.

[0031] Taking the multi-die structure of a CPU chip as an example, such as Figure 1 As shown, the CPU chip (101) consists of a CPU Die (102) and an IO Die (103). The CPU chip is composed of two CPU Dies and one IO Die. The CPU Die and the IO Die are interconnected through a D2D interface (104).

[0032] Data transfer between the CPU Die and the I / O Die is conducted via a D2D interface. Data transfer between dies must ensure both bandwidth and reliability. To guarantee reliability, current CPU chips employ lossless transmission methods for data transfer between multiple dies, utilizing flow control and retransmission to ensure reliable data transmission. For example... Figure 2 As shown, in the CPU chip (201), CPU Die0 (202) and IO Die (203) transmit data through the D2D interface (204). After the chip starts up, CPU Die0 and IO Die first establish a D2D interface connection. After the D2D interface connection is established, CPU Die0 will send the size of the CPU receive credit buffer (205) to IO Die, and IO Die will send the size of the IO receive credit buffer (206) to CPU Die0.

[0033] Data packets sent via D2D between CPU Die0 and IO Die typically include a CRC checksum. Upon receiving the data packet, the receiver performs a CRC check. If the CRC check fails, an error message is sent back to the sender, who then retransmits the data packet. This credit caching management mechanism and the checksum retransmission mechanism ensure lossless data transmission.

[0034] In CPU chips, data transmission between D2D mainly involves memory semantics. Data is sent in whole packets on the sending side and received in whole packets on the receiving side. The transmitted data is usually relatively small, typically not exceeding 256B. This makes the overall size of the receive credit buffer in CPU Die0 and IOD controllable.

[0035] The above example of a CPU chip illustrates the multi-die chip method, which is currently quite common. However, this data transmission method has the following drawbacks:

[0036] a) Since data is sent and received in whole packets, when the data packet length is relatively large (such as 4KB, 8KB, 9.6KB), the credit buffer in the die will be relatively large.

[0037] b) For multi-die chips in the network field, since the message length is relatively large, if this method is adopted, both dies that transmit data through the D2D interface need to reserve sufficient receive credit buffer, which increases the die area. The more dies the chip has, the greater the area increase.

[0038] c) In network switching chips, multiple dies are typically used to form a single chip. In this case, the area cost of the dies is relatively large, such as... Figure 3 It consists of a switching die (301) and eight IO dies (302), and the switching die and IO dies are interconnected through a D2D interface (303). If full packet caching is required on the IO dies and the packet length is large, the area of ​​the IO dies needs to be increased.

[0039] d) Buffering long data packets before sending them increases the transmission time of the packets. The longer the data packet, the longer the buffering time, and the greater the data transmission delay. This is a relatively large overhead for the data transmission delay in the entire system.

[0040] In view of this, embodiments of this application provide a chip system, a data processing method, and a computer system. This chip system can perform long message transmission without increasing the die area. Furthermore, by continuously transmitting data packets of the target message to a remote chip, the transmission time of the data packets can be reduced, thus reducing data latency.

[0041] The chip system provided in this application embodiment can be a chip system containing multiple dies. The chip system can contain one or more chips, and a single chip can contain multiple dies, such as a first die and a second die. A die is an unpackaged semiconductor chip diced from a wafer. Exemplarily, it can be a CPU chip, a network switching chip, etc., but this is not an exhaustive list. It is understood that the first die is the die in the chip system that sends message data, and the second die is the die in the chip that receives the message data sent by the first die. The second die also sends the data packet of the target message sent by the first die to other chips, which may be located in the same chip system as the chip mentioned in the second die, or they may be located in different chip systems. Optionally, if the chip is a network switching chip, the first die can be a switching die (SW Die) in the network switching chip, and the second die can be an interface die (IO Die) in the network switching chip; if the chip is a CPU chip, the first die can be a computing die (CPU Die) in the chip, and the second die can be an interface die (IO Die) in the chip. The CPU chip's compute die includes the CPU core, internal bus, DDR controller, etc. The interface die mainly includes commonly used I / O modules such as PCIe interface, Flash interface, UART, and GPIO. For example, a network switching chip can be placed in a network switching device. A network switching device refers to a communication device specifically designed for receiving, processing, and forwarding data packets in a network, such as, but not limited to: Ethernet switches, routers, switching chips, smart NICs, and forwarding engines in data processing units (DPUs). For ease of understanding, the following explanation uses a network switching chip as an example. Figure 4 As shown.

[0042] In one embodiment, a chip system is provided, comprising a first die and a second die, wherein a cache area is disposed in the second die. Figure 4 Taking the chip system shown as an example, the first die is, for example, a switch die (SW Die), and the second die is, for example, an interface die (IO Die).

[0043] The first die is used to receive the buffer pointer periodically sent by the second die, determine the remaining available space in the buffer based on the latest received buffer pointer, and send multiple first data packets corresponding to the target message to the second die based on the remaining available space. The second die is used to store each received first data packet in the buffer, and, upon receiving the (K+1)th first data packet, to sequentially retrieve each stored first data packet starting from the first first data packet and send them to other chips.

[0044] The cache pointer indicates the latest cache space status of the cache area. The second die periodically generates a cache pointer based on its latest cache space status and sends the generated cache pointer to the first die. The cache pointer indicates the latest cache space status of the cache area, such as how much space the cache area has recently released or occupied. The first die uses a local pointer to record the historical cache space occupancy of the cache area. Therefore, the current remaining available space of the cache area can be determined based on the latest cache space status and the recorded historical cache space occupancy. For example, the difference between the local pointer indicating historical cache space occupancy and the cache pointer indicating the latest cache space status yields the current remaining available space of the cache area.

[0045] In one optional implementation, each time the first die receives a cache pointer, it determines the current remaining available space in the cache based on the cache pointer. In another optional implementation, each time the first die receives a cache pointer, it determines whether the cache pointer is valid, and if the cache pointer is valid, it determines the current remaining available space in the cache based on the cache pointer.

[0046] In this way, since the buffer pointer is passed every clock cycle, even if there is an error in receiving or recognizing the buffer pointer in one clock cycle, the latest remaining available space can be determined based on the buffer pointer in the next clock cycle. That is, the buffer pointer can be recovered at any time, without affecting the accuracy of the first die in determining the current remaining available space of the buffer, nor affecting the data transmission of the target message.

[0047] It is understandable that during chip initialization, the first die and the second die establish a link. The first die receives the initial cache pointer sent by the second die. At this time, the remaining available space determined by the cache pointer can be the maximum available space size of the cache area.

[0048] When the target message is large, for example, greater than the bit width of the D2D transmission interface between the first and second dies, the target message needs to be split into multiple data packets, and each data packet is sent to the second die in batches. To avoid buffer overflow, at the first die end, the first batch of multiple first data packets is determined based on the current remaining available space in the buffer. Optionally, the sum of the space occupied by the multiple first data packets is less than the remaining available space. At the second die end, each first data packet is continuously received, stored, and output as needed.

[0049] In this embodiment of the application, a storage threshold K is preset at the second die end. K is a positive integer.

[0050] The second die stores each received first data packet in a buffer. Upon receiving the (K+1)th first data packet, it sequentially retrieves each stored first data packet, starting from the first first data packet, and sends them to other chips. For example, with K equal to 2, the second die stores the first first data packet upon receiving it; it stores the second first data packet upon receiving it; and upon receiving the third first data packet, it sequentially retrieves each first data packet corresponding to the target message, starting from the first first data packet, and sends them to other chips according to the storage order. In other words, when the number of stored data packets reaches K, it simultaneously receives subsequent first data packets sent by the first die and stores them, while continuously retrieving and sending each first data packet from the buffer.

[0051] It should be noted that due to frequency differences or hardware limitations between the two dies, there may be gaps in the transmission of first data packets from the first die to the second die. However, the second die continuously transmits first data packets to other chips without gaps, ensuring the continuity and integrity of data packet output. It can be understood that each gap decrements the number of first data packets stored in the buffer by 1, i.e., less than K. In this embodiment, to ensure the continuity of data packet transmission to other chips, the value of K is predetermined to ensure that the buffer always contains first data packets. The specific setting method is described below.

[0052] In an optional embodiment of this application, the sum of the space occupied by the K data packets is less than the maximum available credit space. Optionally, the value of K can be set to be small, so that the space occupied in the buffer during the processing of the target packet is smaller, and the buffer can be set to be smaller, so that the raw chip size will not be too large.

[0053] Understandably, at the second die, during the reception of the first data packet, the buffer pointer continues to be sent periodically. At the same time, at the first die, the remaining available space in the buffer is determined based on the latest buffer pointer. Since the K data packets have not completely occupied all available space, there is still remaining available space. If there are remaining data packets of the target message, the first die will send the remaining data packets of the target message to the second die based on the remaining available space.

[0054] In this way, the second die can not only receive target messages of varying lengths, but also avoids excessive buffer space consumption and ensures that the target messages are transmitted completely and continuously to other chips.

[0055] Here, the other chips are either the destination chips for receiving the target message, or intermediate chips for forwarding the target message.

[0056] In an optional embodiment of this application, it can be understood that if the length of the target message is less than the bit width of the interface between the two die-to-die segments, then if the remaining available space is greater than the space occupied by the target message, the target message is directly sent to the second die-to-die segment.

[0057] The aforementioned chip system includes a first die and a second die, with a buffer in the second die. The first die receives a buffer pointer periodically sent by the second die and determines the remaining available space in the buffer based on the latest received pointer. Based on the remaining available space, it sends multiple first data packets corresponding to the target message to the second die. The buffer pointer indicates the latest buffer space status. The second die stores each received first data packet in the buffer and, upon receiving the (K+1)th first data packet, sequentially retrieves and sends each stored first data packet, starting from the first first data packet, to other chips. Thus, during the transmission of the target message, the second die only needs to store K data packets in the buffer to receive the target message data packets sent by the first die and continuously send them to other chips at a remote location. Transmission of the target message can be achieved regardless of its length. That is, it ensures the transmission of long messages without excessively consuming buffer resources. Therefore, the buffer size does not need to be excessive, and the area of ​​the raw chip will not increase, achieving the goal of transmitting long messages without increasing the raw chip area. Furthermore, since the remaining available space of the buffer is determined based on the buffer pointer periodically sent by the second raw chip, the current remaining available space of the buffer can be accurately determined. Based on this, multiple first data packets are sent, ensuring that the buffer of the second raw chip does not overflow. Because the first raw chip can periodically receive the buffer pointer, the latest remaining available space of the buffer can be accurately determined based on the latest received buffer pointer under any circumstances, ensuring the reliability and correctness of buffer management for data packet transmission between raw chips.

[0058] In one embodiment, such as Figure 4 As shown, the first and second dies are equipped with D2D (Die-to-Die) interfaces. The D2D interface is an "inter-chip bus" that packages two independent dies in the same substrate, allowing them to interconnect at high speed like a single chip. It achieves picosecond-level latency and tens of Gbps parallel differential signals per channel through extremely short, impedance-controllable traces, and comes with link training, clock compensation, and CRC retransmission. It can combine multiple CPU, IO, AI, or memory dies into a single large chip, breaking through the limitations of photomask area and reducing the yield cost of a single large chip.

[0059] The two D2D interfaces can communicate directly.

[0060] The first die is used to output the first data packet through its D2D interface. The second die is used to receive the first data packet through its D2D interface. This ensures the accuracy of data transmission between the two dies.

[0061] In one embodiment, the maximum available space size of the buffer is determined based on the bit width and interface latency of the D2D interface.

[0062] Optionally, data packet transmission passes through two D2D interfaces, and there is an interface delay during data packet transmission on each interface. Therefore, the maximum available space size is obtained by multiplying the bit width of the D2D interface by 2 and then multiplying by the interface delay. For example, multiplying the bit width of the D2D interface by 2 and then multiplying by the interface delay gives the initial space size. Dividing the initial space size by 8 bytes gives the maximum available space size (in KB).

[0063] For example, if the total delay of a single D2D interface controller receiving and sending is 15ns, that is, the interface delay is 30ns, and the D2D interface data bit width is 1024bit, then the maximum available space size is: (2*15ns*1024bit) / 8Byte.

[0064] Therefore, the buffer (i.e., the second bare die receive credit buffer) does not need to buffer the entire packet; its size only needs to be large enough to absorb the sum of the receive and transmit delays of the two D2D interface controllers. For example, in a scenario with a bandwidth of 1Tbps, a D2D interface data width of 1024 bits, a frequency of 1GHz, and a total D2D interface controller receive and transmit delay of 30ns, taking a maximum network packet length of 9.6KB as an example, if the entire packet is to be buffered, the buffer size must be at least two 9.6KB to ensure data flow. If the entire packet is not buffered, and the delay of the two D2D interface controllers (totaling 30ns) is absorbed, then 30 1024-bit packets need to be buffered, meaning the maximum usable buffer size can be set to 3.84KB, which is much smaller than 9.6KB. Therefore, the chip in this embodiment can forward long packets without requiring a large credit space, saving buffer resources.

[0065] In one embodiment, such as Figure 5 A flowchart illustrating the process of determining remaining available space using a first die is shown. The first die performs the following steps:

[0066] Step 501: Verify the validity of the received cache pointer.

[0067] Step 502: Determine the remaining available space based on the latest received valid cache pointer that has passed verification.

[0068] In other words, each time a cache pointer is received, its validity is checked according to a preset verification strategy. If the verification passes, the cache pointer is retained, and the remaining available space is determined based on it. Conversely, if the cache pointer fails the verification, it is discarded. This improves the reliability of determining the remaining available space.

[0069] In an optional embodiment of this application, the validity check can be a cyclic redundancy check.

[0070] For example, the first die is used to perform a cyclic redundancy check (CRC) on the received cache pointers. The remaining available space is determined based on the latest received valid cache pointer that passed the CRC check and the local pointer maintained in the first die.

[0071] The local pointer is determined based on the cumulative length of the data packets output by the first bare die. Optionally, the remaining available space is determined based on the difference between the local pointer and the valid buffer pointer.

[0072] In other words, the local pointer is a reference position maintained by the first die itself, marking the data transmission / buffering status; the buffer pointer sent by the second die is a position fed back by the second die, marking the available buffer boundary position for its own receivable data. The local pointer is a locally stored marker used to track the "position of data already sent to the second die" or the "starting position of data to be sent," essentially a record of the first die's own data transmission progress / buffer occupancy status. The buffer pointer is the "maximum position of receivable data / remaining available buffer boundary" fed back by the second die to the first die based on its own receive buffer occupancy; essentially, it is a key marker for the second die to inform the first die "how much more data I can receive."

[0073] In this way, the flow control information (buffer pointer) sent by the second die to the first die includes a CRC bit, increasing data reliability. The first die performs a CRC check upon receiving the flow control information; information with an incorrect CRC is discarded, while flow control information with a correct CRC is used. Therefore, even if an occasional CRC error occurs during flow control synchronization, subsequent flow control information can still ensure that the second die's buffer does not leak.

[0074] In one embodiment, K is determined based on the frequency difference between the data transmission frequencies of the first die and the second die.

[0075] The frequency difference in data transmission refers to the difference between the rate at which the first die transmits data packets and the rate at which the second die receives / processes data packets (e.g., frequency difference, period difference, or throughput difference). This is a key factor affecting the stability of data transmission and buffer utilization. For example, frequency difference = first die transmission rate (packets / second) - second die reception rate (packets / second).

[0076] Optionally, the frequency difference is divided by the unit data packet transmission time to obtain the value of K.

[0077] In this way, even if there is a gap in the output of the first data packet by the first die, the second die can continuously retrieve data packets because K data packets are stored in the buffer. There will be no interruption in the retrieval of data packets, ensuring that the fragmented data packets of the target message are continuously and streamed to other chips.

[0078] In one embodiment, the first bare die is further configured to: repeatedly execute the step of outputting multiple second data packets corresponding to the target message to the second bare die based on the latest determined remaining available space of the buffer, until the data packets corresponding to the target message have been sent.

[0079] Among them, the multiple second data packets are other data packets corresponding to the target message besides the multiple first data packets.

[0080] It is understandable that multiple second data packets can be all the remaining data packets of the target message besides the first data packet, or they can be a portion of the remaining data packets of the target message besides the first data packet, depending on the latest determined remaining available space. That is, the number of data packets to be sent is continuously determined based on the latest remaining available space, and each data packet is sent in batches until all the data packets of the target message have been sent.

[0081] This ensures that the target message is transmitted completely without excessively consuming cache resources.

[0082] It should be noted that during the process of the first die sending the target message data packet to the second die, no other message data packets are sent, ensuring the integrity and validity of the target message data packet transmission between the two dies. That is, after sending each first data packet, the second data packets are sent, and so on, until all data packets of the target message have been sent. If other messages exist, then the other message data packets are transmitted.

[0083] Furthermore, a retransmission mechanism exists at the link layer between chips; that is, if the receiving end receives an error, the sending end retransmits the data. In this embodiment, an error correction and verification mechanism is added to reduce the number of retransmissions.

[0084] In one embodiment, the first die is specifically used to generate an error correction check code for the first data packet and send the first data packet carrying the error correction check code to the second die. The second die is specifically used to correct the first data packet according to the error correction check code in the received first data packet and store the corrected first data packet in a buffer.

[0085] In other words, an error correction and verification mechanism is added to the first data packet to ensure the reliability of data packet transmission. In this way, the accuracy of the first data packet sent by the second die to other dies will be higher, the probability of other chips receiving an erroneous first data packet will be reduced, the number of data packet retransmissions will be reduced, and the latency of transmitting target messages with other chips will be reduced.

[0086] Alternatively, the error correction verification mechanism may be ECC (Error Correcting Code) verification or FEC (Forward Error Correction) verification, etc., which are not fully illustrated here.

[0087] For example, taking ECC verification as an example, an ECC checksum is generated for each first data packet. Correspondingly, the second chip performs ECC verification correction on each first data packet. It can be understood that other data packets of the target message transmitted subsequently (such as the remaining data packets, including the aforementioned second data packet) also undergo error correction verification.

[0088] In other words, an ECC check mechanism is added to each data packet of the target message, which can correct 1-bit errors. This further reduces the bit error rate, which is already very low for the D2D interface, thus enhancing the reliability of data transmission. Even if uncorrectable errors occasionally occur in data packets, the packet retransmission mechanism in the link layer between this chip and other chips can be used to retransmit the message and correct the error. Because of the added ECC check mechanism for error correction, the number of retransmissions can be effectively reduced, thereby improving the efficiency of data packet transmission and saving transmission resources.

[0089] In this embodiment, ECC error correction is performed on the data during inter-die data transmission, effectively improving the signal quality between dies and reducing the bit error rate of data packets. Even if occasional data errors occur, retransmission at the protocol link layer can correct the data packets, ensuring reliable data transmission.

[0090] For ease of understanding, the following describes the process of message transmission on the bare die of the chip provided in this application using a complete embodiment. Figure 6 A schematic diagram of the interaction between two chips is shown.

[0091] Within a single chip, the SW Die and IO Die transmit data via a D2D interface, employing the following measures for data transmission:

[0092] 1. Data transmission between the SW Die and IO Die uses credit-based flow control. Before sending data to the other end, it checks if the other end's credit buffer has sufficient space to prevent data loss and potential functional errors. 2. Flow control information is always reliable and recoverable. CRC checks are added when the Die transmits flow control information. Flow control information can be transmitted every clock cycle. If a CRC error occurs, the flow control information is discarded, and the correct CRC flow control information is used. The goal is that flow control information can be recovered at any time without affecting data transmission. Flow control information is in pointer form. 3. When the SW Die sends long packets to the IO Die, the IO Die no longer performs full packet buffering. For example, after buffering K packets, data can be continuously sent to the remote end while meeting the requirement of uninterrupted business data flow. This effectively reduces data latency and saves IO Die buffer resources. 4. Even if data errors occur, retransmission at the protocol link layer and transport layer can correct the data. 5. ECC error correction is performed on the data during data transmission between Dies.

[0093] The data transfer process between two dies in a single chip system is as follows:

[0094] 1. The SW Die receives the buffer pointers periodically sent by the IO Die and performs CRC checks on the buffer pointers until the check passes. 2. Based on the checked buffer pointers and the locally recorded pointers, the remaining space in the current IO Die is determined. The remaining space represents the size of the remaining buffer space in the current IO Die. The remaining credit space is obtained by subtracting the locally recorded pointer from the buffer pointer. 3. Based on the remaining space, the first batch of consecutive multi-frame data packets corresponding to the target message is output. After determining the next valid buffer pointer and remaining space, the next batch of consecutively sent multi-frame data packets is sent based on the updated remaining space. 4. The SW Die sends data packets carrying ECC checksums to the IO Die via the D2D interface. 5. The IO Die parses the data packets and performs ECC checks based on the ECC checksums. 6. If the ECC check passes, K data packets are stored according to a preset threshold. When the (K+1)th data packet arrives, data packets are continuously sent to the remote chip starting from the first data packet, and the (K+1)th data packet is stored. Here, K is determined by the frequency difference between the data packet transmissions of the SW Die and the IO Die.

[0095] In the transmission between chips, such as Figure 6As shown, the SW Die (603) in CHIP 0 (601) sends the data packet of the target message to the IO Die (604). When the data in the IO Die's receive credit buffer BUF (606) reaches the configurable waterline (e.g., 2), the IO Die starts sending data to the remote device CHIP 1 through the serial-to-parallel converter serdes (610). Under the condition that the bandwidth of the D2D (607) interface between SW Die (603) and IO Die (604) matches the communication bandwidth (i.e., serdes link bandwidth) between CHIP 0 (601) and CHIP 1 (602) (usually the D2D bandwidth is greater than or equal to the serdes link bandwidth), the data packets sent by SW Die (603) can be continuously sent to the SW Die (608) of CHIP 1 (602). For example, in the prior art, a message with 20 data packets is buffered for 20 clock cycles before being sent; however, in this application, only 2 data packets are buffered before sending, saving 18 clock cycles.

[0096] All data transmission between the SW Die (603) and the IO Die (604) is conducted through the D2D interface (607), including flow control information and data packet information. To increase the reliability of data packet transmission, an ECC check mechanism is added to the data packet information, which can correct 1-bit errors. Given the already low bit error rate of the D2D interface, this further reduces the bit error rate and enhances the reliability of data transmission. Even if uncorrectable errors occasionally occur in data packets, the packet retransmission mechanism of the link layers (605, 609) on both sides of CHIP0 and CHIP1 can be used to retransmit the message and correct the error. In this way, ECC check and error correction are performed on the data during data transmission between dies, effectively improving the signal quality between dies and reducing the bit error rate of data packets. Even if data errors occasionally occur, retransmission at the protocol link layer can correct the data packet errors, ensuring reliable data transmission.

[0097] In summary, the chip provided in this application embodiment can ensure uninterrupted data packet flow and reduce latency even without full packet caching in the IO Die. When the SW Die sends a long packet to the IO Die, the IO Die no longer performs full packet caching. After receiving a few data points (e.g., after receiving two data points), and provided the requirement of uninterrupted service data flow is met (e.g., the D2D bandwidth sent by the SW Die to the IO Die is greater than the bandwidth of the IO Die sending data to the remote end via serdes), the IODie can continuously send packet data to the remote end without interrupting the data packet flow. This effectively reduces data latency and saves IO Die caching resources. Therefore, in multi-die interconnect chips, IO Die caching resources are effectively saved. In long packet service data transmission scenarios, compared to full packet caching, it effectively reduces data packet transmission latency. Inter-Die flow control management can be restored under any circumstances, ensuring correct inter-die data transmission caching management. Inter-Die data is supported by correction algorithms such as ECC, which can effectively reduce the inter-die data transmission error rate. Even if occasional errors occur, the upper-layer protocol retransmission mechanism can be used to correct them, ensuring reliable data transmission throughout the system.

[0098] Based on the same inventive concept, this application also provides a data processing method for the aforementioned chip. The solution provided by this data processing method is similar to the implementation described in the aforementioned chip; therefore, specific limitations in one or more data processing method embodiments provided below can be found in the chip limitations described above, and will not be repeated here.

[0099] In one embodiment, such as Figure 7 As shown, a data processing method is provided for use in a chip, the chip including a first die and a second die, wherein a buffer area is set in the second die; the method includes:

[0100] Step 701: Utilize the buffer pointer periodically sent by the second die to receive the first die; determine the current remaining available space in the buffer based on the latest received buffer pointer; and send multiple first data packets corresponding to the target message to the second die based on the remaining available space.

[0101] The cache pointer is used to indicate the latest cache space status of the cache area.

[0102] Step 702: Use the second die to store each of the received first data packets in the buffer area, and when the (K+1)th first data packet is received, retrieve each of the stored first data packets sequentially from the first first data packet and send them to other chips.

[0103] In one embodiment, determining the current remaining available space of the cache based on the most recently received cache pointer includes:

[0104] The validity of the received cache pointers is verified using the first bare die; based on the latest received valid cache pointer that has passed verification, the remaining available space is determined.

[0105] In one embodiment, the received cache pointer is validated using a first die; based on the latest received valid cache pointer, the remaining available space is determined, including:

[0106] The received buffer pointers are subjected to cyclic redundancy check using the first bare chip; the remaining available space is determined based on the latest received valid buffer pointer that has passed the cyclic redundancy check and the local pointer maintained in the first bare chip; wherein, the local pointer is determined based on the cumulative length of the data packets output by the first bare chip.

[0107] In one embodiment, the method further includes:

[0108] The process of repeatedly executing the steps of outputting multiple second data packets corresponding to the target message to the second bare chip based on the latest determined remaining available space in the buffer, using the first bare chip, continues until all data packets corresponding to the target message have been sent.

[0109] In one embodiment, sending a plurality of first data packets corresponding to the target message to the second bare die includes:

[0110] The first bare die is used to generate an error correction check code for the first data packet, and the first data packet carrying the error correction check code is sent to the second bare die;

[0111] The second bare chip is used to correct the first data packet based on the error correction check code in the received first data packet, and the corrected first data packet is stored in the buffer area.

[0112] In one embodiment, K is determined based on the frequency difference between the data transmitted by the first die and the second die.

[0113] In one embodiment, the first die and the second die are respectively provided with D2D interfaces; the step of sending multiple first data packets corresponding to the target message to the second die includes:

[0114] The first data packet is output using the D2D interface on the first die; the first data packet is received using the D2D interface on the second die.

[0115] In one embodiment, the maximum available space size of the buffer is determined based on the bit width and interface latency of the D2D interface.

[0116] In one embodiment, a computer system is provided that includes a chip as described in any of the above embodiments.

[0117] Optionally, the computer system refers to a system capable of performing computing and data processing tasks, including at least one processor, memory, and the aforementioned transmission device. This system can be a standalone device, such as a server integrated with a smart network card, or a system composed of multiple devices interconnected via a network, such as a data center including switches, servers, and storage devices. The chip in this application serves as a message processing component in this system, providing it with message processing and transmission capabilities.

[0118] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0119] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0120] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0121] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0122] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip system, characterized in that, The chip system includes a first die and a second die, wherein a cache area is provided in the second die; The first die is used to receive the cache pointer periodically sent by the second die, and determine the current remaining available space of the cache area based on the latest received cache pointer; Based on the remaining available space, multiple first data packets corresponding to the target message are sent to the second bare die; wherein, the cache pointer is used to indicate the latest cache space status of the cache area; The second die is used to store each received first data packet in the buffer, and, upon receiving the (K+1)th first data packet, to sequentially retrieve each stored first data packet from the first first data packet and send them to other chips.

2. The chip system according to claim 1, characterized in that, The first die is specifically used for: Perform validity checks on the received cache pointers; The remaining available space is determined based on the latest received valid cache pointer that has passed verification.

3. The chip system according to claim 2, characterized in that, The first die is specifically used for: Perform cyclic redundancy check on the received buffer pointers; The remaining available space is determined based on the latest received valid cache pointer that has passed the cyclic redundancy check and the local pointer maintained in the first die; wherein, the local pointer is determined based on the cumulative length of the data packets output by the first die.

4. The chip system according to claim 1, characterized in that, The first die is also used for: The step of outputting multiple second data packets corresponding to the target message to the second bare die based on the latest determined remaining available space of the buffer is repeated until all data packets corresponding to the target message are sent; the multiple second data packets are other data packets corresponding to the target message besides the multiple first data packets.

5. The chip system according to claim 1, characterized in that, The first bare die is specifically used to generate an error correction check code for the first data packet and send the first data packet carrying the error correction check code to the second bare die; The second bare die is specifically used to correct the first data packet according to the error correction check code in the received first data packet, and store the corrected first data packet in the buffer area.

6. The chip system according to any one of claims 1 to 5, characterized in that, K is determined based on the frequency difference between the data transmission frequencies of the first die and the second die.

7. The chip system according to any one of claims 1 to 5, characterized in that, The first die and the second die are each provided with a D2D interface; The first die is used to output the first data packet through the D2D interface in the first die; The second die is used to receive the first data packet through the D2D interface in the second die.

8. The chip system according to claim 7, characterized in that, The maximum available space size of the buffer is determined based on the bit width and interface delay of the D2D interface.

9. A data processing method, characterized in that, The data processing method is used in a chip system, the chip system including a first die and a second die, wherein a buffer is provided in the second die; the method includes: The first die receives the buffer pointer periodically sent by the second die, and determines the current remaining available space of the buffer based on the latest received buffer pointer; based on the remaining available space, multiple first data packets corresponding to the target message are sent to the second die; wherein, the buffer pointer is used to indicate the latest buffer space status of the buffer. The received first data packets are stored in the buffer using the second die, and when the (K+1)th first data packet is received, the stored first data packets are retrieved sequentially from the first first data packet and sent to other chips.

10. A computer system, characterized in that, The computer system integrates a chip system as described in any one of claims 1 to 8.

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