Communication interface address configuration circuit and method and communication equipment thereof

Abstract

The invention discloses a communication device and an address configuration circuit and method of communication interfaces thereof, each communication interface corresponds to an address configuration pin, the address configuration circuit of the communication interface comprises a recognizer, n resistance thresholds are set, the n resistance thresholds form n + 1 resistance intervals, and n is a positive integer; the recognizer recognizes a resistance interval where the equivalent resistance value at the address configuration pin is located and outputs a recognition result, and n is a positive integer; and the compiler compiles based on the identification result to generate an address of the communication interface. The communication address of the communication interface can be determined according to the equivalent resistance value of the address configuration pin, and the circuit structure is simple. And the requirement of the address number can be met by setting the number of the resistance threshold values.

Description

Technical Field

[0001] This application relates to the field of electronic communication technology, and more specifically, to address configuration circuits and methods for communication devices and their communication interfaces. Background Technology

[0002] In communication systems for industrial control, smart homes, and the Internet of Things, each communication interface needs to be assigned a unique address ID to ensure accurate data transmission during communication, so as to achieve accurate and efficient communication between communication components.

[0003] Currently, resistor voltage dividers are commonly used to assign communication addresses to communication interfaces in communication devices. However, this method requires at least two external resistors, or an external resistor with at least two resistor slots, increasing the complexity of the external circuitry. Furthermore, this method can only provide a limited number of addresses to be assigned to the corresponding communication interfaces.

[0004] Therefore, there is an urgent need to design an address allocation circuit, method, and communication device for a simple and easily expandable communication interface. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides an address allocation circuit, method, and communication device for a simple and easily expandable external communication interface.

[0006] According to a first aspect of this application, an address configuration circuit for a communication interface in a communication device is provided, wherein each communication interface corresponds to an address configuration pin, comprising: a recognizer, which sets n resistance thresholds, the n resistance thresholds forming n+1 resistance intervals, the recognizer recognizing the resistance interval where the equivalent resistance value at the address configuration pin is located, and outputting a recognition result, where n is a positive integer; and a compiler, which compiles based on the recognition result to generate the address of the communication interface.

[0007] Optionally, the address configuration pin can be left floating, grounded, or grounded via an external resistor.

[0008] Optionally, the address configuration pin is grounded via an external resistor.

[0009] Optionally, the n resistance thresholds are increased proportionally.

[0010] Optionally, the identifier includes:

[0011] There are n comparators, each with a set resistor threshold, generating a comparison current corresponding to the resistor threshold and a first bias current flowing through the address configuration pin, and comparing the first bias current and the comparison current to generate a corresponding comparison signal.

[0012] The n comparison signals constitute the recognition result.

[0013] Optionally, the n comparators include:

[0014] A bias unit, connected to the address configuration pin, generates a first bias current flowing through the address configuration pin;

[0015] There are n comparison units, each connected to the bias unit, and each comparison unit also generates a comparison current and generates a comparison result of the first bias current and the corresponding comparison current.

[0016] The bias unit and a comparison unit together form a comparator.

[0017] Optionally, each comparator further includes a buffer gate, the input of which is connected to the comparison unit to receive the comparison result, and the output of which outputs the corresponding comparison signal.

[0018] Optionally, each comparator further includes an inverter, the input of which is connected to the comparison unit to receive the comparison result, and the output of which outputs the corresponding comparison signal.

[0019] Optionally, at least one of the n comparison units compares the first bias current with the corresponding comparison current.

[0020] Optionally, the bias unit includes:

[0021] First resistor;

[0022] The first switching transistor has a control terminal connected to the first terminal of the first switching transistor and grounded through a first resistor, and the second terminal of the first switching transistor receives the power supply voltage.

[0023] The second switch is connected to the control terminal of the first switch, and the second terminal of the second switch receives the power supply voltage.

[0024] The third switch has its control terminal connected to its first terminal and also connected to the first terminal of the second switch. The second terminal of the third switch is connected to the address configuration pin and provides the first bias current.

[0025] Optionally, each of the comparison units includes:

[0026] Identify resistors;

[0027] The fourth switch is connected to the control terminal of the second switch, and the second terminal of the fourth switch receives the power supply voltage.

[0028] The fifth switch is connected to the control terminal of the third switch, the first terminal of the fifth switch is connected to the first terminal of the fourth switch, and the second terminal of the fifth switch is grounded and provides the comparison current via the identification resistor.

[0029] Optionally, each of the n comparison units compares the first bias current with the corresponding comparison current.

[0030] Optionally, a portion of the n comparison units compare the first bias current with the corresponding comparison current, and another portion of the n comparison units compare an i-fold mirror current of the first bias current with the corresponding comparison current, where i>1.

[0031] Optionally, the resistance value of each of the n comparators is a resistance threshold, the resistance value of each of the n comparators increases progressively, and the channel width-to-length ratio of the fourth switch in each comparison unit is consistent with the channel width-to-length ratio of the second switch, and the channel width-to-length ratio of the fifth switch in each comparison unit is consistent with the channel width-to-length ratio of the third switch.

[0032] Optionally, among the n comparators, the resistance ratio or resistance difference between the identification resistor in the (m+1)th stage comparator and the identification resistor in the m-th stage comparator is equal, where m is an integer and 0 < m < 0. <m<n。

[0033] Optionally, the resistance value of the identification resistor in each of the n comparators from the first-level comparator to the h-th-level comparator is a resistance threshold, the resistance value of the identification resistor in each of the first-level comparators to the h-th-level comparator increases progressively, and the resistance value of the identification resistor in each of the n comparators from the (h+1)-th-level comparator to the n-th-level comparator is the same as the resistance value of the identification resistor in the h-th-level comparator.

[0034] The channel width-to-length ratio of the fourth switching transistor in each of the comparators from the first-stage comparator to the h-stage comparator is the same as that of the second switching transistor, and the channel width-to-length ratio of the fifth switching transistor in each of the comparators from the first-stage comparator to the h-stage comparator is the same as that of the third switching transistor. The ratio of the channel width-to-length ratio of the fourth switching transistor in the (j + 1)-th comparator to the channel width-to-length ratio of the fourth switching transistor in the j-th comparator among the comparators from the (h + 1)-th stage comparator to the n-th stage comparator is i, and the ratio of the channel width-to-length ratio of the fifth switching transistor in the (j + 1)-th comparator to the channel width-to-length ratio of the fifth switching transistor in the j-th comparator among the comparators from the (h + 1)-th stage comparator to the n-th stage comparator is i, where h is an integer and 1 < h < n; j is an integer and h < j < n.

[0035] Optionally, the ratio or difference in resistance values between the identification resistors in the (k + 1)-th comparator and the identification resistors in the k-th comparator among the comparators from the first-stage comparator to the h-stage comparator is equal, where k is an integer and 0 < k < h.

[0036] Optionally, the bias unit further includes:

[0037] A second resistor connected between the first end of the first switching transistor and the first resistor;

[0038] A sixth switching transistor, the control terminal of the sixth switching transistor is connected to the first end of the first switching transistor and grounded via the second resistor and the first resistor, the second end of the sixth switching transistor receives the power supply voltage, and the first end of the sixth switching transistor is connected to the second end of the first switching transistor;

[0039] A seventh switching transistor, the control terminal of the seventh switching transistor is connected to the control terminal of the sixth switching transistor, the second end of the seventh switching transistor receives the power supply voltage, and the first end of the seventh switching transistor is connected to the second end of the second switching transistor.

[0040] Optionally, each of the comparison units further includes:

[0041] An eighth switching transistor, the eighth switching transistor is connected between the second end of the fourth switching transistor and the power supply voltage, and the control terminal of the eighth switching transistor is connected to the control terminal of the seventh switching transistor,

[0042] where the channel width-to-length ratio of the eighth switching transistor in each of the comparison units is the same as that of the seventh switching transistor.

[0043] Optionally, the first to n-th input terminals of the compiler are connected to the first to n-th comparators one by one to receive corresponding comparison signals.

[0044] According to a second aspect of this application, a communication device is provided, comprising: a plurality of communication components, each communication component including a communication interface, an address configuration pin, and an address configuration circuit for the communication interface as described above.

[0045] According to a third aspect of this application, a method for configuring the address of a communication interface in a communication device is provided, wherein each communication interface corresponds to an address configuration pin, and the method for configuring the address of the communication interface includes:

[0046] Set n resistance thresholds, which form n+1 resistance intervals, and identify the resistance interval where the equivalent resistance value at the address configuration pin is located, and output the identification result, where n is a positive integer; and

[0047] The address of the communication interface is generated based on the identification results.

[0048] Optionally, the n resistance thresholds are increased proportionally.

[0049] Optionally, the resistance range in which the equivalent resistance value at the address configuration pin is located is identified, and the identification result is output, including:

[0050] A resistance threshold is set, and a comparison current corresponding to the resistance threshold and a first bias current flowing through the address configuration pin are generated. The first bias current and the comparison current are compared to generate a corresponding comparison signal.

[0051] The n comparison signals constitute the recognition result.

[0052] This application provides an address allocation circuit, method, and communication device for a communication interface. The address allocation circuit of the communication interface identifies the resistance range containing the equivalent resistance value at the address configuration pin and outputs the identification result. The compiler compiles based on the identification result to generate the address of the communication interface. This application can determine the communication address of the communication interface based on the equivalent resistance value of the address configuration pin, resulting in a simple circuit structure. Furthermore, this application can also meet the address quantity requirements by setting the number of resistance thresholds.

[0053] Furthermore, in this application, the address configuration pin is either left floating, grounded, or grounded via an external resistor to change the equivalent resistance value at the address configuration pin, thereby generating a corresponding communication address. In other words, the peripheral circuitry of the address configuration circuit in this application is simpler.

[0054] Furthermore, in the address configuration circuit of this application, each of the n comparators is configured with a resistance threshold. For example, a recognition resistor with a resistance value corresponding to the resistance threshold is set in the comparison unit of each comparator. This application reduces the resistance value of the recognition resistor with a high resistance threshold in some comparison units, while simultaneously increasing the channel size of the switching transistor in the comparison unit, so as to achieve equivalent scaling of the component size in the address configuration circuit, making the circuit more miniaturized and suitable for application scenarios with multiple communication devices. Attached Figure Description

[0055] Figure 1 This diagram illustrates the structure of a communication component in a communication device according to an embodiment of this application.

[0056] Figure 2 A schematic diagram of an address configuration circuit for a communication interface according to an embodiment of this application is shown;

[0057] Figure 3 A schematic diagram of an address configuration circuit for another communication interface provided according to an embodiment of this application is shown;

[0058] Figure 4 A schematic diagram of an address configuration circuit for another communication interface provided according to an embodiment of this application is shown. Detailed Implementation

[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0060] Figure 1 This diagram illustrates the structure of a communication component in a communication device according to an embodiment of this application.

[0061] In serial or parallel communication scenarios, communication components in a communication system communicate with each other via a bus. A communication system includes at least one communication device, which in turn includes multiple communication components, among which there are master and slave communication components.

[0062] In a serial communication scenario, a unique communication address is assigned to the communication component for reading and writing access by the main communication component, thereby achieving precise communication and accurate data transmission.

[0063] like Figure 1 As shown, each communication component 100 includes a communication interface 300, an address configuration pin ADDR corresponding to the communication interface 300, and an address configuration circuit 200 connected to the communication interface 300.

[0064] The address configuration pin in the communication component 100 is connected to an external resistor, which is connected between the address configuration pin ADDR and ground. In this embodiment, the resistance value of the external resistor is the equivalent resistance value at the address configuration pin ADDR. In an alternative embodiment, when the resistance value of the external resistor is infinitely small or 0 ohms, the external resistor can be omitted and the address configuration pin ADDR can be directly grounded. In an alternative embodiment, when the resistance value of the external resistor is infinitely large, the external resistor can be omitted and the address configuration pin ADDR can be left floating.

[0065] The address configuration circuit 200 identifies the equivalent resistance value at the address configuration pin ADDR and generates the corresponding address ADR based on the identification result, which is then provided to the communication interface 300.

[0066] The communication interface 300 includes, for example, a data interface SDA and a clock interface SCL, for communicating with external components based on the configured address ADR.

[0067] Furthermore, the address configuration circuit 200 includes a recognizer 210 and a compiler 220. The recognizer 210 sets n resistance thresholds, forming n+1 resistance intervals. When the equivalent resistance value at the address configuration pin ADDR falls within each of the n+1 resistance intervals, it represents n+1 addresses, used to configure the addresses of n+1 different communication components. The recognizer is also used to identify the resistance interval where the equivalent resistance value at the address configuration pin ADDR is located. n is a positive integer. The compiler 220 compiles based on the identification results to generate the address ADR for the communication interface and provides the address ADR to the communication interface 300.

[0068] Furthermore, the n resistance thresholds are increased proportionally.

[0069] For example, when n=4, the address configuration circuit 200 forms 5 resistance intervals. When the equivalent resistance value at the address configuration pin ADDR is located within each of the 5 resistance intervals, it represents 5 addresses used to configure the addresses of 5 different communication components. The recognizer 210 identifies the resistance interval where the equivalent resistance value at the address configuration pin ADDR is located, and thus determines the address ADR of the communication interface 300.

[0070] Figure 2 This diagram illustrates an address configuration circuit for a communication interface according to an embodiment of the present application.

[0071] The identifier 210 in the address configuration circuit 200 provided in this application consists of a dozen to several dozen integrated circuit elements and has a simple structure.

[0072] like Figure 2As shown, the recognizer 210 includes n comparators. Each comparator sets a resistance threshold and generates a comparison current (including comparison current I21, comparison current I22, ..., comparison current I2n-1, comparison current I2n) corresponding to the resistance threshold and a first bias current I1 flowing through the address configuration pin ADDR. It also compares the first bias current I1 with the comparison current to generate corresponding comparison signals (including comparison signal O1, comparison signal O2, ..., comparison signal On-1, comparison signal On). The n comparison signals constitute the recognition result.

[0073] For example, the address configuration pin ADDR is grounded via an external resistor R2. It can be understood that when the equivalent resistance at the address configuration pin ADDR is infinitely large or infinitely small, the external resistor can be omitted.

[0074] Furthermore, the recognizer 210 includes a bias unit 211 and n comparison units (e.g., comparison unit 2121, comparison unit 2122, ..., comparison unit 2123, comparison unit 2124). For example, the bias unit 211 and a comparison unit form a comparator.

[0075] In other embodiments, each comparator further includes an inverter (e.g., inverter U1, inverter U2, ..., inverter Un-1, or inverter Un). The input of the inverter is connected to the comparator unit to receive the comparison result, and the output of the inverter outputs the corresponding comparison signal.

[0076] In other embodiments, each comparator further includes a buffer gate. The input of the buffer gate is connected to the comparison unit to receive the comparison result, and the output of the buffer gate outputs the corresponding comparison signal.

[0077] The bias unit 211 is connected to the address configuration pin ADDR, generating a first bias current I1 flowing through the address configuration pin ADDR. Exemplarily, the bias unit 211 includes a first resistor R0, a first switch M1, a second switch M2, and a third switch M3. The control terminal of the first switch M1 is connected to its first end and grounded via the first resistor R0, while its second end receives the power supply voltage VDD. The control terminal of the second switch M2 is connected to the control terminal of the first switch M1, and its second end also receives the power supply voltage VDD. The control terminal of the third switch M3 is connected to its first end and also to the first end of the second switch M2. The second end of the third switch M3 is connected to the address configuration pin ADDR and grounded via an external resistor R2, and its second end provides the first bias current I1. Further, the channel width-to-length ratios of the first switch M1, the second switch M2, and the third switch M3 are consistent. For example, the channel width-to-length ratio among the first switch M1, the second switch M2, and the third switch M3 is 1:1:1.

[0078] It should be noted that the first switch M1 and the second switch M2 are, for example, PMOS transistors, and the third switch M3 is, for example, an NMOS transistor. The control terminals of the first switch M1, the second switch M2, and the third switch M3 are, for example, the gates of the transistors; the first terminals of the first switch M1, the second switch M2, and the third switch M3 are, for example, the drains of the transistors; and the second terminals of the first switch M1, the second switch M2, and the third switch M3 are, for example, the source terminals of the transistors. However, the implementation of this application is not limited to this.

[0079] Each of the n comparison units is connected to the bias unit 211. Each comparison unit also generates a comparison current and generates a comparison result of the first bias current I1 and the corresponding comparison current.

[0080] Furthermore, at least one of the n comparison units compares the first bias current I1 with the corresponding comparison current.

[0081] Exemplarily, each comparison unit includes an identification resistor (including identification resistors R11, R12, ……, R1n-1, R1n), a fourth switching transistor (including fourth switching transistors M41, M42, ……, M4n-1, M4n), and a fifth switching transistor (including fifth switching transistors M51, M52, ……, M5n-1, M5n). The control terminal of the fourth switching transistor is connected to the control terminal of the second switching transistor M2, and the second terminal of the fourth switching transistor receives the power supply voltage VDD. The control terminal of the fifth switching transistor is connected to the control terminal of the third switching transistor M3, the first terminal of the fifth switching transistor is connected to the first terminal of the fourth switching transistor, and the second terminal of the fifth switching transistor is grounded via the identification resistor and provides a comparison current.

[0082] Exemplarily, each of the n comparison units is configured to compare a first bias current I1 with a corresponding comparison current.

[0083] Furthermore, the resistance values of the identification resistors in the n comparators increase gradually, and the channel width-to-length ratio of the fourth switching transistor in each comparison unit is the same as that of the second switching transistor, and the channel width-to-length ratio of the fifth switching transistor in each comparison unit is the same as that of the third switching transistor. Exemplarily, the ratio of the channel width-to-length ratio of the fourth switching transistor to that of the second switching transistor in each comparison unit is 1:1. Exemplarily, the ratio of the channel width-to-length ratio of the fifth switching transistor to that of the third switching transistor in each comparison unit is 1:1.

[0084] Furthermore, among the n comparators, the resistance ratio or resistance difference between the identification resistor in the (m + 1)-th comparator and the identification resistor in the m-th comparator is equal, where m is an integer and 0 < m < n. Exemplarily, R11 < R12 < …… < R1n-1 < R1n. Taking n = 4 as an example, five resistance intervals can be formed (including 0~R11, R11~R12, R12~R13, R13~R14, R14~∞). The resistance values of R11, R12, R13, R14 can be set as: R11 = r, R12 = 2r, R13 = 4r, R14 = 8r. In an alternative embodiment, the resistance values of R11, R12, R13, R14 can also be set as: R11 = r, R12 = 2r, R13 = 3r, R14 = 4r. This setting method can reduce the influence of the increase in circuit volume due to excessive resistance increase. Of course, the specific resistance value of the identification resistor is set according to the requirements of the actual application scenario.

[0085] The input terminal of each of the n inverters is connected to a comparison unit to receive an intermediate signal, and the output terminal of each inverter outputs a corresponding comparison signal. It should be noted that the inverter mainly functions as a buffer. In an alternative embodiment, a buffer gate can be used in each comparator.

[0086] The first to the n input terminals of the compiler 220 are respectively connected to the first to the n-level comparators to receive the corresponding comparison signals, and the output terminal of the compiler 220 outputs a digital address corresponding to the equivalent resistance value at the address configuration pin ADDR, so as to achieve reliable and accurate communication with other communication components.

[0087] Taking the first-level comparator composed of the bias unit 211, the comparison unit 2121, and the inverter U1 as an example. When the external resistor R2 is higher than the recognition resistor R11, the voltage at the control terminal of the third switch tube M3 is relatively high, so that the current flowing through the fifth switch tube M51 (comparison current) is greater than the first bias current flowing through the fourth switch tube M41, and the comparison signal output by the inverter U1 is at a high level. When the external resistor R2 is lower than the recognition resistor R11, the current flowing through the fifth switch tube M51 (comparison current) is less than the first bias current flowing through the fourth switch tube M41, and the comparison signal output by the inverter U1 is at a low level.

[0088] When the external resistor R2 is in the range of R1m to R1m+1 (0 < m < n), the comparison signals O1 to Om output by the first m comparators are all at a high level, and the comparison signals Om+1 to On output by the remaining comparators are all at a low level, and it can represent the (m + 1)-th bit address through the compiler 220.

[0089] Furthermore, the second-level comparator composed of the bias unit 211, the comparison unit 2122, and the inverter U2. The (n - 1)-th level comparator composed of the bias unit 211, the comparison unit 2123, and the inverter Un-1. The n-th level comparator composed of the bias unit 211, the comparison unit 2124, and the inverter Un.

[0090] The address configuration circuit 200 provided by the present application can be easily extended to a communication address number of more than a dozen bits or even dozens of bits according to the requirement of the address quantity by setting the corresponding number of comparison units.

[0091] Figure 3 The schematic diagram of an address configuration circuit of another communication interface provided according to an embodiment of the present application is shown.

[0092] As Figure 3As shown, the difference between the address configuration circuit 400 and the address configuration circuit 200 lies in the different circuit structures of the identifier. Exemplarily, in the identifier 410 of the address configuration circuit 400, a part of the n comparison units are used to compare the first bias current with the corresponding comparison current, and another part of the n comparison units are used to compare the i-fold mirror current of the first bias current with the corresponding comparison current, where i > 1.

[0093] Further, the resistance value of the identification resistor in each of the comparators from the first-stage comparator to the h-stage comparator among the n comparators is a resistance threshold, and the resistance value of the identification resistor in each of the comparators from the first-stage comparator to the h-stage comparator among the n comparators increases step by step. The resistance value of the identification resistor in each of the comparators from the (h + 1)-stage comparator to the n-stage comparator among the n comparators is the same as the resistance value of the identification resistor in the h-stage comparator.

[0094] Further, the channel width-to-length ratio of the fourth switching transistor in each of the comparators from the first-stage comparator to the h-stage comparator is the same as the channel width-to-length ratio of the second switching transistor. The channel width-to-length ratio of the fifth switching transistor in each of the comparators from the first-stage comparator to the h-stage comparator is the same as the channel width-to-length ratio of the third switching transistor. The ratio of the channel width-to-length ratio of the fourth switching transistor in the (j + 1)-stage comparator to the channel width-to-length ratio of the fourth switching transistor in the j-stage comparator among the comparators from the (h + 1)-stage comparator to the n-stage comparator is i, and the ratio of the channel width-to-length ratio of the fifth switching transistor in the (j + 1)-stage comparator to the channel width-to-length ratio of the fifth switching transistor in the j-stage comparator among the comparators from the (h + 1)-stage comparator to the n-stage comparator is i, where h is an integer and 1 < h < n; j is an integer and h < j < n.

[0095] Further, the ratio or difference in resistance values between the identification resistor in the (k + 1)-stage comparator and the identification resistor in the k-stage comparator among the comparators from the first-stage comparator to the h-stage comparator is equal, where k is an integer and 0 < k < h.

[0096] Exemplarily, taking h = n - 1 as an example, the difference between the identifier 410 and the identifier 210 is only the channel sizes of the fourth and fifth switching transistors in the comparison unit of the n-stage comparator.

[0097] Specifically, taking n=4, h=3, i=2, the resistance values ​​of identification resistors R11, R12, R13, and R14 are set as follows: R11=r, R12=2r, R13=4r, R14=4r. In this embodiment, the comparison unit 4124, based on comparison unit 2124, adjusts the channel length-to-width ratio of the fourth switch M4n to the switch M2 to i:1, and adjusts the channel length-to-width ratio of the fifth switch M5n to the switch M3 to i:1. That is, the channel length-to-width ratio of the fourth switch M4n to the fifth switch M5n is doubled, allowing identification resistor R1n-1 to be used as the identification resistor in comparison unit 4124, thus avoiding the identification resistor in the identifier being too large and affecting the area of ​​the entire circuit.

[0098] In other words, this application avoids proportionally increasing the identification resistance in the nth-stage comparator unit compared to the identification resistance in the (n-1)th-stage comparator unit by changing the channel dimensions of the fourth and fifth switching transistors in the nth-stage comparator unit. Furthermore, in an n-bit comparator, the identification resistance value in higher-level comparators (comparators closer to the nth stage) can be reduced, and the dimensions of the fourth and fifth switching transistors can be increased accordingly to achieve a good small circuit size requirement.

[0099] The above embodiments are merely examples, and the implementation of this application is not limited to them. The values ​​of the above parameters can be other values.

[0100] Figure 4 A schematic diagram of an address configuration circuit for another communication interface provided according to an embodiment of this application is shown.

[0101] like Figure 4 As shown, the difference between address configuration circuit 600 and address configuration circuit 200 lies in the different circuit structures of the identifier.

[0102] For example, the biasing unit 611 of the identifier 610 in the address configuration circuit 600 further includes, in addition to the biasing unit 211, a second resistor R3, a sixth switch M6, and a seventh switch M7. The second resistor R3 is connected between the first terminal of the first switch M1 and the first resistor R0. The control terminal of the sixth switch M6 is connected to the first terminal of the first switch M1 and grounded via the second resistor R3 and the first resistor R0. The second terminal of the sixth switch M6 receives the power supply voltage, and the first terminal of the sixth switch M6 is connected to the second terminal of the first switch M1. The control terminal of the seventh switch M7 is connected to the control terminal of the sixth switch M6. The second terminal of the seventh switch M7 receives the power supply voltage, and the first terminal of the seventh switch M7 is connected to the second terminal of the second switch M2.

[0103] For example, each comparison unit of the identifier 610 in the address configuration circuit 600 further includes an eighth switch (including an eighth switch M81, or an eighth switch M82, ..., or an eighth switch M8n-1, or an eighth switch M8n) in addition to each comparison unit of the identifier 210. The eighth switch is connected between the second terminal of the fourth switch and the power supply voltage, and the control terminal of the eighth switch is connected to the control terminal of the seventh switch.

[0104] In each comparison unit, the channel width-to-length ratio of the eighth switch is the same as that of the seventh switch.

[0105] This application also provides an address configuration method for a communication interface in a communication device, wherein each communication interface corresponds to an address configuration pin. The address configuration method for the communication interface includes: setting n resistance thresholds, the n resistance thresholds forming n+1 resistance intervals, identifying the resistance interval where the equivalent resistance value at the address configuration pin is located, and outputting the identification result, where n is a positive integer; and compiling based on the identification result to generate the address of the communication interface.

[0106] Furthermore, the n resistance thresholds are increased proportionally.

[0107] Furthermore, identifying the resistance range where the equivalent resistance value at the address configuration pin is located and outputting the identification result includes: setting a resistance threshold, generating a comparison current corresponding to the resistance threshold and a first bias current flowing through the address configuration pin, and comparing the first bias current and the comparison current to generate a corresponding comparison signal, wherein n comparison signals constitute the identification result.

[0108] This application provides an address allocation circuit, method, and communication device for a communication interface. The address allocation circuit of the communication interface identifies the resistance range containing the equivalent resistance value at the address configuration pin and outputs the identification result. The compiler compiles based on the identification result to generate the address of the communication interface. This application can determine the communication address of the communication interface based on the equivalent resistance value of the address configuration pin, resulting in a simple circuit structure. Furthermore, this application can also meet the address quantity requirements by setting the number of resistance thresholds.

[0109] Furthermore, in this application, the address configuration pin is either left floating, grounded, or grounded via an external resistor to change the equivalent resistance value at the address configuration pin, thereby generating a corresponding communication address. In other words, the peripheral circuitry of the address configuration circuit in this application is simpler.

[0110] Furthermore, in the address configuration circuit of this application, each of the n comparators is configured with a resistance threshold. For example, a recognition resistor with a resistance value corresponding to the resistance threshold is set in the comparison unit of each comparator. This application reduces the resistance value of the recognition resistor with a high resistance threshold in some comparison units, while simultaneously increasing the channel size of the switching transistor in the comparison unit, so as to achieve equivalent scaling of the component size in the address configuration circuit, making the circuit more miniaturized and suitable for application scenarios with multiple communication devices.

[0111] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

[0112] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. An address configuration circuit of a communication interface in a communication device, each of the communication interfaces corresponding to an address configuration pin, wherein, include: The identifier sets n resistance thresholds, which form n+1 resistance intervals. The identifier identifies the resistance interval where the equivalent resistance value at the address configuration pin is located and outputs the identification result, where n is a positive integer. as well as The compiler compiles based on the identification results to generate the address of the communication interface.

2. The address configuration circuit of a communication interface according to claim 1, wherein, The address configuration pin can be left floating, grounded, or grounded via an external resistor.

3. The address configuration circuit of a communication interface according to claim 1, wherein, The address configuration pin is grounded via an external resistor.

4. The address configuration circuit of a communication interface according to claim 1, wherein, The n resistance thresholds are increased proportionally.

5. The address configuration circuit of a communication interface according to any one of claims 1 to 4, wherein, The identifier includes: There are n comparators, each with a set resistor threshold, generating a comparison current corresponding to the resistor threshold and a first bias current flowing through the address configuration pin, and comparing the first bias current and the comparison current to generate a corresponding comparison signal. The n comparison signals constitute the recognition result.

6. The address configuration circuit of a communication interface according to claim 5, wherein, The n comparators include: A bias unit, connected to the address configuration pin, generates a first bias current flowing through the address configuration pin; There are n comparison units, each connected to the bias unit, and each comparison unit also generates a comparison current and generates a comparison result of the first bias current and the corresponding comparison current. The bias unit and a comparison unit together form a comparator.

7. The address configuration circuit of a communication interface according to claim 6, wherein, Each comparator further includes a buffer gate, the input of which is connected to the comparison unit to receive the comparison result, and the output of which outputs the corresponding comparison signal.

8. The address configuration circuit of a communication interface according to claim 6, wherein, Each comparator further includes an inverter, the input of which is connected to the comparison unit to receive the comparison result, and the output of which outputs the corresponding comparison signal.

9. The address configuration circuit of a communication interface according to claim 6, wherein, At least one of the n comparison units compares the first bias current with the corresponding comparison current.

10. The address configuration circuit of the communication interface according to claim 6, wherein, The bias unit includes: First resistor; The first switching transistor has a control terminal connected to the first terminal of the first switching transistor and grounded through a first resistor, and the second terminal of the first switching transistor receives the power supply voltage. The second switch is connected to the control terminal of the first switch, and the second terminal of the second switch receives the power supply voltage. The third switch has its control terminal connected to its first terminal and also connected to the first terminal of the second switch. The second terminal of the third switch is connected to the address configuration pin and provides the first bias current.

11. The address configuration circuit of the communication interface according to claim 9, wherein, Each of the comparison units includes: Identify resistors; The fourth switch is connected to the control terminal of the second switch, and the second terminal of the fourth switch receives the power supply voltage. The fifth switch is connected to the control terminal of the third switch, the first terminal of the fifth switch is connected to the first terminal of the fourth switch, and the second terminal of the fifth switch is grounded and provides the comparison current via the identification resistor.

12. The address configuration circuit of the communication interface according to claim 11, wherein, Each of the n comparison units compares the first bias current with the corresponding comparison current.

13. The address configuration circuit of the communication interface according to claim 11, wherein, A part of the n comparison units compares the first bias current with the corresponding comparison current, and another part of the n comparison units compares the i-fold mirror current of the first bias current with the corresponding comparison current, where i>1.

14. The address configuration circuit of the communication interface according to claim 12, wherein, The resistance value of each identification resistor in the n comparators is a resistance threshold, the resistance values of the identification resistors in the n comparators increase step by step, and the channel width-to-length ratio of the fourth switching transistor in each comparison unit is the same as that of the second switching transistor, and the channel width-to-length ratio of the fifth switching transistor in each comparison unit is the same as that of the third switching transistor.

15. The address configuration circuit of the communication interface according to claim 14, wherein, Among the n comparators, the resistance ratio or resistance difference between the identification resistor in the (m + 1)-th stage comparator and the identification resistor in the m-th stage comparator is equal, where m is an integer and 0 < m < n.

16. The address configuration circuit of the communication interface according to claim 13, wherein, The resistance value of each identification resistor in each of the comparators from the first-stage comparator to the h-th stage comparator among the n comparators is a resistance threshold, and the resistance values of the identification resistors in each of the comparators from the first-stage comparator to the h-th stage comparator increase step by step. The resistance values of the identification resistors in each of the comparators from the (h + 1)-th stage comparator to the n-th stage comparator among the n comparators are the same as the resistance value of the identification resistor in the h-th stage comparator; The channel width-to-length ratio of the fourth switching transistor in each of the comparators from the first-stage comparator to the h-th stage comparator is the same as that of the second switching transistor, and the channel width-to-length ratio of the fifth switching transistor in each of the comparators from the first-stage comparator to the h-th stage comparator is the same as that of the third switching transistor. The ratio of the channel width-to-length ratio of the fourth switching transistor in the (j + 1)-th stage comparator to the channel width-to-length ratio of the fourth switching transistor in the j-th stage comparator among the comparators from the (h + 1)-th stage comparator to the n-th stage comparator is i, and the ratio of the channel width-to-length ratio of the fifth switching transistor in the (j + 1)-th stage comparator to the channel width-to-length ratio of the fifth switching transistor in the j-th stage comparator among the comparators from the (h + 1)-th stage comparator to the n-th stage comparator is i, where h is an integer and 1 < h < n; j is an integer and h < j < n.

17. The address configuration circuit of the communication interface according to claim 16, wherein, The resistance ratio or resistance difference between the identification resistor in the (k + 1)-th stage comparator and the identification resistor in the k-th stage comparator among the comparators from the first-stage comparator to the h-th stage comparator is equal, where k is an integer and 0 < k < h.

18. The address configuration circuit for the communication interface according to claim 10, wherein, The bias unit further includes: A second resistor connected between the first end of the first switching transistor and the first resistor; A sixth switching transistor, the control end of the sixth switching transistor is connected to the first end of the first switching transistor and grounded through the second resistor and the first resistor, the second end of the sixth switching transistor receives the power supply voltage, and the first end of the sixth switching transistor is connected to the second end of the first switching transistor; A seventh switching transistor, the control end of the seventh switching transistor is connected to the control end of the sixth switching transistor, the second end of the seventh switching transistor receives the power supply voltage, and the first end of the seventh switching transistor is connected to the second end of the second switching transistor.

19. The address configuration circuit of the communication interface according to claim 11, wherein, Each comparison unit further includes: The eighth switch is connected between the second terminal of the fourth switch and the power supply voltage, and the control terminal of the eighth switch is connected to the control terminal of the seventh switch. In each of the comparison units, the channel width-to-length ratio of the eighth switching transistor is the same as that of the seventh switching transistor.

20. The address configuration circuit of the communication interface according to claim 5, wherein, The compiler's first to nth input terminals are connected to the first to nth level comparators to receive the corresponding comparison signals.

21. A communication device, wherein, include: Multiple communication components, each communication component including a communication interface, an address configuration pin, and an address configuration circuit for the communication interface as described in any one of claims 1-20.

22. A method for configuring the address of a communication interface in a communication device, wherein each communication interface corresponds to an address configuration pin, wherein, The address configuration method for the communication interface includes: Set n resistance thresholds, which form n+1 resistance intervals, and identify the resistance interval where the equivalent resistance value at the address configuration pin is located, and output the identification result, where n is a positive integer; and The address of the communication interface is generated based on the identification results.

23. The address configuration method for a communication interface according to claim 22, wherein, The n resistance thresholds are increased proportionally.

24. The address configuration method for a communication interface according to any one of claims 22-23, wherein, Identify the resistance range in which the equivalent resistance value at the address configuration pin lies, and output the identification result including: A resistance threshold is set, and a comparison current corresponding to the resistance threshold and a first bias current flowing through the address configuration pin are generated. The first bias current and the comparison current are compared to generate a corresponding comparison signal. The n comparison signals constitute the recognition result.

Images