Low-power-consumption dynamic frequency modulation method of network forwarding system and network forwarding system thereof
By monitoring and dynamically adjusting the global clock frequency of the network forwarding system, the problem of power consumption that cannot be precisely controlled in existing technologies has been solved, achieving low power consumption and improved stability in demanding scenarios such as vehicle gateways.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BLACK SESAME TECH (SHENZHEN) CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-17
AI Technical Summary
Existing network forwarding systems cannot perform fine-grained power consumption control based on real-time dynamic changes in network traffic, resulting in unnecessary power waste under moderate or fluctuating conditions, and failing to meet the battery life and stability requirements of high-demand application scenarios such as vehicle gateways.
By monitoring the runtime statistics of multiple processing modules in the system, a local frequency modulation index is generated, and the maximum value is selected as the system-level frequency modulation index. A delay reduction strategy is applied to dynamically adjust the global clock frequency of the network forwarding system. Combined with digital logic circuits, the delay reduction strategy and multi-level mapping are implemented to achieve precise power consumption control at the system level.
It achieves real-time power consumption control based on network traffic changes, reduces system power consumption, meets the high requirements of application scenarios such as vehicle gateways, extends the driving range of electric vehicles, and ensures system stability and reliability.
Smart Images
Figure CN121888338A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of network communication equipment technology, and in particular to a low-power dynamic frequency modulation method for a network forwarding system and the network forwarding system thereof. Background Technology
[0002] With the rapid development of automotive electronics and IoT technologies, the power consumption of network forwarding systems, especially automotive gateway chips, has become increasingly prominent when handling ever-increasing data traffic. Traditional gateway chips typically have fixed power solutions, thus their power consumption control requirements are relatively low. However, in specific application scenarios such as automotive, stringent requirements for driving range, thermal management, and system stability place extremely high demands on chip power consumption control.
[0003] In existing low-power designs for digital integrated circuits, the industry commonly employs techniques such as clock gating, power gating, and multi-voltage domains. These techniques are mostly based on independent functional modules, which reduce static or dynamic power consumption by turning off their clocks or cutting off their power supplies when the module is idle, thus putting it into a local sleep state.
[0004] However, such methods are essentially a static "on or off" control strategy, whose decisions depend on whether the module is in an active working state, and cannot perceive the continuous changes in the data processing pressure inside the system.
[0005] Specifically, in network forwarding systems, the aforementioned existing technologies cannot precisely control power consumption based on real-time dynamic changes in network traffic. When network traffic is moderate or fluctuating, the system often operates at a fixed high clock frequency even when not running at full load, leading to unnecessary power waste.
[0006] Therefore, there is an urgent need for a new low-power technology that can respond to actual business loads and perform precise system-level power consumption control as an effective supplement to the existing technology system, in order to meet the needs of high-requirement application scenarios such as vehicle gateways. Summary of the Invention
[0008] The purpose of this invention is to provide a low-power dynamic frequency modulation method for network forwarding systems and the network forwarding system thereof, so as to solve the problems pointed out in the background art.
[0009] In a first aspect, embodiments of the present invention provide a low-power dynamic frequency modulation method for a network forwarding system, comprising:
[0010] Runtime statistics of multiple processing modules in the monitoring system;
[0011] The runtime statistics of each processing module are compared with multiple thresholds preset for the corresponding module to independently generate a local frequency modulation index for each processing module. The local frequency modulation index represents the data processing pressure level of the corresponding module.
[0012] The maximum value among all local frequency modulation indices is selected as the system-level frequency modulation index;
[0013] A delayed descent strategy is applied to the system-level frequency modulation index to generate the final frequency modulation command. When the system-level frequency modulation index decreases, the final frequency modulation command must remain at a state where the system-level frequency modulation index is not higher than the decreased value for a duration not less than a preset time threshold before it follows the descent.
[0014] The global clock frequency of the network forwarding system is dynamically adjusted according to the final frequency adjustment command.
[0015] Optionally, the processing module includes an ingress processing module;
[0016] The runtime statistics of the monitoring ingress processing module include: configuring corresponding weights according to the bandwidth of each ingress port, and aggregating the weights of each ingress port with the real-time traffic request status to calculate the total weight value as the runtime statistics.
[0017] Optionally, the total weight value is obtained by multiplying the weight of each ingress port by its real-time traffic request status, and then summing the product of all ports.
[0018] Optionally, the processing module further includes a data path module and an exit processing module;
[0019] The runtime statistics of the data path module are the number of currently accumulated data packets or the percentage of currently occupied storage space to total storage space;
[0020] The runtime statistics of the outgoing processing module are weighted sums calculated based on the bandwidth and real-time data request status of each outgoing port.
[0021] Optionally, the delay reduction strategy is implemented using digital logic circuits, which include:
[0022] A counter is used to count when the system-level frequency modulation index is less than or equal to the current final frequency modulation command, and to reset when it exceeds the limit.
[0023] The comparator is used to trigger the final frequency modulation instruction to update the current system-level frequency modulation index when the value of the counter reaches a preset time threshold.
[0024] Optionally, the mapping relationship between the final frequency modulation command and the global clock frequency is a pre-configured multi-level mapping, which includes at least four different frequency levels.
[0025] Optionally, the multi-level mapping includes mapping the values 1, 2, 3, and 4 of the final frequency modulation command to clock frequencies of 50MHz, 400MHz, 600MHz, and 800MHz, respectively.
[0026] Optionally, the network forwarding system is an Ethernet switching chip or a vehicle gateway chip.
[0027] Optionally, the digital integrated circuits of the network forwarding system are time-constrained according to the highest frequency that the global clock frequency can reach.
[0028] In a second aspect, embodiments of the present invention provide a network forwarding system, comprising:
[0029] A logic circuit configured to perform a low-power dynamic frequency modulation method for a network forwarding system as described in any of the first aspects;
[0030] And an upstream interface module, which has a temporary data buffer, the capacity of which is designed to absorb the amount of data accumulated due to the difference in data transmission rate during the process of the global clock frequency jumping from the lowest level to the highest level.
[0031] The present invention has achieved the following beneficial effects:
[0032] This invention complements existing low-power technologies (such as clock gating and power gating), enabling real-time power consumption control based on changes in network traffic. Through system-level monitoring and decision-making, precise power consumption control is achieved, further reducing system power consumption with minimal area cost, thus meeting the needs of applications with high power consumption requirements, such as automotive gateways.
[0033] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.
[0034] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0035] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0036] Figure 1 This is a schematic diagram of a low-power dynamic frequency modulation method for a network forwarding system according to an embodiment of the present invention;
[0037] Figure 2 This is a simplified block diagram example of a four-port Ethernet forwarding system provided in one embodiment of the present invention;
[0038] Figure 3 A flowchart for generating the clock frequency range index for the entry processing module;
[0039] Figure 4 This is a schematic diagram illustrating that the final clock frequency level index follows the principle of rapid increase and slow decrease.
[0040] Figure 5 This is a timing diagram showing the relationship between the system clock, upstream interface data, and system input data when the clock frequency changes.
[0041] Figure 6 This diagram illustrates how the temporary data buffer of the upstream interface module absorbs the data stream accumulated due to the difference in data transmission rate when the system clock frequency jumps from 50MHz to 800MHz. Detailed Implementation
[0042] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0043] The research and development approach of this application is as follows.
[0044] Figure 1 A flowchart of a low-power dynamic frequency modulation method for a network forwarding system is provided in this application embodiment, as shown below. Figure 1 As shown, the method includes:
[0045] Runtime statistics of multiple processing modules in the monitoring system;
[0046] The runtime statistics of each processing module are compared with multiple thresholds preset for the corresponding module to independently generate a local frequency modulation index for each processing module. The local frequency modulation index represents the data processing pressure level of the corresponding module.
[0047] The maximum value among all local frequency modulation indices is selected as the system-level frequency modulation index;
[0048] A delayed descent strategy is applied to the system-level frequency modulation index to generate the final frequency modulation command. When the system-level frequency modulation index decreases, the final frequency modulation command must remain at a state where the system-level frequency modulation index is not higher than the decreased value for a duration not less than a preset time threshold before it follows the descent.
[0049] The global clock frequency of the network forwarding system is dynamically adjusted according to the final frequency adjustment command.
[0050] This embodiment provides a system-level low-power dynamic frequency modulation method. Its core lies in specifying corresponding statistical items based on the functional characteristics of each module within the network forwarding system, comparing them with configured thresholds at various levels to obtain the frequency modulation index for each module. Subsequently, at the system level, the frequency modulation indices of all internal modules are aggregated, and the maximum value is taken to ensure that the critical path is not congested. Finally, following the principle of fast increase and slow decrease, the index is converted to obtain the final frequency modulation index, which is then used by the clock management module to control the frequency of each system clock, completing the dynamic frequency modulation.
[0051] This invention complements existing low-power technologies (such as clock gating and power gating), enabling real-time power consumption control based on changes in network traffic. Through system-level monitoring and decision-making, precise power consumption control is achieved, further reducing system power consumption with minimal area cost, thus meeting the needs of applications with high power consumption requirements, such as automotive gateways.
[0052] In one embodiment, the processing module includes an ingress processing module;
[0053] The runtime statistics of the monitoring ingress processing module include: configuring corresponding weights according to the bandwidth of each ingress port, and aggregating the weights of each ingress port with the real-time traffic request status to calculate the total weight value as the runtime statistics.
[0054] This embodiment specifies the monitoring method for the ingress processing module. Weights are configured based on the bandwidth limit of each ingress port (e.g., a 1G port has a weight of 1, and a 10G port has a weight of 10). The total weight value is calculated by aggregating the weights of each ingress port with the real-time traffic request status (1 for data requests, 0 for idle), and serves as the runtime statistic for this module.
[0055] This method can accurately reflect the overall data pressure at the ingress point. By configuring weights, it distinguishes the traffic contribution of ports with different bandwidths, making the assessment of system load more accurate. This provides a reliable data foundation for subsequent dynamic frequency adjustment and avoids performance degradation or power waste caused by inaccurate assessment.
[0056] In one embodiment, the total weight value is obtained by multiplying the weight of each ingress port by its real-time traffic request status, and then summing the products of all ports.
[0057] This embodiment clarifies the specific algorithm for the total weight value, which involves multiplying the weight of each inbound port by its real-time traffic request status, and then summing the products of all ports. For example, the total weight = (port 1 weight × port 1 status) + (port 2 weight × port 2 status) + ... + (port N weight × port N status).
[0058] This calculation method is simple to implement, has low hardware overhead, and can integrate traffic information from all inbound ports in real time and efficiently, transforming a complex multi-port status assessment problem into a simple numerical value that is easy to compare with thresholds and quickly generate frequency modulation indexes.
[0059] In one embodiment, the processing module further includes a data path module and an exit processing module;
[0060] The runtime statistics of the data path module are the number of currently accumulated data packets or the percentage of currently occupied storage space to total storage space;
[0061] The runtime statistics of the outgoing processing module are weighted sums calculated based on the bandwidth and real-time data request status of each outgoing port.
[0062] This embodiment extends the monitoring scope to other key processing modules. For the data path module, the statistics can be the number of currently accumulated data packets or the percentage of currently occupied storage space to the total storage space. For the egress processing module, the statistics are weighted sums calculated based on the bandwidth limit of each egress port and the real-time data request situation.
[0063] By using multiple methods to monitor the processing pressure at different stages within the system in real time (such as queue depth, cache usage, and outgoing queue scheduling pressure), fine-grained monitoring of the entire data path chain is achieved. This ensures that the system can promptly detect and respond to any bottleneck that occurs in any module, thereby achieving optimal global power consumption while ensuring no data loss and no system congestion.
[0064] In one embodiment, the delay reduction strategy is implemented using digital logic circuitry, which includes:
[0065] A counter is used to count when the system-level frequency modulation index is less than or equal to the current final frequency modulation command, and to reset when it exceeds the limit.
[0066] The comparator is used to trigger the final frequency modulation instruction to update the current system-level frequency modulation index when the value of the counter reaches a preset time threshold.
[0067] This embodiment details the hardware implementation mechanism of the "fast rise, slow fall" principle. This strategy is implemented through a digital logic circuit containing a counter and a comparator. When the system-level frequency modulation index decreases, the counter starts counting. Only when the count value reaches a preset time threshold (e.g., 4 clock cycles) does the comparator trigger the final frequency modulation command to fall. If the system-level index rises again during this period, the counter is immediately reset.
[0068] The "fast increase, slow decrease" strategy can quickly process sudden traffic surges, avoiding data loss or system congestion. Simultaneously, the introduction of latency reduction prevents frequent clock frequency fluctuations due to momentary load jitter, enhancing system stability and reliability. This hardware implementation offers fast response times and does not consume significant software resources.
[0069] In one embodiment, the mapping relationship between the final frequency modulation command and the global clock frequency is a pre-configured multi-level mapping, which includes at least four different frequency levels.
[0070] The multi-level mapping includes mapping the values 1, 2, 3, and 4 of the final frequency modulation command to clock frequencies of 50MHz, 400MHz, 600MHz, and 800MHz, respectively.
[0071] This embodiment defines the mapping relationship between the final frequency modulation command and the physical clock frequency. The system clock frequency is preset to multiple levels; for example, the final frequency modulation index values of 1, 2, 3, and 4 are mapped to clock frequencies of 50MHz, 400MHz, 600MHz, and 800MHz, respectively. This mapping relationship allows the system to make large-step, efficient switching between power consumption and performance.
[0072] The multi-level configuration provides a flexible power consumption and performance trade-off strategy. Under low loads, the system can operate at low frequencies such as 50MHz, significantly reducing dynamic power consumption; when sudden traffic surges occur, it can quickly switch to a high frequency of 800MHz to ensure performance. This design makes power consumption control more precise and efficient. At the same time, the explicit level mapping simplifies the design of the clock management module.
[0073] In one embodiment, the network forwarding system is an Ethernet switching chip or an in-vehicle gateway chip.
[0074] This embodiment specifies the specific application scenario to which the method and system are applicable, namely Ethernet forwarding systems, especially automotive gateway chips with stringent power consumption requirements. In such scenarios, the system needs to handle network data exchange from different bandwidth ports (such as 1G and 10G).
[0075] Applying this invention to scenarios such as automotive gateways can directly address the technical challenge of increasingly demanding power consumption requirements. By dynamically adjusting the frequency, it effectively reduces the chip's operating power consumption while ensuring network forwarding performance, thus helping to extend the driving range of electric vehicles and meeting the stringent reliability and thermal management requirements of automotive-grade chips.
[0076] In one embodiment, the digital integrated circuits of the network forwarding system are time-constrained according to the highest frequency that the global clock frequency can reach.
[0077] This embodiment specifies the design rules for digital integrated circuits used to implement this dynamic frequency modulation system. Although the clock frequency changes dynamically, the timing design (static timing analysis) of the entire circuit must be constrained according to the highest clock frequency (such as the aforementioned 800MHz). This means that the circuit must meet timing requirements even in the worst-case scenario.
[0078] This design principle ensures that the system functions correctly at any frequency modulation setting, preventing data errors or system crashes due to timing violations. It provides a fundamental guarantee for the reliable implementation of dynamic frequency modulation and is the basis for ensuring the chip can operate stably under various complex operating conditions.
[0079] This application provides a network forwarding system, including:
[0080] Logic circuits configured to perform a low-power dynamic frequency modulation method for a network forwarding system as described in any of the above items;
[0081] And an upstream interface module, which has a temporary data buffer, the capacity of which is designed to absorb the amount of data accumulated due to the difference in data transmission rate during the process of the global clock frequency jumping from the lowest level to the highest level.
[0082] The core of the network forwarding system described in this embodiment lies in its innovative integration of an upstream interface module with a temporary data buffer while executing the aforementioned dynamic frequency modulation method through logic circuits. The capacity of this buffer is precisely designed to address the transient mismatch in data flow caused by drastic clock frequency changes during dynamic frequency modulation. Specifically, when the system needs to rapidly jump from the lowest frequency range (e.g., 50MHz) to the highest frequency range (e.g., 800MHz) due to a sudden surge in traffic, the high-speed influx of data will temporarily exceed the system's processing speed during the period before the frequency switch is completed and the system reaches full capacity. At this time, the temporary data buffer of the upstream interface module temporarily absorbs and buffers this data accumulated due to the data transmission rate difference, acting like a temporary "reservoir" to ensure that data is not lost due to insufficient processing time during the frequency modulation transition period.
[0083] This embodiment introduces an upstream temporary data buffer of a specific capacity, providing crucial data integrity assurance and system stability support for the entire dynamic frequency modulation system. Its direct benefit is the effective prevention of packet loss or system congestion that may occur during rapid clock frequency increases due to the system's processing capacity temporarily failing to keep up with the input data rate, thus ensuring the reliability of network forwarding functions. This allows for the safe implementation of a bold and efficient dynamic frequency modulation strategy without the need to conservatively maintain a higher base frequency for fear of data loss. Ultimately, this design, without sacrificing system performance and data reliability, supports and amplifies the low-power benefits of dynamic frequency modulation, serving as a key and necessary engineering guarantee for achieving the low-power goal of this invention.
[0084] In a more specific embodiment, this invention provides clock frequency level indices for each functional module, taking into account the structural characteristics of the Ethernet forwarding system. These level indices are aggregated and processed at the system level to obtain the final level index. The clock management module then uses this level index to change the system clock frequency in real time to reduce power consumption. Figure 2 This describes a simplified block diagram example of a 4-port Ethernet forwarding system. First, weights are configured based on the bandwidth limit of each ingress port. Assuming ingress ports 1 and 2 are 1G ports each, and ingress ports 3 and 4 are 10G ports each, a reasonable weight configuration for the four ingress ports is: w in1 =1, w in2 =1, w in3 =10, w in4 =10. Based on the real-time traffic status of each port, the weight values of the four ingress ports are added together to obtain the formula for the total weight of the ingress processing module as follows:
[0085] w int =w in1 ×r in1 +w in2 ×r in2 +w in3 ×r in3 +w in4 ×r in4
[0086] r in the formula in1 r in2 r in3 r in4 These represent the real-time traffic request status of the four inbound ports. When inbound port 1 is idle, r in1 When the value is 0, and there is a data request on port 1, r in1 The value of r is 1. in2 r in3 r in4 The assignment method and r in1The same applies. If there are a total of 4 clock frequency levels, then three thresholds (th1) need to be configured. in ,th2 in ,th3 in In the input processing module, the given clock frequency level index lp in The relationship with the above three thresholds is as follows: Figure 3 As described. In data path module 1, the clock frequency level index lp d1 It can be made by w d1 With the third-level threshold th1 d1 ,th2 d1 ,th3 d1 The comparison yields the following result. In data path module 2, the clock frequency level index lp is... d2 It can be made by w d2 With the third-level threshold th1 d2 ,th2 d2 ,th3 d2 The comparison yields the following result. In the export processing module, the clock frequency level index lp... out It can be made by w out With the third-level threshold th1 out ,th2 out ,th3 out This was obtained through comparison. d1 w d2 w out The meaning of can be determined and calculated based on the actual application scenario of the current module. For example: w d1 w represents the number of data packets currently accumulated in data path module 1. d2 This represents the percentage of storage space currently occupied by data path module 2 relative to the total storage space, w. out This indicates the weights calculated by the outgoing processing module based on the bandwidth limit of each outgoing port and the real-time data request situation.
[0087] In the above processing, four clock frequency level indices lp were obtained. in , lp d1 , lp d2 , lp out Of these four clock level indices, only four valid values exist: 1, 2, 3, and 4. A smaller clock level index indicates a lower data processing load for the corresponding module. A larger clock level index indicates a higher data processing load for the corresponding module, requiring a higher clock frequency. The module with the largest clock level index is likely the critical path in the entire data processing chain. Since the system clock frequency is positively correlated with the clock level index, the largest clock level index should be used to control the system clock to ensure that the entire data path does not become congested. The largest clock level index is lp. max It is given by the following formula:
[0088] lp max =max{lp in , lp d1 , lp d2 , lp out}
[0089] The final clock frequency and step index should follow a fast rise and slow fall principle to process burst traffic as quickly as possible and avoid data loss or system congestion. In digital integrated circuit design, assume a step index descent time threshold th. clk =4 (unit is cycle, i.e., number of clock cycles), then the final clock frequency level index lp of the system is... top and lp max The relationship can be used Figure 4 (Note: Due to the influence of dynamic frequency modulation, the actual time of each clock cycle may be different. Here, the same length is used for illustration.) Figure 4 This is just an example; in practice, to maintain system stability, the clk The value of can be much greater than 4. In the diagram, when lp... max When the time it takes for the value to decrease from 4 to 3, and is less than or equal to 3, reaches 4 clock cycles, lp top This results in a transition from 4 to 3. Finally, the clock management module determines the final time based on the lp... top The mapping relationship with the configured clock frequency needs to be established, and the clock frequency adjusted in real time. Additionally, the temporary data caching capability of upstream modules interfacing with this system needs to be designed. Assuming in lp... top When the values are 1, 2, 3, and 4, the clock frequencies mapped to system clock 1 (clk_sys1) are 50MHz, 400MHz, 600MHz, and 800MHz, respectively. If the clock periods for the four clock frequencies are represented by T1, T2, T3, and T4, then according to the conversion relationship between clock period and frequency, we know that T1 = 16T4, T2 = 2T4, and T3 = 1.33T4. If a traffic burst occurs, the clock frequency may jump from 50MHz to 800MHz. Assuming the data width is x bits, without considering the time overhead of interface handshake, the upstream interface module still needs to have a temporary buffer capacity to absorb 16x bits of data. For details, please refer to [reference needed]. Figure 5 and Figure 6 ,from Figure 6 As can be seen, when data_in finishes processing data D1, data_up has already started transmitting data D17. Besides temporary buffering capabilities, the entire system, in digital integrated circuit design, requires timing constraints based on the highest clock frequency (800MHz in this case).
[0090] The methods and processes described above together form a complete low-power design system. By monitoring and calculating various internal states in real time, the system clock frequency is controlled, and dynamic frequency adjustment is achieved. Ultimately, this reduces system power consumption.
[0091] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A low-power dynamic frequency modulation method for a network forwarding system, characterized in that, include: Runtime statistics of multiple processing modules in the monitoring system; The runtime statistics of each processing module are compared with multiple thresholds preset for the corresponding module to independently generate a local frequency modulation index for each processing module. The local frequency modulation index represents the data processing pressure level of the corresponding module. The maximum value among all local frequency modulation indices is selected as the system-level frequency modulation index; A delayed descent strategy is applied to the system-level frequency modulation index to generate the final frequency modulation command. When the system-level frequency modulation index decreases, the final frequency modulation command must remain at a state where the system-level frequency modulation index is not higher than the decreased value for a duration not less than a preset time threshold before it follows the descent. The global clock frequency of the network forwarding system is dynamically adjusted according to the final frequency adjustment command.
2. The low-power dynamic frequency modulation method for a network forwarding system as described in claim 1, characterized in that, The processing module includes an ingress processing module; The runtime statistics of the monitoring ingress processing module include: configuring corresponding weights according to the bandwidth of each ingress port, and aggregating the weights of each ingress port with the real-time traffic request status to calculate the total weight value as the runtime statistics.
3. The method of claim 2, wherein, The total weight value is obtained by multiplying the weight of each ingress port by its real-time traffic request status, and then summing the product of all ports.
4. The method of claim 1, wherein, The processing module also includes a data path module and an output processing module; The runtime statistics of the data path module are the number of currently accumulated data packets or the percentage of currently occupied storage space to total storage space; The runtime statistics of the outgoing processing module are weighted sums calculated based on the bandwidth and real-time data request status of each outgoing port.
5. The method of claim 1, wherein, The delay reduction strategy is implemented using digital logic circuits, which include: A counter is used to count when the system-level frequency modulation index is less than or equal to the current final frequency modulation command, and to reset when it exceeds the limit. The comparator is used to trigger the final frequency modulation instruction to update the current system-level frequency modulation index when the value of the counter reaches a preset time threshold.
6. The method of claim 1, wherein, The mapping relationship between the final frequency modulation command and the global clock frequency is a pre-configured multi-level mapping, which includes at least four different frequency levels.
7. The method of claim 6, wherein, The multi-level mapping includes mapping the values 1, 2, 3, and 4 of the final frequency modulation command to clock frequencies of 50MHz, 400MHz, 600MHz, and 800MHz, respectively.
8. The method of claim 1, wherein, The network forwarding system is an Ethernet switching chip or a vehicle gateway chip.
9. The method of claim 1, wherein, The digital integrated circuits of the network forwarding system are time-constrained according to the highest frequency that the global clock frequency can reach.
10. A network forwarding system, characterized by, include: A logic circuit configured to perform a low-power dynamic frequency modulation method for a network forwarding system as described in any one of claims 1 to 9; And an upstream interface module, which has a temporary data buffer, the capacity of which is designed to absorb the amount of data accumulated due to the difference in data transmission rate during the process of the global clock frequency jumping from the lowest level to the highest level.