Microcavity chip and preparation method and application thereof

Abstract

The invention provides a microcavity chip and a preparation method and application thereof. The microcavity chip comprises a substrate layer, a first electrode layer, a second electrode layer and a microcavity layer. The first electrode layer is located on the first surface of the substrate layer, and the first electrode layer is provided with a plurality of first electrodes; the micro-cavity layer is located on the surface of the first electrode layer and is provided with a plurality of micro-cavities, and each micro-cavity at least covers part of the first electrode; the second electrode layer is located on the side, away from the substrate layer, of the microcavity layer and makes contact with the microcavity, and the second electrode layer is provided with at least one second electrode. Compared with the prior art, the chip has at least one of the following beneficial effects of reducing signal interference of an electric field on the microcavity, reducing power consumption, improving working efficiency of the chip, improving flux, saving space, reducing cost and better realizing miniaturization.

Description

Technical Field

[0001] This application relates to the field of biochips, specifically to a microcavity chip and its preparation method and applications. Background Technology

[0002] As a novel platform, microcavity chips possess a microcavity structure that can enhance signals, enabling them to sense minute changes and allowing for highly sensitive detection and sensing with fast response times. Furthermore, by altering the structure or external conditions of the microcavity chip, its characteristics can be tuned to achieve various functions. Therefore, microcavity chips have wide applications in the field of biotechnology. However, existing microcavity chip technologies still have significant room for improvement in areas such as structural design, high throughput, signal-to-noise ratio, miniaturization and portability, high precision, and manufacturing cost, requiring further research and innovation to meet the evolving needs of biotechnology.

[0003] Therefore, current microcavity chips still need improvement. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a microcavity chip that can at least alleviate or even solve at least one of the problems mentioned in the background art to a certain extent.

[0005] In one aspect of the present invention, a microcavity chip is provided, the microcavity chip comprising a substrate layer, a first electrode layer, a second electrode layer, and a microcavity layer; the first electrode layer is located on a first surface of the substrate layer and has a plurality of first electrodes; the microcavity layer is located on the surface of the first electrode layer and has a plurality of microcavities, each microcavity at least covering a portion of the first electrode; the second electrode layer is located on the side of the microcavity layer opposite to the substrate layer and is in contact with the microcavities, the second electrode layer having at least one second electrode.

[0006] Furthermore, the substrate layer includes at least one of a silicon substrate layer, a glass substrate layer, and a polymer substrate layer.

[0007] Furthermore, the microcavity chip further includes a connection layer; the connection layer is located on a first surface of the substrate layer and has conductive traces; or, the connection layer has conductive vias penetrating the substrate layer; the connection layer is connected to the first electrode layer.

[0008] Furthermore, the microcavity chip further includes a third electrode layer; the third electrode layer is located on the second surface of the substrate layer, the third electrode layer has a plurality of third electrodes, and the third electrodes are connected to the first electrode through the conductive vias penetrating the substrate layer.

[0009] Furthermore, the microcavity chip further includes an auxiliary electrode layer having at least one auxiliary electrode, the auxiliary electrode layer being located between the microcavity layer and the first electrode layer, and in contact with the microcavity layer and the first electrode layer respectively; wherein each microcavity at least covers a portion of the auxiliary electrode.

[0010] Furthermore, the material of the conductive traces or conductive vias forming the connection layer includes at least one of Cu, Au, and Ni.

[0011] Furthermore, the materials forming the first electrode, the second electrode, the third electrode, and the auxiliary electrode each independently include at least one of Au, Al, and Ag, and preferably, the material forming the auxiliary electrode is Ag.

[0012] Furthermore, the material forming the microcavity layer includes a polymer material, and the polymer material includes at least one of SU8 and PI.

[0013] Furthermore, in the microcavity layer, a plurality of microcavities are arranged in an array, and the openings of the microcavities include at least one of a plane, a single inclined plane, and a double inclined plane.

[0014] Furthermore, the opening of the microcavity is a single inclined plane and / or a double inclined plane, wherein the angle between the inclined plane and the plane at the bottom of the microcavity layer is 0-90°, excluding 0° and 90°.

[0015] Preferably, the angle between the inclined plane and the plane at the bottom of the microcavity layer is 30-60°.

[0016] Furthermore, the height of the microcavity is 1-100 μm.

[0017] Furthermore, the cross-sectional width of the microcavity is 1-100 μm.

[0018] Furthermore, the aspect ratio of the microcavity is 0.1-100.

[0019] Furthermore, the opening, bottom, and / or sidewalls of the microcavity are covered with a membrane.

[0020] Furthermore, the surfaces of the first electrode and / or auxiliary electrode in contact with the microcavity have surface modifications.

[0021] In another aspect of the present invention, the present invention provides a method for fabricating the above-mentioned microcavity chip, the method comprising: providing a substrate layer; forming a first electrode layer on the substrate layer; forming a microcavity layer on the first electrode layer; and disposing of a second electrode layer.

[0022] Further, the method further includes the step of forming the interconnect layer, the step comprising at least one of the following: the interconnect layer is located on a first surface of the substrate layer, and the interconnect layer is formed on the first surface of the substrate layer by at least one of a lift-off process, a photolithography-IBE etching process, and a metal etching process; or, the interconnect layer is embedded inside the substrate layer, a metal material layer is deposited on the first surface of the substrate layer having vias, the metal material layer is filled into the vias by electroplating to form the interconnect layer, and the interconnect layer is processed by a CMP planarization process.

[0023] Further, when the substrate is a polymer substrate, the method includes the step of forming a connection layer while providing the substrate. The step includes: depositing a sacrificial layer on a silicon substrate, coating the surface of the sacrificial layer with a material of the polymer substrate, and forming a via structure using photolithography to form a polymer substrate; depositing a metal material layer on the surface of the polymer substrate with vias, filling the vias with the metal material layer by electroplating to form the connection layer, and processing the connection layer using a CMP planarization process; covering the surface of the polymer substrate with the connection layer with a barrier film, and then etching the sacrificial layer with an etching solution to obtain a polymer substrate with the connection layer.

[0024] In another aspect, the present invention provides the use of the above-described microcavity chip for non-diagnostic purposes in the biomedical field.

[0025] Furthermore, the uses include at least one of biosynthetic reactions, biomolecular characterization, and nucleotide detection.

[0026] The present invention has at least one of the following beneficial effects:

[0027] 1. The microcavity chip of the present invention has a substrate layer with high insulation, which can reduce the signal interference generated by the electric field on the microcavity;

[0028] 2. The microcavity chip of the present invention can use glass and polymer as substrates, eliminating the need to prepare an insulating layer, which can reduce costs. Furthermore, glass and polymer have no freely moving charges and excellent dielectric properties, which can reduce power consumption and improve chip operating efficiency.

[0029] 3. The microcavity chip of the present invention has a high microcavity arrangement density, which can improve throughput, save space, reduce cost, and better realize miniaturization;

[0030] 4. The method for fabricating microcavity chips of the present invention can simplify MEMS processes, save costs, and produce high-throughput, miniaturized microcavity chips.

[0031] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0032] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0033] Figure 1 This is a schematic diagram of the structure of a microcavity chip according to an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of a microcavity chip according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of a microcavity chip according to an embodiment of the present invention;

[0036] Figure 4 This illustrates the correspondence between the microcavity and the electrode in one embodiment of the present invention.

[0037] Figure 5 The phase shape and arrangement of electrodes according to an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the shape of a microcavity according to an embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the structure of a microcavity chip according to an embodiment of the present invention;

[0040] Figure 8 for Figure 7 A cross-sectional view of the microcavity chip in the image;

[0041] Figure 9 This is a comparison diagram of a planar-opening microcavity and a sloped-opening microcavity according to an embodiment of the present invention;

[0042] Figure 10 This is a flowchart of the fabrication method of the microcavity chip in Embodiment 2 of the present invention;

[0043] Figure 11 This is a flowchart of the fabrication method of the microcavity chip in Embodiment 3 of the present invention;

[0044] Figure 12 This is a flowchart of the fabrication method of the microcavity chip in Embodiment 4 of the present invention.

[0045] Explanation of reference numerals in the attached figures: 100-substrate layer, 200-first electrode layer, 300-microcavity layer, 400-second electrode layer, 500-connection layer, 600-terminal, 700-auxiliary electrode layer, 800-third electrode layer, 10-silicon wafer, 20-AF32 glass, 30-sacrificial layer. Detailed Implementation

[0046] To more clearly understand the technical features, objectives, and beneficial effects of the present invention, the technical solution of the present invention will now be described in further detail. In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0047] In one aspect, the present invention provides a microcavity chip. (See reference...) Figure 1 The microcavity chip includes a substrate 100, a first electrode layer 200, a second electrode layer 400, and a microcavity layer 300. The first electrode layer 200 is located on a first surface of the substrate 100; the microcavity layer 300 is located on the surface of the first electrode layer 200; the second electrode layer 400 is located on the side of the microcavity layer 300 opposite to the substrate 100, and the second electrode layer 400 is in contact with the microcavity layer 300 to form a circulation path between the first electrode layer 200, the microcavity layer 300, and the second electrode layer 400. The first electrode layer 200 has multiple first electrode layers 200, the second electrode layer 400 has at least one second electrode, and the microcavity layer 300 has multiple microcavities, with each microcavity at least partially covering the first electrode. The microcavity chip has at least one of the following beneficial effects: reducing signal interference caused by the electric field on the microcavity, reducing power consumption, improving chip operating efficiency, increasing throughput, saving space, reducing cost, and enabling better miniaturization.

[0048] According to embodiments of the present invention, the size of the microcavity chip and the thickness of each layer therein are not particularly limited, and can be adjusted arbitrarily according to the desired function of the microcavity chip. Furthermore, it should be noted that the second electrode layer 400 can exist independently when the microcavity chip is in a non-operating state, and can cover the surface of the microcavity when the microcavity chip is in an operating state, forming a circulation path between the first electrode layer 200, the microcavity layer 300, and the second electrode layer 400 to detect changes occurring within the microcavity. Therefore, the second electrode layer 400 is not shown in some examples or figures provided in this application.

[0049] The structure of the microcavity chip according to a specific embodiment of the present invention will be further described in detail below:

[0050] According to embodiments of the present invention, the substrate layer 100 includes a silicon substrate layer, a glass substrate layer, a polymer substrate layer, or a combination thereof, and the types of materials used in the silicon substrate layer, glass substrate layer, and polymer substrate layer are not particularly limited. Specifically, the material of the silicon substrate layer can be a silicon-containing chip, for example, including but not limited to low-resistivity silicon chips, high-resistivity silicon chips, or combinations thereof; the material of the glass substrate layer includes but is not limited to EXG material, AF32 material, or combinations thereof; the material of the polymer substrate layer includes but is not limited to SU8, PI, or combinations thereof. In a specific embodiment, a silicon oxide layer may be further disposed on the surface of the silicon substrate layer to improve the insulation of the silicon substrate layer, thereby reducing signal interference experienced by the microcavity when operating under an electric field; the glass substrate layer and the polymer substrate layer have good insulation properties, so there is no need to dispose of an insulating layer on their surfaces. In addition, due to the characteristics that glass and polymer themselves have no freely moving charges and excellent dielectric properties, the power consumption of the microcavity chip with a glass substrate layer and / or a polymer substrate layer of the present invention is reduced and the operating efficiency is improved.

[0051] According to an embodiment of the present invention, the microcavity chip may further include a connection layer 500 connected to the first electrode layer 200. The material forming the connection layer 500 is not particularly limited, and can be a metallic material, including but not limited to Cu, Au, Ni, or combinations thereof. The connection layer 500 may be located on the first surface of the substrate layer 100, forming a conductive trace connected to the first electrode layer 200; or, the connection layer 500 may penetrate the interior of the substrate layer 100, forming a conductive via connected to the first electrode layer 200. In one example, when the connection layer 500 is on the first surface of the substrate layer 100 and has conductive traces, the microcavity chip may further include one or more terminals 600, and the terminals 600 are also located on the first surface of the substrate layer 100, preferably on the edge of the first surface of the substrate layer 100. The correspondence between the conductive traces and the first electrode is not particularly limited; for example, in one example, one end of each trace may be connected to a first electrode, and the other end to a terminal 600. Alternatively, in other examples, a single terminal 600 may be connected to multiple traces simultaneously. Alternatively, multiple first electrodes may be connected to the same conductive trace, with the terminal 600 positioned on the side of the conductive trace closest to the edge of the substrate 100. Specifically, refer to... Figure 2 The diagram shows a schematic of a microcavity chip. In this microcavity chip, a connection layer 500 forms conductive traces on the first surface of a substrate layer 100, with one end of each trace connected to a first electrode and the other end connected to a terminal 600. However, it should be noted that the arrangement of the first electrode, conductive traces, and terminals 600 is not particularly limited and is not restricted to any particular configuration. Figure 2 The form shown.

[0052] In another example, when the interconnect layer 500 penetrates the interior of the substrate layer 100 and forms a conductive via, the microcavity chip may further include a third electrode layer 800. The third electrode layer 800 has multiple third electrodes and is located on the second surface of the substrate layer 100; that is, the first electrode layer 200 and the third electrode layer 800 are located on opposite sides of the substrate layer 100. Each via is connected at one end to the first electrode and at the other end to the third electrode; that is, the first and third electrodes are distributed on opposite sides of the substrate layer 100 and interconnected through conductive vias penetrating the interior of the substrate layer 100. Specifically, refer to... Figure 3 The diagram shows a schematic of a microcavity chip, in which a connecting layer 500 penetrates the substrate layer 100 and forms a conductive via, through which a first electrode and a third electrode are connected. However, it should be noted that the arrangement and dimensions of the first electrode, the conductive via, and the third electrode are not limited to... Figure 3 The form shown can be adjusted arbitrarily according to the characteristics of the target microcavity chip. In addition, compared with the interconnect layer 500 being located on the first surface of the substrate layer 100, the interconnect layer 500 penetrating the interior of the substrate layer 100 can increase the available area on the first surface of the substrate layer 100, enabling the arrangement of more electrodes and microcavities, further increasing the microcavity arrangement density, improving throughput, saving space, and reducing costs.

[0053] According to an embodiment of the present invention, the microcavity chip may further include an auxiliary electrode layer 700 to further improve the accuracy of the chip. The auxiliary electrode layer 700 includes a plurality of auxiliary electrodes. The auxiliary electrode layer 700 may be located on the surface of the first electrode layer 200, that is, between the microcavity layer 300 and the first electrode layer 200, and is in contact with both the microcavity layer 300 and the first electrode. Each microcavity in the microcavity layer 300 at least covers a portion of the auxiliary electrode; that is, in the presence of the auxiliary electrode layer 700, each microcavity at least covers a portion of the first electrode and / or the auxiliary electrode. For example, in… Figure 2 and Figure 3 In the structure shown, the auxiliary electrode is located on the surface of the first electrode and corresponds to the microcavity. However, in specific embodiments, the position of the auxiliary electrode and its correspondence with the microcavity are not limited to... Figure 2 and Figure 3 As shown in the diagram. That is to say, as long as each microcavity at least partially covers the first electrode and / or auxiliary electrode, detection of the microcavity can be achieved. For example, refer to... Figure 4This displays the correspondence between a single microcavity and a single electrode, meaning that one electrode can correspond to one or more microcavities. For example, one electrode can correspond to one microcavity, or one electrode can correspond to more than one microcavity, such as one electrode corresponding to two microcavities, one electrode corresponding to three microcavities, one electrode corresponding to four microcavities, one electrode corresponding to five microcavities, one electrode corresponding to six microcavities, and so on. When one electrode corresponds to multiple microcavities, the electrode can completely cover all microcavities, or it can cover a portion of each microcavity. Having one electrode corresponding to multiple microcavities allows for the superposition of detection data from several microcavities to increase the electrode's input and output, i.e., achieving the detection purpose by increasing the number of detection samples. For example, this can be applied to situations where a single sample cannot detect the electrode signal. Figure 4 The electrode shown can be either the first electrode or an auxiliary electrode.

[0054] According to embodiments of the present invention, the materials, shapes, and arrangements of the first electrode, second electrode, third electrode, and auxiliary electrode are not particularly limited. For example, in a specific embodiment, the materials of the first electrode, second electrode, third electrode, and auxiliary electrode can be independently selected from at least one of Au, Al, and Ag, and preferably the materials of the first electrode, second electrode, and third electrode are independently selected from at least one of Au and Al, and more preferably the material of the auxiliary electrode is Ag. The shapes of the first electrode, second electrode, third electrode, and auxiliary electrode can be independently selected from any geometric shape, such as, but including but not limited to, circles, ellipses, triangles, squares, rectangles, rhombuses, and other polygons; and the first electrode, second electrode, third electrode, and auxiliary electrode can be arbitrarily arranged in their respective positions, but in order to make full use of chip space, it is preferable to make adjacent individual electrodes closely connected to each other to improve electrode density. For example, refer to Figure 5 The figure illustrates the possible shapes and high-density arrangements of the first, second, third, and auxiliary electrodes. However, the shape and arrangement of individual electrodes within each electrode layer are not limited to the structures shown in the figure. Furthermore, in specific embodiments, to further enrich the functionality of the microcavity chip, the surfaces of the first and / or auxiliary electrodes in contact with the microcavity layer 300 may be modified with, for example, chemical groups, reaction substrates, enzymes, and probes. This allows for real-time monitoring of reaction progress and kinetic parameters, providing important tools and platforms for biosynthesis, enzyme-catalyzed reactions, and molecular detection.

[0055] In a specific embodiment, the material forming the microcavity layer 300 includes a polymer material, and the type of polymer material is not particularly limited, for example, including but not limited to SU8, PI, or combinations thereof. When the substrate layer 100 is a polymer substrate layer, the material of the microcavity layer 300 can be the same as the material of the polymer substrate layer to ensure good compatibility and lower cost.

[0056] According to embodiments of the present invention, the size, shape, and volume of the microcavities in the microcavity layer 300 are not particularly limited, but can be determined based on the desired volume of the microcavity chip and the structure of the microcavity layer 300. Furthermore, the size, shape, and volume of each of the multiple microcavities can be the same or different. Specifically, the shape of each microcavity can be independently a geometric shape with a certain volume, for example, including but not limited to… Figure 6 Some shapes are shown in the figure. In specific embodiments, to avoid the microcavity volume being too large and affecting the chip's function, the height of the microcavity is preferably set to 1-100 μm, the cross-sectional width of the microcavity is set to 1-100 μm, and the aspect ratio of the microcavity is set to 0.1-100. For example, in some embodiments, the height of the microcavity is set to 3-10 μm. In some embodiments, the width of the microcavity is set to 3-10 μm. In some embodiments, the width of the microcavity is set to 5 μm or 2.5-4.5 μm. Furthermore, the arrangement of the multiple microcavities in the microcavity layer 300 is not particularly limited and can be arbitrarily arranged, as long as the microcavities at least cover a portion of the first electrode and / or auxiliary electrode. However, in specific embodiments, to make full use of space, the multiple microcavities are preferably arranged in an array.

[0057] Furthermore, each microcavity has an opening that allows reactants to enter and exit, and the form of the microcavity opening is not particularly limited, and can include, but is not limited to, at least one of planar openings, single-sloped openings, and double-sloped openings. That is to say, given that the microcavities are arranged in an array, the structure of the microcavity layer 300 can be classified into a planar through-hole array structure, a single-sloped through-hole array structure, and a double-sloped through-hole array structure based on the form of the microcavity openings. However, in specific embodiments, the structure of the microcavity layer 300 is not limited to the types listed above. When the microcavities are arranged in a non-array configuration, the structure of the microcavity layer 300 will change accordingly with the arrangement of the microcavities. For example, Figure 2 and Figure 3 The structure of the microcavity layer 300 in the microcavity chip shown is a flat via array structure. (Reference) Figure 7 The diagram shows a schematic of a microcavity chip, wherein the microcavity layer 300 has a single-beveled through-hole array structure, and its cross-sectional view is shown below. Figure 8As shown. It should also be noted that when the microcavity opening is in the form of a single-sloped opening or a double-sloped opening, the inclination of the slope is not restricted in any way. Specifically, the angle between the slope of the opening and the plane at the bottom of the microcavity layer 300 can be 0-90° (excluding 0° and 90°), such as 5-85°, 10-80°, 15-75°, 30-45°, 30-60° or 45-60°, etc. When the microcavity opening size is the same, compared with the planar opening, the microcavities with single-sloped openings and double-sloped openings occupy a smaller area and can achieve a denser arrangement. For example, compared to a planar opening, when the angle between the bevel and the plane at the bottom of the microcavity layer 300 is 30°, the packing density increases by 1.25 times; when the angle is 45°, the packing density increases by 1.43 times; and when the angle is 60°, the packing density increases by 2 times. Therefore, within a limited chip area, the beveled opening increases the packing density of the functional patterns (or microcavities), thereby increasing the chip's detection throughput.

[0058] For example, refer to Figure 9 This shows a microcavity with an opening in a 5 μm plane. Figure 9 A) and a microcavity with a 5μm single-sloped opening ( Figure 9 As can be clearly seen in section B), when the microcavity opening size and volume are the same, the cross-sectional width of the microcavity with a single-sloped opening is significantly smaller than that of the microcavity with a planar opening. Therefore, a flat through-hole array structure can increase the number of cells arranged. By using single-sloped and double-sloped through-hole array structures, the microcavity arrangement density can be further increased within the constraints of the microcavity surface area, thereby further saving space, increasing throughput, reducing costs, and achieving miniaturized portable packaging.

[0059] Furthermore, in specific embodiments, a membrane, such as a functional membrane, can be provided at the opening, bottom, or sidewall of the microcavity to facilitate the fixation of specific biomolecules (such as proteins, antibodies, DNA molecules, polymers, etc.) on the surface of the microcavity. The special structure of the microcavity helps to achieve rapid and accurate detection and analysis of biomolecules.

[0060] In another aspect of the present invention, a method for fabricating the aforementioned microcavity chip is provided. The method includes: providing a substrate layer 100; forming a connection layer 500 on a first surface or inside the substrate layer 100; forming a first electrode layer 200 electrically connected to the connection layer 500; and forming a microcavity layer 300 on the first electrode layer 200. This method has at least one of the following beneficial effects: it simplifies MEMS processes, saves costs, and enables the fabrication of high-throughput, miniaturized microcavity chips.

[0061] The types, materials, and arrangements of the layers in the microcavity chip have been described in detail above and will not be repeated here. Furthermore, it should be noted that the order of the steps in the method of this application is not particularly restricted, and two adjacent steps can be performed simultaneously.

[0062] According to embodiments of the present invention, since the substrate 100 of the microcavity chip of this application includes a silicon substrate, a glass substrate, and a polymer substrate, the step of providing the substrate 100 includes at least one of the steps of providing a silicon substrate, providing a glass substrate, and providing a polymer substrate. In a specific embodiment, the step of providing the silicon substrate includes forming a silicon oxide layer on the silicon substrate material by a deposition or thermal oxidation process to obtain the silicon substrate; or, forming a via structure on the silicon substrate material using photolithography, and then forming a silicon oxide layer using a thermal oxidation process to obtain the silicon substrate. The step of providing the glass substrate includes laser-modifying the glass substrate material to form a via structure, and etching the vias using an etchant to obtain a glass substrate with a via structure. The step of providing the polymer substrate includes using the silicon substrate material as a support; specifically, depositing a sacrificial layer on the silicon substrate material, coating the surface of the polymer substrate material on the sacrificial layer, and optionally forming a via structure using photolithography to form the polymer substrate. The thermal oxidation process can prepare a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. The materials used for the sacrificial layer include, but are not limited to, the AZ series (AZ4562, AZ5214), the SU8 series, and PMMA materials. In specific embodiments, the thickness of the polymer substrate layer is determined by the coating method and speed, offering the advantage of adjustable thickness and resistance to damage.

[0063] According to embodiments of the present invention, since the interconnect layer 500 of the microcavity chip of this application can be located on the first surface of the substrate layer 100, or located inside the substrate layer 100 and penetrating the substrate layer 100, the step of forming the interconnect layer 500 includes forming the interconnect layer 500 on the first surface of the substrate layer 100, and / or forming the interconnect layer 500 inside the substrate layer 100. In one example, when the substrate layer 100 does not have a via structure, the interconnect layer 500 can be disposed on the first surface of the substrate layer 100. Specific steps include forming the interconnect layer 500 on the first surface of the substrate layer 100 by at least one of a lift-off process, a photolithography-IBE etching process, and a metal etching process. In another example, when the substrate 100 has a via structure, the interconnect layer 500 can penetrate the interior of the substrate 100 to form a conductive via penetrating the substrate 100. The specific steps include depositing a metal material layer on the first surface of the substrate 100 with the via, filling the via with the metal material layer by electroplating to form the interconnect layer 500, and processing the interconnect layer 500 using a CMP planarization process to form an interconnect layer 500 structure penetrating the substrate 100.

[0064] According to an embodiment of the present invention, when the substrate 100 is a polymer substrate, the method of the present invention further includes the step of forming a connecting layer 500 while providing the substrate 100, so as to prepare the connecting layer 500 at the same time as providing the polymer substrate, thereby reducing the number of process steps. Specifically, this step includes: depositing a sacrificial layer on a silicon substrate, coating the surface of the sacrificial layer with the material of the polymer substrate, and forming a via structure by photolithography to obtain a polymer substrate with a via structure; depositing a metal material layer on the surface of the polymer substrate with vias obtained above, filling the vias with the metal material layer by electroplating to form the connecting layer 500, and treating the connecting layer 500 by a CMP planarization process; then covering the surface of the polymer substrate with the connecting layer 500 with a barrier film, and then etching the sacrificial layer with an etching solution to obtain the polymer substrate with the connecting layer 500. The type of barrier film used is not particularly limited, and includes, for example, but not limited to, silicon nitride, silicon oxide, aluminum oxide, polyimide, and / or silicon oxynitride. The types of corrosive solutions are not particularly limited, including but not limited to hydrofluoric acid, potassium hydroxide, ferric chloride, or aminodiacetic acid.

[0065] According to an embodiment of the present invention, after providing a substrate layer 100 and fabricating a connection layer 500, the method of the present invention further includes the step of forming a first electrode layer 200 electrically connected to the connection layer 500. Specifically, this step includes forming the first electrode layer 200 on a first surface of the substrate layer 100 using at least one of a lift-off process, a photolithography-IBE etching process, and a metal etching process, and connecting the first electrode layer 200 to the connection layer 500. In a specific embodiment, it is preferable that each first electrode in the first electrode layer 200 is connected to the connection layer 500.

[0066] Furthermore, in a specific embodiment, when the substrate layer 100 does not have a via structure and the connecting layer 500 forms a conductive trace structure on the surface of the substrate layer 100, the method further includes the step of setting a terminal 600. Specifically, one or more terminals 600 can be set at the edge of the substrate layer 100, and the end of the wire trace that is not connected to the first electrode layer 200 is connected to a terminal 600. However, it should be noted that a terminal 600 can be connected to multiple traces simultaneously. However, when the substrate layer 100 has a via structure and the connecting layer 500 penetrates the interior of the substrate layer 100 to form a conductive via structure, the method further includes the step of forming a third electrode layer 800. Specifically, a third electrode layer 800 can be formed on the second surface of the substrate layer 100, and the third electrode layer 800 is connected to the first electrode layer 200 through a conductive via.

[0067] According to an embodiment of the present invention, the method may further include the step of forming an auxiliary electrode layer 700 on the surface of the first electrode layer 200. Specifically, the auxiliary electrode layer 700 may be formed using at least one of a lift-off process, a photolithography-IBE etching process, and a metal etching process. Furthermore, it should be noted that the second electrode layer 400 of this application is made of Au, Al, and Ag, or a combination thereof. It can exist independently when the microcavity chip is in a non-operating state, and can cover the surface of the microcavity when the microcavity chip is in an operating state, forming a circulation path between the first electrode layer 200, the microcavity layer 300, and the second electrode layer 400 to detect minute changes occurring within the microcavity.

[0068] According to an embodiment of the present invention, the method further includes the step of forming a microcavity layer 300, which is located on the surface of the first electrode layer 200. When an auxiliary electrode layer 700 is present, the microcavity layer 300 is located on the surface of the first electrode layer 200 and / or the auxiliary electrode layer 700. In a specific embodiment, the step of forming the microcavity layer 300 includes coating a material of the microcavity layer 300 onto the surface of the first electrode layer 200 and / or the auxiliary electrode layer 700, and then forming microcavities by photolithography, nanoimprinting, or a combination thereof, to obtain a microcavity layer 300 having multiple microcavities, thereby fabricating the microcavity chip of the present application.

[0069] In another aspect, the present invention provides the use of the above-described microcavity chip in the field of biomedicine.

[0070] According to embodiments of the present invention, the microcavity chip of this application has the advantages of high density and high throughput, and can be applied to high-sensitivity detection in large-scale, high-throughput biopharmaceutical industries. Specifically, it can be used for biosynthetic reactions, biomolecular characterization, and nucleotide detection or combinations thereof. More specifically, by integrating bioreactive substances, enzymes, or substrates into the microcavity chip of this application, the dynamic process of biosynthetic reactions can be monitored in real time, providing an important tool and platform for biosynthesis, enzyme-catalyzed reactions, etc. Furthermore, by immobilizing cells or specific biomolecules (such as proteins, antigens, antibodies, DNA molecules, polymer molecules, etc.) on the top, bottom, and / or sidewalls of the microcavity, the specialized design and high-density arrangement of the microcavity can achieve rapid and accurate detection, analysis, and characterization of biomolecules or cells. Additionally, by introducing specific sensors into the top, bottom, and / or sidewalls of the microcavity, high-throughput detection of target substances can be achieved.

[0071] Example

[0072] The microcavity chip proposed in this invention will be described in detail below through specific embodiments. Unless otherwise specified, the methods used in the following embodiments are conventional methods, and the reagents used are commercially available unless otherwise specified.

[0073] Example 1

[0074] This embodiment utilizes the method of the present invention to prepare a microcavity chip, and uses the obtained microcavity chip to generate electrochemical sensing related to electron transfer during material reactions. In this embodiment, the substrate layer 100 is a silicon substrate layer, the interconnect layer 500 is made of Cu, the first electrode layer 200 is made of Au, the auxiliary electrode layer 700 is made of Pt (platinum), and the microcavity layer 300 is made of Su8.

[0075] 1. Fabrication of a microcavity chip: A silicon oxide layer is deposited on the surface of a silicon wafer 10 by deposition to obtain a silicon substrate layer. The interconnect layer 500 is formed on the surface of the silicon substrate layer using the material of the interconnect layer 500 through a lift-off process. The first electrode layer 200 is formed on the surface of the interconnect layer 500 using the material of the first electrode layer 200 through a lift-off process. The auxiliary electrode layer 700 is formed on the surface of the first electrode layer 200 using the material of the auxiliary electrode layer 700 through a lift-off process. The material of the microcavity layer 300 is coated on the surface of the auxiliary electrode layer 700, and the microcavity layer 300 is formed on the surface of the auxiliary electrode layer 700 by a photolithography process.

[0076] Example 2

[0077] This embodiment utilizes the method of the present invention to prepare a microcavity chip, and uses the obtained microcavity chip for DNA sequence-related electrochemical sensing.

[0078] In this embodiment, the substrate layer 100 is a silicon substrate layer, the interconnect layer 500 is made of Cu, the first electrode layer 200 is made of Au, the third electrode layer 800 is made of Au, the auxiliary electrode layer 700 is made of Ag, and the microcavity layer 300 is made of Su8.

[0079] 1. Fabrication of microcavity chips: such as Figure 10 As shown, firstly, a via structure is etched on the surface of silicon wafer 10 using photolithography, and then a silicon oxide layer is grown using a thermal oxidation process to obtain a silicon substrate layer. A metal material layer is deposited on the surface of the silicon substrate layer, and the metal material layer is filled with vias by electroplating to form a connection layer 500. The connection layer 500 is then processed using a CMP planarization process. The first electrode layer 200 is formed on the first surface of the substrate layer 100 using the material of the first electrode layer 200 through a lift-off process. The third electrode layer 800 is formed on the second surface of the substrate layer 100 using the material of the third electrode layer 800 through a lift-off process. The auxiliary electrode layer 700 is formed on the surface of the first electrode layer 200 using the material of the auxiliary electrode layer 700 through a lift-off process. The material of the microcavity layer 300 is coated on the surface of the auxiliary electrode layer 700, and the microcavity layer 300 is formed on the surface of the auxiliary electrode layer 700 using a photolithography process.

[0080] Example 3

[0081] This embodiment utilizes the method of the present invention to fabricate a microcavity chip, wherein the microcavities in the microcavity array involve beveled openings. The resulting microcavity chip can capture and detect single cells.

[0082] In this embodiment, the substrate layer 100 is an AF32 glass substrate layer, the connecting layer 500 is made of Cu, the first electrode layer 200 is made of Au, the third electrode layer 800 is made of Au, the auxiliary electrode layer 700 is made of Ag, and the microcavity layer 300 is made of Su8.

[0083] 1. Fabrication of microcavity chips: such as Figure 11As shown, firstly, AF32 glass 20 is modified by laser to form a through-hole structure. The through-hole is etched using an etchant to obtain a glass substrate layer with a through-hole structure. A metal material layer is deposited on the surface of the glass substrate layer. The metal material layer is then electroplated to fill the through-hole to form a connection layer 500. The connection layer 500 is then processed using a CMP planarization process. The first electrode layer 200 is formed on the surface of the connection layer 500 using the material of the first electrode layer 200 through a lift-off process. The third electrode layer 800 is formed on the second surface of the substrate layer 100 using the material of the third electrode layer 800 through a lift-off process. The auxiliary electrode layer 700 is formed on the surface of the first electrode layer 200 using the material of the auxiliary electrode layer 700 through a lift-off process. The material of the microcavity layer 300 is coated on the surface of the auxiliary electrode layer 700, and the microcavity layer 300 is formed on the surface of the auxiliary electrode layer 700 through a photolithography process.

[0084] Example 4

[0085] This embodiment utilizes the method of the present invention to fabricate a microcavity chip, wherein the microcavity array design is performed with the diameter of the microcavities decreasing.

[0086] In this embodiment, the substrate layer 100 is a polymer substrate layer (Su8), the connecting layer 500 is made of Cu, the first electrode layer 200 is made of Au, the third electrode layer 800 is made of Au, the auxiliary electrode layer 700 is made of Ag, and the microcavity layer 300 is made of Su8.

[0087] 1. Fabrication of microcavity chips: such as Figure 12 As shown, firstly, a sacrificial layer 30 is deposited on silicon wafer 10. The material of the polymer substrate layer is coated onto the surface of the sacrificial layer, and a through-hole structure is formed using photolithography to obtain a polymer substrate layer with a through-hole structure. A metal material layer is deposited on the surface of the polymer substrate layer with through-holes, and the metal material layer is electroplated to fill the through-holes to form a connection layer 500. The connection layer 500 is then processed using a CMP planarization process. A barrier film is then covered on the surface of the polymer substrate layer with the connection layer 500 embedded. Finally, the sacrificial layer is etched using an etching solution, and the substrate layer with the connection layer 500 is obtained. A polymer substrate layer; the first electrode layer 200 is formed on the surface of the interconnect layer 500 using the material of the first electrode layer 200 through a lift-off process; the third electrode layer 800 is formed on the second surface of the substrate layer 100 using the material of the third electrode layer 800 through a lift-off process; the auxiliary electrode layer 700 is formed on the surface of the first electrode layer 200 using the material of the auxiliary electrode layer 700 through a lift-off process; the material of the microcavity layer 300 is coated on the surface of the auxiliary electrode layer 700, and the microcavity layer 300 is formed on the surface of the auxiliary electrode layer 700 through a photolithography process.

[0088] In summary, the microcavity chip proposed in this invention has a highly insulating substrate layer, which can reduce signal interference caused by the electric field to the microcavity; it can use glass and polymer as substrate layers, eliminating the need to prepare an insulating layer, thereby reducing costs, power consumption, and improving chip efficiency; the high microcavity packing density can increase throughput, save space, reduce costs, and better achieve miniaturization.

[0089] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or basic characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects.

[0090] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A microcavity chip, characterized in that, The microcavity chip includes a substrate layer, a first electrode layer, a second electrode layer, and a microcavity layer; The first electrode layer is located on a first surface of the substrate layer, and the first electrode layer has a plurality of first electrodes; The microcavity layer is located on the surface of the first electrode layer and has a plurality of microcavities, each of the microcavities at least covering a portion of the first electrode; The second electrode layer is located on the side of the microcavity layer opposite to the substrate layer and is in contact with the microcavity. The second electrode layer has at least one second electrode.

2. The microcavity chip according to claim 1, characterized in that, The substrate layer includes at least one of a silicon substrate layer, a glass substrate layer, and a polymer substrate layer.

3. The microcavity chip according to claim 1, characterized in that, It further includes a connection layer; The interconnect layer is located on a first surface of the substrate layer and has conductive traces; or... The connecting layer has a conductive via penetrating the substrate layer; The connecting layer is connected to the first electrode layer.

4. The microcavity chip according to claim 3, characterized in that, It further includes a third electrode layer; The third electrode layer is located on the second surface of the substrate layer. The third electrode layer has a plurality of third electrodes, and the third electrodes are connected to the first electrode through the conductive vias penetrating the substrate layer.

5. The microcavity chip according to claim 4, characterized in that, The system further includes an auxiliary electrode layer having at least one auxiliary electrode, the auxiliary electrode layer being located between the microcavity layer and the first electrode layer, and being in contact with both the microcavity layer and the first electrode layer respectively; Each of the microcavities covers at least a portion of the auxiliary electrode.

6. The microcavity chip according to claim 5, characterized in that, At least one of the following conditions must be met: The material of the conductive traces or conductive vias forming the interconnect layer includes at least one of Cu, Au, and Ni; The materials forming the first electrode, the second electrode, the third electrode, and the auxiliary electrode each independently include at least one of Au, Al, and Ag, and preferably, the material forming the auxiliary electrode is Ag; The material forming the microcavity layer includes a polymer material, and the polymer material includes at least one of SU8 and PI.

7. The microcavity chip according to claim 1, characterized in that, In the microcavity layer, a plurality of microcavities are arranged in an array, and the openings of the microcavities include at least one of a plane, a single inclined plane, and a double inclined plane; Preferably, the opening of the microcavity is a single inclined plane and / or a double inclined plane, wherein the angle between the inclined plane and the plane at the bottom of the microcavity layer is 0-90°, excluding 0° and 90°, and preferably 30-60°.

8. The microcavity chip according to claim 7, characterized in that, At least one of the following conditions must be met: The height of the microcavity is 1-100 μm; The cross-sectional width of the microcavity is 1-100 μm; The aspect ratio of the microcavity is 0.1-100.

9. The microcavity chip according to claim 7, characterized in that, The opening, bottom, and / or sidewalls of the microcavity are covered with a membrane.

10. The microcavity chip according to claim 7, characterized in that, The surfaces of the first electrode and / or auxiliary electrode that are in contact with the microcavity have surface modifications.

11. A method for preparing a microcavity chip according to any one of claims 1-10, characterized in that, The method includes: Provide a substrate layer; A first electrode layer is formed on the substrate layer; A microcavity layer is formed on the first electrode layer; and A second electrode layer is provided.

12. The method according to claim 11, characterized in that, The step further includes forming the connection layer, the step comprising at least one of the following: The interconnect layer is located on the first surface of the substrate layer and is formed on the first surface of the substrate layer by at least one of lift-off process, photolithography-IBE etching process and metal etching process. or, The connecting layer is embedded inside the substrate layer. A metal material layer is deposited on the first surface of the substrate layer with through holes. The metal material layer is filled with through holes by electroplating to form the connecting layer. The connecting layer is then processed using a CMP planarization process.

13. The method according to claim 11, characterized in that, When the substrate layer is a polymer substrate layer, the method includes the step of forming a bonding layer while providing the substrate layer, the step including: A sacrificial layer is deposited on a silicon substrate, the material of the polymer substrate layer is coated on the surface of the sacrificial layer, and a through-hole structure is formed by photolithography to form the polymer substrate layer. A metal material layer is deposited on the surface of the polymer substrate layer with through holes, and the metal material layer is filled with through holes by electroplating to form the connection layer. The connection layer is then processed using a CMP planarization process. A barrier film is covered on the surface of the polymer substrate with the connecting layer embedded, and then the sacrificial layer is etched with an etching solution to obtain the polymer substrate with the connecting layer.

14. The use of the microcavity chip according to any one of claims 1-10 for non-diagnostic purposes in the biomedical field; optionally, the use includes at least one of biosynthetic reactions, biomolecular characterization, and nucleotide detection.

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