Field effect transistor aging test screening system and method

Abstract

The invention discloses a field effect transistor aging test screening system and method, and relates to the technical field of field effect transistor test.The system comprises a micro-control module, three sets of field effect transistors connected with a field effect transistor module are driven in sequence, an aging detection module detects the aging degree of the field effect transistors in the driving state, and meanwhile when driving starts, the field effect transistors in the field effect transistor module are subjected to aging test; the turn-on detection module is used for timing and detecting the turn-on delay state of the field-effect tubes, when the aged field-effect tubes are not detected to end at the turn-on delay stage, the energy storage size of the normal field-effect tubes is used as a timing basis, and when the other field-effect tubes are subjected to driving control, the energy storage size of the normal field-effect tubes is used as a timing basis; whether the turn-on delay time of other field effect transistors is in a normal state can be detected through the error detection module. According to the field-effect tube aging test screening system and the field-effect tube aging test screening method, aging detection can be automatically and sequentially carried out on the field-effect tubes, the detection means is simple, and software timing and turn-on delay time detection on the field-effect tubes are not needed.

Description

Technical Field

[0001] This invention relates to the field of field-effect transistor (FET) testing technology, specifically a field-effect transistor aging test screening system and method. Background Technology

[0002] A field-effect transistor (FET) is a semiconductor device that uses the electric field effect of the input circuit to control the current in the output circuit. In order to detect the aging of multiple FETs at once, relevant personnel use relevant aging test instruments to perform aging tests on the FETs in sequence. The test method is complex and cumbersome, and it also requires relevant software programs to detect the turn-on delay time of the FETs. Therefore, it needs to be improved. Summary of the Invention

[0003] This invention provides a field-effect transistor aging test screening system and method to solve the problems mentioned in the background art.

[0004] According to an embodiment of the present invention, a field-effect transistor aging test screening system is provided, comprising: The field-effect transistor module is connected to the microcontroller module and is used to receive the first drive signal, the second drive signal and the third drive signal output by the microcontroller module and drive the three sets of field-effect transistors connected in sequence. The aging detection module is connected to the field-effect transistor module and is used to extract the saturation on-state voltage drop of the conducting field-effect transistors in the three groups of field-effect transistors. When the saturation on-state voltage drop is greater than the aging threshold, the first aging signal is output. The activation detection module is connected to the field-effect transistor module and the aging detection module. It is used to start energy storage when it receives the first drive signal, the second drive signal or the third drive signal. It samples the current of the field-effect transistor in the driving state among the three groups of field-effect transistors. When the sampled signal is greater than the set activation detection threshold, the activation delay stage of the field-effect transistor in the driving state ends and the first activation signal is output and the energy storage operation is stopped. It samples and holds the stored energy and outputs the first sampling signal. When the first activation signal is output and the first aging signal is not received, the first detection signal is output. The error detection module, connected to the power-on detection module, is used to subtract and perform absolute value processing on the first sampling signal and the electrical energy stored in real time by the power-on detection module, and outputs the second aging signal when the processed signal is greater than the set error threshold. The microcontroller module, connected to the aging detection module, the power-on detection module, and the error detection module, is used to sequentially output a first drive signal, a second drive signal, and a third drive signal. It controls the power-on detection module to sample the stored electrical energy, receive the first aging signal and record the aging process. When the first detection signal is received for the first time, it controls the power-on detection module to perform sample-and-hold processing. When the first power-on signal is received subsequently, it controls the error detection module to receive the electrical energy stored in real time by the power-on detection module and to receive the second aging signal output by the error detection module.

[0005] As a further embodiment of the present invention: the field-effect transistor module includes a first field-effect transistor interface, a second field-effect transistor interface and a third field-effect transistor interface; the microcontroller module includes a first controller; the turn-on detection module includes a first inductor, a first resistor, a first capacitor, a first comparator and a first reference power supply; Preferably, the input terminal of the first field-effect transistor interface is connected to the input terminals of the second and third field-effect transistor interfaces. The output terminal of the first field-effect transistor interface is connected to the output terminals of the second and third field-effect transistor interfaces and the first terminal of the first inductor. It is connected to the non-inverting terminal of the first comparator and one terminal of the first capacitor through the first resistor. The other terminal of the first capacitor is connected to the second terminal of the first inductor and ground. The inverting terminal of the first comparator is connected to the first reference power supply. The output terminal of the first comparator is connected to the IO9 terminal of the first controller. The driving terminals of the first, second, and third field-effect transistor interfaces are respectively connected to the IO1, IO2, and IO3 terminals of the first controller.

[0006] As a further embodiment of the present invention: the activation detection module further includes a first diode, a second diode, a third diode, a fourth capacitor, a sixth resistor, a first switching transistor, a second switching transistor, a second voltage regulator, a fifth capacitor, and a sample-and-hold circuit; Preferably, the anodes of the first diode, the second diode, and the third diode are connected to the IO1, IO2, and IO3 terminals of the first controller, respectively. The cathode of the first diode is connected to the cathodes of the second and third diodes and one end of the fourth capacitor, and is connected to the base of the second switch and the collector of the first switch through a sixth resistor. The collector of the second switch is connected to the second voltage regulator. The emitter of the second switch is connected to the input terminal of the sample-and-hold circuit, and is connected to the emitter of the first switch, the other end of the fourth capacitor, and ground through a fifth capacitor. The base of the first switch is connected to the output terminal of the first comparator. The control terminal of the sample-and-hold circuit is connected to the IO6 terminal of the first controller.

[0007] As a further embodiment of the present invention: the aging detection module includes a first voltage regulator, a second resistor, an eighth diode, a third resistor, a second capacitor, a third capacitor, a fifth resistor, a fourth diode, a fifth diode, a sixth diode, a seventh diode, a fourth resistor, a first operational amplifier, a second comparator, and a second reference power supply; Preferably, the anode of the eighth diode is connected to the anode of the sixth diode and the non-inverting input of the first operational amplifier, and is connected to the first voltage regulator and one end of the fourth resistor through the second resistor. The other end of the fourth resistor is connected to the inverting input of the first operational amplifier and the anode of the seventh diode. The cathode of the sixth diode is connected to the anode of the fourth diode, one end of the fifth resistor, one end of the third capacitor, one end of the second capacitor, and the cathode of the eighth diode, the other end of the second capacitor, and the input terminal of the first field-effect transistor interface through the third resistor. The cathode of the seventh diode is connected to the anode of the fifth diode, the other end of the fifth resistor, the other end of the third capacitor, and ground. The cathode of the fourth diode is connected to the cathode of the fifth diode. The output terminal of the first operational amplifier is connected to the non-inverting input of the second comparator. The inverting input of the second comparator is connected to the second reference power supply. The output terminal of the second comparator is connected to the IO4 terminal of the first controller.

[0008] As a further embodiment of the present invention: the activation detection module further includes a first inverter and a first logic unit; Preferably, the input terminal of the first inverter is connected to the output terminal of the second comparator, the output terminal of the first inverter is connected to the A terminal of the first logic device, the B terminal of the first logic device is connected to the output terminal of the first comparator, and the Y terminal of the first logic device is connected to the IO5 terminal of the first controller.

[0009] As a further embodiment of the present invention: the error detection module includes a first analog switch, a subtraction processor, a third comparator, and a third reference power supply; Preferably, the third terminal of the first analog switch is connected to the input terminal of the sample-and-hold circuit, the first input terminal of the subtraction processor is connected to the output terminal of the sample-and-hold circuit, the fourth terminal of the first analog switch is connected to the second input terminal of the subtraction processor, the output terminal of the subtraction processor is connected to the non-inverting terminal of the third comparator, the inverting terminal of the third comparator is connected to the third reference power supply, and the fifth terminal of the first analog switch and the output terminal of the third comparator are respectively connected to the IO7 and IO8 terminals of the first controller.

[0010] Furthermore, to achieve the above objectives, this invention also proposes a field-effect transistor (FET) aging test screening method, which is applied to the aforementioned FET aging test screening system. The steps of the method include: The three sets of field-effect transistors in the driving field-effect transistor module are turned on sequentially; Acquire the aging status of the field-effect transistor when it is in conduction as detected by the aging detection module and record the aging status; At the start of the drive, the turn-on detection module is controlled to store energy, acquire the turn-on delay end information of the field-effect transistor detected by the turn-on detection module, record the state of the field-effect transistor, and control the turn-on detection module to perform sampling and holding processing on the stored electrical energy. The control error detection module performs error processing based on the sampled and held signal and the real-time stored power voltage, and obtains the error of the turn-on delay time of the three sets of field-effect transistors detected by the error detection module, and records the aging process.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: The field-effect transistor aging test screening system and method of the present invention can sequentially drive three groups of field-effect transistors connected to the field-effect transistor module through a micro-control module. The aging detection module detects the aging degree of the field-effect transistors in the driving state by comparing the saturation conduction voltage drop with the aging threshold voltage. At the same time, at the start of driving, the turn-on detection module uses energy storage to time and detect the turn-on delay state of the field-effect transistors in the driving state. When the turn-on delay stage of the field-effect transistor that has not been detected for aging ends, the energy storage size of the normal field-effect transistor is used as the timing basis. When driving and controlling the remaining field-effect transistors, the error detection module can detect whether the turn-on delay time of the remaining field-effect transistors is in a normal state. The aging test of the field-effect transistors can be automatically performed sequentially, and the detection method is simple, without the need for software timing and turn-on delay time detection of the field-effect transistors. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic block diagram of a field-effect transistor aging test screening system provided in an embodiment of the present invention.

[0014] Figure 2 The circuit diagram is provided for a field-effect transistor aging test screening system according to an embodiment of the present invention.

[0015] Figure 3 The circuit diagram is provided for the error detection module in an embodiment of the present invention.

[0016] Figure 4 This is a flowchart of a field-effect transistor aging test screening method provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In one embodiment, see Figure 1 A field-effect transistor aging test screening system, comprising: The field-effect transistor module 1 is connected to the microcontroller module 5 and is used to receive the first drive signal, the second drive signal and the third drive signal output by the microcontroller module 5 and drive the three sets of field-effect transistors connected in sequence. The aging detection module 2 is connected to the field-effect transistor module 1 and is used to extract the saturation conduction voltage drop of the conducting field-effect transistors in the three groups of field-effect transistors. When the saturation conduction voltage drop is greater than the aging threshold, the first aging signal is output. The activation detection module 3 is connected to the field-effect transistor module 1 and the aging detection module 2. It is used to start energy storage when it receives the first drive signal, the second drive signal or the third drive signal. It samples the current of the field-effect transistors in the drive state among the three groups of field-effect transistors. When the sampled signal is greater than the set activation detection threshold, the activation delay stage of the field-effect transistor in the drive state ends and the first activation signal is output and the energy storage work is stopped. It samples and holds the stored energy and outputs the first sampling signal. When the first activation signal is output and the first aging signal is not received, the first detection signal is output. Error detection module 4, connected to power-on detection module 3, is used to subtract and perform absolute value processing on the first sampling signal and the electrical energy stored in real time by power-on detection module 3, and outputs a second aging signal when the processed signal is greater than the set error threshold. The microcontroller module 5 is connected to the aging detection module 2, the power-on detection module 3, and the error detection module 4. It is used to output the first drive signal, the second drive signal, and the third drive signal in sequence, control the power-on detection module 3 to sample the stored electrical energy, receive the first aging signal and record the aging process, control the power-on detection module 3 to perform sample-and-hold processing when the first detection signal is received for the first time, and control the error detection module 4 to receive the electrical energy stored in real time by the power-on detection module 3 and receive the second aging signal output by the error detection module 4 when the first detection signal is received thereafter.

[0019] In a specific embodiment, the aforementioned field-effect transistor module 1 can be a field-effect transistor circuit composed of field-effect transistor interfaces, connected to three sets of field-effect transistors, but is not limited to three sets of field-effect transistor interfaces; the aforementioned aging detection module 2 can be an aging detection circuit composed of diodes, resistors, operational amplifiers, comparators, etc. When the three sets of field-effect transistors are off, it divides and reverses the voltage of the input field-effect transistor module 1, stops sampling, and when the three sets of field-effect transistors are in a conducting state, it outputs a voltage proportional to the saturation conduction voltage drop through a differential amplifier, and then extracts the saturation conduction voltage drop of the conducting field-effect transistors in the three sets of field-effect transistors, and performs aging judgment by comparing the voltage magnitude of the set aging threshold with the voltage magnitude of the saturation conduction voltage drop; the aforementioned turn-on detection module 3 can be a turn-on detection circuit composed of inductors, resistors, comparators, transistors, sample-and-hold circuits, etc., which can perform energy storage work at the start of driving, sample the current of the field-effect transistors in the driving state, and detect the end state of the turn-on delay stage by the set turn-on detection threshold. After the delay phase ends, the energy storage function stops and the stored electrical energy voltage is sampled and held. The energy storage rate remains constant during the energy storage process. Therefore, the sampled and held stored electrical energy voltage can be used as a timing reference to provide a basis for error judgment by the error detection module 4. The turn-on detection threshold serves as the basis for the end of the turn-on delay time. The error detection module 4 can be an error detection circuit composed of a subtraction processor, analog switch, comparator, etc. When the turn-on detection module 3 is performing sample-and-hold operation, it subtracts the electrical energy voltage re-stored by the turn-on detection module 3 from the voltage output of the sample-and-hold operation and performs absolute value processing. The processed signal is then compared with the set error threshold to detect whether the turn-on delay time of the other field-effect transistors is similar to the turn-on delay time of the normal field-effect transistors. The microcontroller module 5 can be a microcontroller circuit composed of a single-chip microcomputer, which integrates many components such as an arithmetic unit, a controller, a memory, and input / output devices to realize functions such as signal processing, data storage, module control, and timing control.

[0020] In this embodiment, please refer to Figure 2 and Figure 3 The field-effect transistor module 1 includes a first field-effect transistor interface, a second field-effect transistor interface, and a third field-effect transistor interface; the microcontroller module 5 includes a first controller U1; the turn-on detection module 3 includes a first inductor L1, a first resistor R1, a first capacitor C1, a first comparator A1, and a first reference power supply VF1; Specifically, the input terminal of the first field-effect transistor interface is connected to the input terminals of the second and third field-effect transistor interfaces. The output terminal of the first field-effect transistor interface is connected to the output terminals of the second and third field-effect transistor interfaces and the first terminal of the first inductor L1. It is connected to the non-inverting terminal of the first comparator A1 and one terminal of the first capacitor C1 through the first resistor R1. The other terminal of the first capacitor C1 is connected to the second terminal of the first inductor L1 and the ground terminal. The inverting terminal of the first comparator A1 is connected to the first reference power supply VF1. The output terminal of the first comparator A1 is connected to the IO9 terminal of the first controller U1. The driving terminals of the first, second, and third field-effect transistor interfaces are respectively connected to the IO1, IO2, and IO3 terminals of the first controller U1.

[0021] In a specific embodiment, the input terminals of the first, second, and third field-effect transistor interfaces are all connected to a set of DC regulated voltages required for testing, and the first, second, and third field-effect transistor interfaces are connected to three sets of field-effect transistors; the first controller U1 can be an STM32 microcontroller; the first inductor L1, the first resistor R1, and the first capacitor C1 are used for current sampling; the first comparator A1 can be an LM358 comparator; and the first reference power supply VF1 can provide an on-state detection threshold.

[0022] Furthermore, the activation detection module 3 also includes a first diode D1, a second diode D2, a third diode D3, a fourth capacitor C4, a sixth resistor R6, a first switch V1, a second switch V2, a second voltage regulator VCC2, a fifth capacitor C5, and a sample-and-hold circuit; Specifically, the anodes of the first diode D1, the second diode D2, and the third diode D3 are connected to the IO1, IO2, and IO3 terminals of the first controller U1, respectively. The cathode of the first diode D1 is connected to the cathodes of the second diode D2 and the third diode D3, and one end of the fourth capacitor C4, and is connected to the base of the second switch V2 and the collector of the first switch V1 through the sixth resistor R6. The collector of the second switch V2 is connected to the second voltage regulator VCC2. The emitter of the second switch V2 is connected to the input terminal of the sample-and-hold circuit, and is connected to the emitter of the first switch V1, the other end of the fourth capacitor C4, and ground through the fifth capacitor C5. The base of the first switch V1 is connected to the output terminal of the first comparator A1. The control terminal of the sample-and-hold circuit is connected to the IO6 terminal of the first controller U1.

[0023] In a specific embodiment, both the first switching transistor V1 and the second switching transistor V2 can be NPN transistors; the fifth capacitor C5 can be an energy storage capacitor, which is stabilized and controlled by the second voltage regulator VCC2 when the second switching transistor V2 is turned on; the sample-and-hold circuit can be composed of an operational amplifier, an analog switch, a capacitor, a resistor, and a diode. When the control terminal of the sample-and-hold circuit is high, real-time signal sampling is performed, and when the control terminal is low, the sample-and-hold process is completed.

[0024] Furthermore, the aging detection module 2 includes a first regulated power supply VCC1, a second resistor R2, an eighth diode D8, a third resistor R3, a second capacitor C2, a third capacitor C3, a fifth resistor R5, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, a fourth resistor R4, a first operational amplifier OP1, a second comparator A2, and a second reference power supply VCC2. Specifically, the anode of the eighth diode D8 is connected to the anode of the sixth diode D6 and the non-inverting input of the first operational amplifier OP1, and is connected to the first voltage regulator VCC1 and one end of the fourth resistor R4 through the second resistor R2. The other end of the fourth resistor R4 is connected to the inverting input of the first operational amplifier OP1 and the anode of the seventh diode D7. The cathode of the sixth diode D6 is connected to the anode of the fourth diode D4, one end of the fifth resistor R5, one end of the third capacitor C3 and one end of the second capacitor C2, and is connected to the cathode of the eighth diode D8, the other end of the second capacitor C2 and the input terminal of the first field-effect transistor interface through the third resistor R3. The cathode of the seventh diode D7 is connected to the anode of the fifth diode D5, the other end of the fifth resistor R5, the other end of the third capacitor C3 and ground. The cathode of the fourth diode D4 is connected to the cathode of the fifth diode D5. The output terminal of the first operational amplifier OP1 is connected to the non-inverting input of the second comparator A2. The inverting input of the second comparator A2 is connected to the second reference power supply VCC2. The output terminal of the second comparator A2 is connected to the IO4 terminal of the first controller U1.

[0025] In a specific embodiment, the third resistor R3, the second capacitor C2, the third capacitor C3, and the fifth resistor R5 can be used for voltage division; the sixth diode D6, the fourth diode D4, the fifth diode D5, and the seventh diode D7 can be used for reverse bias and protection when the three sets of field-effect transistors are off, and for clamping and sampling when the three sets of field-effect transistors are on; the first operational amplifier OP1 can be an OP07 operational amplifier; the second comparator A2 can be an LM358 comparator, and the second reference power supply VCC2 provides the aging threshold.

[0026] Furthermore, the activation detection module 3 also includes a first inverter INV1 and a first logic unit J1; Specifically, the input terminal of the first inverter INV1 is connected to the output terminal of the second comparator A2, the output terminal of the first inverter INV1 is connected to the A terminal of the first logic device J1, the B terminal of the first logic device J1 is connected to the output terminal of the first comparator A1, and the Y terminal of the first logic device J1 is connected to the IO5 terminal of the first controller U1.

[0027] In a specific embodiment, the first inverter INV1 can be a NOT gate; the first logic unit J1 can be an AND gate.

[0028] Furthermore, the error detection module 4 includes a first analog switch U2, a subtraction processor, a third comparator A3, and a third reference power supply VF3; Specifically, the third terminal of the first analog switch U2 is connected to the input terminal of the sample-and-hold circuit, the first input terminal of the subtraction processor is connected to the output terminal of the sample-and-hold circuit, the fourth terminal of the first analog switch U2 is connected to the second input terminal of the subtraction processor, the output terminal of the subtraction processor is connected to the non-inverting input of the third comparator A3, the inverting input of the third comparator A3 is connected to the third reference power supply VF3, and the fifth terminal of the first analog switch U2 and the output terminal of the third comparator A3 are respectively connected to the IO7 and IO8 terminals of the first controller U1.

[0029] In a specific embodiment, the first analog switch U2 can be a CD4066 chip; the subtraction processor can be composed of a subtractor and an absolute value device; the third comparator A3 can be an LM358 comparator; and the third reference power supply VF3 provides an error threshold.

[0030] In this embodiment, please refer to Figure 4 The present invention also proposes a field-effect transistor (FET) aging test screening method, which is applied to the above-mentioned FET aging test screening system. The steps of the method include: S100, the three sets of field-effect transistors in the driving field-effect transistor module are turned on in sequence; S200: Obtain the aging status of the field-effect transistor when it is in conduction as detected by the aging detection module and record the aging status. S300: At the start of the drive, control the turn-on detection module to store energy, obtain the turn-on delay end information of the field-effect transistor detected by the turn-on detection module, record the state of the field-effect transistor, and control the turn-on detection module to perform sampling and holding processing on the stored electrical energy. The S400 control error detection module performs error processing based on the sampled and held signal and the real-time stored power voltage, and obtains the error of the turn-on delay time of the three sets of field-effect transistors detected by the error detection module, and records the aging process.

[0031] The working principle of the field-effect transistor (FET) aging test screening system of the present invention is as follows: A first FET interface, a second FET interface, and a third FET interface are respectively connected to three sets of FETs. A first drive signal, a second drive signal, and a third drive signal are sequentially output from the IO1, IO2, and IO3 terminals of a first controller U1. Specifically, when the first drive signal is output from the IO1 terminal of the first controller U1 and drives the FET connected to the first FET interface, the second switch V2 is triggered to conduct through the third diode D3, the fourth capacitor C4, and the sixth resistor R6. The fifth capacitor C5 stores the electrical energy provided by the second voltage regulator VCC2. The IO6 terminal of the first controller U1 controls the sample-and-hold circuit to charge the electrical energy in the fifth capacitor C5. The voltage is sampled in real time, while the first inductor L1, the first resistor R1, and the first capacitor C1 sample the current. The first comparator A1, in conjunction with the first reference power supply VF1, detects the end of the turn-on delay. The first operational amplifier OP1, in conjunction with the first voltage regulator VCC1, the second resistor R2, the eighth diode D8, the third resistor R3, the second capacitor C2, the third capacitor C3, the fifth resistor R5, the fourth diode D4, the fifth diode D5, the sixth diode D6, the seventh diode D7, and the fourth resistor R4, extracts the saturation conduction voltage drop of the conducting field-effect transistors in the three groups. When the saturation conduction voltage drop is not greater than the aging threshold, it indicates that the field-effect transistor connected to the first field-effect transistor interface is normal. After the turn-on delay stage ends, the first comparator A1... 1. A high-level output, i.e., the first turn-on signal, triggers the first switching transistor V1 to conduct. Simultaneously, the first inverter INV1 and the first logic unit J1 provide a high-level output to the I05 terminal of the first controller U1, i.e., the first detection signal. This allows the first controller U1 to know that the field-effect transistor is normal and the turn-on delay stage has ended. The I06 terminal of the first controller U1 will then cease operation. The sample-and-hold circuit will hold the sampled signal and output the first sampled signal, which serves as the error detection basis for the error detection module 4. Next, the I02 terminal of the first controller U1 will output the second drive signal and drive the field-effect transistor connected to the second field-effect transistor interface. Similarly, aging detection is performed by the aging detection module 2, and the turn-on delay stage end detection is performed by the turn-on detection module 3. After the turn-on delay phase ends, the IO7 pin of the first controller U1 controls the first analog switch U2 to turn on, causing the voltage stored in the fifth capacitor C5 to be subtracted from the signal voltage sampled and held by the sample-and-hold circuit, and the absolute value is processed. When the processed signal is greater than the error threshold, the third comparator A3 outputs a second aging signal, which is received by the IO8 pin of the first controller U1. Similarly, the field-effect transistors connected to the third field-effect transistor interface are driven and detected by driving and detecting the second field-effect transistor interface. If the saturation on-state voltage drop of the field-effect transistor connected to the first field-effect transistor interface is greater than the aging threshold, it indicates that the field-effect transistor is aging. The second comparator A2 outputs a first aging signal, which is received by the IO4 pin of the first controller U1.At this point, the first controller will drive the next field-effect transistor (FET) to find one whose saturation on-state voltage drop is less than the aging threshold, and then proceed with subsequent testing.

[0032] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0033] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A field-effect transistor aging test and screening system, characterized in that, The system includes: The field-effect transistor module is connected to the microcontroller module and is used to receive the first drive signal, the second drive signal and the third drive signal output by the microcontroller module and drive the three sets of field-effect transistors connected in sequence. The aging detection module is connected to the field-effect transistor module and is used to extract the saturation on-state voltage drop of the conducting field-effect transistors in the three groups of field-effect transistors. When the saturation on-state voltage drop is greater than the aging threshold, the first aging signal is output. The activation detection module is connected to the field-effect transistor module and the aging detection module. It is used to start energy storage when it receives the first drive signal, the second drive signal or the third drive signal. It samples the current of the field-effect transistor in the driving state among the three groups of field-effect transistors. When the sampled signal is greater than the set activation detection threshold, the activation delay stage of the field-effect transistor in the driving state ends and the first activation signal is output and the energy storage operation is stopped. It samples and holds the stored energy and outputs the first sampling signal. When the first activation signal is output and the first aging signal is not received, the first detection signal is output. The error detection module, connected to the power-on detection module, is used to subtract and perform absolute value processing on the first sampling signal and the electrical energy stored in real time by the power-on detection module, and outputs the second aging signal when the processed signal is greater than the set error threshold. The microcontroller module, connected to the aging detection module, the power-on detection module, and the error detection module, is used to sequentially output a first drive signal, a second drive signal, and a third drive signal. It controls the power-on detection module to sample the stored electrical energy, receive the first aging signal and record the aging process. When the first detection signal is received for the first time, it controls the power-on detection module to perform sample-and-hold processing. When the first power-on signal is received subsequently, it controls the error detection module to receive the electrical energy stored in real time by the power-on detection module and to receive the second aging signal output by the error detection module.

2. The field-effect transistor aging test and screening system according to claim 1, characterized in that, The field-effect transistor module includes a first field-effect transistor interface, a second field-effect transistor interface, and a third field-effect transistor interface; the microcontroller module includes a first controller; the turn-on detection module includes a first inductor, a first resistor, a first capacitor, a first comparator, and a first reference power supply. The input terminal of the first field-effect transistor interface is connected to the input terminals of the second and third field-effect transistor interfaces. The output terminal of the first field-effect transistor interface is connected to the output terminals of the second and third field-effect transistor interfaces and the first terminal of the first inductor. It is connected to the non-inverting terminal of the first comparator and one terminal of the first capacitor through the first resistor. The other terminal of the first capacitor is connected to the second terminal of the first inductor and ground. The inverting terminal of the first comparator is connected to the first reference power supply. The output terminal of the first comparator is connected to the IO9 terminal of the first controller. The driving terminals of the first, second, and third field-effect transistor interfaces are respectively connected to the IO1, IO2, and IO3 terminals of the first controller.

3. The field-effect transistor aging test and screening system according to claim 2, characterized in that, The power-on detection module also includes a first diode, a second diode, a third diode, a fourth capacitor, a sixth resistor, a first switching transistor, a second switching transistor, a second voltage regulator, a fifth capacitor, and a sample-and-hold circuit; The anodes of the first diode, the second diode, and the third diode are respectively connected to the IO1, IO2, and IO3 terminals of the first controller. The cathode of the first diode is connected to the cathodes of the second and third diodes and one end of the fourth capacitor, and is connected to the base of the second switch and the collector of the first switch through the sixth resistor. The collector of the second switch is connected to the second voltage regulator. The emitter of the second switch is connected to the input terminal of the sample-and-hold circuit, and is connected to the emitter of the first switch, the other end of the fourth capacitor, and ground through the fifth capacitor. The base of the first switch is connected to the output terminal of the first comparator. The control terminal of the sample-and-hold circuit is connected to the IO6 terminal of the first controller.

4. The field-effect transistor aging test and screening system according to claim 3, characterized in that, The aging detection module includes a first voltage regulator, a second resistor, an eighth diode, a third resistor, a second capacitor, a third capacitor, a fifth resistor, a fourth diode, a fifth diode, a sixth diode, a seventh diode, a fourth resistor, a first operational amplifier, a second comparator, and a second reference power supply. The anode of the eighth diode is connected to the anode of the sixth diode and the non-inverting input of the first operational amplifier, and is connected to the first voltage regulator and one end of the fourth resistor through the second resistor. The other end of the fourth resistor is connected to the inverting input of the first operational amplifier and the anode of the seventh diode. The cathode of the sixth diode is connected to the anode of the fourth diode, one end of the fifth resistor, one end of the third capacitor, one end of the second capacitor, and the cathode of the eighth diode, the other end of the second capacitor, and the input terminal of the first field-effect transistor interface through the third resistor. The cathode of the seventh diode is connected to the anode of the fifth diode, the other end of the fifth resistor, the other end of the third capacitor, and ground. The cathode of the fourth diode is connected to the cathode of the fifth diode. The output terminal of the first operational amplifier is connected to the non-inverting input of the second comparator. The inverting input of the second comparator is connected to the second reference power supply. The output terminal of the second comparator is connected to the IO4 terminal of the first controller.

5. The field-effect transistor aging test and screening system according to claim 4, characterized in that, The activation detection module further includes a first inverter and a first logic unit; The input terminal of the first inverter is connected to the output terminal of the second comparator, the output terminal of the first inverter is connected to the A terminal of the first logic device, the B terminal of the first logic device is connected to the output terminal of the first comparator, and the Y terminal of the first logic device is connected to the IO5 terminal of the first controller.

6. The field-effect transistor aging test and screening system according to claim 5, characterized in that, The error detection module includes a first analog switch, a subtraction processor, a third comparator, and a third reference power supply; The third terminal of the first analog switch is connected to the input terminal of the sample-and-hold circuit, the first input terminal of the subtraction processor is connected to the output terminal of the sample-and-hold circuit, the fourth terminal of the first analog switch is connected to the second input terminal of the subtraction processor, the output terminal of the subtraction processor is connected to the non-inverting terminal of the third comparator, the inverting terminal of the third comparator is connected to the third reference power supply, and the fifth terminal of the first analog switch and the output terminal of the third comparator are respectively connected to the IO7 and IO8 terminals of the first controller.

7. A method for screening field-effect transistors through aging tests, characterized in that, The method is applied to the field-effect transistor aging test screening system according to claims 1-6, and includes the following steps: The three sets of field-effect transistors in the driving field-effect transistor module are turned on sequentially; Acquire the aging status of the field-effect transistor when it is in conduction as detected by the aging detection module and record the aging status; At the start of the drive, the turn-on detection module is controlled to store energy, acquire the turn-on delay end information of the field-effect transistor detected by the turn-on detection module, record the state of the field-effect transistor, and control the turn-on detection module to perform sampling and holding processing on the stored electrical energy. The control error detection module performs error processing based on the sampled and held signal and the real-time stored power voltage, and obtains the error of the turn-on delay time of the three sets of field-effect transistors detected by the error detection module, and records the aging process.

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