Band-gap reference compensation circuit

Abstract

A band-gap reference compensation circuit relates to the technical field of integrated circuits and comprises a high-order temperature compensation MOS (metal oxide semiconductor) resistor array unit and a grid voltage generation unit of high-order temperature compensation MOS resistors, and the high-order temperature compensation MOS resistor array unit consists of at least two NMOS (N-channel metal oxide semiconductor) tubes which are connected in parallel. On the basis of the temperature characteristic of the base current of the BJT, the MOS resistor with the negative second-order temperature coefficient is generated, and the high-order nonlinearity, caused by process mismatch and deviation, of the band-gap reference voltage with the positive second-order temperature coefficient can be compensated by superposing the voltage drop of the resistor under the current to the output reference voltage. And the dependency of the high-precision reference voltage design on the process is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a compensation circuit for a bandgap reference with a positive second-order temperature coefficient. Background Technology

[0002] Reference voltages are indispensable components in circuits such as digital-to-analog converters (DACs), analog-to-digital converters (ADCs), switching regulators, linear regulators, temperature sensors, and rechargeable battery protection chips; they are crucial modules in analog integrated circuits. With the development of integrated circuits, the accuracy requirements for reference voltages are becoming increasingly stringent. The temperature coefficient of traditional bandgap reference voltages is approximately 20 ppm / ℃. However, if second-order temperature compensation is applied to the bandgap reference voltage, its temperature coefficient can reach 5 ppm / ℃ to 10 ppm / ℃. Under most process technologies, V... BE The second-order temperature coefficient is negative, and after first-order compensation, V REF The voltage curve is a downward-opening parabola. Existing literature on high-precision reference voltage designs often focuses on high-order compensation of the reference voltage in this scenario. However, during actual fabrication, due to significant process variations in CMOS technology, the performance parameters of BJT transistors deviate considerably from theoretical values, frequently resulting in V... BE The second-order temperature coefficient is positive, or due to a large mismatch introduced by the process or circuit structure, V after first-order compensation is negative. REF The voltage curve is an upward-opening parabola. However, high-order compensation designs for the reference voltage in this case are rarely mentioned in the literature.

[0003] Existing patents, such as CN202511451866.9 "A bandgap reference circuit and chip," mainly use a voltage generation module to generate a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient, and then generate a reference voltage with zero temperature coefficient based on the first and second voltages. CN202511333228.7 "A bandgap reference voltage source circuit with high-order compensation" designs a high-order compensation circuit that generates an IPTAT2 current through high-order compensation to offset the nonlinear temperature coefficient in the base-emitter voltage, thereby enabling the bandgap reference voltage source circuit with high-order compensation to have a low temperature coefficient. Summary of the Invention

[0004] The purpose of this invention is to propose a new circuit structure for the case where the second-order temperature coefficient is positive. This structure utilizes a MOS resistor with a negative second-order temperature coefficient to generate a voltage containing a higher-order term of temperature T under current, and then superimposes this voltage onto the output voltage to compensate for the higher-order nonlinearity of the bandgap reference voltage, thereby reducing the dependence of high-precision reference voltage design on the manufacturing process.

[0005] To achieve the above objectives, the technical solution adopted by this invention is: a bandgap reference compensation circuit, characterized in that: it includes a high-order temperature-compensated MOS resistor array unit, and a gate voltage generation unit for the high-order temperature-compensated MOS resistor connected to the high-order temperature-compensated MOS resistor array unit, wherein:

[0006] The gate voltage generation unit of the high-order temperature-compensated MOS resistor has a gate voltage output terminal for outputting a gate voltage V that is related to temperature T. A ;

[0007] The high-order temperature-compensated MOS resistor array unit consists of at least two NMOS transistors connected in parallel. The drain of each NMOS transistor is connected to the first-order bandgap junction, and the source of each NMOS transistor is grounded. The gate of one of the NMOS transistors is connected to the gate voltage V. A The gates of the remaining NMOS transistors are connected to the gate voltage output terminal through switches, which are turned on or off under the control of a control signal.

[0008] The gate voltage generation unit of the high-order temperature-compensated MOS resistor includes BJT transistors Q1 and Q2, resistors R1 and R2, PMOS transistors M0, M1, and M2, and NMOS transistor M3, wherein:

[0009] The source of PMOS transistor M0 is connected to the power supply VCC, the gate of M0 is connected to the drain of M0, and the drain of M0 is connected to the zero-temperature drift current source I0.

[0010] The source of PMOS transistor M1 is connected to the power supply VCC, the gate is connected to the gate of M1, and the drain is connected to the collector of Q1.

[0011] The source of PMOS transistor M2 is connected to power supply VCC, the gate is connected to the gate of M1, and the drain is connected to the collector of Q2.

[0012] The base of BJT transistor Q1 is connected to the collector of Q1, and the emitter of Q1 is grounded through resistor R1.

[0013] The base of BJT transistor Q2 is connected to the base of Q1, and the emitter of Q2 is grounded through resistor R2.

[0014] The source of NMOS transistor M3 is grounded, the drain is connected to the emitter of Q2, and the gate is connected to the collector of Q2.

[0015] The collector of Q2 serves as the output terminal of the gate voltage generation unit for the high-order temperature-compensated MOS resistor, outputting the gate voltage V. A .

[0016] Each NMOS transistor in the high-order temperature-compensated MOS resistor array unit has the same size as the NMOS transistor M3; the PMOS transistors M1 and M2 have the same size.

[0017] The beneficial effects of this invention are:

[0018] This invention utilizes the temperature characteristics of the base current of a BJT transistor to generate a MOS resistor with a negative second-order temperature coefficient. By superimposing the voltage drop across this resistor at current onto the output reference voltage, the high-order nonlinearity of the bandgap reference voltage, which has a positive second-order temperature coefficient due to process mismatches and deviations, can be compensated. The use of this compensation technique significantly reduces the dependence of high-precision reference voltage design on process technology. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the present invention. Detailed Implementation

[0020] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 This illustration shows a specific embodiment of the compensation circuit for a bandgap reference with a positive second-order temperature coefficient according to the present invention, including a high-order temperature-compensating MOS resistor array unit and a gate voltage generation unit for the high-order temperature-compensating MOS resistor, wherein:

[0022] The gate voltage generation unit of the high-order temperature-compensated MOS resistor is used to generate a gate voltage V that is related to temperature T. A Its components include BJT transistors Q1 and Q2, resistors R1 and R2, PMOS transistors M0, M1, and M2, and NMOS transistor M3, wherein:

[0023] The source of PMOS transistor M0 is connected to the power supply VCC, the gate of M0 is connected to the drain of M0, and the drain of M0 is connected to the zero-temperature drift current source I0.

[0024] The source of PMOS transistor M1 is connected to the power supply VCC, the gate is connected to the gate of M1, and the drain is connected to the collector of Q1.

[0025] The source of PMOS transistor M2 is connected to power supply VCC, the gate is connected to the gate of M1, and the drain is connected to the collector of Q2.

[0026] The base of BJT transistor Q1 is connected to the collector of Q1, and the emitter of Q1 is grounded through resistor R1.

[0027] The base of BJT transistor Q2 is connected to the base of Q1, and the emitter of Q2 is grounded through resistor R2.

[0028] The source of NMOS transistor M3 is grounded, the drain is connected to the emitter of Q2, and the gate is connected to the collector of Q2.

[0029] The collector of Q2 serves as the output terminal of the gate voltage generation unit of the high-order temperature-compensated MOS resistor, outputting the gate voltage V. A .

[0030] In this embodiment, the emitter area ratio of Q1 to Q2 is M:1, and the PMOS transistors M1 and M2 have the same dimensions.

[0031] The high-order temperature-compensated MOS resistor array unit consists of at least two NMOS transistors connected in parallel. The drain of each NMOS transistor is connected to the first-order bandgap connection terminal (the first-order bandgap connection terminal is used to connect to the first-order compensation resistor in the first-order temperature-compensated bandgap reference circuit unit), and the source of each NMOS transistor is grounded. The gate of one of the NMOS transistors is connected to the gate voltage V. A The gates of the remaining NMOS transistors are respectively connected to the gate voltage V through switches. A The switch is turned on or off under the control of a control signal.

[0032] In this embodiment, the first-order temperature-compensated bandgap reference circuit unit consists of resistors R3, R4, R5, R6, BJT transistors Q3 and Q4, and operational amplifier OPA. Its specific structure is as follows:

[0033] The first end of resistor R3 is connected to power supply VCC, and the second end is connected to the inverting input of operational amplifier OPA and the collector of BJT transistor Q3.

[0034] The first end of resistor R4 is connected to power supply VCC, and the second end is connected to the non-inverting input of operational amplifier OPA and the collector of BJT transistor Q4.

[0035] The output terminal of the op-amp OPA is connected to the base of Q3 and the base of Q4;

[0036] The emitter of BJT transistor Q3 is connected to the first terminal of resistor R5;

[0037] The emitter of BJT transistor Q4 is connected to the second terminal of resistor R5 and the first terminal of resistor R6.

[0038] The output terminal of the op-amp OPA serves as the bandgap reference voltage output terminal VREF.

[0039] In this embodiment, the high-order temperature-compensated MOS resistor array unit is composed of multiple NMOS transistors M4, M5, M6, etc. connected in parallel. Specifically, the drains of MOS transistors M4, M5, and M6 are all connected to the second terminal of resistor R6, and the sources of MOS transistors M4, M5, and M6 are all grounded. The gate of M4 is connected to the gate voltage V. A The gates of MOS transistors such as M5 and M6 are respectively connected to the gate voltage V via switches. A The switch is turned on or off under the control of a control signal.

[0040] The MOS transistors M4, M5, and M6 have the same dimensions as M3.

[0041] The following is combined Figure 1 Explanation of the working principle of the circuit in this embodiment:

[0042] M4, M5, M6, etc., are connected in parallel to form a high-order temperature-compensated MOS resistor. The voltage drop across this resistor is superimposed on the output. In terms of voltage, compensation The higher-order temperature coefficient. The gate voltage generation unit of the higher-order temperature-compensated MOS resistor provides the gate voltage for M4, M5, M6, etc., which is related to the temperature T. I0 is the current with zero temperature drift. M0, M1, and M2 form a current mirror. M1 and M2 have the same size, so I1 and I2 are both currents with zero temperature drift and I1=I2.

[0043] M4 gate and the gate voltage V A Connected, the gates of M5, M6, etc. are connected to the gate voltage V via a switch. A Connected. The control signal controls the on / off state of the switch, which in turn controls the number of MOSFETs connected in parallel with M4, thereby adjusting the high-order temperature compensation MOSFET resistor. The size and the second-order temperature coefficient of the MOS resistor.

[0044] In this embodiment, the output reference voltage of the first-order temperature-compensated bandgap reference circuit unit is:

[0045] （1）

[0046] Where N is the ratio of the emitter areas of Q3 to Q4. Thermoelectric voltage, .

[0047] This structure only performs first-order compensation for the output voltage, ignoring... The higher-order terms. In fact, BJT's It does not change linearly with temperature. Related to the process, its formula is as follows:

[0048] （2）

[0049] It is the bandgap voltage of silicon at 0K. It is absolute temperature. For reference temperature, BJT at reference temperature Voltage, It is a quantity related to the structure of the transistor. It is not related to temperature but to the process. It is a quantity related to the current flowing through the transistor. When the PTAT current flows through the transistor... The value is 1 when a temperature-independent current flows through the transistor. It is 0.

[0050] The second term on the right side of equation (2) is temperature. The first term is a first-order term, and the third term on the right is a higher-order term of temperature. It is difficult to obtain a band gap reference with a very low temperature coefficient by relying solely on first-order temperature compensation, so higher-order temperature compensation is required.

[0051] In most processes, in equation (2) The value is approximately 4. The second-order temperature coefficient is negative, and after first-order compensation... The voltage curve is a downward-opening parabola. Existing literature primarily addresses this type of high-precision reference voltage design. High-order compensation. However, in actual tape-out, due to large process deviations in CMOS technology, the performance parameters of BJT transistors deviate significantly from theoretical values, often resulting in... The second-order temperature coefficient is positive, or due to a large mismatch introduced by the process or circuit structure, after first-order compensation... The voltage curve is an upward-opening parabola. However, high-order compensation designs for the reference voltage in this case are rarely mentioned in the literature.

[0052] This embodiment adopts Figure 1 The circuit shown Curvature compensation was performed when the second-order temperature coefficient was positive to meet the design requirements of a high-precision reference voltage.

[0053] Depend on Figure 1 From the circuit, we can see that:

[0054] （3） （4） （5） （6） （7） （8） （9）

[0055] These are the collector currents of transistors Q1 and Q2, respectively; , These are the base currents of transistors Q1 and Q2, respectively. This is the amplification factor of transistor Q2; This is the ratio of the emitter areas of transistors Q1 and Q2; This is the on-resistance of transistor M3.

[0056] The first-order temperature coefficient of the amplification factor β of a BJT tube is positive, while the second-order temperature coefficient is negative. It is a zero-temperature drift current, therefore The first-order temperature coefficient is negative, and the second-order temperature coefficient is positive.

[0057] In equation (9), the second-order temperature coefficients of the first and second terms on the right are both negative. It is a zero-temperature-drift resistor, therefore The second-order temperature coefficient is negative.

[0058] When transistor M3 operates in the linear region, its on-resistance is as follows:

[0059] （10）

[0060] The carrier mobility of the NMOS transistor. The oxide capacitance per unit area of ​​the MOSFET. The aspect ratio of the MOSFET. This is the gate-source voltage of the MOSFET. This is the threshold voltage of the MOSFET.

[0061] In formula (10) The temperature coefficient is negative. The temperature coefficient is negative. Combining equations (9) and (10), a reasonable design is needed. , , , The value of makes Operating in the linear region, and with the voltage at point A lower than the supply voltage minus the overdrive voltage of transistor M2 across the entire temperature range, a MOS resistor with a negative second-order temperature coefficient can be obtained. Since M4, M5, M6, etc., have the same dimensions and gate-source voltage as M3, their impedances are the same as those of M3. The higher-order compensation resistor can be changed by altering the number of NMOS transistors connected in parallel with M4 using a control signal. The magnitude of the second-order temperature coefficient. Current flowing through this... The generated voltage is superimposed on the output reference voltage, thus enabling the application of voltages with a positive second-order temperature coefficient. Perform high-order nonlinear compensation.

Claims

1. A bandgap reference compensation circuit, characterized in that: It includes a high-order temperature-compensated MOS resistor array unit and a gate voltage generation unit for the high-order temperature-compensated MOS resistor, wherein: The gate voltage generation unit of the high-order temperature-compensated MOS resistor is used to generate a gate voltage V that is related to temperature T. A ; The high-order temperature-compensated MOS resistor array unit consists of at least two NMOS transistors connected in parallel. The drain of each NMOS transistor is connected to the first-order bandgap junction, and the source of each NMOS transistor is grounded. The gate of one of the NMOS transistors is connected to the gate voltage V. A The gates of the remaining NMOS transistors are respectively connected to the gate voltage V through switches. A The switch is turned on or off under the control of a control signal.

2. The bandgap reference compensation circuit according to claim 1, characterized in that, The gate voltage generation unit of the high-order temperature-compensated MOS resistor includes BJT transistors Q1 and Q2, resistors R1 and R2, PMOS transistors M0, M1, and M2, and NMOS transistor M3, wherein: The source of PMOS transistor M0 is connected to the power supply VCC, the gate of M0 is connected to the drain of M0, and the drain of M0 is connected to the zero-temperature drift current source I0. The source of PMOS transistor M1 is connected to the power supply VCC, the gate is connected to the gate of M1, and the drain is connected to the collector of Q1. The source of PMOS transistor M2 is connected to power supply VCC, the gate is connected to the gate of M1, and the drain is connected to the collector of Q2. The base of BJT transistor Q1 is connected to the collector of Q1, and the emitter of Q1 is grounded through resistor R1. The base of BJT transistor Q2 is connected to the base of Q1, and the emitter of Q2 is grounded through resistor R2. The source of NMOS transistor M3 is grounded, the drain is connected to the emitter of Q2, and the gate is connected to the collector of Q2. The collector of Q2 serves as the output terminal of the gate voltage generation unit for the high-order temperature-compensated MOS resistor, outputting the gate voltage V. A .

3. The bandgap reference compensation circuit according to claim 2, characterized in that: Each NMOS transistor in the high-order temperature-compensated MOS resistor array unit has the same size as the NMOS transistor M3; the PMOS transistors M1 and M2 have the same size.

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