Memory synchronization method and device and system-on-chip

Abstract

The invention provides a memory synchronization method and device and a system-on-chip, and relates to the technical field of computers, and the method comprises the steps: monitoring the writing of a hardware mailbox through a tag management unit deployed in the system-on-chip SoC, and directly updating an access control right tag corresponding to a target memory after memory synchronization information is obtained. Therefore, memory synchronization between the on-chip function modules is completed without participation of a CPU, additional delay and system overhead caused by dependence on CPU scheduling, system calling or interrupt processing in the prior art are avoided, and memory synchronization efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a memory synchronization method, apparatus, and system-on-a-chip. Background Technology

[0002] A heterogeneous multi-core system-on-a-chip (SoC) refers to a single chip that integrates multiple different types of processor cores. It contains numerous on-chip functional modules, such as a Graphics Processing Unit (GPU), a Neural-network Processing Unit (NPU), a Display Processing Unit (DPU), a Video Processing Unit (VPU), and an Image Signal Processor (ISP). Data exchange between these on-chip functional modules is achieved through shared memory technology for data synchronization.

[0003] In heterogeneous multi-core SoC architectures, data exchange between multiple on-chip functional modules typically relies on shared physical memory. To ensure data consistency, the system employs a mechanism based on low-level semaphores and spinlocks (such as Direct Memory Access-fence, DMA-fence) in conjunction with software-triggered cross-module interrupts for synchronization. This approach requires each synchronization to undergo a complete process of "system call → lock contention → interrupt dispatch → central processing unit (CPU) context switching," leading to frequent CPU intervention in the critical path, significantly increasing latency and reducing the efficiency of multi-module collaboration. Summary of the Invention

[0004] In view of this, this application provides a memory synchronization method, apparatus, and system-on-a-chip to solve the problems of latency and low efficiency in shared memory of on-chip functional modules in a system-on-a-chip.

[0005] Specifically, this application is implemented through the following technical solution: In a first aspect, embodiments of this application provide a memory synchronization method applied to a tag management unit deployed on a system-on-a-chip (SoC); the method includes: Write monitoring is performed on the hardware mailbox deployed on the SoC; In response to the detection that memory synchronization information is written to the Mailbox, the memory synchronization information is obtained; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory; Based on the memory synchronization information, the target memory is determined from the shared memory of the SoC, and the access control tag corresponding to the target memory is updated from the first identification information to the second identification information; the access control tag is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory; Send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

[0006] In some implementations, determining the target memory from the shared memory of the SoC based on the memory synchronization information, and updating the access control tag corresponding to the target memory from the first identification information to the second identification information, includes: Based on the starting address and offset indicated by the address information, the target memory is determined from the shared memory; the target memory includes a first memory space and a second memory space; the first memory space is used to store data written by the on-chip functional modules; the second memory space is used to store the access control tag corresponding to the target memory; Update the access control label stored in the second memory space from the first identification information to the second identification information.

[0007] In some implementations, the shared memory is divided into fixed-size memory granularities; each memory granularity corresponds to an access control tag; and the target memory corresponds to at least one of the plurality of memory granularities.

[0008] In some implementations, the shared memory is the internal memory of the SoC.

[0009] In some implementations, updating the access control tag corresponding to the target memory from the first identification information to the second identification information is an atomic operation.

[0010] In some implementations, the tag management unit is a hardware unit within the SoC, including at least one hardware state machine.

[0011] Secondly, embodiments of this application provide a memory synchronization device for a tag management unit deployed on a system-on-a-chip (SoC); the device includes: The monitoring module is used to monitor write operations to the hardware mailbox deployed on the SoC. The acquisition module is used to acquire the memory synchronization information in response to detecting that memory synchronization information is written to the Mailbox; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory; The management module is used to determine the target memory from the shared memory of the SoC based on the memory synchronization information, and update the access control right label corresponding to the target memory from the first identification information to the second identification information; the access control right label is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory; The sending module is used to send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

[0012] Thirdly, embodiments of this application provide a system-on-a-chip, including: Multiple on-chip functional modules are used to perform their respective computing tasks and access shared memory; At least one hardware mailbox for receiving memory synchronization information from any of the on-chip functional modules; A tag management unit is used to perform the steps of the memory synchronization method as described in the first aspect or any embodiment of the first aspect; Shared memory is used to store data and access control tags of each on-chip functional module, and to verify the access behavior of any of the on-chip functional modules based on the access control tags. At least one doorbell hardware component is required to provide a doorbell communication mechanism.

[0013] Fourthly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the memory synchronization method as described in the first aspect or any embodiment of the first aspect.

[0014] Fifthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the memory synchronization method as described in the first aspect or any embodiment of the first aspect.

[0015] The memory synchronization method, apparatus, and system-on-a-chip provided in this application monitor the writes to the hardware mailbox by deploying a tag management unit within the system-on-a-chip (SoC), and directly update the access control tag corresponding to the target memory after obtaining memory synchronization information. This allows memory synchronization between on-chip functional modules to be completed without CPU involvement, avoiding the additional latency and system overhead caused by relying on CPU scheduling, system calls, or interrupt handling in the prior art, and improving memory synchronization efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a system-on-a-chip (SoC) illustrated in an exemplary embodiment of this application; Figure 2 This is a flowchart illustrating a memory synchronization method in an exemplary embodiment of this application; Figure 3 This is a flowchart illustrating another memory synchronization method in an exemplary embodiment of this application; Figure 4 This is a schematic diagram illustrating the storage structure of the access control label in an exemplary embodiment of this application; Figure 5 This is a schematic diagram illustrating a Mailbox signal writing mechanism according to an exemplary embodiment of this application; Figure 6 This is a schematic diagram illustrating tag updating in an exemplary embodiment of this application; Figure 7 This is a schematic diagram illustrating the Doorbell notification mechanism in an exemplary embodiment of this application; Figure 8 This is a schematic diagram illustrating an on-chip functional module accessing shared memory, as shown in an exemplary embodiment of this application; Figure 9 This is a schematic diagram illustrating a memory synchronization device according to an exemplary embodiment of this application; Figure 10 This is a schematic diagram of a computer device structure shown in an exemplary embodiment of this application. Detailed Implementation

[0017] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0018] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0019] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0020] Research has revealed that in heterogeneous multi-core SoC architectures, data exchange between multiple on-chip functional modules typically relies on shared physical memory. To ensure data consistency, the system employs a low-level semaphore and spinlock mechanism combined with software-triggered cross-module interrupts for synchronization. This approach requires each synchronization to undergo a complete process of "system call → lock contention → interrupt dispatch → CPU context switch," leading to frequent CPU intervention in the critical path, significantly increasing latency and reducing the efficiency of multi-module collaboration.

[0021] In view of this, embodiments of this application provide a memory synchronization method, apparatus, and system-on-a-chip. By monitoring the writes to the hardware mailbox via a tag management unit deployed within the system-on-a-chip (SoC), and directly updating the access control tag corresponding to the target memory after obtaining memory synchronization information, memory synchronization between on-chip functional modules can be completed without CPU involvement. This avoids the additional latency and system overhead caused by relying on CPU scheduling, system calls, or interrupt handling in the prior art, thereby improving memory synchronization efficiency.

[0022] The deficiencies of the existing technical solutions are the result of the inventor's practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in this application below should be considered as the inventor's contributions to this application.

[0023] To facilitate understanding of this embodiment, the application scenarios of the memory synchronization method disclosed in this application embodiment will first be introduced. The execution subject of the memory synchronization method provided in this application embodiment can be a tag management unit, which can be a hardware unit inside a system-on-a-chip (SoC) and may include at least one hardware state machine.

[0024] Reference Figure 1 The diagram shown is a schematic representation of a system-on-a-chip (SoC) provided in an exemplary embodiment of this application. The SoC includes multiple on-chip functional modules, at least one hardware mailbox, a tag management unit, shared memory, and at least one doorbell hardware component. On-chip functional modules are used to perform their respective computing tasks and access shared memory. For example, on-chip functional modules may include a graphics processing unit (GPU), a neural network processing unit (NPU), a display processing unit (DPU), a video processing unit (VPU), an image signal processor (ISP), etc.

[0025] The hardware mailbox is used to receive memory synchronization information from any of the on-chip functional modules. It is a hardware-level inter-core / subsystem communication mechanism used to transmit control information, events, or small amounts of data between different processing units.

[0026] Doorbell hardware provides a doorbell communication mechanism, which is a hardware event notification mechanism deployed in a system-on-a-chip (SoC) to trigger asynchronous notifications between different on-chip functional modules or processing units.

[0027] Shared memory is used to store data and access control tags for each on-chip functional module, and to verify permissions for access behavior of any on-chip functional module based on the access control tags.

[0028] The tag management unit is used to execute the steps of the memory synchronization method provided in the embodiments of this application.

[0029] The memory synchronization method provided in the embodiments of this application will be described below.

[0030] See Figure 2 The diagram shows a flowchart of a memory synchronization method provided in an embodiment of this application. The execution entity of this method can be a tag management unit, and the method includes steps S201-S204, wherein: S201. Perform write monitoring on the hardware mailbox deployed on the SoC.

[0031] In this embodiment, on-chip functional modules within the SoC can use shared memory. On-chip functional modules using shared memory need to have access control rights to the corresponding memory. These access control rights can be maintained through access control right tags. Access control right tags can indicate the on-chip functional modules that have access control rights to the memory. For example, the content of the access control right tag can be an identifier specifying the on-chip functional module.

[0032] The identifiers of the on-chip functional modules can be pre-configured to uniquely identify them globally. For example, the identifiers of the on-chip functional modules can be in the form of 0x1, 0x2, etc.

[0033] In some embodiments, the access control tag can be stored in shared memory. When an on-chip functional module accesses the shared memory, the shared memory can authenticate the accessing module based on the stored access control tag.

[0034] When a shared memory is used by an on-chip functional module and the access rights to the shared memory need to be transferred to the next on-chip functional module, the on-chip functional module can write memory synchronization information into the hardware mailbox. This allows the tag management unit to obtain the memory synchronization information and transfer access control to the new on-chip functional module based on the memory synchronization information.

[0035] S202. In response to detecting that memory synchronization information is written to the Mailbox, the memory synchronization information is obtained; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory.

[0036] When the tag management unit detects that memory synchronization information has been written to the Mailbox, the tag management unit can obtain the memory synchronization information and parse it to extract the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory.

[0037] The first on-chip functional module can be the on-chip functional module that currently has access control over the target memory, and the second on-chip functional module can be the target on-chip functional module to which the first on-chip functional module wants to transfer access control.

[0038] The target memory mentioned above can refer to a segment of shared memory or the entire shared memory. In some embodiments, the shared memory can be divided into fixed-size memory granularities, with each memory granularity corresponding to an access control tag, and the target memory corresponding to at least one of multiple memory granularities.

[0039] For example, shared memory can be divided into multiple memory spaces with a 16-byte granularity. The storage space for the access control label can be a part of the shared memory. Specifically, a 4-bit storage space can be set for the access control label in each memory granularity.

[0040] In this way, by dividing shared memory into fixed-size memory granularities and configuring corresponding access control tags for each memory granularity, access permissions can be precisely applied to one or more memory granularities corresponding to the target memory, thereby avoiding unnecessary impacts caused by permission switching across the entire memory block and improving the flexibility and resource utilization efficiency of the memory synchronization process.

[0041] S203. Based on the memory synchronization information, determine the target memory from the shared memory of the SoC, and update the access control tag corresponding to the target memory from the first identification information to the second identification information; the access control tag is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory.

[0042] In this step, the tag management unit can determine the target memory based on memory synchronization information and update the access control tag of the target memory, thereby transferring access control of the target memory to the second on-chip functional module. The target memory can refer to a single memory granularity or multiple memory granularities. The memory synchronization information can indicate the address information of multiple target memories.

[0043] In some embodiments, determining the target memory from the shared memory of the SoC based on the memory synchronization information, and updating the access control tag corresponding to the target memory from the first identification information to the second identification information, includes: Based on the starting address and offset indicated by the address information, the target memory is determined from the shared memory; the target memory includes a first memory space and a second memory space; the first memory space is used to store data written by the on-chip functional modules; the second memory space is used to store the access control tag corresponding to the target memory; Update the access control label stored in the second memory space from the first identification information to the second identification information.

[0044] In this step, the tag management unit divides the target memory into spaces according to preset memory layout rules, thereby determining the first memory space and the second memory space.

[0045] In this way, by using the starting address and offset indicated in the memory synchronization information, the target memory is determined from the shared memory, and the target memory is divided into a first memory space for storing data and a second memory space for storing access control labels. This enables the separate management of data storage and access control information, avoids the mixing of access control labels and data, and improves the accuracy of target memory location and the reliability of access permission management.

[0046] Furthermore, by setting the second memory space directly within the target memory, the access control tags stored therein can be associated with the target memory to form a mapping relationship, which facilitates the verification of access control rights.

[0047] In this embodiment, the tag management unit has the ability to directly access shared memory, which is physical memory that can be directly read and written by the tag management unit, thereby modifying and updating the tags in the second memory space.

[0048] In some implementations, the SoC may deploy at least one CPU that can initialize access control tags in each of the secondary memory spaces when the system starts up, and then maintain them by a tag management terminal.

[0049] In some embodiments, the step of updating the access control tag corresponding to the target memory from the first identification information to the second identification information is an atomic operation. Here, "atomic operation" refers to a series of operations in the SoC field that are logically uninterruptible or indivisible.

[0050] This ensures that there is no intermediate state that can be observed externally during the switching of access control rights between the first and second identification information, thereby effectively avoiding data competition or illegal access caused by on-chip functional modules during access permission switching, and improving the security and consistency of system operation.

[0051] In this embodiment, the tag management unit can automatically parse the content written to the Mailbox without CPU intervention or reliance on ARM STG instructions (Store Tag instructions in the ARM architecture), and supports updates of access control tags at multiple memory granularities.

[0052] S204. Send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

[0053] In this step, after updating the access control tag corresponding to the target memory, the tag management unit sends a doorbell signal to the second on-chip functional module to indicate that the access control of the target memory has been synchronized.

[0054] The Doorbell signal is sent to the corresponding control interface via the Doorbell network. The Doorbell network is a dedicated path built into the SoC and is not a Generic Interrupt Controller (GIC) interrupt. It features low latency and point-to-point connection and is used only for notification of access control transfer.

[0055] Specifically, the Doorbell signal is a hardware notification signal provided within the SoC. The tag management unit sends access control synchronization completion information to the second on-chip functional module through the Doorbell communication mechanism established with the second on-chip functional module. The Doorbell signal is used to indicate that the access control tag corresponding to the target memory has been updated to the second identification information, thereby indicating that the second on-chip functional module has obtained access rights to the target memory.

[0056] In this embodiment, the Doorbell signal is sent after the access control tag update operation is completed, to ensure that the second on-chip functional module can access the target memory after receiving the Doorbell signal and pass the shared memory permission verification mechanism. Upon receiving the Doorbell signal, the second on-chip functional module can trigger an access operation to the target memory based on the Doorbell signal without needing to confirm the access control status through software polling or CPU interrupts.

[0057] Through the Doorbell notification method described above, this application can realize the instant notification of the synchronous completion of access control rights in hardware, reduce the synchronization waiting time between on-chip functional modules, and improve the efficiency and determinism of cross-on-chip functional module collaborative processing.

[0058] The memory synchronization method provided in this application monitors the writes to the hardware mailbox by deploying a tag management unit within the system-on-a-chip (SoC), and directly updates the access control tag corresponding to the target memory after obtaining memory synchronization information. This allows memory synchronization between on-chip functional modules to be completed without CPU involvement, avoiding the additional latency and system overhead caused by relying on CPU scheduling, system calls, or interrupt handling in the prior art, and improving memory synchronization efficiency.

[0059] See Figure 3 The diagram shown is a flowchart of another memory synchronization method provided in an exemplary embodiment of this application. In this method, a first on-chip functional module writes memory synchronization information to the Mailbox hardware. The tag management unit detects the write event, determines the target memory, updates the access control tag stored in the second memory space, and then sends a Doorbell signal to the second on-chip functional module, indicating that the data in the target memory is ready. The second on-chip functional module then uses its corresponding second identification information to access the shared memory. Figure 3 The solid arrows in the diagram indicate hardware signals or data streams.

[0060] See Figure 4 The diagram shown is a schematic representation of the storage structure of an access control tag provided in an exemplary embodiment of this application. Figure 4 In this system, access control tags are stored in a second memory space, which is part of shared memory. The CPU can initialize the access control tags stored in the second memory space, and the tag management unit can directly read and write to the second memory space to update the access control tags.

[0061] See Figure 5 The diagram shown is a schematic of the Mailbox signal writing mechanism provided in an exemplary embodiment of this application. Figure 5 In the process, the on-chip functional module can write memory synchronization messages into the Mailbox hardware register. The write event can be monitored by the tag management unit. When the write event is triggered, the tag management unit can obtain the written memory synchronization message.

[0062] See Figure 6 The diagram shown is a schematic representation of tag updating provided in an exemplary embodiment of this application. Figure 6 In the process, the tag management unit detects the write event of the Mailbox hardware, obtains and parses the written memory synchronization information, and then atomically updates the tag corresponding to the second memory space.

[0063] See Figure 7 The diagram shown is a schematic representation of the Doorbell notification mechanism provided in an exemplary embodiment of this application. Figure 7 In the process, the tag management unit sends a Doorbell signal through the doorbell network, and the Doorbell interrupt is input to the target on-chip functional module through the corresponding interface.

[0064] See Figure 8 The diagram shown is a schematic of an on-chip functional module accessing shared memory provided in an exemplary embodiment of this application. Figure 8In this process, the on-chip functional module uses its own identification information to request access to the target memory. The shared memory reads the access control tag from the second memory space corresponding to the target memory and uses the access control tag to verify the permissions with the identification information sent by the on-chip functional module. After successful verification, the data to be shared in the target memory is returned to the on-chip functional module.

[0065] Corresponding to the aforementioned embodiments of the memory synchronization method, this application also provides embodiments of a memory synchronization device.

[0066] See Figure 9 The diagram shown is a schematic representation of a memory synchronization device according to an exemplary embodiment of this application. The device is used in a tag management unit and includes: The monitoring module 910 is used to monitor writes to the hardware mailbox deployed on the SoC; The acquisition module 920 is used to acquire the memory synchronization information in response to detecting that memory synchronization information is written to the Mailbox; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory; The management module 930 is used to determine the target memory from the shared memory of the SoC based on the memory synchronization information, and update the access control right label corresponding to the target memory from the first identification information to the second identification information; the access control right label is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory; The transmitting module 940 is used to send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

[0067] In some implementations, the management module 930 is used for: Based on the starting address and offset indicated by the address information, the target memory is determined from the shared memory; the target memory includes a first memory space and a second memory space; the first memory space is used to store data written by the on-chip functional modules; the second memory space is used to store the access control tag corresponding to the target memory; Update the access control label stored in the second memory space from the first identification information to the second identification information.

[0068] In some implementations, the shared memory is divided into fixed-size memory granularities; each memory granularity corresponds to an access control tag; and the target memory corresponds to at least one of the plurality of memory granularities.

[0069] In some implementations, the shared memory is the internal memory of the SoC.

[0070] In some implementations, updating the access control tag corresponding to the target memory from the first identification information to the second identification information is an atomic operation.

[0071] In some implementations, the tag management unit is a hardware unit within the SoC, including at least one hardware state machine.

[0072] The memory synchronization device provided in this application monitors the writing of the hardware mailbox by deploying a tag management unit within the system-on-a-chip (SoC), and directly updates the access control tag corresponding to the target memory after obtaining memory synchronization information. This allows memory synchronization between on-chip functional modules to be completed without CPU involvement, avoiding the additional latency and system overhead caused by relying on CPU scheduling, system calls, or interrupt handling in the prior art, and improving memory synchronization efficiency.

[0073] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0074] This application also provides a computer device, such as... Figure 10 The diagram shown is a schematic representation of a computer device structure according to an exemplary embodiment of this application. The computer device includes: A processor 101 and a memory 102; the memory 102 stores machine-readable instructions executable by the processor 101, and the processor 101 executes the machine-readable instructions stored in the memory 102. When the machine-readable instructions are executed by the processor 101, the processor 101 performs the following steps: Write monitoring is performed on the hardware mailbox deployed on the SoC; In response to the detection that memory synchronization information is written to the Mailbox, the memory synchronization information is obtained; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory; Based on the memory synchronization information, the target memory is determined from the shared memory of the SoC, and the access control tag corresponding to the target memory is updated from the first identification information to the second identification information; the access control tag is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory; Send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

[0075] In some implementations, determining the target memory from the shared memory of the SoC based on the memory synchronization information, and updating the access control tag corresponding to the target memory from the first identification information to the second identification information, includes: Based on the starting address and offset indicated by the address information, the target memory is determined from the shared memory; the target memory includes a first memory space and a second memory space; the first memory space is used to store data written by the on-chip functional modules; the second memory space is used to store the access control tag corresponding to the target memory; Update the access control label stored in the second memory space from the first identification information to the second identification information.

[0076] In some implementations, the shared memory is divided into fixed-size memory granularities; each memory granularity corresponds to an access control tag; and the target memory corresponds to at least one of the plurality of memory granularities.

[0077] In some implementations, the shared memory is the internal memory of the SoC.

[0078] In some implementations, updating the access control tag corresponding to the target memory from the first identification information to the second identification information is an atomic operation.

[0079] In some implementations, the tag management unit is a hardware unit within the SoC, including at least one hardware state machine.

[0080] The aforementioned memory 102 includes a main memory 1021 and an external memory 1022; the main memory 1021, also known as internal memory, is used to temporarily store the computational data in the processor 101, as well as the data exchanged with external memory 1022 such as a hard disk. The processor 101 exchanges data with the external memory 1022 through the main memory 1021.

[0081] The specific execution process of the above instructions can be referred to the steps of the memory synchronization method described in the embodiments of this application, and will not be repeated here.

[0082] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0083] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the memory synchronization method described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0084] This application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the memory synchronization method provided in the various embodiments of this application.

[0085] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0086] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division; in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0087] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0089] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0091] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A memory synchronization method, characterized in that, A tag management unit deployed on a system-on-a-chip (SoC); the method includes: Write monitoring is performed on the hardware mailbox deployed on the SoC; In response to the detection that memory synchronization information is written to the Mailbox, the memory synchronization information is obtained; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory; Based on the memory synchronization information, the target memory is determined from the shared memory of the SoC, and the access control tag corresponding to the target memory is updated from the first identification information to the second identification information; the access control tag is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory; Send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

2. The method according to claim 1, characterized in that, The step of determining the target memory from the shared memory of the SoC based on the memory synchronization information and updating the access control tag corresponding to the target memory from the first identification information to the second identification information includes: Based on the starting address and offset indicated by the address information, the target memory is determined from the shared memory; the target memory includes a first memory space and a second memory space; the first memory space is used to store data written by the on-chip functional modules; the second memory space is used to store the access control tag corresponding to the target memory; Update the access control label stored in the second memory space from the first identification information to the second identification information.

3. The method according to claim 2, characterized in that, The shared memory is divided into fixed-size memory granularities; each memory granularity corresponds to an access control tag; the target memory corresponds to at least one of the multiple memory granularities.

4. The method according to claim 1, characterized in that, The shared memory is the internal memory of the SoC.

5. The method according to claim 1, characterized in that, The step of updating the access control label corresponding to the target memory from the first identification information to the second identification information is an atomic operation.

6. The method according to claim 1, characterized in that, The tag management unit is a hardware unit inside the SoC, including at least one hardware state machine.

7. A memory synchronization device, characterized in that, A tag management unit for deployment on a system-on-a-chip (SoC); the device includes: The monitoring module is used to monitor write operations to the hardware mailbox deployed on the SoC. The acquisition module is used to acquire the memory synchronization information in response to detecting that memory synchronization information is written to the Mailbox; the memory synchronization information is used to indicate the first identification information of the first on-chip functional module, the second identification information of the second on-chip functional module, and the address information of the target memory; The management module is used to determine the target memory from the shared memory of the SoC based on the memory synchronization information, and update the access control right label corresponding to the target memory from the first identification information to the second identification information; the access control right label is used by the shared memory to verify the permissions of on-chip functional modules accessing the target memory; The sending module is used to send a doorbell signal to the second on-chip functional module; the doorbell signal is used to indicate that the access control of the target memory has been synchronized to the second on-chip functional module.

8. A system-on-a-chip, characterized in that, include: Multiple on-chip functional modules are used to perform their respective computing tasks and access shared memory; At least one hardware mailbox for receiving memory synchronization information from any of the on-chip functional modules; The tag management unit is used to perform the steps of the memory synchronization method as described in any one of claims 1 to 6; Shared memory is used to store data and access control tags of each on-chip functional module, and to verify the access behavior of any of the on-chip functional modules based on the access control tags. At least one doorbell hardware component is required to provide a doorbell communication mechanism.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the memory synchronization method as described in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the memory synchronization method as described in any one of claims 1 to 6.

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