Display driving framework and time sequence control method thereof, display panel and display equipment

Abstract

The invention discloses a display driving framework and a time sequence control method thereof, a display panel and display equipment, and relates to the technical field of display, the display driving framework comprises a pixel array formed by a plurality of pixels distributed in an array, a gate driving circuit and a time sequence control module, the pixels are composed of sub-pixels of different colors which are sequentially arranged in the column direction, and the colors of the sub-pixels in the same row are the same; the gate driving circuit is electrically connected with the sub-pixels in the corresponding rows through the gate scanning lines in the rows; the time sequence control module is electrically connected with the gate driving circuit, and the time sequence control module is configured to respond to a preset double-gate line driving mode, provide a gate driving time sequence for the gate driving circuit and control the gate driving circuit to perform gate driving on the pixel array according to the gate driving time sequence, therefore, grid scanning lines corresponding to two sub-pixel rows which belong to the same color and are spaced by two rows in the column direction are opened at the same time, and a double-grid-line driving mode is compatible under a three-row driving framework.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driving architecture and its timing control method, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, users have placed higher demands on display solutions with high refresh rates and low costs. Currently, the industry typically adopts TRD (Tri-Row Drive) architecture and DLG (Dual Line Gate) mode as the mainstream technologies for improving refresh rates and reducing driving costs. However, in the TRD architecture, since the R, G, and B subpixels are arranged vertically and adjacent rows of subpixels have different colors, directly using the conventional DLG driving method to simultaneously activate two adjacent rows will cause data voltage to be charged into subpixels of the wrong color, resulting in abnormal images. If it is desired to charge subpixels of the same color simultaneously, subpixels in two rows separated by a certain number must be activated simultaneously. This conflicts with the constraint in the GOA (Gate on Array) driving circuit that odd and even rows are activated in a fixed order, making it impossible to directly implement the traditional DLG mode in the TRD architecture.

[0003] Currently, existing technologies attempt to address the technical challenges of implementing traditional DLG modes directly within the TRD architecture by altering the pixel arrangement architecture or adjusting the GOA driving method. Specifically, this involves connecting adjacent left and right sub-pixels to the same data line to achieve a horizontal DLG effect, or changing the bilateral GOA driving to a single-sided driving to match the activation timing of sub-pixels of the same color. However, these solutions all require modifications to the panel's internal structure or photomask design, increasing manufacturing costs and potentially leading to decreased display uniformity due to drive signal attenuation, resulting in horizontal bright and dark stripes and negatively impacting the visual experience.

[0004] Therefore, while maintaining the low-cost advantage of the TRD architecture, how to achieve an efficient and stable DLG driving mode has become a technical challenge that urgently needs to be solved in the display panel industry. Summary of the Invention

[0005] The main objective of this application is to provide a display driving architecture and its timing control method, a display panel, and a display device, which aim to implement a dual gate line driving mode in a three-row driving architecture.

[0006] To achieve the above objectives, this application provides a display driver architecture, which includes: A pixel array comprising a plurality of array-distributed pixels, wherein each pixel is composed of sub-pixels of different colors arranged sequentially along a column direction, and all sub-pixels in the same row have the same color; A gate driving circuit, wherein the gate driving circuit is electrically connected to the sub-pixels of the corresponding rows through each row of gate scan lines; A timing control module is electrically connected to the gate driving circuit. The timing control module is configured to provide a gate driving timing to the gate driving circuit in response to a preset dual gate line driving mode, and control the gate driving circuit to perform gate driving on the pixel array according to the gate driving timing, so that the gate scan lines corresponding to two sub-pixel rows that belong to the same color and are separated by two rows in the column direction are turned on simultaneously.

[0007] In one embodiment, the data line connection architecture of the pixel array includes: A single-column, single-data-line architecture, wherein the single-column, single-data-line architecture is composed of rows of sub-pixels arranged continuously along a column direction, electrically connected to the same data line; and / or, A single-column dual-data-line architecture is configured to electrically connect all the sub-pixels in the latter half of the same column to the data lines of the corresponding column, and to electrically connect all the sub-pixels in the first half of the same column to the next data line of the corresponding column data lines.

[0008] Furthermore, this application provides a timing control method applied to the display driver architecture described above, the timing control method comprising: In response to a preset dual gate line driving mode, the timing control module provides the gate driving timing to the gate driving circuit and controls the gate driving circuit to drive the pixel array according to the gate driving timing, so that the gate scan lines corresponding to two sub-pixel rows of the same color and separated by two rows in the column direction are turned on simultaneously.

[0009] In one embodiment, the timing control method includes: In response to the pixel array's data line connection architecture being at least one of a single-column single-data-line architecture and a single-column dual-data-line architecture, the gate driving timing is determined to be the first driving timing.

[0010] In one embodiment, the operation steps corresponding to the first driving timing include: A pixel driving unit is defined as two consecutive rows of pixels arranged in a column direction. The pixel driving unit includes a first sub-pixel row and a fourth sub-pixel row, a second sub-pixel row and a fifth sub-pixel row, and a third sub-pixel row and a sixth sub-pixel row, all of the same color. One of the two pixel rows is composed of the first sub-pixel row, the second sub-pixel row, and the third sub-pixel row, while the other pixel row is composed of the third sub-pixel row, the fourth sub-pixel row, and the fifth sub-pixel row. In each of the pixel driving units, the gate scan line where the second sub-pixel row is located is turned on, and while delaying the turn-on time of the gate scan line where the second sub-pixel row is located, the gate scan lines corresponding to the first sub-pixel row and the fourth sub-pixel row are controlled to be turned on synchronously. After the first sub-pixel row and the fourth sub-pixel row are simultaneously filled with the same pixel grayscale data, the gate scan lines corresponding to the third sub-pixel row and the sixth sub-pixel row are triggered to be turned on synchronously. After the third sub-pixel row and the sixth sub-pixel row are simultaneously filled with the same pixel grayscale data, the gate scan line where the fifth sub-pixel row is located is triggered to turn on, and the delayed turn-on time is cut off until the gate scan line where the fifth sub-pixel row is located is turned off, so that the second sub-pixel row receives and maintains the same pixel grayscale data as the fifth sub-pixel row.

[0011] In one embodiment, the timing control method includes: Based on the response of the single-row single-data-line architecture to the preset hardware super-resolution mode, the gate driving timing is switched from the first driving timing to an alternating driving timing. The alternating driving timing is configured to alternately execute the first driving timing and the preset second driving timing during multiple consecutive frame refresh cycles.

[0012] In one embodiment, the operation steps corresponding to the second driving timing include: In the pixel driving unit, after the gate scan lines corresponding to the first sub-pixel row and the third sub-pixel row are turned on in sequence, when the gate scan line where the second sub-pixel row is located is turned on, the gate scan line where the fifth sub-pixel row is located is turned on simultaneously, and the turn-on time of the gate scan line where the fifth sub-pixel row is located is delayed. While delaying the opening time of the gate scan line where the fifth sub-pixel row is located, the gate scan lines corresponding to the fourth sub-pixel row in the pixel driving unit and the first sub-pixel row in the next pixel driving unit are controlled to be opened synchronously so as to fill in the same pixel grayscale data. The gate scan lines corresponding to the sixth sub-pixel row in the pixel driving unit and the third sub-pixel row in the next pixel driving unit are synchronously turned on so as to fill in the same pixel grayscale data; The gate scan line where the second sub-pixel row is located in the next pixel driving unit is triggered to turn on, and the delayed turn-on time is cut off when the gate scan line where the second sub-pixel row is located in the next pixel driving unit is turned off, so that the second sub-pixel row in the pixel driving unit receives and maintains the same pixel grayscale data as the second sub-pixel row in the next pixel driving unit.

[0013] In addition, this application provides a display panel, which includes the display driving architecture described above; The display panel further includes a display area and a non-display area surrounding the display area; The pixel array in the display driver architecture is disposed within the display area; The non-display area is provided with the gate driving circuit in the display driving architecture, and the gate driving circuit is disposed on both sides of the display area; The timing control module in the display driver architecture is located on the circuit assembly board, which is positioned on the side of the circuit assembly board closer to the non-display area and farther from the display area.

[0014] In one embodiment, a gate driving circuit disposed on one side of the display area is electrically connected to the gate scan lines corresponding to the odd number of sub-pixel rows; The gate driving circuit, located on the other side of the display area, is electrically connected to the gate scan lines corresponding to the even-numbered sub-pixel rows.

[0015] Furthermore, this application provides a display device including the display panel described above, the display device being configured to perform the steps of the timing control method described above.

[0016] This application provides a display driving architecture that successfully solves the technical defect of the TRD architecture being incompatible with the DLG (Dual Line Gate) mode by introducing a timing control module and configuring a preset gate driving timing under the TRD (Tri-Row Drive) architecture. Specifically, firstly, based on the inherent pixel arrangement of the TRD architecture—that is, sub-pixels of different colors in a pixel are arranged sequentially along the column direction and sub-pixels in the same row are of the same color—a fixed and reliable physical basis is provided for the timing control module's timing control. Next, based on the timing control module's response to the preset dual-gate line drive mode, the reconstructed gate driving timing is output to the gate driving circuit. This controls the gate driving circuit to synchronously turn on the gate scan lines corresponding to sub-pixel rows of the same color that are two rows apart in the column direction, while maintaining its original bilateral driving and odd-even row grouping sequence driving physical constraints. This ensures that the gate scan lines corresponding to two sub-pixel rows of the same color that are two rows apart in the column direction are turned on simultaneously, overcoming the GOA (Gate on) limitation. The inherent constraint of the grouping and driving order of odd and even rows in the array (array substrate row drive) driving circuit enables the application of the same data voltage to sub-pixels of the same color that are separated by two rows in the TRD architecture without changing the internal physical structure of the panel, photomask design or GOA driving method. This allows for the successful realization of high refresh rate DLG display effect without introducing horizontal display unevenness or increasing additional manufacturing costs, effectively solving the long-standing technical problem that the TRD architecture cannot be compatible with DLG mode. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a structural block diagram of the first embodiment of the display driver architecture of this application; Figure 2 This is a schematic diagram of the TRD architecture involved in the embodiments of this application; Figure 3 This is a schematic diagram of a conventional architecture involved in the embodiments of this application; Figure 4 This is a schematic diagram of a single-column, single-data-line architecture corresponding to the TRD architecture involved in the embodiments of this application; Figure 5 This is a schematic diagram of a single-column dual-data-line architecture corresponding to the TRD architecture involved in the embodiments of this application; Figure 6 This is a schematic diagram of the first driving timing waveform of the TRD architecture involved in the embodiment of this application; Figure 7 This is a schematic diagram of the second driving timing waveform of the TRD architecture involved in the embodiment of this application; Figure 8 This application's embodiment relates to a display effect diagram in hardware super-resolution mode; Figure 9 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0020] Explanation of icon numbers: 10. Pixel; 20. Gate drive circuit; 30. Timing control module; 1001. Processor; 1002. Communication bus; 1003. User interface; 1004. Network interface; 1005. Memory.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0024] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] With the continuous development of display technology, users have placed higher demands on display solutions with high refresh rates and low costs. Currently, the industry typically adopts TRD (Tri-Row Drive) architecture and DLG (Dual Line Gate) mode as the mainstream technologies for improving refresh rates and reducing driving costs. However, in the TRD architecture, since the R, G, and B subpixels are arranged vertically and adjacent rows of subpixels have different colors, directly using the conventional DLG driving method to simultaneously activate two adjacent rows will cause data voltage to be charged into subpixels of the wrong color, resulting in abnormal images. If it is desired to charge subpixels of the same color simultaneously, subpixels in two rows separated by a certain number must be activated simultaneously. This conflicts with the constraint in the GOA (Gate on Array) driving circuit that odd and even rows are activated in a fixed order, making it impossible to directly implement the traditional DLG mode in the TRD architecture.

[0027] Currently, existing technologies attempt to address the technical challenges of implementing traditional DLG modes directly within the TRD architecture by altering the pixel arrangement architecture or adjusting the GOA driving method. Specifically, this involves connecting adjacent left and right sub-pixels to the same data line to achieve a horizontal DLG effect, or changing the bilateral GOA driving to a single-sided driving to match the activation timing of sub-pixels of the same color. However, these solutions all require modifications to the panel's internal structure or photomask design, increasing manufacturing costs and potentially leading to decreased display uniformity due to drive signal attenuation, resulting in horizontal bright and dark stripes and negatively impacting the visual experience.

[0028] Therefore, while maintaining the low-cost advantage of the TRD architecture, how to achieve an efficient and stable DLG driving mode has become a technical challenge that urgently needs to be solved in the display panel industry.

[0029] To address the aforementioned technical deficiencies, this application provides a display driver architecture and its timing control method, a display panel, and a display device.

[0030] This application provides a display driver architecture, which includes: A pixel array comprising a plurality of arrayed pixels 10, wherein each pixel 10 is composed of sub-pixels of different colors arranged sequentially along a column direction, and each sub-pixel in the same row has the same color.

[0031] In this embodiment, the pixel array adopts Figure 2 The TRD architecture shown here, where subpixels of different colors in pixel 10 are arranged vertically along the column direction and the subpixels in the same row have the same color, can reduce the number of horizontal subpixels to [number missing]. Figure 3 The pixel array is one-third the size of the conventional architecture shown (i.e., sub-pixels of different colors in pixel 10 are arranged horizontally along the row direction, and sub-pixels in the same column have the same color), thus significantly reducing the number of Source COF (Chip of Fabric) chips required for driving and achieving significant manufacturing cost optimization. Meanwhile, the pixel array is based on... Figure 2 The color distribution rules of pixel 10 in the TRD architecture shown provide a fixed and predictable sub-pixel layout for the timing control module 30, making it possible to perform precise timing control on sub-pixel rows of the same color. This is the structural basis for realizing DLG driving under the TRD architecture.

[0032] It should be noted that each pixel 10 in the pixel array is usually composed of... Figures 1 to 2 It consists of three sub-pixels: R (Red), G (Green), and B (Blue). These three sub-pixels are arranged in sequence along the column direction to form continuous color stripes.

[0033] In a specific embodiment, such as Figure 3 The image shows a physical resolution of 1920. A 1080p display panel with 1920 horizontal sub-pixels. 3=5760, the vertical sub-pixel count is 1080; if the pixel array of this display panel is changed from... Figure 3 The conventional architecture shown has been changed to Figure 2 The TRD architecture shown has 1920 horizontal sub-pixels and 1080 vertical sub-pixels for the display panel. 3=3240, based on Figure 2 The subpixel arrangement of the TRD architecture shown makes the number of horizontal subpixels become Figure 3 The architecture shown is 1 / 3 of the conventional architecture, which in turn reduces the number of source chips required to drive the subpixels to 1 / 3. Figure 3 The architecture shown is 1 / 3 of the conventional architecture, for a physical resolution of 1920. For a 1080p display panel, the number of source chips required is reduced from 6 to 2.

[0034] Gate driving circuit 20, which is electrically connected to the sub-pixels of the corresponding rows through each row of gate scan lines.

[0035] In this embodiment, the gate driving circuit 20 includes multiple cascaded GOA units, also called gate driving units. Each gate driving unit controls the on / off state of a row of sub-pixels through a gate scan line. The gate driving circuit 20 employs a bilateral driving design to ensure signal uniformity. Specifically, refer to... Figure 1 The gate driving circuits 20 are distributed on both sides of the pixel array. The gate driving circuit 20 on one side of the pixel array (i.e., the odd-numbered gate driving module) is electrically connected to the gate scan lines corresponding to the odd-numbered sub-pixel rows, while the gate driving circuit 20 on the other side of the pixel array (i.e., the even-numbered gate driving module) is electrically connected to the gate scan lines corresponding to the even-numbered sub-pixel rows. Thus, without changing the hardware constraints of the bilateral driving and odd-even row grouping connection, the gate driving timing in the dual-gate line driving mode can be adjusted by the timing control module 30, so that the two driving groups, odd and even, can be separated. The gate scan lines corresponding to the same color sub-pixel rows (such as row 1 and row 4) (i.e., gate scan line G1 for row 1 and gate scan line G4 for row 4) can be precisely and synchronously activated. Thus, while strictly adhering to the grouping order driving rules at the hardware level, the key operation necessary for DLG mode is successfully implemented at the functional level: activating two rows of the same color sub-pixel rows that could not be triggered simultaneously due to color misalignment and grouping limitations, and filling them with the same pixel grayscale data. This lays a solid foundation for achieving a doubling of refresh rate without changing any panel physical design.

[0036] Multiple gate scan lines can be gate scan lines G1, G2, G3, G4, G5, G6, ..., Gn, etc., each corresponding one-to-one with the sub-pixels arranged in rows in the pixel array. In the TRD architecture, sub-pixels are arranged sequentially in the column direction according to RGB color order, and sub-pixels in the same row have the same color. For example, gate scan line G1 controls the on / off state of the red sub-pixels in the first row; gate scan line G2 controls the on / off state of the green sub-pixels in the second row; gate scan line G3 controls the on / off state of the blue sub-pixels in the third row; gate scan line G4 corresponds to the red (R) sub-pixels in the fourth row, and so on, with every three rows forming a complete RGB pixel cycle.

[0037] A timing control module 30 is electrically connected to the gate driving circuit 20. The timing control module 30 is configured to provide a gate driving timing sequence to the gate driving circuit 20 in response to a preset dual gate line driving mode, and control the gate driving circuit 20 to perform gate driving on the pixel array according to the gate driving timing sequence, so that the gate scan lines corresponding to two sub-pixel rows that belong to the same color and are separated by two rows in the column direction are turned on simultaneously.

[0038] In this embodiment, in order to achieve a high refresh rate DLG mode under the TRD architecture, the timing control module 30 responds to the preset dual gate line driving mode (i.e., DLG mode) and is triggered to generate a gate driving timing that can realize the DLG mode under the TRD architecture according to the rule that the sub-pixel colors in the TRD pixel array are arranged in a periodic vertical direction (such as the R, G, B sequence cycle) and the hardware constraints of the inherent bilateral and odd-even group driving of the gate driving circuit 20. This successfully enables the same color sub-pixel rows that are spaced two rows apart in the column direction to be turned on simultaneously, overcoming the inherent constraint of the odd and even row group driving sequence in the GOA (Gate on Array) driving circuit. This allows the same data voltage to be applied directly to the same color sub-pixels that are spaced two rows apart in the TRD architecture without changing the internal physical structure of the panel, the photomask design or the GOA driving method. Thus, without introducing horizontal display unevenness or increasing additional manufacturing costs, a high refresh rate DLG display effect is successfully achieved, effectively solving the technical problem that the TRD architecture has long been unable to be compatible with the DLG mode.

[0039] Furthermore, in some other feasible embodiments, the data line connection architecture of the pixel array includes: A single-column single-data-line architecture, wherein the single-column single-data-line architecture is composed of rows of sub-pixels arranged continuously along a column direction and electrically connected to the same data line.

[0040] In this embodiment, Figure 4 The single-column, single-data-line architecture shown ensures that all consecutively arranged sub-pixels in each column are electrically connected to the same data line. This guarantees that, regardless of row position or color, the grayscale data of all sub-pixels in that column is provided by the same data line. Figure 4 The single-row single-data-line architecture shown provides the simplest and conflict-free data path foundation for the timing control module to implement gate drive timing in DLG mode or the more advanced HSR (Hardware Super Resolution) mode.

[0041] Specifically, due to Figure 4 The single-column, single-data-line architecture shown allows all sub-pixels within a column to share the same data line. When the timing control module controls the gate scan lines of two sub-pixel rows of the same color to be activated simultaneously (e.g., gate scan line G1 and gate scan line G4), the same pixel grayscale data is provided to the sub-pixels electrically connected to gate scan line G1 and gate scan line G4 in the corresponding column through the data line of each column, thereby achieving a high refresh rate DLG display effect. Simultaneously, Figure 4The single-column, single-data-line architecture shown can also achieve HSR display effects through inter-frame mixing, providing better visual clarity than DLG mode.

[0042] And / or, a single-column dual-data-line architecture, wherein the single-column dual-data-line architecture is configured to electrically connect all the sub-pixels in the latter half of the same column to the data lines of the corresponding column, and electrically connect all the sub-pixels in the first half of the same column to the next data line of the corresponding column data lines.

[0043] In this embodiment, Figure 5 The single-column dual-data-line architecture shown divides a column of sub-pixels vertically into a front half and a rear half. All sub-pixels in the rear half of the column are electrically connected to the corresponding column's data lines, and all sub-pixels in the front half of the column are electrically connected to the next data line of the corresponding column's data lines. Figure 5 The single-column dual-data-line architecture shown is based on the gate drive timing provided by the timing control module in the dual-gate-line drive mode. While achieving high refresh rate DLG display effect, it also introduces two data lines to share the driving load of a column of sub-pixels, reducing the wiring density and charging pressure of a single data line in ultra-high row counts (such as 3240 rows). This helps to reduce signal transmission delay, improve charging rate and optimize the wiring layout of the panel.

[0044] It should be noted that, referring to Figure 5 The first half of a column of subpixels includes at least one pixel driving unit, which is composed of two pixels arranged consecutively in the column direction.

[0045] In a specific embodiment, with Figure 5Taking the first column from left to right as an example, where all sub-pixels are in the first sub-pixel row / column, gate scan line G1 corresponds to the first row, gate scan line G2 corresponds to the second row, gate scan line G3 corresponds to the third row, and so on. The first to sixth rows of sub-pixels in the first sub-pixel row / column constitute the first half of the first sub-pixel row / column, and the seventh to twelfth rows of sub-pixels constitute the second half of the first sub-pixel row / column. Next, the second half of the sub-pixels in the first sub-pixel row / column is electrically connected to the corresponding data line S1, and the first half of the sub-pixels in the first sub-pixel row / column is electrically connected to the next data line (i.e., data line S2). The timing control module provides the gate driving timing in the dual-gate line driving mode to the gate driving circuit to control the gate driving circuit to synchronously open the gate scan lines corresponding to the first and fourth red sub-pixels in the first sub-pixel row / column, since both the first and fourth red sub-pixels in the first sub-pixel row / column are connected to data line S2. At this time, the pixel grayscale data representing the grayscale change of the red sub-pixel output on the data line S2 can be accurately written to the first row of red sub-pixels and the fourth row of red sub-pixels in the first sub-pixel row and column at the same time, thereby realizing the DLG display effect of charging in two rows of the same color.

[0046] Furthermore, based on the first embodiment of the display driver architecture of this application, a second embodiment of the timing control method of this application is proposed.

[0047] The timing control method of this application is applied to the display driver architecture described above. The timing control method of this application is executed by the display device applied to the display driver architecture. The timing control method of this application includes the following implementation steps S10.

[0048] Step S10: In response to the preset dual gate line driving mode, the timing control module provides the gate driving timing to the gate driving circuit and controls the gate driving circuit to drive the pixel array according to the gate driving timing, so that the gate scan lines corresponding to two sub-pixel rows of the same color and separated by two rows in the column direction are turned on simultaneously.

[0049] In this embodiment, when the row scanning mode of the pixel array switches from the conventional progressive scan mode to the preset dual gate line drive mode, the timing control module is activated in this dual gate line drive mode to generate a gate drive timing sequence (i.e., the first drive timing sequence) that is compatible with the DLG mode under the TRD architecture, based on the TRD architecture characteristics of the pixel array and the hardware constraints of the dual-side drive of the gate drive circuit. The gate drive timing sequence characterizing the first drive timing sequence is provided to the gate drive circuit to control the gate drive circuit to perform gate drive on the pixel array according to the gate drive timing sequence characterizing the first drive timing sequence. This allows the same color sub-pixel rows that are spaced two rows apart in the column direction to be opened simultaneously, overcoming the GOA (Gateway-Oriented Alternating Current) problem. The inherent constraint of the grouping and sequential driving of odd and even rows in the onArray (array substrate row drive) driving circuit allows for the direct application of the same data voltage to sub-pixels of the same color that are separated by two rows in the TRD architecture without changing the internal physical structure of the panel, photomask design, or GOA driving method. This enables the successful realization of high refresh rate DLG display effect without introducing horizontal display unevenness or increasing additional manufacturing costs, effectively solving the long-standing technical problem that the TRD architecture cannot be compatible with DLG mode.

[0050] It should be noted that the signal waveform diagram for the gate drive timing as the first drive timing can be referred to Figure 6 As shown. Figure 6 In this context, "Data" represents pixel grayscale data; specifically, pixel grayscale data "Data" can be... Figure 6 The data shown are R1, B1, C1, R2, B2, and C2.

[0051] Furthermore, in some feasible embodiments, the timing control method may include the following implementation step A10.

[0052] Step A10: In response to the pixel array's data line connection architecture being at least one of a single-column single-data-line architecture and a single-column dual-data-line architecture, the gate driving timing is determined to be the first driving timing.

[0053] In this embodiment, due to the limitations of the bilateral driving design of the gate driving circuit, the opening sequence of odd-numbered rows of the odd-numbered gate driving module can only be 2N+1, 2N+3, 2N+5..., while the opening sequence of even-numbered rows of the even-numbered gate driving module is 2N+2, 2N+4, 2N+6..., where N is a non-negative integer. This inherent bilateral driving grouping order rule directly contradicts the goal of "simultaneous opening of rows 2N+1 and 2N+4" expected in the DLG mode (i.e., synchronously filling the same pixel grayscale data into sub-pixel rows of the same color that are spaced two rows apart). To resolve the aforementioned contradiction, when the timing control module detects that the pixel array's data line connection architecture is at least one of a single-column single-data-line architecture or a single-column dual-data-line architecture, it selects a first driving timing sequence matching the connection architecture characteristics as the gate driving timing sequence in DLG mode. This lays a fundamental timing foundation for the reliable and efficient implementation of DLG functionality in TRD panel designs corresponding to single-column single-data-line or single-column dual-data-line architectures. Next, this gate driving timing sequence is applied to the gate driving circuit, causing the gate driving signal output by the gate driving circuit under the first driving timing sequence to synchronously activate the gate scan lines corresponding to the same-color sub-pixel rows spaced two rows apart in the column direction, overcoming the GOA (Gate on...) problem. The inherent constraint of the grouping and driving order of odd and even rows in the array (array substrate row drive) driving circuit enables the application of the same data voltage to sub-pixels of the same color that are separated by two rows in the TRD architecture without changing the internal physical structure of the panel, photomask design or GOA driving method. This allows for the successful realization of high refresh rate DLG display effect without introducing horizontal display unevenness or increasing additional manufacturing costs, effectively solving the long-standing technical problem that the TRD architecture cannot be compatible with DLG mode.

[0054] Furthermore, in some other feasible embodiments, the operation steps corresponding to the first driving timing in step A10 above may include the following implementation steps B10 to B40.

[0055] Step B10: A pixel driving unit is formed by two consecutive pixel rows arranged in the column direction. The pixel driving unit includes a first sub-pixel row and a fourth sub-pixel row, a second sub-pixel row and a fifth sub-pixel row, and a third sub-pixel row and a sixth sub-pixel row, all of the same color. One of the two pixel rows is composed of the first sub-pixel row, the second sub-pixel row, and the third sub-pixel row, and the other pixel row is composed of the third sub-pixel row, the fourth sub-pixel row, and the fifth sub-pixel row.

[0056] In this embodiment, a pixel array using a TRD architecture is defined as a pixel driving unit consisting of two consecutive rows of pixels arranged in the column direction. This pixel driving unit integrates three pairs of sub-pixel rows with the same color and spaced two rows apart: a first sub-pixel row 6N+1 and a fourth sub-pixel row 6N+4 both red; a second sub-pixel row 6N+2 and a fifth sub-pixel row 6N+5 both green; and a third sub-pixel row 6N+3 and a sixth sub-pixel row 6N+6 both blue. In other words, this application, through the model of the aforementioned pixel driving unit, reduces the number of sub-pixel rows that originally involved thousands of rows. The complex full-screen driving problem is decomposed into repetitive and standardized timing operations on individual pixel driving units with identical structures. This not only provides a concise and accurate physical logic framework for describing the operation steps corresponding to the first driving timing, but more importantly, the construction of this pixel driving unit reveals the inherent color correspondence and timing dependency between each sub-pixel row in the driving process of the gate driving circuit based on the first driving timing. This ensures that the gate scan lines corresponding to the same color sub-pixel rows that are spaced two rows apart in the column direction achieve the charging target of synchronous activation in DLG mode, which can be systematically and periodically achieved.

[0057] It should be noted that, since N is a non-negative integer, the first sub-pixel row 6N+1 can be understood as the first row of sub-pixels of the (N+1)th pixel driving unit; the second sub-pixel row 6N+2 can be understood as the second row of sub-pixels of the (N+1)th pixel driving unit; the third sub-pixel row 6N+3 can be understood as the third row of sub-pixels of the (N+1)th pixel driving unit; the fourth sub-pixel row 6N+4 can be understood as the fourth row of sub-pixels of the (N+1)th pixel driving unit; the fifth sub-pixel row 6N+5 can be understood as the fifth row of sub-pixels of the (N+1)th pixel driving unit; and the sixth sub-pixel row 6N+6 can be understood as the sixth row of sub-pixels of the (N+1)th pixel driving unit.

[0058] Figure 6 The sub-pixel lines corresponding to gate scan lines G1 to G6 shown represent a pixel driving unit. An adjacent pixel driving unit refers to... Figure 6 The sub-pixel rows corresponding to gate scan lines G7 to G12 are shown. For example, taking a pixel driving unit constructed from the sub-pixel rows corresponding to gate scan lines G1 to G6, the sub-pixel row corresponding to gate scan line G1 refers to the first sub-pixel row 6N+1; the sub-pixel row corresponding to gate scan line G2 refers to the second sub-pixel row 6N+2; the sub-pixel row corresponding to gate scan line G3 refers to the third sub-pixel row 6N+3; the sub-pixel row corresponding to gate scan line G4 refers to the fourth sub-pixel row 6N+4; the sub-pixel row corresponding to gate scan line G5 refers to the fifth sub-pixel row 6N+5; and the sub-pixel row corresponding to gate scan line G6 refers to the sixth sub-pixel row 6N+6.

[0059] Step B20: In each pixel driving unit, the gate scan line where the second sub-pixel row is located is turned on, and while delaying the turn-on time of the gate scan line where the second sub-pixel row is located, the gate scan lines corresponding to the first sub-pixel row and the fourth sub-pixel row are controlled to be turned on synchronously.

[0060] In this embodiment, taking the pixel driving unit constructed from the sub-pixel rows corresponding to gate scan lines G1 to G6 as an example, firstly, the even-numbered gate driving module outputs a high-level gate scan signal to turn on the gate scan line G2 corresponding to the second sub-pixel row 6N+2, and the turn-on time of the gate scan line G2 where the second sub-pixel row 6N+2 is located is extended by delaying the duration of the high-level pulse of the gate scan signal acting on the gate scan line G2; then, when the odd-numbered gate driving module outputs a high-level gate scan signal to turn on the gate scan line G1 where the first sub-pixel row (i.e., the red pixel row) 6N+1 is located, the even-numbered gate driving module simultaneously outputs a high-level gate scan signal to turn on the gate scan line G4 where the fourth sub-pixel row (i.e., the red pixel row) 6N+4 is located, so that the first sub-pixel row (i.e., the red pixel row) 6N+1 and the fourth sub-pixel row (i.e., the red pixel row) 6N+4 are simultaneously charged. Figure 6 The pixel grayscale data R1 shown overcomes the fundamental technical defect in the TRD architecture that prevents the simultaneous activation of sub-pixel rows of the same color belonging to different driving groups (such as 6N+1 and 6N+4) due to the inherent odd-even row grouping driving rule of the gate driving circuit. This allows two rows of red sub-pixel rows that were originally unable to align due to the odd-even row grouping driving rule to be activated precisely and synchronously, thus providing a crucial timing window for the same color sub-pixel pairs required by the DLG mode to be filled with the same data at the same time.

[0061] Step B30: After the first sub-pixel row and the fourth sub-pixel row are simultaneously filled with the same pixel grayscale data, the gate scan lines corresponding to the third sub-pixel row and the sixth sub-pixel row are triggered to be turned on synchronously.

[0062] In this embodiment, the first sub-pixel row (i.e., the red pixel row) 6N+1 and the fourth sub-pixel row (i.e., the red pixel row) 6N+4 are simultaneously filled. Figure 6 After the pixel grayscale data R1 is shown, when the odd-numbered gate drive module outputs a high-level gate scan signal to turn on the gate scan line G3 where the third sub-pixel row (i.e., the blue pixel row) 6N+3 is located, the even-numbered gate drive module simultaneously outputs a high-level gate scan signal to turn on the gate scan line G6 where the sixth sub-pixel row (i.e., the blue pixel row) 6N+6 is located, so that the third sub-pixel row (i.e., the blue pixel row) 6N+3 and the sixth sub-pixel row (i.e., the blue pixel row) 6N+6 are simultaneously filled. Figure 6The pixel grayscale data B1 shown enables the synchronous activation of two blue sub-pixel rows in DLG mode.

[0063] Step B40: After the third sub-pixel row and the sixth sub-pixel row are synchronously filled with the same pixel grayscale data, the gate scan line where the fifth sub-pixel row is located is triggered to turn on, and the delayed turn-on time is cut off until the gate scan line where the fifth sub-pixel row is located is turned off, so that the second sub-pixel row receives and maintains the same pixel grayscale data as the fifth sub-pixel row.

[0064] In this embodiment, the third sub-pixel row (i.e., the blue pixel row) 6N+3 and the sixth sub-pixel row (i.e., the blue pixel row) 6N+6 are simultaneously filled. Figure 6 After the pixel grayscale data B1 is shown, the data synchronization writing of the last pair of green sub-pixel rows (i.e., the second sub-pixel row 6N+2 and the fifth sub-pixel row 6N+5) in the pixel driving unit is completed. Specifically, the gate scan signal corresponding to the fifth sub-pixel row 6N+5 is first turned on by outputting a high-level gate scan signal through the odd gate driving module, and the gate scan signal of the gate scan line G2 where the second sub-pixel row 6N+2 is located is extended in step S20. That is, the cutoff time (falling edge) of the gate scan signal acting on the gate scan line G2 when it is in the high-level pulse is precisely aligned with the turn-off time of the gate scan line G5, so as to construct the data latch synchronization window of the second sub-pixel row 6N+2 and the fifth sub-pixel row 6N+5. Within this data latching synchronization window, although the earliest activated second sub-pixel row 6N+2 experiences voltage changes in its corresponding pixel grayscale data R1 and pixel grayscale data B1 sequentially during the extended activation period, when the gate scan signals corresponding to gate scan lines G2 and G5 synchronously switch from high-level pulses to low-level pulses—that is, at the instant gate scan lines G2 and G5 synchronously close—this second sub-pixel row 6N+2 synchronously latches the data charged by the fifth sub-pixel row 6N+5. Figure 6 The pixel grayscale data C1 shown implicitly and equivalently realizes the synchronous charging of the two green sub-pixel rows, ensuring that the three pairs of sub-pixel rows of the same color in the pixel driving unit can complete the correct data writing, thus fully realizing the high refresh rate driving target of DLG mode at the system level.

[0065] Furthermore, in some feasible embodiments, the timing control method may also include the following implementation step C10.

[0066] Step C10: Based on the response of the single-row single-data-line architecture to the preset hardware super-resolution mode, the gate driving timing is switched from the first driving timing to the alternating driving timing. The alternating driving timing is configured to alternately execute the first driving timing and the preset second driving timing during multiple consecutive frame refresh cycles.

[0067] In this embodiment, this application Figure 4 The single-column single-data-line architecture shown, building upon the successful implementation of basic DLG high refresh rate functionality, further unlocks a more advanced hardware super-resolution mode. Specifically, based on the single-column single-data-line architecture's response to the preset hardware super-resolution mode, the timing control module switches the gate drive timing from the first drive timing to an alternating drive timing and provides it to the gate drive circuit. Since this alternating drive timing is configured to alternately execute the first drive timing and a preset second drive timing within multiple consecutive frame refresh cycles, the gate drive circuit alternately executes the gate scan operations corresponding to the first and second drive timings within these consecutive frame refresh cycles. This maintains a high refresh rate while visually blending and compensating for the portion of image information lost due to the sacrifice of vertical physical resolution in DLG mode, i.e., alternately displaying the corresponding data from the first drive timing. Figure 8 The DLG screen shown in (a) and the corresponding second drive timing are shown in the image. Figure 8 As shown in (b) of the image, the DLG image exhibits sub-pixel-level misalignment in the pixel space. When viewed continuously, the human eye perceives the two alternating DLG images as a single image with higher visual clarity. Figure 8 The image shown in (c) demonstrates how a pure timing control method with alternating drive timing can intelligently balance the usually contradictory requirements of high refresh rate and high definition without increasing data transmission bandwidth or changing the physical structure of the panel. This significantly improves the visual experience and detail of dynamic images, adding more competitive high-end display functions to TRD architecture products.

[0068] It should be noted that the successful implementation of the hardware super-resolution mode relies heavily on the electrical foundation provided by the single-column, single-data-line architecture, where all sub-pixels in the entire column are driven by the same data line. The alternating drive timing provided by the timing control module can only achieve the more advanced hardware super-resolution mode when applied to the single-column, single-data-line architecture.

[0069] The display effect corresponding to the hardware super resolution mode Figure 8 In the image shown in (c), the sub-pixels in row 2N+1 are filled with the normally displayed pixel grayscale data, and the sub-pixels in row 2N+2 are filled with a mixture of the pixel grayscale data from rows 2N+1 and 2N+3. N is a non-negative integer.

[0070] The signal waveform diagram for the second driving timing can be referenced. Figure 7 As shown. Figure 7 In this context, "Data" represents pixel grayscale data; specifically, pixel grayscale data "Data" can be... Figure 7 The data shown are R1, B1, C1, R2, B2, C2, R3, B3, and C3.

[0071] Furthermore, in some other feasible embodiments, the operation steps corresponding to the second driving timing in step C10 above may include the following implementation steps D10 to D40.

[0072] Step D10: In the pixel driving unit, after sequentially turning on the gate scan lines corresponding to the first sub-pixel row and the third sub-pixel row, when turning on the gate scan line where the second sub-pixel row is located, the gate scan line where the fifth sub-pixel row is located is simultaneously turned on, and the turn-on time of the gate scan line where the fifth sub-pixel row is located is delayed.

[0073] In this embodiment, the current pixel driving unit is the sub-pixel row corresponding to gate scan lines G1 to G6, and the next pixel driving unit is the sub-pixel row corresponding to gate scan lines G7 to G12. Specifically, firstly, the odd-numbered gate driving module is used according to... Figure 7 The second driving timing output high-level gate scan signal sequentially turns on the gate scan lines G1 and G3 corresponding to the first sub-pixel (i.e., the red sub-pixel row) 6N+1 and the third sub-pixel (i.e., the blue sub-pixel row) 6N+3, respectively. This allows the red sub-pixel row 6N+1 and the blue sub-pixel row 6N+3 to be sequentially filled with the corresponding pixel grayscale data R1 and pixel grayscale data B1. Subsequently, when the even-number gate driving module outputs a high-level gate scan signal to turn on the gate scan line G2 corresponding to the second sub-pixel (i.e., the green sub-pixel row) 6N+2, the odd-number gate driving module simultaneously outputs a high-level gate scan signal to turn on the gate scan line G5 corresponding to the fifth sub-pixel (i.e., the green sub-pixel row) 6N+5, and delays the opening time of the gate scan line G5 where the fifth sub-pixel (i.e., the green sub-pixel row) 6N+5 is located. This allows the opening state of the gate scan line G5 to cover the gate scan operation corresponding to the next pixel driving unit of the current pixel driving unit, thus providing a key time window for solving the data transmission and alignment problem across units caused by the change in timing structure.

[0074] Step D20: While delaying the opening time of the gate scan line where the fifth sub-pixel row is located, control the gate scan lines corresponding to the fourth sub-pixel row in the pixel driving unit and the first sub-pixel row in the next pixel driving unit to be opened synchronously so as to fill in the same pixel grayscale data.

[0075] In this embodiment, when the gate scan line G5 is still in the delayed on state, the timing control module controls the even-numbered gate drive module to output a high-level gate scan signal to turn on the gate scan line G4 corresponding to the fourth sub-pixel (i.e., the red sub-pixel row) 6N+4. Simultaneously, the odd-numbered gate drive module outputs a high-level gate scan signal to turn on the gate scan line G7 corresponding to the first sub-pixel (i.e., the red sub-pixel row) 6(N+1)+1 in the next pixel drive unit. At this time, because the single-column single-data-line architecture ensures that the red sub-pixels in the same column 6N+4 and 6(N+1)+1 are connected to the same data line, the same red pixel grayscale data (e.g., ...) provided by this data line... Figure 7 The pixel grayscale data R2 shown is simultaneously written into the red sub-pixels in the same column 6N+4 and 6(N+1)+1, thereby realizing cross-unit synchronous charging of the red sub-pixels in the current pixel driving unit in the 6N+4 row and the red sub-pixels in the next pixel driving unit in the 6(N+1)+1 row, and creating spatial dislocations for the visual blending required to achieve HSR in the future.

[0076] Step D30: Control the gate scan lines corresponding to the sixth sub-pixel row in the pixel driving unit and the third sub-pixel row in the next pixel driving unit to be turned on synchronously so as to fill in the same pixel grayscale data.

[0077] In this embodiment, immediately following step D20, the gate drive circuit, provided by the timing control module... Figure 7 Under the second driving timing shown, when the even-numbered gate driving module outputs a high-level gate scan signal to enable the gate scan line G6 corresponding to the sixth sub-pixel (i.e., the blue sub-pixel row) 6N+6, the odd-numbered gate driving module simultaneously outputs a high-level gate scan signal to enable the gate scan line G9 corresponding to the third sub-pixel (i.e., the blue sub-pixel row) 6(N+1)+3 in the next pixel driving unit. At this time, due to the single-column single-data-line architecture, the blue sub-pixels in the same column 6N+6 and 6(N+1)+3 are connected to the same data line, and the same blue pixel grayscale data (e.g., the data line provides the same blue pixel grayscale data) Figure 7The pixel grayscale data B2 shown is simultaneously written into the blue sub-pixels in the same column 6N+6 and 6(N+1)+3, thereby realizing the synchronous charging of the blue sub-pixels in the current pixel driving unit in the 6N+6 row and the blue sub-pixels in the next pixel driving unit across units. This is in stark contrast to the strict "same color row pairing within the unit" structure of the first driving sequence, and is the basis for the alternating driving to produce super-resolution visual mixing effects.

[0078] Step D40: Trigger the gate scan line where the second sub-pixel row is located in the next pixel driving unit to turn on, and extend the delayed turn-on time until the gate scan line where the second sub-pixel row is located in the next pixel driving unit turns off, so that the fifth sub-pixel row in the pixel driving unit receives and maintains the same pixel grayscale data as the second sub-pixel row in the next pixel driving unit.

[0079] In this embodiment, immediately following step D30, the timing control module triggers the even-numbered gate driving module to output a high-level gate scan signal to enable the gate scan line G8 corresponding to the second sub-pixel (i.e., the green sub-pixel row) 6(N+1)+2 in the next pixel driving unit. Simultaneously, the timing control module precisely controls the cutoff time (falling edge) of the gate high-level signal acting on the gate scan line G5 where the fifth sub-pixel (i.e., the green sub-pixel row) 6N+5 is located, which has been delayed since step D10 in the current pixel driving unit, to be completely synchronized with the closing time of the gate scan line G8; that is, when the gate scan line G5 and the gate scan line G8 are closed synchronously, it ensures that the fifth sub-pixel row (i.e., the green sub-pixel row) 6N+5 in the current pixel driving unit receives and maintains the same green pixel grayscale data (e.g., as in the second sub-pixel row (i.e., the green sub-pixel row) 6(N+1)+2 in the next pixel driving unit. Figure 7 The pixel grayscale data C2 shown realizes the precise alignment and synchronous transmission of green sub-pixel data between adjacent pixel driving units, providing a basis for generating... Figure 8 The DLG screen shown in (b) lays the final foundation.

[0080] In summary, this application provides a display driving architecture that successfully solves the technical defect of the TRD architecture being incompatible with the DLG (Dual Line Gate) mode by introducing a timing control module and configuring a preset gate driving timing under the TRD (Tri-Row Drive) architecture. Specifically, firstly, based on the inherent pixel arrangement of the TRD architecture—that is, sub-pixels of different colors in a pixel are arranged sequentially along the column direction and sub-pixels in the same row are of the same color—a fixed and reliable physical basis is provided for the timing control of the subsequent timing control module. Next, based on the response of the timing control module to the preset dual-gate line drive mode, the reconstructed gate driving timing is output to the gate driving circuit, thereby controlling the gate driving circuit to synchronously turn on the gate scan lines corresponding to the same color sub-pixel rows that are two rows apart in the column direction, while maintaining its original bilateral driving and odd-even row grouping sequence driving physical constraints. This ensures that the gate scan lines corresponding to two sub-pixel rows of the same color that are two rows apart in the column direction are turned on simultaneously, overcoming the GOA (Gate on The inherent constraint of the grouping and driving order of odd and even rows in the array (array substrate row drive) driving circuit enables the application of the same data voltage to sub-pixels of the same color that are separated by two rows in the TRD architecture without changing the internal physical structure of the panel, photomask design or GOA driving method. This allows for the successful realization of high refresh rate DLG display effect without introducing horizontal display unevenness or increasing additional manufacturing costs, effectively solving the long-standing technical problem that the TRD architecture cannot be compatible with DLG mode.

[0081] Furthermore, this application also provides a display panel, the display panel including the display driving architecture described above; the display panel further includes a display area and a non-display area disposed around the periphery of the display area; the pixel array in the display driving architecture is disposed within the display area; the non-display area is provided with a gate driving circuit in the display driving architecture, the gate driving circuit being disposed on both sides of the display area; the timing control module in the display driving architecture is disposed on a circuit assembly board, the circuit assembly board being disposed on the side closer to the non-display area and farther from the display area.

[0082] Furthermore, in some feasible embodiments, the gate driving circuit disposed on one side of the display area is electrically connected to the gate scan lines corresponding to the odd-numbered sub-pixel rows; the gate driving circuit disposed on the other side of the display area is electrically connected to the gate scan lines corresponding to the even-numbered sub-pixel rows.

[0083] In addition, this application also provides a display device. Please refer to... Figure 9 , Figure 9This is a schematic diagram of the structure of a display device involved in an embodiment of this application. Specifically, the display device in this embodiment may be a device for a locally running sequence control method.

[0084] The display device includes the display panel described above, and the display device is configured to perform the steps of the timing control method described above.

[0085] like Figure 9 As shown in the embodiments of this application, the display device may further include: a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to implement communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0086] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0087] Those skilled in the art will understand that Figure 9 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0088] like Figure 9 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a driver program.

[0089] exist Figure 9 In the display device shown, the processor 1001 can be used to call the driver stored in the memory 1005 and execute the steps of the timing control method described above.

[0090] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0091] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0093] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display driver architecture, characterized in that, The display driver architecture includes: A pixel array comprising a plurality of pixels distributed in an array, wherein the pixels are composed of sub-pixels of different colors arranged sequentially along a column direction, and the sub-pixels in the same row have the same color; A gate driving circuit, wherein the gate driving circuit is electrically connected to the sub-pixels of the corresponding rows through each row of gate scan lines; A timing control module is electrically connected to the gate driving circuit. The timing control module is configured to provide a gate driving timing to the gate driving circuit in response to a preset dual gate line driving mode, and control the gate driving circuit to perform gate driving on the pixel array according to the gate driving timing, so that the gate scan lines corresponding to two sub-pixel rows that belong to the same color and are separated by two rows in the column direction are turned on simultaneously.

2. The display driver architecture as described in claim 1, characterized in that, The data line connection architecture of the pixel array includes: A single-column, single-data-line architecture, wherein the single-column, single-data-line architecture is composed of rows of sub-pixels arranged continuously along a column direction, electrically connected to the same data line; and / or, A single-column dual-data-line architecture is configured to electrically connect all the sub-pixels in the latter half of the same column to the data lines of the corresponding column, and to electrically connect all the sub-pixels in the first half of the same column to the next data line of the corresponding column data lines.

3. A timing control method, characterized in that, The timing control method is applied to the display driver architecture according to any one of claims 1 to 2, and the timing control method includes: In response to a preset dual gate line driving mode, the timing control module provides the gate driving timing to the gate driving circuit and controls the gate driving circuit to drive the pixel array according to the gate driving timing, so that the gate scan lines corresponding to two sub-pixel rows of the same color and separated by two rows in the column direction are turned on simultaneously.

4. The timing control method as described in claim 3, characterized in that, The timing control method includes: In response to the pixel array's data line connection architecture being at least one of a single-column single-data-line architecture and a single-column dual-data-line architecture, the gate driving timing is determined to be the first driving timing.

5. The timing control method as described in claim 4, characterized in that, The operation steps corresponding to the first driving timing include: A pixel driving unit is defined as two consecutive rows of pixels arranged in a column direction. The pixel driving unit includes a first sub-pixel row and a fourth sub-pixel row, a second sub-pixel row and a fifth sub-pixel row, and a third sub-pixel row and a sixth sub-pixel row, all of the same color. One of the two pixel rows is composed of the first sub-pixel row, the second sub-pixel row, and the third sub-pixel row, while the other pixel row is composed of the third sub-pixel row, the fourth sub-pixel row, and the fifth sub-pixel row. In each of the pixel driving units, the gate scan line where the second sub-pixel row is located is turned on, and while delaying the turn-on time of the gate scan line where the second sub-pixel row is located, the gate scan lines corresponding to the first sub-pixel row and the fourth sub-pixel row are controlled to be turned on synchronously. After the first sub-pixel row and the fourth sub-pixel row are simultaneously filled with the same pixel grayscale data, the gate scan lines corresponding to the third sub-pixel row and the sixth sub-pixel row are triggered to be turned on synchronously. After the third sub-pixel row and the sixth sub-pixel row are synchronously filled with the same pixel grayscale data, the gate scan line where the fifth sub-pixel row is located is triggered to turn on, and the delayed turn-on time is cut off when the gate scan line where the fifth sub-pixel row is located is turned off, so that the second sub-pixel row receives and maintains the same pixel grayscale data as the fifth sub-pixel row.

6. The timing control method as described in claim 5, characterized in that, The timing control method includes: Based on the response of the single-row single-data-line architecture to the preset hardware super-resolution mode, the gate driving timing is switched from the first driving timing to an alternating driving timing. The alternating driving timing is configured to alternately execute the first driving timing and the preset second driving timing during multiple consecutive frame refresh cycles.

7. The timing control method as described in claim 6, characterized in that, The operation steps corresponding to the second driving timing include: In the pixel driving unit, after the gate scan lines corresponding to the first sub-pixel row and the third sub-pixel row are turned on in sequence, when the gate scan line where the second sub-pixel row is located is turned on, the gate scan line where the fifth sub-pixel row is located is turned on simultaneously, and the turn-on time of the gate scan line where the fifth sub-pixel row is located is delayed. While delaying the opening time of the gate scan line where the fifth sub-pixel row is located, the gate scan lines corresponding to the fourth sub-pixel row in the pixel driving unit and the first sub-pixel row in the next pixel driving unit are controlled to be opened synchronously so as to fill in the same pixel grayscale data. The gate scan lines corresponding to the sixth sub-pixel row in the pixel driving unit and the third sub-pixel row in the next pixel driving unit are synchronously turned on so as to fill in the same pixel grayscale data; The gate scan line where the second sub-pixel row is located in the next pixel driving unit is triggered to turn on, and the delayed turn-on time is cut off when the gate scan line where the second sub-pixel row is located in the next pixel driving unit is turned off, so that the second sub-pixel row in the pixel driving unit receives and maintains the same pixel grayscale data as the second sub-pixel row in the next pixel driving unit.

8. A display panel, characterized in that, The display panel includes the display driving architecture according to any one of claims 1 to 2; The display panel further includes a display area and a non-display area surrounding the display area; The pixel array in the display driver architecture is disposed within the display area; The non-display area is provided with the gate driving circuit in the display driving architecture, and the gate driving circuit is disposed on both sides of the display area; The timing control module in the display driver architecture is located on the circuit assembly board, which is positioned on the side of the circuit assembly board closer to the non-display area and farther from the display area.

9. The display panel as described in claim 8, characterized in that, The gate driving circuit located on one side of the display area is electrically connected to the gate scan lines corresponding to the odd number of sub-pixel rows. The gate driving circuit, located on the other side of the display area, is electrically connected to the gate scan lines corresponding to the even-numbered sub-pixel rows.

10. A display device, characterized in that, The display device includes the display panel as described in any one of claims 8 to 9, and the display device is configured to perform the steps of the timing control method as described in any one of claims 3 to 7.

Images