Solid-state battery and preparation method, preparation equipment and power utilization equipment thereof

Abstract

This application relates to a solid-state battery, a preparation method thereof, preparation equipment, and an electrical equipment. The solid-state battery of this application includes a positive electrode, a sulfide solid electrolyte layer, and a nanocrystal layer; the positive electrode and the nanocrystal layer are respectively located on two opposite surfaces of the sulfide solid electrolyte layer; the material of the nanocrystal layer includes at least one of a lithium-silicon compound, a lithium-silicon-germanium compound, and a doped or undoped lithium-germanium compound; the lithium-silicon compound includes at least one of Li 12 Si7, Li 13 Si4, and Li7Si3 and at least includes Li 12 Si7; the lithium-silicon-germanium compound includes Li 12 (Si 1‑x Ge x )7, where 0 < x ≤ 0.3; the lithium-germanium compound includes at least one of Li 12 Ge7, Li7Ge3, and Li 13 Ge4, and the doping element in the lithium-germanium compound includes at least one of Al, Ga, and B; the grain diameter in the nanocrystal layer is 3 nm to 20 nm; the solid-state battery has no initial negative electrode. The solid-state battery of this application can deposit lithium orderly on the surface of the sulfide solid electrolyte, and the nucleation overpotential is relatively low.

Description

Technical Field

[0001] This application relates to the technical field of solid-state batteries, in particular to solid-state batteries, their preparation methods, preparation equipment, and electrical equipment. Background Art

[0002] All-solid-state batteries use solid electrolytes to replace flammable liquid electrolytes and are an important development direction for next-generation high-energy-density batteries. Among them, the lithium-free solid-state battery can maximize the energy density of the battery by completely eliminating the initial lithium metal anode and relying only on the lithium extracted from the cathode to in-situ form an anode on the current collector. Sulfide solid electrolytes are considered to be one of the most promising solid electrolytes due to their high room-temperature ionic conductivity, good mechanical ductility, and low grain boundary impedance. However, in lithium-free solid-state batteries, directly depositing lithium on the surface of sulfide solid electrolytes faces severe challenges. The first nucleation is highly random, resulting in a too high nucleation overpotential. At the same time, the uneven nucleation distribution will evolve into dendritic growth, eventually piercing the electrolyte and causing a short circuit, and the contact between lithium and sulfide solid electrolyte is also prone to trigger interfacial reduction decomposition, forming a high-impedance layer and consuming active lithium. Summary of the Invention

[0003] Based on this, it is necessary to provide a solid-state battery, its preparation method, preparation equipment, and electrical equipment. The solid-state battery of this application can deposit lithium orderly on the surface of sulfide solid electrolyte with a lower nucleation overpotential.

[0004] In a first aspect, this application provides a solid-state battery, including a positive electrode, a sulfide solid electrolyte layer, and a nanocrystal layer; the positive electrode and the nanocrystal layer are respectively located on two opposite surfaces of the sulfide solid electrolyte layer; the material of the nanocrystal layer includes at least one of lithium-silicon compounds, lithium-silicon-germanium compounds, and doped or undoped lithium-germanium compounds; the lithium-silicon compounds include at least one of Li 12 Si7, Li 13 Si4, and Li7Si3 and at least includes Li 12 Si7; the lithium-silicon-germanium compounds include Li 12 (Si 1-x Ge x )7, where 0 < x ≤ 0.3; the lithium-germanium compounds include at least one of Li 12 Ge7, Li7Ge3, and Li 13 Ge4, and the doping elements in the lithium-germanium compounds include at least one of Al, Ga, and B; the grain diameter in the nanocrystal layer is 3 nm to 20 nm; the solid-state battery has no initial negative electrode.

[0005] In some embodiments, in the lithium-silicon compound, Li 12The molar percentage of Si7 is 80%~100%.

[0006] In some embodiments, the molar ratio of the dopant element to Ge in the doped lithium germanium compound is (0.001~0.02):1.

[0007] In some embodiments, the thickness of the nanocrystalline layer is 8 nm to 40 nm.

[0008] In some embodiments, the material of the sulfide solid electrolyte layer includes Li6PS5X and Li7P3S. 11 Li 10 GeP2S 12 And at least one of Li3PS4, wherein X represents Cl, Br or I.

[0009] In some embodiments, the relative density of the sulfide solid electrolyte layer is greater than or equal to 95%.

[0010] In some embodiments, the surface roughness Ra of the sulfide solid electrolyte layer is 20 nm to 100 nm.

[0011] In some embodiments, the water and oxygen content of the sulfide solid electrolyte layer is less than or equal to 10 ppm.

[0012] In some embodiments, a transition layer is also included; the transition layer is located between the sulfide solid electrolyte and the nanocrystalline layer; the transition layer is a Si transition layer or a Li3PS4 transition layer.

[0013] In some embodiments, the thickness of the Si transition layer is 1 nm to 3 nm.

[0014] In some embodiments, the thickness of the Li3PS4 transition layer is 1 nm to 2 nm.

[0015] Secondly, this application provides a method for preparing a solid-state battery as described in any one of the above-mentioned methods, comprising the following steps:

[0016] An amorphous precursor layer is deposited on the surface of the sulfide solid electrolyte layer to obtain a pre-finished product.

[0017] The amorphous precursor layer is subjected to electrochemical treatment to transform it into the nanocrystalline layer.

[0018] In some embodiments, the electrochemical treatment includes:

[0019] The pre-assembled product is assembled into a battery, and a constant voltage of -10mV to -30mV is applied to the negative electrode of the battery, while controlling the capacity to be limited to 0.02mAh / cm³. 2~ 0.1mAh / cm 2 .

[0020] In some embodiments, the temperature of the electrochemical treatment is controlled at 35°C to 50°C, and the time of the electrochemical treatment is 10 min to 30 min.

[0021] In some embodiments, depositing an amorphous precursor layer on the surface of the sulfide solid electrolyte layer includes the following steps:

[0022] An amorphous precursor layer is deposited by magnetron sputtering using a first target comprising Li and a second target comprising at least one of Si and Ge.

[0023] In some embodiments, the sputtering power of the first target is 30W to 60W.

[0024] In some embodiments, the sputtering power of the second target is 20W to 40W.

[0025] In some embodiments, the sputtering power of the first target is 1.5 to 2 times that of the sputtering power of the second target.

[0026] In some embodiments, the target-substrate distance of the first target material is 80mm to 120mm.

[0027] In some embodiments, the target-substrate distance of the second target material is 80mm to 120mm.

[0028] In some embodiments, the deposition rate of the first target is 0.3 Å / s to 0.5 Å / s.

[0029] In some embodiments, the deposition rate of the second target is 0.15 Å / s to 0.25 Å / s.

[0030] In some embodiments, the following steps are included before depositing an amorphous precursor layer on the surface of the sulfide solid electrolyte layer:

[0031] The surface of the sulfide solid electrolyte layer is subjected to plasma treatment, wherein the plasma treatment power is 10W~20W, the plasma treatment time is 10s~30s, and the plasma treatment pressure is 0.1Torr~0.3Torr.

[0032] In some embodiments, depositing an amorphous precursor layer on the surface of the sulfide solid electrolyte layer includes the following steps:

[0033] A transition layer is deposited on the surface of the sulfide solid electrolyte layer, wherein the transition layer is a Si transition layer or a Li3PS4 transition layer;

[0034] An amorphous precursor layer is deposited on the surface of the transition layer opposite to the sulfide solid electrolyte layer.

[0035] Thirdly, this application provides an apparatus for fabricating a solid-state battery, comprising:

[0036] A deposition apparatus for depositing an amorphous precursor layer on the surface of a sulfide solid electrolyte layer;

[0037] An electrochemical device is used to electrochemically treat the amorphous precursor layer to transform it into a nanocrystalline layer.

[0038] Fourthly, this application provides an electrical device comprising the solid-state battery described in any one of the above-mentioned methods, or a solid-state battery prepared by the method described in any one of the above-mentioned methods.

[0039] In the aforementioned solid-state battery without an initial negative electrode, a nanocrystalline layer is present on the surface of the sulfide solid electrolyte layer. The material of the nanocrystalline layer includes at least one of lithium silicon compounds, lithium silicon-germanium compounds, and doped or undoped lithium-germanium compounds. This application proposes a negative electrode-free solid-state battery based on "lattice template-guided nucleation," utilizing Zintl-phase nanocrystals as a heterogeneous nucleation layer. The nanocrystalline layer in this application can serve as a heterogeneous nucleation layer, possessing a unique crystal structure consisting of an anionic framework of silicon or germanium and embedded Li... + The three-dimensional open framework composed of cations can provide natural, high-density, and energy-optimized nucleation sites for subsequent lithium atom deposition, thereby achieving lower nucleation overpotential and ordered lithium deposition.

[0040] Furthermore, this application fully considers the multifunctionality of the interface layer. The nanocrystalline layer of this application not only provides a lattice template but also exhibits mixed (ion / electron) conduction behavior at the nanoscale that enables lateral uniform flow. This characteristic allows the lithium-ion flux from the electrolyte to redistribute rapidly in a two-dimensional plane, while the electron flow is also homogenized, fundamentally avoiding the formation of local hot spots. In addition, the Zintl phase layer also acts as a chemical buffer layer, mitigating the direct reaction between metallic lithium and the sulfide electrolyte, thus improving the long-term stability of the interface.

[0041] Furthermore, compared to the random nucleation or nucleation mechanisms relying solely on surface energy differences in traditional solid-state batteries, this application achieves templated and ordered nucleation processes by pre-constructing a Zintl phase layer with a specific lattice structure. An amorphous precursor is first deposited on the surface of the sulfide solid electrolyte, and then an electrochemically driven in-situ crystallization process is used to transform the amorphous state into highly ordered nanocrystals at extremely low current densities. This electrochemical crystallization avoids high-temperature processing and protects the structural integrity of the sulfide electrolyte. Detailed Implementation

[0042] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0046] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0047] In electrodeless solid-state batteries, the deposition of lithium directly on the surface of sulfide solid electrolytes faces severe challenges. The initial nucleation is highly random, resulting in nucleation overpotentials as high as hundreds of millivolts; uneven nucleation distribution can evolve into dendrite growth, eventually piercing the electrolyte and causing a short circuit; direct contact between lithium and sulfide solid electrolytes can also trigger interfacial reduction and decomposition, forming a high-resistivity layer and consuming active lithium.

[0048] To address the aforementioned problems, traditional technical solutions mainly employ the following strategies. However, the inventors have discovered that these solutions still suffer from the following drawbacks:

[0049] (1) Noble metal interlayer. Noble metal interlayers, such as gold and silver, are formed on the surface of solid electrolytes by magnetron sputtering or vapor deposition to form nanoscale thin films. These metal layers have good electronic conductivity and can homogenize the current distribution to a certain extent. The working principle is to use the high electronic conductivity of metals to laterally disperse the current and reduce the concentration of local current density. However, noble metals lack specific lattice matching for lithium, which cannot fundamentally reduce the nucleation barrier, and the high cost limits practical applications.

[0050] (2) Carbon material modification. Carbon material modification is another commonly used method, including carbon nanotubes, graphene, carbon fibers, etc. These materials are introduced into the interface through coating, transfer printing, or in-situ growth. The high specific surface area and conductivity of carbon materials help to disperse current, and their surface defects can serve as nucleation sites. However, the interaction between carbon materials and lithium is weak, the nucleation overpotential is still high, and it may catalyze the decomposition of electrolytes.

[0051] (3) Amorphous alloy layers. Amorphous alloy layers prepared by co-evaporation or sputtering using Li-Sn, Li-Si, Li-Al, etc., as buffer layers have a certain lithium affinity and can reduce the lithium nucleation barrier. However, amorphous structures lack long-range order and cannot provide regular nucleation templates, resulting in limited uniformity and repeatability of nucleation. Moreover, these alloy layers are prone to phase separation or crystallization during cycling, leading to performance degradation.

[0052] (4) Chemical passivation layer. Such as LiF, Li3N, Li3PO4, etc., which are formed on the surface of the electrolyte by chemical vapor deposition, atomic layer deposition or solution method. These materials are chemically stable and can protect the electrolyte from reduction, but they are usually electron insulators and will increase the interfacial resistance. Even if they have certain ionic conductivity, the lack of electronic conductivity makes it difficult to effectively disperse the current.

[0053] (5) High-temperature annealing treatment. Improve the interface through heat treatment, such as heating in an inert atmosphere to promote interfacial reactions or crystallization. However, sulfide solid electrolytes are sensitive to temperature, and high-temperature treatment is likely to cause decomposition or uncontrollable reactions with lithium, generating by-products with low ionic conductivity and deteriorating the interfacial properties.

[0054] Based on this, an embodiment of the present application provides a solid-state battery, including a positive electrode, a sulfide solid electrolyte layer, and a nanocrystal layer; the positive electrode and the nanocrystal layer are respectively located on two opposite surfaces of the sulfide solid electrolyte layer; the material of the nanocrystal layer includes at least one of lithium-silicon compounds, lithium-silicon-germanium compounds, and doped or undoped lithium-germanium compounds; the lithium-silicon compounds include at least one of Li 12 Si7, Li 13 Si4, and Li7Si3 and at least include Li 12 Si7; the lithium-silicon-germanium compounds include Li 12 (Si 1-x Ge x )7, where 0 < x ≤ 0.3; the lithium-germanium compounds include at least one of Li 12 Ge7, Li7Ge3, and Li 13 Ge4, and the doping elements in the lithium-germanium compounds include at least one of Al, Ga, and B; the grain diameter in the nanocrystal layer is 3 nm to 20 nm; the solid-state battery has no initial negative electrode.

[0055] In the above solid-state battery without an initial negative electrode, a nanocrystal layer is provided on the surface of the sulfide solid electrolyte layer, and the material of the nanocrystal layer includes at least one of lithium-silicon compounds, lithium-silicon-germanium compounds, and doped or undoped lithium-germanium compounds. The present application proposes a negative electrode-free solid-state battery using Zintl-phase nanocrystals as a heterogeneous nucleation layer based on "lattice template-guided nucleation". The nanocrystal layer in the present application can serve as a heterogeneous nucleation layer, which has a unique crystal structure, a three-dimensional open framework composed of an anionic skeleton of silicon or germanium and Li + cations embedded therein, and can provide natural, high-density, and energy-optimized nucleation sites for the subsequent deposition of lithium atoms, thereby achieving a lower nucleation overpotential and ordered deposition of lithium.

[0056] Furthermore, this application fully considers the multifunctionality of the interface layer. The nanocrystalline layer of this application not only provides a lattice template but also exhibits mixed (ion / electron) conduction behavior at the nanoscale that enables lateral uniform flow. This characteristic allows the lithium-ion flux from the electrolyte to redistribute rapidly in a two-dimensional plane, while the electron flow is also homogenized, fundamentally avoiding the formation of local hot spots. In addition, the Zintl phase layer also acts as a chemical buffer layer, mitigating the direct reaction between metallic lithium and the sulfide electrolyte, thus improving the long-term stability of the interface.

[0057] Furthermore, compared to the random nucleation or nucleation mechanisms relying solely on surface energy differences in traditional solid-state batteries, this application achieves templated and ordered nucleation processes by pre-constructing a Zintl phase layer with a specific lattice structure. An amorphous precursor is first deposited on the surface of the sulfide solid electrolyte, and then an electrochemically driven in-situ crystallization process is used to transform the amorphous state into highly ordered nanocrystals at extremely low current densities. This electrochemical crystallization avoids high-temperature processing and protects the structural integrity of the sulfide electrolyte.

[0058] Alternatively, x can be 0.01, 0.02, 0.05, 0.1, 0.15, 0.2, 0.25, or 0.3, or x can be within the range of any two of the above values.

[0059] Optionally, the grain diameter in the nanocrystalline layer is 3nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm or 20nm, or the grain diameter in the nanocrystalline layer may be within the range of the above two diameters.

[0060] Furthermore, the solid-state battery of this application has the following advantages:

[0061] (1) Zintl phase lattice template effect: In this application, the unique anionic framework structure of the Zintl phase is used as a lattice template for lithium atom deposition to achieve atomically ordered heterogeneous nucleation sites. For example, Li 12 Taking Si7 as an example, its anionic framework is [Si7]. 12- .

[0062] (2) Electrochemical in-situ crystallization strategy: In this application, a pre-deposited amorphous precursor, such as an amorphous Li-Si thin film, is transformed in-situ into a highly ordered nanocrystalline layer, such as Li, through a low-current-density initial charging process. 12 Si7 avoids damage to the sulfide solid electrolyte during high-temperature processing.

[0063] (3) Hybrid Ionic Electron Conductor (MIEC) Current Equalization Design: Utilizing the hybrid conduction behavior exhibited by nanocrystalline thin films at the nanoscale, such as Li 12Si7 enables lateral current sharing, fundamentally suppressing local current density concentration.

[0064] (4) Optimization of anode-free architecture: Completely eliminate the initial metallic lithium anode and realize the controllable in-situ generation of lithium through Zintl phase heterogeneous nucleation layer, thereby maximizing the improvement of battery mass and volumetric energy density.

[0065] (5) Closed-loop precise control of composition: The use of low-temperature substrate magnetron co-sputtering combined with a real-time monitoring system enables precise control of the Li:Si atomic ratio and batch-to-batch consistency.

[0066] In some embodiments, in lithium-silicon compounds, Li 12 The molar percentage of Si7 is 80%~100%.

[0067] It is understandable that Li in lithium-silicon compounds 12 The 80%~100% molar percentage of Si7 refers to the fact that the lithium silicon compound is Li. 12 The Si7 pure phase, or lithium-silicon compound as the main phase, with a small amount of Li allowed. 13 Miscellaneous items including Si4 and Li7Si3. Li 12 Si7, as the host phase, can provide a lattice template function. Optionally, in lithium-silicon compounds, Li... 12 The molar percentage of Si7 is 80%, 82%, 84%, 86%, 88%, 90%, 92%, 94%, 96%, 98%, or 100%, or, in lithium-silicon compounds, Li... 12 The molar percentage of Si7 can also be within the range of any two of the above percentages.

[0068] In some embodiments, the nanocrystalline layer is made of Li 12 Composed of Si7 nanocrystals, and containing Li 13 Si4 and / or Li7Si3 impurity phases.

[0069] In some embodiments, the nanocrystalline layer is made of Li 12 Composed of Si7 nanocrystals.

[0070] In some embodiments, the molar ratio of the dopant element to Ge in the doped lithium germanium compound is (0.001~0.02):1.

[0071] Optionally, the molar ratio of the dopant element to Ge in the doped lithium germanium compound is 0.001:1, 0.002:1, 0.005:1, 0.008:1, 0.01:1, 0.012:1, 0.015:1, 0.018:1, or 0.02:1. Alternatively, the molar ratio of the dopant element to Ge in the doped lithium germanium compound may also be within the range of any two of the above ratios.

[0072] In some embodiments, the thickness of the nanocrystalline layer is 8 nm to 40 nm.

[0073] Optionally, the thickness of the nanocrystalline layer is 8nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm or 40nm, or the thickness of the nanocrystalline layer may be within any two of the above thicknesses.

[0074] In some embodiments, the materials of the sulfide solid electrolyte layer include Li6PS5X and Li7P3S. 11 Li 10 GeP2S 12 And at least one of Li3PS4, wherein X represents Cl, Br or I.

[0075] In some embodiments, the relative density of the sulfide solid electrolyte layer is greater than or equal to 95%.

[0076] It is understood that a relative density of ≥95% for the sulfide solid electrolyte layer means that its apparent relative density reaches or exceeds 95% of the true relative density of the corresponding material, which is a key characteristic of the sulfide solid electrolyte layer, indicating a high degree of densification and extremely low porosity. That is, the porosity of the sulfide solid electrolyte layer is less than or equal to 5%. Optionally, the relative density of the sulfide solid electrolyte layer is 95%~99%, and more preferably, it is 95%, 95.5%, 96%, 96.5%, 97%, 97.5%, 98%, 98.5%, or 99%. Alternatively, the relative density of the sulfide solid electrolyte layer can also be within the range of any two of the above relative densities.

[0077] In some embodiments, the surface roughness Ra of the sulfide solid electrolyte layer is 20 nm to 100 nm.

[0078] Optionally, the surface roughness Ra of the sulfide solid electrolyte layer is 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, or the surface roughness Ra of the sulfide solid electrolyte layer may be within the range of any two of the above roughness Ra.

[0079] In some embodiments, the water and oxygen content of the sulfide solid electrolyte layer is less than or equal to 10 ppm.

[0080] In some embodiments, a transition layer is also included; the transition layer is located between the sulfide solid electrolyte and the nanocrystalline layer; the transition layer is a Si transition layer or a Li3PS4 transition layer.

[0081] The transition layer can increase the bonding force between the nanocrystalline layer and the sulfide solid electrolyte layer.

[0082] In some embodiments, the thickness of the Si transition layer is 1 nm to 3 nm.

[0083] Optionally, the thickness of the Si transition layer is 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.2 nm, 2.5 nm, 2.8 nm or 3 nm, or the thickness of the Si transition layer can be within any two of the above thicknesses.

[0084] In some embodiments, the thickness of the Li3PS4 transition layer is 1 nm to 2 nm.

[0085] Optionally, the thickness of the Li3PS4 transition layer is 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm or 2 nm, or the thickness of the Li3PS4 transition layer can be within any two of the above thicknesses.

[0086] In some of these implementations, the solid-state battery operates in the voltage range of 2.8V to 3.8V.

[0087] In some of these implementations, the solid-state battery operates at a temperature of 25°C to 45°C.

[0088] In some of these embodiments, the assembly pressure of the solid-state battery is 5 MPa to 20 MPa.

[0089] In some embodiments, the edges of the solid-state battery are encapsulated with fluorinated polymers or UV-inert acrylic resins, with the encapsulation width being a non-active area of ​​0.3 mm to 1 mm.

[0090] In some embodiments, the fluorinated polymer includes at least one of FEP and ETFE.

[0091] Another embodiment of this application provides a method for preparing a solid-state battery according to any one of the above claims, comprising the following steps:

[0092] An amorphous precursor layer is deposited on the surface of a sulfide solid electrolyte layer to obtain a pre-finished product.

[0093] Electrochemical treatment of the amorphous precursor layer transforms it into a nanocrystalline layer.

[0094] Through electrochemical treatment, Li atoms in the amorphous precursor layer rearrange to form an ordered lattice structure with Si atoms or Ge. The resulting nanocrystals, with a thickness at the nanometer scale, exhibit mixed (ion / electron) conduction behavior that enables lateral uniform flow and provide a lattice template effect for regular lithium sites.

[0095] In some embodiments, the electrochemical treatment includes:

[0096] The pre-assembled products are assembled into batteries, and a constant voltage of -10mV to -30mV is applied to the negative electrode of the battery, while controlling the capacity to be limited to 0.02mAh / cm³. 2 ~0.1mAh / cm 2 .

[0097] Optionally, the constant voltage is -10mV, -15mV, -20mV, -25mV or -30mV, or the constant voltage may be within the range of any two of the above voltages.

[0098] Understandably, the capacity limit refers to the point at which the voltage is stopped when the charging and discharging of the negative electrode reaches its upper limit. Optionally, the capacity limit is 0.02 mAh / cm³. 2 0.04mAh / cm 2 0.06mAh / cm 2 0.08mAh / cm 2 or 0.1mAh / cm 2 Alternatively, the capacity limit can be within the range of any two of the above capacity limits.

[0099] In some embodiments, the temperature of the electrochemical treatment is controlled at 35°C to 50°C, and the time of the electrochemical treatment is 10 min to 30 min.

[0100] Optionally, the temperature of the electrochemical treatment can be controlled at 35°C, 38°C, 40°C, 42°C, 45°C, 48°C or 50°C, or the temperature of the electrochemical treatment can be controlled within any two of the above temperatures.

[0101] Optionally, the electrochemical treatment time is 10 min, 12 min, 15 min, 18 min, 20 min, 22 min, 25 min, 28 min or 30 min, or the electrochemical treatment time can be within any two of the above time ranges.

[0102] Within the range of parameters for the aforementioned electrochemical treatments, it is easy to transform the amorphous precursor layer into a nanocrystalline layer with an ordered lattice, and the nanocrystalline layer can have a suitable grain diameter, thereby enabling the solid-state battery to deposit lithium in an orderly manner on the surface of the sulfide solid electrolyte, and with a low nucleation overpotential.

[0103] In some embodiments, electrochemical processing is performed using a pulse signal, wherein the single pulse duration of the pulse signal is 5s to 30s and the duty cycle is 1:(1 to 3).

[0104] Using pulsed signals for electrochemical treatment is beneficial for promoting uniform crystallization. Optionally, the single pulse duration of the pulse signal is 5s, 10s, 15s, 20s, 25s, or 30s, or the single pulse duration can be within any two of the above-mentioned times. Optionally, the duty cycle is 1:1, 1:1.2, 1:1.5, 1:1.8, 1:2, 1:2.2, 1:2.5, 1:2.8, or 1:3, or the duty cycle can be within any two of the above-mentioned times.

[0105] In some embodiments, the method for preparing a solid-state battery further includes the following steps:

[0106] A positive electrode is prepared on the surface of a sulfide solid electrolyte layer, with the positive electrode and an amorphous precursor layer located on the opposite surface of the sulfide solid electrolyte layer.

[0107] It is understandable that the cathode can be prepared either before or after the deposition of the amorphous precursor layer.

[0108] In some implementations, the positive electrode of the solid-state battery includes an LFP positive electrode.

[0109] In some embodiments, depositing an amorphous precursor layer on the surface of a sulfide solid electrolyte layer includes the following steps:

[0110] An amorphous precursor layer is deposited by magnetron sputtering using a first target and a second target, wherein the first target comprises Li and the second target comprises at least one of Si and Ge.

[0111] Using a first and a second target to deposit an amorphous precursor layer via magnetron sputtering helps avoid damage to the sulfide solid electrolyte layer and also facilitates control over the atomic ratio of elements in the nanocrystalline layer.

[0112] In some embodiments, during magnetron sputtering, the temperature of the substrate is controlled to be -20°C to 25°C.

[0113] In magnetron sputtering, controlling the substrate temperature between -20°C and 25°C can suppress Li volatilization. Preferably, in magnetron sputtering, the substrate temperature is controlled between 0°C and 15°C. Optionally, the substrate temperature can be controlled at 0°C, 2°C, 5°C, 8°C, 10°C, 12°C, or 15°C, or the substrate temperature can be controlled within any two of the above-mentioned temperature ranges.

[0114] In some embodiments, the magnetron sputtering atmosphere is high-purity argon.

[0115] In some of these embodiments, the magnetron sputtering pressure is 2 mTorr to 5 mTorr.

[0116] Optionally, the magnetron sputtering pressure is 2 mTorr, 2.5 mTorr, 3 mTorr, 3.5 mTorr, 4 mTorr, 4.5 mTorr or 5 mTorr, or the magnetron sputtering pressure can be within the range of any two of the above pressures.

[0117] In some embodiments, to avoid ion bombardment damage to the sulfide electrolyte, the substrate bias is preferably 0V, or the substrate bias can be controlled to ≤10V and the sputtering time can be controlled.

[0118] In some embodiments, depositing an amorphous precursor layer by magnetron sputtering using a first target and a second target includes the following steps:

[0119] The first sublayer is deposited using a preset power of 65% to 75%, and the thickness of the first sublayer is 15% to 25% of that of the amorphous precursor layer;

[0120] A second sublayer is deposited on the first sublayer using a preset power, and the thickness of the second sublayer is 50% to 70% of the thickness of the amorphous precursor layer.

[0121] Gradually reduce the preset power until deposition stops, and deposit the third sublayer on the second sublayer;

[0122] It then cooled naturally to room temperature.

[0123] In some embodiments, the sputtering power of the first target is 30W to 60W.

[0124] Optionally, the sputtering power of the first target is 30W, 35W, 40W, 45W, 50W, 55W or 60W, or the sputtering power of the first target can be within the range of any two of the above power values.

[0125] In some embodiments, the sputtering power of the second target is 20W to 40W.

[0126] Optionally, the sputtering power of the second target is 20W to 40W, or the sputtering power of the second target can be within the range of any two of the above power values.

[0127] In some embodiments, the sputtering power of the first target is 1.5 to 2 times that of the sputtering power of the second target.

[0128] Optionally, the sputtering power of the first target is 1.5 times, 1.6 times, 1.7 times, 1.8 times, 1.9 times, or 2 times the sputtering power of the second target, or the multiple of the sputtering power of the first target to the sputtering power of the second target can be within any two of the above multiples.

[0129] In some embodiments, the target-substrate distance of the first target material is 80mm to 120mm.

[0130] Optionally, the target-base distance of the first target material is 80mm, 90mm, 100mm, 110mm or 120mm, or the target-base distance of the first target material can be within the range of any two of the above target-base distances.

[0131] In some embodiments, the target-substrate distance of the second target is 80mm to 120mm.

[0132] Optionally, the target-base distance of the second target material is 80mm, 90mm, 100mm, 110mm or 120mm, or the target-base distance of the second target material can be within the range of any two of the above target-base distances.

[0133] In some of these embodiments, the deposition rate of the first target is 0.3 Å / s to 0.5 Å / s.

[0134] Optionally, the deposition rate of the first target is 0.3 Å / s, 0.35 Å / s, 0.4 Å / s, 0.45 Å / s, or 0.5 Å / s, or the deposition rate of the first target may be within the range of any two of the above deposition rates.

[0135] In some embodiments, the deposition rate of the second target is 0.15 Å / s to 0.25 Å / s.

[0136] Optionally, the deposition rate of the second target is 0.3 Å / s, 0.35 Å / s, 0.4 Å / s, 0.45 Å / s, or 0.5 Å / s, or the deposition rate of the second target may be within the range of any two of the above deposition rates.

[0137] In some embodiments, the following steps are included before depositing an amorphous precursor layer on the surface of the sulfide solid electrolyte layer:

[0138] The surface of the sulfide solid electrolyte layer is subjected to plasma treatment with a power of 10W~20W, a treatment time of 10s~30s, and a pressure of 0.1Torr~0.3Torr.

[0139] Within the range of the parameters described above for plasma treatment, contaminants on the surface of the sulfide solid electrolyte layer can be treated without causing etching to the sulfide solid electrolyte layer.

[0140] Optionally, the power of the plasma treatment is 10W, 12W, 14W, 16W, 18W or 20W, or the power of the plasma treatment may be within the range of any two of the above power values.

[0141] Optionally, the plasma treatment time is 10s, 15s, 20s, 25s or 30s, or the plasma treatment time can be within any two of the above times.

[0142] Optionally, the plasma treatment pressure is 0.1 Torr, 0.15 Torr, 0.2 Torr, 0.25 Torr, or 0.3 Torr, or the plasma treatment pressure may be within the range of any two of the above pressures.

[0143] In some embodiments, depositing an amorphous precursor layer on the surface of a sulfide solid electrolyte layer includes the following steps:

[0144] A transition layer is deposited on the surface of the sulfide solid electrolyte layer. The transition layer is either a Si transition layer or a Li3PS4 transition layer.

[0145] An amorphous precursor layer is deposited on the surface of the transition layer away from the sulfide solid electrolyte layer.

[0146] In some embodiments, after converting the amorphous precursor layer into a nanocrystalline layer, the following steps are also included:

[0147] The first charge causes lithium atoms to preferentially nucleate at specific sites in the nanocrystalline layer, forming a lithium layer.

[0148] In some implementations, the initial charge is performed at a rate of 0.1C to 3.8V.

[0149] Furthermore, the solid-state battery of this application has the following advantages compared to traditional solid-state batteries:

[0150] (1) Lattice template effect vs. random nucleation mechanism

[0151] Existing noble metal or carbon material interface layers only provide an electronic conductivity network; lithium nucleation on their surface remains a random process, resulting in high and unevenly distributed nucleation overpotentials. The Zintl phase nanocrystalline layer of this application possesses a unique framework structure, with Li... 12 Taking Si7 as an example, its anionic framework is [Si7]. 12- The pre-existing Li sites and voids provide energy-optimal nucleation sites for newly deposited lithium atoms. This lattice template transforms nucleation from a random process into an ordered one, significantly reducing the nucleation overpotential.

[0152] (2) Mixed conduction behavior vs. single conductivity characteristics

[0153] Traditional interface layers are either electronic conductors or ionic conductors, making it difficult to simultaneously meet the requirements for current equalization. The nanocrystalline layer in this application exhibits hybrid (ionic / electronic) conduction behavior at a thickness of nanometers, enabling lateral current equalization, avoiding local charge accumulation, and achieving true two-dimensional current equalization.

[0154] (3) Electrochemical in-situ crystallization vs. high-temperature treatment

[0155] Existing technologies require high-temperature annealing above 300°C, which can easily damage the sulfide electrolyte, or the direct deposition of crystalline materials involves complex processes. This invention achieves in-situ transformation from amorphous to nanocrystalline structures under mild conditions of 35°C to 50°C through precisely controlled electrochemical driving, thus protecting the integrity of the sulfide electrolyte.

[0156] (4) Composition closed-loop control vs. composition drift

[0157] The high volatility of Li makes composition control difficult. This application employs a low-temperature substrate (0℃~15℃) and Li target overpower compensation (1.5x~2x) to ensure precise control of the atomic ratio in the amorphous precursor.

[0158] (5) Multi-level interface engineering vs. single interface layer

[0159] Traditional methods use a single material layer. This invention provides a multi-layer option: a Si transition layer of 1nm~3nm or a Li3PS4 transition layer with a thickness of less than or equal to 2nm, combined with an amorphous main functional layer of 10nm~25nm, which can be flexibly combined according to requirements.

[0160] (6) Scalable material systems vs. single material routes

[0161] The material system in this application is not limited to Li 12 Si7 can be extended to Li-Ge systems, Si-Ge hybrid systems, and trace Al / Ga / B doped systems; the electrolyte can be extended from LPSCl to the entire sulfide family; and a platform-based technical route is provided.

[0162] (7) Mild and safe process vs. harsh conditions

[0163] The solid-state battery fabrication method described in this application involves low-temperature (<50℃), low-power (to avoid damage), no polar solvents, and gradient deposition for stress reduction. The process conditions are mild, the equipment requirements are conventional, and it is easy to transfer to industrialization.

[0164] This application provides an apparatus for fabricating solid-state batteries, comprising:

[0165] A deposition apparatus for depositing an amorphous precursor layer on the surface of a sulfide solid electrolyte layer;

[0166] An electrochemical device is used to electrochemically treat an amorphous precursor layer, transforming it into a nanocrystalline layer.

[0167] Another embodiment of this application provides an electrical device including any of the solid-state batteries described above, or a solid-state battery prepared by any of the methods described above.

[0168] The following are specific examples:

[0169] Example 1

[0170] Solid-state battery fabrication methods:

[0171] Step (1): Surface treatment of Li6PS5Cl ceramic sheet.

[0172] First, the Li6PS5Cl ceramic sheet was mechanically polished using diamond polishing paste (particle size 0.5μm~1μm) to achieve a target surface roughness Ra≤100nm. Polishing was performed in an anhydrous and oxygen-free environment, using dry polishing or a low surface energy fluorinated solvent such as HFE-7100 as a small amount of lubricant, without using any polar solvents. The polished sample was immediately transferred to an argon glove box (H2O<1ppm, O2<1ppm).

[0173] Step (2): Plasma cleaning.

[0174] Mild conditions were used to avoid etching damage. Parameters: argon flow rate 20 sccm, RF power 15W, processing time 20s, pressure 0.2 Torr. The mild plasma treatment only removed organic contaminants from the Li6PS5Cl ceramic sheet surface, without etching the electrolyte itself. The treated sample surface appeared clean and activated.

[0175] Step (3): Preparation of the magnetron co-sputtering system.

[0176] The sputtering equipment employs a glovebox-integrated multi-target magnetron sputtering system, ensuring that samples are never exposed to the atmosphere throughout the process. The Li target uses a lithium metal sheet (50mm diameter, 3mm thickness), which is quickly installed after being sealed in packaging; the Si target uses high-purity single-crystal silicon (resistivity >1000Ω·cm). The target surfaces are pre-cleaned for 5 minutes before sputtering. The substrate cooling system uses circulating coolant to control the substrate stage temperature between 0℃ and 15℃, with a maximum of 25℃ and a temperature accuracy of ±1℃. Low temperature effectively suppresses Li volatilization, ensuring precise composition control.

[0177] Step (4): Deposition of amorphous Li-Si thin film.

[0178] The pretreated Li6PS5Cl ceramic sheet was fixed on the substrate, and a vacuum was drawn to <5×10⁻⁶. -7Torr. High-purity argon gas (99.999%) is introduced, and the pressure is stabilized at 2 mTorr~5 mTorr. The substrate bias voltage is controlled at 0V to avoid ion bombardment damage.

[0179] Co-sputtering parameters: Li target power 45W (DC), Si target power 30W (RF), with the Li target power being 1.5 times that of the Si target. Li target-substrate distance 100mm, Si target-substrate distance 100mm. Deposition rate: Li approximately 0.4 Å / s, Si approximately 0.2 Å / s, monitored in real time via QCM.

[0180] Composition closed-loop control: QCM monitoring rate, ellipsometry monitoring optical constants, and power fine-tuning every 5nm. First and last batches are sampled for XPS / RBS verification of the Li:Si atomic ratio, ensuring it remains within ±8% of 12:7, and the data is written back to form closed-loop control.

[0181] Gradient deposition strategy: 70% target power for the initial 5nm; standard power for the main layer; gradually reduced power for the last 5nm; natural cooling to avoid thermal stress. Total deposition time for the 25nm film was 6 minutes.

[0182] Step (5): Electrochemical in-situ crystallization process.

[0183] Electrolyte sheets with amorphous Li-Si thin films are assembled into coin cells or pouch cells in a glove box. The positive electrode uses LFP with a capacity of 12 mg / cm³. 2 Assembly pressure: 10 MPa. Crystallization procedure: Preferred three-electrode constant potential mode, with -20 mV applied to the negative electrode side (vsLi / Li⁺), limited capacity: 0.06 mAh / cm³. 2 Temperature control: 40℃ micro-heating assistance for 20 minutes. Pulse protocol: single pulse 20s, duty cycle 1:2, repeated 8 times to avoid local overheating.

[0184] Determining the completion of crystallization: Characteristics of the voltage plateau and changes in impedance spectrum can be observed in Li using GI-XRD / SAED. 12 Si7 characteristic diffraction was used for confirmation.

[0185] Step (6) Conventional lithium deposition and battery operation.

[0186] After crystallization, the first charge is performed at a rate of 0.1C to 3.8V. Li 12 The Si7 lattice template allows lithium atoms to preferentially nucleate at specific sites, forming a uniform lithium layer. Subsequent cycling: rate capability 0.5C-2C, voltage window 2.8V-3.8V, operating temperature 25℃-45℃. Periodic 0.05C deep charge / discharge maintenance is required. Edge packaging: Utilizes fluorinated polymer FEP, with a 0.6mm wide inactive area to prevent edge effects.

[0187] Example 2

[0188] The solid-state battery preparation methods in Example 2 and Example 1 are basically the same, except that the thickness of the amorphous Li-Si thin film in step (4) is 8 nm.

[0189] Example 3

[0190] The solid-state battery preparation methods in Example 3 and Example 1 are basically the same, except that the thickness of the amorphous Li-Si thin film in step (4) is 40 nm.

[0191] Example 4

[0192] The solid-state battery preparation methods in Example 4 and Example 1 are basically the same, except that the crystallization potential in step (5) is -10mV.

[0193] Example 5

[0194] The solid-state battery preparation methods in Example 5 and Example 1 are basically the same, except that the crystallization potential in step (5) is -30mV.

[0195] Example 6

[0196] The solid-state battery preparation methods in Example 6 and Example 1 are basically the same, the only difference being that the capacity limit in step (5) is 0.02 mAh / cm³. 2 .

[0197] Example 7

[0198] The solid-state battery preparation methods in Example 7 and Example 1 are basically the same, the only difference being that the capacity limit in step (5) is 0.1 mAh / cm³. 2 .

[0199] Example 8

[0200] The preparation methods of solid-state batteries in Example 8 and Example 1 are basically the same, except that the crystallization temperature in step (5) is 35°C.

[0201] Example 9

[0202] The preparation methods of solid-state batteries in Example 9 and Example 1 are basically the same, except that the crystallization temperature in step (5) is 50°C.

[0203] Example 10

[0204] The solid-state batteries in Example 10 and Example 1 are prepared by essentially the same method, except that a 2nm thick Si transition layer is added between the amorphous Li-Si thin film and the solid electrolyte.

[0205] Example 11

[0206] The solid-state battery preparation methods in Example 11 and Example 1 are basically the same, except that a Li3PS4 transition layer with a thickness of 1.5 nm is added between the amorphous Li-Si thin film and the solid electrolyte.

[0207] Example 12

[0208] The preparation methods of the solid-state batteries in Example 12 and Example 1 are basically the same, the only difference being that the solid electrolyte in step (4) is replaced with Li7P3S. 11 .

[0209] Example 13

[0210] The solid-state battery preparation methods in Example 13 and Example 1 are basically the same, the only difference being that in step (4), the amorphous Li-Si thin film is replaced with Li 12 (Si 0.8 Ge 0.2 7.

[0211] Example 14

[0212] The solid-state battery preparation methods in Example 14 and Example 1 are basically the same, except that the thickness of the amorphous Li-Si thin film in step (4) is 5 nm.

[0213] Example 15

[0214] The solid-state battery preparation methods in Example 15 and Example 1 are basically the same, except that the thickness of the amorphous Li-Si thin film in step (4) is 50 nm.

[0215] Comparative Example 1

[0216] The preparation methods of solid-state batteries in Comparative Example 1 and Example 1 are basically the same, except that steps (4) and (5) are not performed, and Li deposition is performed directly.

[0217] Comparative Example 2

[0218] The preparation methods of solid-state batteries in Comparative Example 2 and Example 1 are basically the same, except that step (5) is not performed and Li deposition is performed directly.

[0219] Comparative Example 3

[0220] The preparation methods of solid-state batteries in Comparative Example 3 and Example 1 are basically the same, except that steps (4) and (5) are not performed, and Li is deposited after preparing an Au metal intermediate layer with a thickness of 10 nm on the surface of the solid electrolyte.

[0221] The solid-state batteries prepared in Examples 1 to 15 and Comparative Examples 1 to 3 were tested as follows:

[0222] (1) First lithium deposition nucleation overpotential

[0223] Test platform: Cu half-cell (Cu|SSE|interface layer|Li).

[0224] Test objective: To verify the core effect of Zintl phase lattice template in reducing nucleation barrier.

[0225] Test method: During the first charging process, the voltage-time curve was recorded, and the difference between the lowest voltage point at nucleation and the steady-state deposition voltage was read.

[0226] Test conditions: Current density 0.2 mA / cm² 2 Single deposition capacity: 0.5 mAh / cm³ 2 Temperature 25℃; Stacking pressure 10MPa; Electrolyte thickness 500μm.

[0227] (2) Critical current density

[0228] Test platform: Cu half-cell or symmetric cell.

[0229] Test objective: To verify the lateral flow uniformity of the hybrid conductive layer and its effect in suppressing local hot spots.

[0230] Test method: from 0.1mA / cm 2 Initially, increase by 0.1 mA / cm per level. 2 Each stage runs for 1 hour, and the maximum stable current density before a voltage drop or short circuit occurs is recorded.

[0231] Test conditions: Single charge capacity 0.5mAh / cm³ 2 Temperature 25℃; Stacking pressure 10MPa; Electrolyte thickness 500μm.

[0232] (3) Interface impedance

[0233] Test platform: symmetrical battery or full battery.

[0234] Test objective: To verify the effect of the interface layer in reducing interface impedance and suppressing impedance growth.

[0235] Test method: After EIS test, the high-frequency intercept (Rs) is read as the total impedance; Test nodes: initial, after the 50th cycle; relative comparison is performed under the same electrolyte thickness and compaction conditions.

[0236] Test conditions: Frequency range 0.1Hz-1MHz; AC amplitude 10mV; temperature 25℃; stacking pressure 10MPa.

[0237] (4) First-cycle coulombic efficiency of the whole cell

[0238] Test platform: Electrodeless full cell (LFP|SSE|interface layer).

[0239] Test objective: To verify the overall reversibility of the first charge-discharge cycle and the formation of the SEI.

[0240] Test method: Record the ratio of the initial charge capacity to the initial discharge capacity.

[0241] Test conditions: charge / discharge rate 0.1C; voltage window 2.8-3.8V; temperature 25℃; stacking pressure 10MPa.

[0242] (5) Cyclic capacity retention

[0243] Test platform: Electrodeless full cell (LFP|SSE|interface layer).

[0244] Test objective: To verify the effect of the interface layer on improving long-term cycle stability.

[0245] Test method: Record the discharge capacity of the 1st and 100th discharges at a fixed rate, and calculate the retention rate = capacity of the 100th discharge / capacity of the 1st discharge.

[0246] Test conditions: charge / discharge rate 0.5C; voltage window 2.8-3.8V; temperature 25℃; stacking pressure 10MPa.

[0247] The test results are shown in Table 1 below. It is understandable that due to the inherent error range in the preparation process and test results, each test result is recorded as the range of all test results for the 50 test samples.

[0248] Table 1

[0249]

[0250] Results analysis:

[0251] Comparing the initial nucleation overpotential data of Example 1 and Comparative Example 1, Example 1 exhibits a significantly reduced nucleation overpotential, indicating that Li 12 The specific lattice structure of the Si7 nanocrystal surface provides energy-optimized nucleation sites for lithium atoms. This lattice template effect lies in the Li12 [Si7] of Si7 12- Anionic framework and embedded Li + The cations form a three-dimensional open framework with regular spacing, allowing newly deposited lithium atoms to directly embed into these pre-existing lattice sites without overcoming the high energy barrier required to form new nuclei on the amorphous surface. In contrast, in Comparative Example 1, when lithium is directly deposited on the surface of a sulfide electrolyte without any interface layer, the lack of specific nucleation sites means that lithium atoms need to randomly aggregate on the surface and reach a critical size before forming stable nuclei, a process that corresponds to a significantly increased nucleation overpotential.

[0252] Comparing the data from Example 1 and Comparative Example 2 clearly distinguishes the lattice template effect from the general alloying effect. Although Comparative Example 2 also has an amorphous Li-Si layer, because the electrochemical crystallization step was skipped, the film still maintains a disordered amorphous structure and lacks long-range ordered lattice arrangement. Although amorphous Li-Si shows some improvement in lithium affinity compared to the bare electrolyte surface, the reduction in nucleation overpotential is significantly less than that of Example 1. This comparison clearly demonstrates that simply changing the chemical composition, i.e., introducing silicon, is insufficient to achieve excellent nucleation promotion. Only by forming a nanocrystalline layer with a specific Zintl phase lattice structure through electrochemical in-situ crystallization can the unique advantages of the lattice template be fully utilized. From the perspective of electrochemical kinetics, the lattice template reduces the Gibbs free energy change for lithium nucleation, decreases the height and width of the nucleation barrier, and allows lithium atoms to rapidly form a large number of uniformly distributed nucleation sites on the nanocrystalline surface at a lower overpotential, laying the foundation for subsequent uniform deposition.

[0253] Comparative Example 3 uses traditional noble metals such as gold or silver as the interface layer. Although these metals have excellent electronic conductivity and can disperse current to some extent, their effect on reducing nucleation overpotential is still significantly inferior to that of Example 1. The fundamental reason for this difference is that although the surface of noble metals can achieve lateral current distribution through electronic conductivity, its lattice structure does not match the lattice parameters of lithium, and therefore cannot provide heterogeneous nucleation sites with optimal energy. Lithium nucleation on the surface of gold or silver is still a process with a high energy barrier, requiring a large overpotential to form a stable lithium nucleus. In addition, the interface energy between noble metals and lithium is high, and strain and interfacial reactions at the interface also consume some energy, further increasing the total energy consumption for nucleation. In contrast, Li 12 As a lithium silicide, Si7 naturally contains a large number of lithium atoms, exhibiting inherent chemical and structural compatibility with newly deposited lithium. Its extremely low interfacial energy allows lithium atoms to embed almost effortlessly into lattice sites. This combination of affinity with elements of the same group and the lattice template effect gives Zintl phase heteronucleation layers excellent performance in reducing nucleation overpotential.

[0254] Furthermore, in Example 14, when the nanocrystalline layer thickness was reduced to 5 nm, although the lattice template effect still existed, a noticeable decrease in performance occurred. The main reason for this decrease is that the excessively thin nanocrystalline layer could not form a complete and continuous coverage on the sulfide electrolyte surface. Due to the microscopic roughness of 50 nm to 100 nm on the sulfide electrolyte surface, the 5 nm thick film may not completely cover some recessed areas, resulting in direct exposure of the sulfide electrolyte in some areas. In these exposed areas, lithium deposition behavior reverts to a random nucleation mode without an interface layer. In addition, the excessively thin nanocrystalline layer cannot provide sufficient lateral mixing and conduction channels, limiting the homogenization ability of local current density. Lithium deposition preferentially occurs in fully covered areas, but due to the presence of uncovered high-resistivity regions around it, the current still tends to concentrate in a few channels, failing to fully utilize the advantages of surface current homogenization. Therefore, although the performance of Example 14 is worse than Comparative Example 1, it is not as good as Example 1.

[0255] Example 2 used an 8 nm thick nanocrystalline layer. Experimental results showed that an 8 nm thickness was sufficient to form a nearly continuous coverage on the electrolyte surface, fully demonstrating the lattice template effect and significantly reducing the nucleation overpotential. However, compared to Example 1, the 8 nm sample still lagged behind in terms of critical current density and long-term cycling stability. This difference can be understood from the microstructure and functional characteristics of the nanocrystalline layer. An 8 nm thickness corresponds to a smaller number of grain stacked layers, resulting in a relatively smaller number of grain boundaries in the film. While this reduces grain boundary impedance, it also limits the lateral ion and electron transport capabilities of the nanocrystalline layer. At higher current densities, the bottleneck of lateral transport begins to appear, and the uniformity of current distribution decreases slightly.

[0256] Example 3 used a 40 nm thickness. Experimental data showed that the core indicators of the 40 nm sample, such as nucleation overpotential and lithium deposition stripping coulombic efficiency, remained excellent, proving that the lattice template effect did not fail with increased thickness. However, compared with Example 1, the interfacial impedance of the 40 nm sample began to show a noticeable increase. This is because as the thickness increases, the path for lithium ions and electrons through the nanocrystalline layer becomes longer, and the series impedance increases accordingly. Although the nanocrystalline layer exhibits mixed conductivity at the nanoscale, its ionic conductivity is still lower than that of the sulfide electrolyte itself. An excessively thick nanocrystalline layer will increase the overall interfacial impedance to some extent. In addition, a 40 nm thickness means more consumption of inactive material, which is not the optimal choice from the perspective of energy density optimization.

[0257] Example 15 used a thickness of 50 nm, exceeding the upper limit of the claims. Although this sample still exhibited the advantage of a lattice template in terms of nucleation overpotential, the increase in interfacial impedance became significant, and cycling performance began to decline. The excessively thick nanocrystalline layer increased the series impedance of lithium-ion transport, leading to increased polarization, especially at high rates or low temperatures, where the impedance effect was further amplified. The experimental results of Example 15 demonstrate that while excessively increasing the thickness does not completely eliminate functionality, it leads to adverse effects on cost, impedance, and stability.

[0258] Furthermore, the electrochemical parameter settings of the crystallization process are crucial for achieving high-quality Li. 12 The key to the Si7 nanocrystalline layer lies in the use of a constant potential mode, applying a potential of -10mV to -30mV relative to lithium metal on the negative electrode side. This potential range is near the lithium nucleation overpotential, driving lithium atoms to migrate from the electrolyte side to the amorphous Li-Si layer and undergo an alloying reaction, while providing a moderate driving force to prevent the rapid deposition of large amounts of lithium and the formation of coarse grains. Simultaneously, the constant potential is applied with a capacitive capacity of 0.02 mAh / cm³. 2 Up to 0.1mAh / cm 2 The crystallization process automatically stops when the amount of charge passing through reaches this limit. Setting the limit capacity allows for sufficient crystallization while avoiding overgrowth.

[0259] Temperature control during crystallization has a significant impact on the quality and size distribution of the final nanocrystals. The preferred crystallization temperature range is 35°C to 50°C. This range provides sufficient thermal activation energy to promote the rearrangement of Li and Si atoms, accelerating the crystallization process. Simultaneously, the temperature remains within the safe range for the sulfide electrolyte, especially at the interface with the lithium-containing precursor, preventing significant decomposition or interfacial side reactions. Compared to high-temperature annealing processes that often reach hundreds of degrees Celsius, the mild temperature conditions of this invention completely avoid thermal damage to the sulfide electrolyte.

[0260] Example 10 introduced a 2 nm thick pure Si transition layer between the sulfide electrolyte and the amorphous Li-Si film. Experimental data showed that the interfacial impedance of Example 10 was improved compared to Example 1, and the high-frequency semicircle diameter of the electrochemical impedance spectroscopy was reduced, demonstrating the effect of the silicon transition layer in improving interfacial charge transfer. In terms of long-term cycling stability, Example 10 exhibited good capacity retention, indicating that the enhanced interfacial adhesion helps suppress the mechanical degradation of the film and maintains the long-term integrity of the interface.

[0261] Example 11 uses a 1.5 nm thick Li3PS4 transition layer. Introducing the Li3PS4 transition layer can provide a buffer with good ion conductivity, slowing down the reaction between the solid electrolyte and Li. 12The chemical potential gradient between Si7 atoms lowers the ion transport barrier at the interface. Experimental results show that the interfacial impedance of Example 11 is superior among all examples, with a lower impedance value than that of Example 1. This result demonstrates that the Li3PS4 transition layer effectively improves the ion transport kinetics at the interface and reduces interfacial polarization. Long-term cycling tests show that Example 11 exhibits a slower coulombic efficiency decay rate and higher capacity retention, demonstrating the positive role of the Li3PS4 transition layer in suppressing interfacial side reactions.

[0262] Example 12 uses Li7P3S 11 Replacing Li6PS5Cl as a sulfide solid electrolyte verifies the adaptability of the present invention to different electrolyte systems. Experimental results show that in Li7P3S... 11 Li electrolyte surface constructed using the same process 12 The Si7 nanocrystalline layer can also effectively reduce the nucleation overpotential and achieve uniform lithium deposition, with performance indicators close to those of the Li6PS5Cl system. This result proves that the Zintl phase lattice template effect has a universal mechanism and is not dependent on a specific electrolyte composition.

[0263] Example 13 uses Li 12 (Si 0.8 Ge 0.2 7. Partially germanium-substituted Zintl phase. Electrochemical testing showed that the performance of Example 13 was close to that of Example 1, demonstrating the feasibility of the germanium substitution scheme. This example demonstrates the flexibility of Zintl phase heteronucleation layers in terms of material composition, reserving space for customized designs for specific applications.

[0264] Through systematic analysis of all embodiments and comparative examples, the technical solution of this invention based on Zintl phase controllable crystallization heteronucleation layer achieves significant improvements in several key performance dimensions of anode-free solid-state batteries. Regarding interface nucleation behavior, Li... 12 The Si7 nanocrystalline layer significantly reduces the nucleation overpotential of lithium metal through the lattice template effect. This improvement is directly related to the initial stage of lithium deposition, laying the foundation for subsequent uniform deposition. From a microscopic perspective, the low nucleation overpotential means that lithium atoms can nucleate simultaneously at more sites, forming a high-density nucleation site array, avoiding the random nucleation and dendrite growth problems common in traditional anode-free batteries. Regarding interfacial reversibility and stability, the nanocrystalline layer exhibits excellent lithium deposition stripping coulombic efficiency. The high coulombic efficiency depends on the Li... 12The Si7 nanocrystalline layer has multiple functions: the lattice template effect lowers the deposition barrier, the mixed conductivity enables lateral flow uniformity, and the chemical buffering effect mitigates side reactions with the electrolyte. The evolution of interfacial impedance over cycling shows that the impedance growth rate of the example group is significantly lower than that of the control group, proving that the nanocrystalline layer effectively protects the sulfide electrolyte and inhibits interfacial degradation.

[0265] The example group was able to operate stably at a significantly higher current density than the control group, and this performance improvement directly corresponds to an increase in safety margin. The physical basis of the high critical current density lies in the lateral mixing and conduction characteristics of the nanocrystalline layer. The lithium-ion flux and electron flow from the electrolyte can be rapidly redistributed within the nanocrystalline layer, uniformly dispersing the high current density that might otherwise be concentrated in certain local areas to the entire interface. This two-dimensional current equalization mechanism fundamentally eliminates the driving force for dendrite formation, realizing planar growth of lithium rather than point growth. In terms of long-term cycle stability, the anode-free full-cell test showed that after multiple charge-discharge cycles, the example group still maintained good capacity, while the control group showed significant capacity decay. The main reasons for capacity decay include active lithium loss, interfacial impedance growth, and electrode material degradation, among which active lithium loss is the most critical in the anode-free system. The Zintl phase heteronucleation layer reduces irreversible lithium consumption through multiple pathways by maintaining high coulombic efficiency, suppressing dead lithium formation, and mitigating interfacial side reactions, thereby significantly extending battery life.

[0266] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0267] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A solid-state battery, characterized in that, It includes a positive electrode, a sulfide solid electrolyte layer, and a nanocrystal layer; the thickness of the nanocrystal layer is 8 nm to 40 nm; the positive electrode and the nanocrystal layer are respectively located on two opposite surfaces of the sulfide solid electrolyte layer; the material of the nanocrystal layer is at least one of lithium-silicon compounds, lithium-silicon-germanium compounds, and lithium-germanium compounds; the lithium-silicon compounds include at least one of Li 12 Si7, Li 13 Si4, and Li7Si3 and at least includes Li 12 Si7; the lithium-silicon-germanium compounds include Li 12 (Si 1-x Ge x )7, where 0 < x ≤ 0.3; the lithium-germanium compounds include Li 12 Ge7; the grain diameter in the nanocrystal layer is 3 nm to 20 nm; the solid-state battery has no initial negative electrode; The method for preparing the solid-state battery includes the following steps: An amorphous precursor layer is deposited on the surface of the sulfide solid electrolyte layer to obtain a pre-finished product. The amorphous precursor layer is subjected to electrochemical treatment to transform it into the nanocrystalline layer. The electrochemical treatment includes assembling the pre-finished product into a battery, applying a constant voltage to the negative electrode of the battery, the constant voltage being -10mV to -30mV, and controlling the temperature of the electrochemical treatment to be 35℃ to 50℃.

2. The solid-state battery according to claim 1, characterized in that, In the lithium-silicon compound, Li 12 The molar percentage of Si7 is 80%~100%.

3. The solid-state battery according to claim 1, characterized in that, The molar ratio of the dopant element to Ge in the doped lithium germanium compound is (0.001~0.02):

1.

4. The solid-state battery according to claim 1, characterized in that, The sulfide solid electrolyte layer is made of materials including Li6PS5X and Li7P3S. 11 Li 10 GeP2S 12 And at least one of Li3PS4, wherein X represents Cl, Br or I.

5. The solid-state battery according to claim 4, characterized in that, The sulfide solid electrolyte layer satisfies at least one of the following characteristics: (1) The relative density of the sulfide solid electrolyte layer is greater than or equal to 95%; (2) The surface roughness Ra of the sulfide solid electrolyte layer is 20 nm to 100 nm; (3) The water and oxygen content of the sulfide solid electrolyte layer is less than or equal to 10 ppm.

6. The solid-state battery according to any one of claims 1 to 5, characterized in that, It also includes a transition layer; the transition layer is located between the sulfide solid electrolyte and the nanocrystalline layer; the transition layer is a Si transition layer or a Li3PS4 transition layer.

7. The solid-state battery according to claim 6, characterized in that, The thickness of the Si transition layer is 1 nm to 3 nm; or the thickness of the Li3PS4 transition layer is 1 nm to 2 nm.

8. A method for preparing a solid-state battery according to any one of claims 1 to 7, characterized in that, Includes the following steps: An amorphous precursor layer is deposited on the surface of the sulfide solid electrolyte layer to obtain a pre-finished product. The amorphous precursor layer is subjected to electrochemical treatment to transform it into the nanocrystalline layer.

9. The method for preparing a solid-state battery according to claim 8, characterized in that, The electrochemical treatment includes: The pre-assembled product is assembled into a battery, and a constant voltage of -10mV to -30mV is applied to the negative electrode of the battery, while controlling the capacity to be limited to 0.02mAh / cm³. 2 ~0.1mAh / cm 2 .

10. The method for preparing a solid-state battery according to claim 8, characterized in that, The temperature of the electrochemical treatment is controlled at 35℃~50℃, and the time of the electrochemical treatment is 10min~30min.

11. The method for preparing a solid-state battery according to claim 8, characterized in that, Depositing an amorphous precursor layer on the surface of the sulfide solid electrolyte layer includes the following steps: An amorphous precursor layer is deposited by magnetron sputtering using a first target comprising Li and a second target comprising at least one of Si and Ge.

12. The method for preparing a solid-state battery according to claim 11, characterized in that, The magnetron sputtering satisfies at least one of the following characteristics: (1) The sputtering power of the first target is 30W~60W; (2) The sputtering power of the second target is 20W~40W; (3) The sputtering power of the first target is 1.5 to 2 times that of the sputtering power of the second target; (4) The target-substrate distance of the first target material is 80mm~120mm; (5) The target-substrate distance of the second target material is 80mm~120mm; (6) The deposition rate of the first target material is 0.3 Å / s to 0.5 Å / s; (7) The deposition rate of the second target is 0.15 Å / s to 0.25 Å / s.

13. The method for preparing a solid-state battery according to claim 8, characterized in that, The following steps are included before depositing the amorphous precursor layer on the surface of the sulfide solid electrolyte layer: The surface of the sulfide solid electrolyte layer is subjected to plasma treatment, wherein the plasma treatment power is 10W~20W, the plasma treatment time is 10s~30s, and the plasma treatment pressure is 0.1Torr~0.3Torr.

14. The method for preparing a solid-state battery according to claim 8, characterized in that, Depositing an amorphous precursor layer on the surface of the sulfide solid electrolyte layer includes the following steps: A transition layer is deposited on the surface of the sulfide solid electrolyte layer, wherein the transition layer is a Si transition layer or a Li3PS4 transition layer; An amorphous precursor layer is deposited on the surface of the transition layer opposite to the sulfide solid electrolyte layer.

15. An electrical appliance, characterized in that, The solid-state battery includes any one of claims 1 to 7, or any one of claims 8 to 14, prepared by the method of preparing the solid-state battery.

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