Control device and control method for preventing current backflow in abnormal power failure of synchronous rectification circuit

Abstract

The invention discloses a current backflow prevention control device and method for abnormal power failure of a synchronous rectification circuit, and the device comprises a power supply unit which is used for accessing an input voltage, converting the input voltage into a power supply voltage, and supplying power to a current backflow prevention control unit and a synchronous rectification unit; the current backflow prevention control unit is used for sampling the input voltage in real time and outputting a turn-off control signal to the synchronous rectification unit after abnormal power failure of the input voltage is detected; and the synchronous rectification unit is used for rectifying the input voltage accessed to the input end of the synchronous rectification unit, outputting the rectified input voltage from the output end of the synchronous rectification unit, and disconnecting the connection path between the input end and the output end of the synchronous rectification unit after receiving the turn-off control signal. According to the invention, reliable current backflow prevention protection is realized through a simple and ingenious circuit structure.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a synchronous rectifier circuit abnormal power failure prevention current backflow control device and control method. Background Technology

[0002] In circuit structures with high output current, the synchronous rectification unit uses power MOSFETs instead of traditional diodes for rectification. Because power MOSFETs have extremely low on-state voltage drops, the efficiency improvement is particularly significant, effectively reducing heat accumulation and thus improving reliability. The synchronous rectification unit controls the complementary conduction of the primary switching transistor and the secondary synchronous rectifier transistor, and sets an appropriate dead time. After the synchronous rectification unit starts working, it completes the charging of the output capacitor and the power supply to the subsequent load. Under no-load conditions, only the output capacitor is charged. If the power is turned off at this time, the output capacitor is in a fully charged state, the duty cycle of the primary power transistor drops to zero, and the duty cycle of the secondary synchronous rectifier transistor rises to 100%, i.e., it is in a long-term shoot-through state until the drive voltage of the secondary synchronous rectifier transistor naturally discharges before turning off. During this period, the energy on the output capacitor will be rapidly discharged through the low-impedance path formed by the synchronous rectifier, resulting in a very large reverse current. Simultaneously, at the instant the secondary synchronous rectifier is turned off after its drive voltage has naturally discharged, the very high di / dt generates a very high voltage spike on the synchronous rectifier, potentially causing it to fail. Currently, the industry has recognized the severity of this problem and therefore, specific designs have been implemented in the synchronous rectifier unit to address the reverse current issue by rapidly turning off the secondary synchronous rectifier.

[0003] However, while rapidly turning off the secondary synchronous rectifier can solve the current backflow during power-off, the energy on the output capacitor is not quickly discharged and continues to be stored in the output capacitor for natural discharge. In practical applications, when the input voltage is abnormally interrupted and then quickly restarted, during the startup phase, due to the limitations of the soft-start function, the drive duty cycle of the primary switch gradually increases from 0%. Since the drive of the secondary synchronous rectifier is complementary to that of the primary switch, the drive of the secondary synchronous rectifier gradually decreases from 100%. At this time, the energy still stored in the output capacitor is also rapidly discharged through the low-impedance path formed by the synchronous rectifier, resulting in a very large backflow current and a very high di / dt. At the moment the secondary synchronous rectifier is turned off, a very high peak voltage is generated, which can also cause the synchronous rectifier to fail. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a reliable synchronous rectifier circuit abnormal power failure prevention current backflow control device and control method.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a synchronous rectifier circuit abnormal power failure anti-current backflow control device, comprising: The power supply unit is used to connect the input voltage and convert the input voltage into the supply voltage to power the anti-current backflow control unit and the synchronous rectification unit; The anti-current backflow control unit is used to sample the input voltage in real time and output a shutdown control signal to the synchronous rectification unit after detecting an abnormal power failure in the input voltage; and The synchronous rectification unit is used to rectify the input voltage connected to its input terminal and output it from its output terminal, and disconnect the connection between its input terminal and output terminal after receiving a shutdown control signal.

[0006] Furthermore, the anti-current backflow control unit includes: The input sampling subunit is used to perform real-time voltage division sampling of the input voltage to obtain the sampled voltage; The shutdown control subunit is used to compare the sampled voltage with a set reference voltage. When the sampled voltage is less than the reference voltage, it outputs a shutdown control signal to shut down the synchronous rectification unit until a set delay time is reached, at which point it stops outputting the shutdown control signal.

[0007] Furthermore, the anti-current backflow control unit also includes a first port, a second port, a third port, a fourth port, and a fifth port; the first port is electrically connected to the positive input terminal, the fifth port is electrically connected to the negative input terminal, the second port is electrically connected to the output terminal of the power supply unit, the third port is used to receive the pulse signal output by the synchronous rectification unit, and the fourth port is used to output the shutdown control signal to the synchronous rectification unit.

[0008] Furthermore, the input sampling subunit includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is electrically connected to the first port of the anti-current backflow control unit, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected to the fifth port of the anti-current backflow control unit, and the second end of the first resistor R1 serves as the output terminal of the input sampling subunit and is electrically connected to the input terminal of the shutdown control subunit.

[0009] Furthermore, the shutdown control subunit includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a reference chip IC1, a PNP transistor V1, an NMOS transistor V2, a first capacitor C1, a second capacitor C2, a first diode D1, and a second diode D2. One end of the third resistor R3 is electrically connected to the second port, and the other end is electrically connected to the A terminal of the reference chip IC1; the R terminal of the reference chip IC1 is electrically connected to the second terminal of the first resistor R1 to receive the sampling voltage, and the K terminal of the reference chip IC1 is electrically connected to the fifth port; the emitter of the PNP transistor V1 is electrically connected to the A terminal of the reference chip IC1, the collector of the PNP transistor V1 is electrically connected to the fifth port, the base of the PNP transistor V1 is electrically connected to the first terminal of the sixth resistor R6, and the second terminal of the sixth resistor R6 is connected to the fifth port through the fourth resistor R4; the anode of the first diode D1 is electrically connected to the third port, and the first diode D1... The cathode of the first diode is electrically connected to the second terminal of the sixth resistor R6; the positive terminal of the first capacitor C1 is electrically connected to the cathode of the first diode D1, and the negative terminal of the first capacitor C1 is electrically connected to the fifth port; the anode of the second diode D2 is electrically connected to terminal A of the reference chip IC1, and the cathode of the second diode D2 is connected to the fifth port through the second capacitor C2; one end of the fifth resistor R5 is electrically connected to the cathode of the second diode D2, and the other end of the fifth resistor R5 is electrically connected to the fifth port; the gate of the NMOS transistor V2 is electrically connected to the cathode of the second diode D2, the drain of the NMOS transistor V2 is electrically connected to the fourth port, and the source of the NMOS transistor V2 is electrically connected to the fifth port.

[0010] Furthermore, the reference chip IC1 is model number TLV431.

[0011] Furthermore, the synchronous rectification unit includes a first undervoltage divider resistor Ruv1, a second undervoltage divider resistor Ruv2, a PWM controller U1, and a synchronous rectification power conversion and feedback subunit; the first terminal of the first undervoltage divider resistor Ruv1 is electrically connected to the positive input terminal, the second terminal of the first undervoltage divider resistor Ruv1 is electrically connected to the first terminal of the second undervoltage divider resistor Ruv2, and the second terminal of the second undervoltage divider resistor Ruv2 is electrically connected to the negative input terminal; the first terminal of the second undervoltage divider resistor Ruv2 is electrically connected to the UVLO pin of the PWM controller U1. The Vi pin of the PWM controller U1 is electrically connected to the output terminal of the power supply unit; the PWM pin of the PWM controller U1 is electrically connected to the third port; the UVLO pin of the PWM controller U1 is electrically connected to the fourth port; the GND pin of the PWM controller U1 is electrically connected to the negative input terminal; the PWM controller U1 is connected to the synchronous rectification power conversion and feedback subunit; the first output terminal of the synchronous rectification power conversion and feedback subunit is electrically connected to the positive output terminal; and the second output terminal of the synchronous rectification power conversion and feedback subunit is electrically connected to the output ground terminal.

[0012] Furthermore, the trigger voltage of the anti-current backflow control unit is set lower than the undervoltage turn-on voltage of the synchronous rectification unit.

[0013] Furthermore, the delay time for the synchronous rectification unit to remain in the off state is set by setting the capacitance of the second capacitor C2 and the resistance value of the fifth resistor R5.

[0014] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a control method for preventing backflow of current during abnormal power failure of a synchronous rectifier unit, which is implemented based on the aforementioned control device for preventing backflow of current during abnormal power failure of the synchronous rectifier circuit, comprising: When the input voltage is first powered on, no shutdown control signal is output, and the synchronous rectifier unit starts normally; When the input voltage fails due to an abnormal power loss, the output shutdown control signal disconnects the connection between the input and output terminals of the synchronous rectifier unit.

[0015] The subject matter of this invention has at least the following beneficial effects: This invention monitors input voltage changes in real time through an anti-current backflow control unit. Upon detecting an abnormal power outage, it outputs a shutdown control signal. During rapid restart, the shutdown control signal delays the startup of the synchronous rectifier unit, providing sufficient energy discharge time for the capacitor to reduce its voltage to a safe level. This completely avoids the huge current and voltage spikes caused by current backflow during the restart of the synchronous rectifier unit, preventing the synchronous rectifier tube and other power devices from burning out. By setting the trigger voltage of the anti-current backflow control unit lower than the undervoltage turn-on voltage of the synchronous rectifier unit, it can accurately distinguish between normal shutdown and abnormal power outage, avoiding malfunctions, and ensuring that current backflow is prevented during abnormal power outage restarts. This solution does not require complex digital processors or dedicated chips, has a simple structure, is easy to implement and integrate, significantly reducing the complexity and manufacturing cost of the solution, and is conducive to widespread adoption. The shutdown delay time of the synchronous rectifier unit can be flexibly adjusted according to the output capacitor capacity and load characteristics of different products to achieve the best protection effect, meeting the needs of diverse application scenarios. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the synchronous rectifier circuit abnormal power failure and current backflow prevention control device of the present invention.

[0017] Figure 2 This is a circuit diagram of the synchronous rectifier circuit abnormal power failure and backflow prevention control device of the present invention.

[0018] Figure 3 This is a comparison of the measured operating waveforms of the input and output voltages of the synchronous rectifier circuit before and after the abnormal power failure and rapid restart process using the synchronous rectifier circuit abnormal power failure and backflow prevention control device. Detailed Implementation The invention will now be further described with reference to the accompanying drawings.

[0019] Please see Figure 1 and Figure 2 The synchronous rectification circuit abnormal power failure anti-current backflow control device of the present invention includes a power supply unit 100, an anti-current backflow control unit 200, and a synchronous rectification unit 300. The power supply unit 100 is used to receive the input voltage and convert it into a supply voltage VCC to power the anti-current backflow control unit 200 and the synchronous rectification unit 300. The anti-current backflow control unit 200 is used to sample the input voltage in real time and output a shutdown control signal to the synchronous rectification unit 300 after detecting an abnormal power failure of the input voltage. The synchronous rectification unit 300 is used to rectify the input voltage connected to its input terminal and output it from its output terminal, and disconnects the connection between its input terminal and output terminal after receiving the shutdown control signal.

[0020] Specifically, the anti-current backflow control unit 200 includes an input sampling subunit 210 and a shutdown control subunit 220. The input sampling subunit 210 performs real-time voltage division sampling of the input voltage to obtain a sampled voltage. The shutdown control subunit 220 compares the sampled voltage with a set reference voltage. When the sampled voltage is less than the reference voltage, an abnormal power failure is determined, and a shutdown control signal is output to shut down the synchronous rectifier unit 300 until a set delay time is reached, at which point the output of the shutdown control signal stops. For example, when the voltage abnormally fails and then quickly restarts, by promptly shutting down the synchronous rectifier unit 300 and delaying its restart for a period of time, the large capacitor (not shown in the figure) connected to the output terminal of the synchronous rectifier unit 300 has sufficient time to discharge to a safe voltage, preventing current backflow from burning out the circuit. Furthermore, the synchronous rectifier unit 300 can continue to operate after a rapid voltage restart.

[0021] The anti-current backflow control unit 200 also includes a first port 1, a second port 2, a third port 3, a fourth port 4, and a fifth port 5. The first port 1 is electrically connected to the positive input terminal, the fifth port 5 is electrically connected to the negative input terminal, the second port 2 is electrically connected to the output terminal of the power supply unit 100, the third port 3 receives the pulse signal output by the synchronous rectification unit 300, and the fourth port 4 outputs the shutdown control signal to the synchronous rectification unit 300.

[0022] Specifically, the input sampling subunit 210 includes a first resistor R1 and a second resistor R2. Both the first resistor R1 and the second resistor R2 are used as voltage divider resistors. The first end of the first resistor R1 is electrically connected to port 1 of the anti-current backflow control unit 200, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected to port 5 of the anti-current backflow control unit 200, and the second end of the first resistor R1 serves as the output terminal of the input sampling subunit 210 and is electrically connected to the input terminal of the shutdown control subunit 220.

[0023] Specifically, the shutdown control subunit 220 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a reference chip IC1, a PNP transistor V1, an NMOS transistor V2, a first capacitor C1, a second capacitor C2, a first diode D1, and a second diode D2. The third resistor R3 and the sixth resistor R6 are current-limiting resistors, the fourth resistor R4 and the fifth resistor R5 are discharge resistors, the first capacitor C1 and the second capacitor C2 are energy storage capacitors, and the first diode D1 and the second diode D2 are rectifier diodes. In this embodiment, the reference chip IC1 is preferably a TLV431.

[0024] One end of the third resistor R3 is electrically connected to the second port 2, and the other end is electrically connected to the A terminal of the reference chip IC1. The R terminal of the reference chip IC1 is electrically connected to the second terminal of the first resistor R1 to receive the sampling voltage, and the K terminal of the reference chip IC1 is electrically connected to the fifth port 5. The emitter of the PNP transistor V1 is electrically connected to the A terminal of the reference chip IC1, the collector of the PNP transistor V1 is electrically connected to the fifth port 5, and the base of the PNP transistor V1 is electrically connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the fifth port 5 through the fourth resistor R4. The anode of the first diode D1 is electrically connected to the third port 3, and the cathode of the first diode D1 is electrically connected to the second terminal of the sixth resistor R6. The positive terminal of the first capacitor C1 is electrically connected to the cathode of the first diode D1, and the negative terminal of the first capacitor C1 is electrically connected to the fifth port 5. The anode of the second diode D2 is electrically connected to terminal A of the reference chip IC1, and the cathode of the second diode D2 is connected to the fifth port 5 through the second capacitor C2. One end of the fifth resistor R5 is electrically connected to the cathode of the second diode D2, and the other end of the fifth resistor R5 is electrically connected to the fifth port 5. The gate of the NMOS transistor V2 is electrically connected to the cathode of the second diode D2, the drain of the NMOS transistor V2 is electrically connected to the fourth port 4, and the source of the NMOS transistor V2 is electrically connected to the fifth port 5.

[0025] The delay time (i.e., the turn-off time) for maintaining the synchronous rectification unit 300 in the off state can be set by adjusting the capacitance of the second capacitor C2 and the resistance value of the fifth resistor R5. This delay time determines the duration for which the synchronous rectification unit 300 is forcibly turned off when the input voltage is rapidly restarted after an abnormal power outage. This delay time can be set according to actual needs to ensure that the large capacitor (not shown in the figure) connected to the output terminal of the synchronous rectification unit 300 has sufficient time to discharge to a safe voltage, thereby preventing current backflow and circuit burnout. The second capacitor C2, as an energy storage element, directly affects the discharge speed; a larger capacitance means more stored charge, a longer discharge time to the NMOS transistor V2 threshold voltage Vth, and a longer turn-off time. The fifth resistor R5 is connected in parallel with the second capacitor C2, providing a discharge path for C2. A larger resistance value of the fifth resistor R5 results in a smaller discharge current, a slower discharge speed, and a longer turn-off time. The turn-off time is proportional to the capacitance of the second capacitor C2 and the resistance of the fifth resistor R5.

[0026] Even if the input voltage restarts rapidly within the set delay time, the synchronous rectifier unit 300 remains inactive, and the voltage on the large capacitor connected to the output terminal of the synchronous rectifier unit 300 continues to discharge. Once the set delay time is reached, the output shutdown control signal stops, and the synchronous rectifier unit 300 starts operating. At this time, the voltage on the large capacitor discharges to a safe voltage, preventing backflow current from occurring during the rapid restart of the synchronous rectifier unit 300. This effectively prevents damage to the secondary synchronous rectifier diodes caused by backflow current during rapid restart.

[0027] Specifically, the synchronous rectification unit 300 includes a first undervoltage divider resistor Ruv1, a second undervoltage divider resistor Ruv2, a PWM controller U1, and a synchronous rectification power conversion and feedback subunit 310. The first terminal of the first undervoltage divider resistor Ruv1 is electrically connected to the positive input terminal. The second terminal of the first undervoltage divider resistor Ruv1 is electrically connected to the first terminal of the second undervoltage divider resistor Ruv2. The second terminal of the second undervoltage divider resistor Ruv2 is electrically connected to the negative input terminal. The first terminal of the second undervoltage divider resistor Ruv2 is electrically connected to the UVLO pin of the PWM controller U1. The Vi pin of the PWM controller U1 is electrically connected to the output terminal of the power supply unit 100. The PWM pin of the PWM controller U1 is electrically connected to the third port 3. The UVLO pin of the PWM controller U1 is electrically connected to the fourth port 4. The GND pin of the PWM controller U1 is electrically connected to the negative input terminal. The PWM controller U1 is connected to the synchronous rectification power conversion and feedback subunit 310. The first output terminal of the synchronous rectification power conversion and feedback subunit 310 is electrically connected to the positive output terminal, and the second output terminal of the synchronous rectification power conversion and feedback subunit 310 is electrically connected to the output ground terminal. The synchronous rectification power conversion and feedback subunit 310 has a conventional structure and will not be described in detail here.

[0028] To prevent misjudgment of abnormal power outages and to prevent current backflow during rapid restarts after an abnormal power outage, as a preferred implementation, the trigger voltage of the anti-current backflow control unit 200 is set lower than the undervoltage turn-on voltage of the synchronous rectification unit 300. The trigger voltage of the anti-current backflow control unit 200 refers to the input voltage when the voltage obtained by voltage division through the first resistor R1 and the second resistor R2 (i.e., the sampling voltage) is equal to the reference voltage of the reference chip IC1. The undervoltage turn-on voltage of the synchronous rectification unit 300 refers to the input voltage when the voltage at the UVLO pin of the synchronous rectification unit 300 (i.e., the voltage obtained by voltage division through the first undervoltage divider resistor Ruv1 and the second undervoltage divider resistor Ruv2) is equal to the turn-on threshold of the PWM controller U1. Specifically, this can be achieved by setting the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 to be less than the ratio of the resistance value of the first undervoltage divider resistor Ruv1 to the resistance value of the second undervoltage divider resistor Ruv2, thus ensuring that the trigger voltage of the anti-current backflow control unit 200 is lower than the undervoltage turn-on voltage of the synchronous rectification unit 300.

[0029] When the input voltage drops below the undervoltage lock-up voltage of the synchronous rectifier unit 300 but above the trigger voltage of the reverse current protection control unit 200, it is not an abnormal power failure, and the reverse current protection control unit 200 will not output a shutdown control signal. When the input voltage drops below the trigger voltage of the reverse current protection control unit 200, it is an abnormal power failure, and the reverse current protection control unit 200 will output a shutdown control signal to the synchronous rectifier unit 300.

[0030] The working principle of the synchronous rectifier circuit abnormal power failure anti-current backflow control device of the present invention is as follows: When the input voltage initially rises below the trigger voltage of the anti-current backflow control unit 200, the power supply voltage is established normally, and the reference chip IC1 does not pull down the voltage VA at terminal A. Simultaneously, because the input voltage is lower than the undervoltage lockout voltage of the synchronous rectifier unit 300, the PWM controller U1 also does not operate. The base voltage of the PNP transistor V1 is 0 (i.e., the voltage VB at terminal B is 0), and the PNP transistor V1 conducts, pulling down the voltage VA at terminal A. The VG voltage is low, and the NMOS transistor V2 does not conduct, thus not outputting a shutdown control signal and not affecting the normal establishment of the UVLO pin voltage of the PWM controller U1.

[0031] When the input voltage rises above the trigger voltage of the anti-current backflow control unit 200, but is below the undervoltage turn-on voltage of the synchronous rectification unit 300, the voltage division value (sampled voltage) obtained by dividing the input voltage using the first resistor R1 and the second resistor R2 is greater than the reference voltage of the reference chip IC1, and the voltage VA at terminal A of the reference chip IC1 is pulled low. Simultaneously, because the input voltage is below the undervoltage turn-on voltage of the synchronous rectification unit 300, the PWM controller U1 also does not operate. The base voltage of the PNP transistor V1 is 0, and PNP transistor V1 conducts, pulling the voltage VA low. The VG voltage is low, the NMOS transistor V2 does not conduct, and no shutdown control signal is output, thus not affecting the normal establishment of the UVLO pin voltage of the PWM controller U1.

[0032] When the input voltage rises above the undervoltage lockout voltage of the synchronous rectification unit (300V), the PWM controller U1 starts outputting PWM pulses. These pulses are rectified by the first diode D1 and the first capacitor C1 to obtain a high-level voltage VB at terminal B, turning off the PNP transistor V1. If the sampled voltage is greater than the reference voltage of the reference chip IC1, the voltage VA at terminal A of the reference chip IC1 is pulled low. At this time, the VG voltage is low, the NMOS transistor V2 is not turned on, and no turn-off control signal is output, thus not affecting the normal establishment of the UVLO pin voltage of the PWM controller U1.

[0033] During normal operation, if the input voltage exceeds the undervoltage turn-on voltage of the synchronous rectification unit 300, the PWM controller U1 will operate normally. The sampling voltage of the input sampling subunit 210 is greater than the reference voltage of the reference chip IC1. The voltage VA at terminal A of the reference chip IC1 is pulled low. The voltage VG is obtained by subtracting the forward voltage drop of the second diode D2 from the voltage VA. At this time, the voltage VG is lower than the threshold voltage Vth of the NMOS transistor V2, so the NMOS transistor V2 is not turned on and will not output a turn-off control signal. Therefore, the anti-current backflow control unit 200 does not affect the normal operation of the synchronous rectification unit 300.

[0034] When the input voltage fails to drop below the undervoltage turn-on voltage of the synchronous rectifier unit 300 and restarts immediately, the synchronous rectifier unit 300 remains in normal working condition and there is no current backflow problem. The entire synchronous rectifier circuit's abnormal power failure anti-current backflow control device is in normal working condition.

[0035] When the input voltage abnormally drops below the undervoltage turn-on voltage of the synchronous rectification unit 300, the PWM pulse signal is rectified by the first diode D1 and the first capacitor C1 to obtain a high-level voltage VB at terminal B. This VB is then naturally discharged through the fourth resistor R4, maintaining a high level, and the PNP transistor V1 remains off. When the input voltage is lower than the trigger voltage of the anti-current-backflow control unit 200, the sampling voltage is less than the reference voltage of the reference chip IC1. The voltage VA at terminal A of the reference chip IC1 is pulled up to the supply voltage VCC. The voltage VA at terminal A of the reference chip IC1 charges the second capacitor C2 through the second diode D2. After the gate voltage VG of the NMOS transistor V2 is charged to VCC-VBE, the NMOS transistor V2 turns on, outputting a turn-off control signal that pulls down the voltage of the UVLO pin of the PWM controller U1, causing the synchronous rectification unit 300 to stop working. At this time, the second capacitor C2 is discharged through the fifth resistor R5, causing the gate voltage VG of NMOS transistor V2 to decrease. Before the gate voltage VG of NMOS transistor V2 discharges to its threshold voltage Vth, NMOS transistor V2 remains on, outputting a turn-off control signal that continuously pulls the voltage of the UVLO pin of PWM controller U1 low, and the synchronous rectification unit 300 remains inactive. When the gate voltage VG of NMOS transistor V2 is discharged to a level less than or equal to its threshold voltage Vth, NMOS transistor V2 turns off, and the voltage of the UVLO pin of PWM controller U1 is obtained by dividing the input voltage through the first undervoltage divider resistor Ruv1 and the second undervoltage divider resistor Ruv2, thereby enabling the synchronous rectification unit 300 to start normally.

[0036] Please see Figure 3 , Figure 3(a) is the working waveform diagram of the synchronous rectifier circuit when it is under the control of anti-current backflow without abnormal power failure and when it is quickly restarted after abnormal power failure. During the rapid restart of the input voltage, the current backflow phenomenon occurs at the output terminal. Because the current is large and the energy is consumed quickly during the current backflow, the output voltage drops rapidly in a short period of time. Figure 3 (b) is a waveform diagram of the working process of abnormal power failure and fast restart after the synchronous rectifier circuit abnormal power failure and anti-current backflow control device of the present invention. During the rapid restart of the input voltage, there is no current backflow phenomenon in the output, and the output terminal discharges smoothly until the turn-off time reaches the set turn-off time. At this time, the output voltage has been discharged to the safe voltage, the input voltage restarts, the output voltage is established normally, and there is no current backflow.

[0037] This invention also discloses a method for preventing backflow of current during abnormal power failure of a synchronous rectifier circuit. The method is based on the synchronous rectifier circuit abnormal power failure prevention backflow control device described in the above embodiments. One embodiment of the control method of this invention includes: when the input voltage is first powered on, no shutdown control signal is output, and the synchronous rectifier unit starts normally; when the input voltage remains normal, no shutdown control signal is output, and the synchronous rectifier unit operates normally; when the input voltage experiences an abnormal power failure, a shutdown control signal is output to disconnect the connection path between the input and output terminals of the synchronous rectifier unit to prevent backflow of current.

[0038] This invention utilizes a reverse current control unit to monitor input voltage changes in real time. Upon detecting an abnormal power outage, it outputs a shutdown control signal. During rapid restart, the shutdown control signal delays the startup of the synchronous rectifier unit, providing sufficient energy discharge time for the capacitor to drop its voltage to a safe level. This completely avoids the massive current and voltage spikes caused by reverse current during the restart of the synchronous rectifier unit, preventing the synchronous rectifier diodes and other power devices from burning out. By setting the trigger voltage of the reverse current control unit lower than the undervoltage lockout voltage of the synchronous rectifier unit, it accurately distinguishes between normal shutdown and abnormal power outages, avoiding malfunctions, and ensures prevention of reverse current during abnormal power outage restarts. This solution requires no complex digital processors or dedicated chips, featuring a simple structure that is easy to implement and integrate, significantly reducing the complexity and manufacturing cost, and facilitating widespread adoption. The shutdown delay time of the synchronous rectifier unit can be flexibly adjusted according to the output capacitor capacity and load characteristics of different products to achieve optimal protection, meeting the needs of diverse application scenarios.

[0039] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A synchronous rectifier circuit abnormal power failure prevention and current backflow control device, characterized in that, include: The power supply unit is used to connect the input voltage and convert the input voltage into the supply voltage to power the anti-current backflow control unit and the synchronous rectification unit; The anti-current backflow control unit is used to sample the input voltage in real time and output a shutdown control signal to the synchronous rectification unit after detecting an abnormal power failure of the input voltage; as well as The synchronous rectification unit is used to rectify the input voltage connected to its input terminal and output it from its output terminal, and disconnect the connection between its input terminal and output terminal after receiving a shutdown control signal.

2. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 1, characterized in that, The anti-current backflow control unit includes: The input sampling subunit is used to perform real-time voltage division sampling of the input voltage to obtain the sampled voltage; The shutdown control subunit is used to compare the sampled voltage with a set reference voltage. When the sampled voltage is less than the reference voltage, it outputs a shutdown control signal to shut down the synchronous rectification unit until a set delay time is reached, at which point it stops outputting the shutdown control signal.

3. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 2, characterized in that: The anti-current backflow control unit further includes a first port, a second port, a third port, a fourth port, and a fifth port; the first port is electrically connected to the positive input terminal, the fifth port is electrically connected to the negative input terminal, the second port is electrically connected to the output terminal of the power supply unit, the third port is used to receive the pulse signal output by the synchronous rectification unit, and the fourth port is used to output the shutdown control signal to the synchronous rectification unit.

4. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 3, characterized in that: The input sampling subunit includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is electrically connected to the first port of the anti-current backflow control unit, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected to the fifth port of the anti-current backflow control unit, and the second end of the first resistor R1 serves as the output end of the input sampling subunit and is electrically connected to the input end of the shutdown control subunit.

5. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 4, characterized in that: The shutdown control subunit includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a reference chip IC1, a PNP transistor V1, an NMOS transistor V2, a first capacitor C1, a second capacitor C2, a first diode D1, and a second diode D2. One end of the third resistor R3 is electrically connected to the second port, and the other end is electrically connected to the A terminal of the reference chip IC1; the R terminal of the reference chip IC1 is electrically connected to the second terminal of the first resistor R1 to receive the sampling voltage, and the K terminal of the reference chip IC1 is electrically connected to the fifth port; the emitter of the PNP transistor V1 is electrically connected to the A terminal of the reference chip IC1, the collector of the PNP transistor V1 is electrically connected to the fifth port, the base of the PNP transistor V1 is electrically connected to the first terminal of the sixth resistor R6, and the second terminal of the sixth resistor R6 is connected to the fifth port through the fourth resistor R4; the anode of the first diode D1 is electrically connected to the third port, and the first diode D1... The cathode of the first diode is electrically connected to the second terminal of the sixth resistor R6; the positive terminal of the first capacitor C1 is electrically connected to the cathode of the first diode D1, and the negative terminal of the first capacitor C1 is electrically connected to the fifth port; the anode of the second diode D2 is electrically connected to terminal A of the reference chip IC1, and the cathode of the second diode D2 is connected to the fifth port through the second capacitor C2; one end of the fifth resistor R5 is electrically connected to the cathode of the second diode D2, and the other end of the fifth resistor R5 is electrically connected to the fifth port; the gate of the NMOS transistor V2 is electrically connected to the cathode of the second diode D2, the drain of the NMOS transistor V2 is electrically connected to the fourth port, and the source of the NMOS transistor V2 is electrically connected to the fifth port.

6. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 5, characterized in that: The reference chip IC1 is model TLV431.

7. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 3, characterized in that: The synchronous rectification unit includes a first undervoltage divider resistor Ruv1, a second undervoltage divider resistor Ruv2, a PWM controller U1, and a synchronous rectification power conversion and feedback subunit; the first terminal of the first undervoltage divider resistor Ruv1 is electrically connected to the positive input terminal, the second terminal of the first undervoltage divider resistor Ruv1 is electrically connected to the first terminal of the second undervoltage divider resistor Ruv2, and the second terminal of the second undervoltage divider resistor Ruv2 is electrically connected to the negative input terminal; the first terminal of the second undervoltage divider resistor Ruv2 is electrically connected to the UVLO pin of the PWM controller U1; the PW The Vi pin of the M controller U1 is electrically connected to the output terminal of the power supply unit. The PWM pin of the PWM controller U1 is electrically connected to the third port. The UVLO pin of the PWM controller U1 is electrically connected to the fourth port. The GND pin of the PWM controller U1 is electrically connected to the negative input terminal. The PWM controller U1 is connected to the synchronous rectified power output ground conversion and feedback subunit. The first output terminal of the synchronous rectified power conversion and feedback subunit is electrically connected to the positive output terminal. The second output terminal of the synchronous rectified power conversion and feedback subunit is electrically connected to the output ground terminal.

8. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 2, characterized in that: The trigger voltage of the anti-current backflow control unit is set lower than the undervoltage turn-on voltage of the synchronous rectification unit.

9. The synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in claim 5, characterized in that: The delay time for the synchronous rectification unit to remain in the off state is set by setting the capacitance of the second capacitor C2 and the resistance value of the fifth resistor R5.

10. A method for preventing backflow of current during abnormal power failure of a synchronous rectifier unit, characterized in that, Based on the synchronous rectifier circuit abnormal power failure anti-current backflow control device as described in any one of claims 1-9, including: When the input voltage is first powered on, no shutdown control signal is output, and the synchronous rectifier unit starts normally; When the input voltage fails due to an abnormal power loss, the output shutdown control signal disconnects the connection between the input and output terminals of the synchronous rectifier unit.

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