Automatic gain control device and method, electronic equipment, chip and medium
By generating a synchronous update signal in hardware, the asynchronous AGC update problem of PCC and SCC in non-continuous carrier aggregation system is solved, synchronous control of AGC gain is realized, and signal quality is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2025-12-12
- Publication Date
- 2026-04-21
AI Technical Summary
In a non-continuous carrier aggregation system, the asynchronous AGC update signals and path enable of the PCC and SCC configured in the software cause gain and phase fluctuations in the PCC when the SCC is turned on and off, affecting signal quality.
A hardware update flag is generated by hardware, the LNA status is detected and a synchronous update signal is generated to ensure that the AGC gain configuration and path enable of PCC and SCC are effective synchronously, thus avoiding gain and phase fluctuations.
Synchronous control of AGC updates for PCC and SCC in NCCA mode was achieved, eliminating timing issues of asynchronous software operation and ensuring signal quality.
Smart Images
Figure CN121907171A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of gain control technology, and in particular to an automatic gain control device and method, electronic device, chip and medium. Background Technology
[0002] In communication systems, multiple non-adjacent carrier elements can be aggregated within the same frequency band to achieve greater transmission bandwidth. In Non-Contiguous Carrier Aggregation (NCCA) systems, the Primary Carrier Component (PCC) and Secondary Carrier Component (SCC) work together. The PCC provides basic connectivity and control functions, while the SCC supplements and expands the system's bandwidth and capacity, jointly providing higher-quality communication services to the User Equipment (UE). Summary of the Invention
[0003] This disclosure provides an automatic gain control device and method, electronic device, chip and medium, and proposes a method to enable simultaneous activation of AGC (Automatic Gain Control) configuration and path enablement of PCC and SCC through hardware in NCCA mode.
[0004] A first aspect of this disclosure provides an automatic gain control device, comprising: a hardware update flag generation module, a logic synthesis module, and a gain control module; the logic synthesis module is connected to both the hardware update flag generation module and the gain control module; the hardware update flag generation module includes at least one low-noise amplifier (LNA) detection unit and a logic OR unit, wherein the LNA detection unit is used to detect the state of at least one LNA, and the logic OR unit is used to generate a hardware update flag in response to an enable signal of a first LNA and a state switch of a third LNA in at least one second LNA under non-continuous carrier aggregation (NCCA) mode; the logic synthesis module is used to perform a logical AND operation on the hardware update flag with a primary carrier PCC path enable signal and a secondary carrier SCC path enable signal to generate a synchronization update signal; and the gain control module is used to synchronously update the automatic gain control (AGC) gain of the PCC and SCC according to the synchronization update signal.
[0005] In some embodiments of this disclosure, the device further includes a path enable interface module connected to the logic synthesis module; the path enable interface module is used to receive the PCC path enable signal and the SCC path enable signal.
[0006] In some embodiments of this disclosure, the LNA detection unit is configured to: in NCCA mode, detect the state of at least one second LNA in response to an open signal of a first LNA; output a detection signal in response to an open signal of the first LNA and an open signal or a closed signal of the third LNA, wherein there are exactly two LNAs that have detected an open signal; and the logic OR unit is configured to generate a hardware update flag in response to the detection signal output by any one of the at least one LNA detection units.
[0007] In some embodiments of this disclosure, the logic synthesis module is used to: generate a synchronous update signal for PCC in response to both the hardware update flag and the PCC path enable signal being valid; and generate a synchronous update signal for SCC in response to both the hardware update flag and the SCC path enable signal being valid.
[0008] In some embodiments of this disclosure, the gain control module is used to: simultaneously apply the first AGC gain value corresponding to PCC to the PCC receiving path and apply the second AGC gain value corresponding to SCC to the SCC receiving path when the synchronization update signal is active.
[0009] In some embodiments of this disclosure, the gain control module is used to: read a first AGC gain value from the storage location corresponding to the PCC and apply it to the interface controlling the PCC receiving path; and read a second AGC gain value from the storage location corresponding to the SCC and apply it to the interface controlling the SCC receiving path.
[0010] In the above embodiments, the automatic gain control device, in NCCA mode, detects the status of other LNAs after the first LNA is turned on, and generates a hardware update flag when the third LNA is turned on or off. The hardware update flag is then logically ANDed with a pre-configured software path enable signal to determine the validity of the hardware update flag and generate a synchronization update signal. This synchronization update signal ensures that the PCC and SCC can perform AGC gain updates synchronously, realizing synchronous control of AGC updates for two carriers in NCCA mode, avoiding gain and phase fluctuations, eliminating timing issues of asynchronous software operation, and ensuring signal quality.
[0011] A second aspect of this disclosure provides an automatic gain control method, comprising: in discontinuous carrier aggregation (NCCA) mode, in response to the activation of a first low-noise amplifier (LNA), generating a hardware update flag based on the state of at least one second LNA; generating a synchronization update signal based on the hardware update flag, a primary carrier PCC path enable signal, and a secondary carrier SCC path enable signal; and synchronously updating the automatic gain control (AGC) gain of the PCC and SCC according to the synchronization update signal.
[0012] In some embodiments of this disclosure, in response to the first low-noise amplifier (LNA) being turned on, a hardware update flag is generated based on the state of at least one second LNA, including: in response to an on or off signal of a third LNA in at least one second LNA, generating a hardware update flag, wherein there are exactly two LNAs that have detected an on signal.
[0013] In some embodiments of this disclosure, a synchronization update signal is generated based on a hardware update flag, a primary carrier PCC path enable signal, and a secondary carrier SCC path enable signal, including: generating a PCC synchronization update signal in response to both the hardware update flag and the PCC path enable signal being valid; and generating an SCC synchronization update signal in response to both the hardware update flag and the SCC path enable signal being valid.
[0014] In some embodiments of this disclosure, the automatic gain control (AGC) gain of PCC and SCC is synchronously updated according to the synchronization update signal, including: when the synchronization update signal of PCC is active, applying the first AGC gain value corresponding to PCC to the PCC receiving path; when the synchronization update signal of SCC is active, applying the second AGC gain value corresponding to SCC to the SCC receiving path, wherein the effective time of the synchronization update signal of PCC is the same as the effective time of the synchronization update signal of SCC.
[0015] In some embodiments of this disclosure, an AGC gain table is determined; a first AGC gain value is determined in the AGC gain table based on the effective time of the PCC synchronization update signal, and a second AGC gain value is determined in the AGC gain table based on the effective time of the SCC synchronization update signal.
[0016] In the above embodiments, the automatic gain control method in NCCA mode generates a hardware update flag at the moment when the third LNA is turned on or off. The hardware update flag is enabled by a pre-configured path enable signal to generate a synchronous update signal. The synchronous update signal ensures that the PCC and SCC can perform AGC gain updates synchronously, realizing synchronous control of AGC updates of two carriers in NCCA mode, avoiding gain and phase fluctuations, eliminating timing problems of asynchronous software operation, and ensuring signal quality.
[0017] A third aspect of this disclosure provides a communication apparatus comprising: a generation module for generating a hardware update flag in response to the activation of a first low-noise amplifier (LNA) and based on the state of at least one second LNA, in a discontinuous carrier aggregation (NCCA) mode; a processing module for generating a synchronization update signal based on the hardware update flag, a primary carrier PCC path enable signal, and a secondary carrier SCC path enable signal; and a control module for synchronously updating the automatic gain control (AGC) gain of the PCC and SCC according to the synchronization update signal.
[0018] In some embodiments of this disclosure, the generation module is configured to generate a hardware update flag in response to an open or closed signal of a third LNA in at least one second LNA, wherein there are exactly two LNAs that detect an open signal.
[0019] In some embodiments of this disclosure, the processing module is configured to: generate a synchronization update signal for the PCC in response to both the hardware update flag and the PCC path enable signal being valid; and generate a synchronization update signal for the SCC in response to both the hardware update flag and the SCC path enable signal being valid.
[0020] In some embodiments of this disclosure, the control module is configured to: apply the first AGC gain value corresponding to the PCC to the PCC receiving path when the PCC synchronization update signal is active; and apply the second AGC gain value corresponding to the SCC to the SCC receiving path when the SCC synchronization update signal is active, wherein the effective time of the PCC synchronization update signal is the same as the effective time of the SCC synchronization update signal.
[0021] In some embodiments of this disclosure, the control module is configured to: determine an AGC gain table; determine a first AGC gain value in the AGC gain table based on the effective time of the PCC synchronization update signal; and determine a second AGC gain value in the AGC gain table based on the effective time of the SCC synchronization update signal.
[0022] In the above embodiments, the communication device generates a hardware update flag at the moment when the third LNA is turned on or off in NCCA mode. The hardware update flag is enabled by a pre-configured path enable signal to generate a synchronous update signal. The synchronous update signal ensures that the PCC and SCC can perform AGC gain updates synchronously. This achieves synchronous control of AGC updates for the two carriers in NCCA mode, avoids gain and phase fluctuations, eliminates timing problems of asynchronous software operation, and ensures signal quality.
[0023] A fourth aspect of this disclosure provides an electronic device comprising: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method described in any one of the second aspects of this disclosure, or includes the means described in any one of the first aspects of this disclosure, or includes the means described in any one of the third aspects of this disclosure.
[0024] A fifth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method described in any of the second aspects of this disclosure.
[0025] A sixth aspect of this disclosure provides a computer program product that, when run on a computer, causes the computer to perform the method as described in any one of the second aspects of this disclosure.
[0026] A seventh aspect of this disclosure provides a chip including at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in any one of the second aspects of this disclosure through logic circuits or executing code instructions.
[0027] An eighth aspect of this disclosure provides a chip that includes the apparatus described in any one of the first aspects of this disclosure.
[0028] In summary, the automatic gain control device, method, electronic device, chip, and medium proposed in this disclosure, in NCCA mode, generate a hardware update flag at the moment the third LNA is turned on or off. The activation of the hardware update flag is controlled by a pre-configured path enable signal to generate a synchronous update signal. The synchronous update signal ensures that the PCC and SCC can perform AGC gain updates synchronously, realizing synchronous control of AGC updates of two carriers in NCCA mode, avoiding gain and phase fluctuations, eliminating timing problems of asynchronous software operation, ensuring signal quality, and solving the problem of gain and phase fluctuations in the PCC at the moment the SCC is turned on and off.
[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.
[0031] Figure 1 This is a schematic diagram of automatic gain control. Figure 2 This is a timing diagram for automatic gain control. Figure 3 This is a structural block diagram of an automatic gain control device proposed in an embodiment of this disclosure; Figure 4 This is a flowchart illustrating an automatic gain control method proposed in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating another automatic gain control method proposed in an embodiment of this disclosure; Figure 6 This is a flowchart illustrating another automatic gain control method proposed in an embodiment of this disclosure; Figure 7A The hardware structure diagram shows the AGC gain update method for PCC and SCC in non-continuous carrier aggregation mode. Figure 7B The timing diagram shows the AGC gain update method for PCC and SCC in discontinuous carrier aggregation mode; Figure 7C This is a flowchart illustrating the AGC gain update method for PCC and SCC in non-continuous carrier aggregation mode. Figure 8 This is a schematic diagram of the structure of a communication device according to an embodiment of the present disclosure; Figure 9 This is a schematic diagram of an electronic device for implementing the above-described automatic gain control method according to an exemplary embodiment; Figure 10 This is a schematic diagram of the structure of a chip for implementing the above-described automatic gain control method, according to an exemplary embodiment. Detailed Implementation
[0032] Embodiments of this disclosure are described in detail below, with examples of embodiments illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.
[0033] In communication systems, signals with varying sensitivity ranges need to be processed, and the input amplitude range of an ADC is limited. Therefore, the system needs to use AGC (Automatic Gain Control) to dynamically adjust the gain of the analog module to ensure the RF system operates at optimal performance. For example... Figure 1 The diagram shown illustrates the automatic gain control method. The CPU (Central Processing Unit), localbus, and AGC control are digital modules. Automatic gain control of the analog modules LNA (Low Noise Amplifier), LNA load, Mixer, ABB (Analog Baseband Processor), and ADC (Analog-to-Digital Converter) is achieved through the CPU-localbus-AGC control path.
[0034] In discontinuous carrier aggregation systems, because the software-configured PCC and SCC AGC update signals and path enable are asynchronous, the software cannot guarantee that the AGC configuration update signals and path enable will take effect simultaneously. This can lead to gain and phase fluctuations in the PCC when the SCC is turned on and off, resulting in a deterioration of the instantaneous EVM (Error Vector Magnitude). Figure 2 The timing diagram for the automatic gain control mode shown indicates that the AGC control word triggers an AGC update on the rising edge of the software-configured AGC update signal, i.e., updating from 1cc configuration to 2cc configuration. On the second rising edge, it triggers another AGC update, i.e., updating from 2cc configuration to 1cc configuration. However, in carrier aggregation mode, because the software-configured AGC update signal is asynchronous with the PCC and SCC activation times, precise alignment cannot be achieved. Therefore, after the PCC enable switch is set to 1, the SCC enable switch is also set to 1, triggering an AGC update. Specifically, on the rising edge of the SCC enable switch, it triggers an update from 1cc mode to 2cc mode, and on the falling edge of the SCC enable switch, it triggers another AGC update, i.e., updating from 2cc mode to 1cc mode. When the 1cc mode is updated to 2cc mode in carrier aggregation mode, the AGC control word is still configured as 1cc, which will cause the 2cc mode to use the 1cc configuration, thus affecting performance and causing EVM degradation. Similarly, when the 2cc mode is updated to 1cc mode in carrier aggregation mode, the AGC control word is still configured as 2cc, which will cause the 1cc mode to use the 2cc configuration, thus affecting performance and causing EVM degradation.
[0035] Therefore, this disclosure proposes an automatic gain control device and method that, through hardware, ensures that when the SCC is turned on and off, the AGC configuration and path enable of the PCC and SCC are simultaneously effective, and the PCC will not experience gain and phase fluctuations, thus ensuring that the EVM will not deteriorate.
[0036] The automatic gain control device and automatic gain control method proposed in this application will be described in detail below with reference to the accompanying drawings.
[0037] Figure 3 This is a structural block diagram of an automatic gain control device proposed in an embodiment of this disclosure, as shown below. Figure 3 As shown, the automatic gain control device 300 includes: a hardware update flag generation module 310, a logic synthesis module 320, and a gain control module 330.
[0038] The logic synthesis module is connected to the hardware update flag generation module and the gain control module, respectively.
[0039] The hardware update flag generation module includes at least one low-noise amplifier (LNA) detection unit and a logic OR unit. The LNA detection unit is used to detect the state of at least one LNA, and the logic OR unit is used to generate a hardware update flag in response to the turn-on signal of the first LNA and the state switching of the third LNA in at least one second LNA in the non-continuous carrier aggregation (NCCA) mode.
[0040] The logic synthesis module is used to perform logical AND processing on the hardware update flag with the primary carrier PCC path enable signal and the secondary carrier SCC path enable signal respectively to generate a synchronous update signal.
[0041] The gain control module is used to synchronously update the automatic gain control (AGC) gain of PCC and SCC according to the synchronization update signal.
[0042] In some embodiments, the first LNA may be the LAN corresponding to the primary carrier, and at least one second LNA may be all LNAs except the first LNA, that is, the hardware update flag generation module can detect the status of all LNAs.
[0043] In some embodiments, since there is no strict correspondence between PCC / SCC and LNA, in NCCA mode, regardless of which LNA is turned on, the status of all LNAs except that LNA will be checked to determine the time when the hardware update flag is generated.
[0044] In some embodiments, the detection unit is configured to: in NCCA mode, detect the state of at least one second LNA in response to an open signal of a first LNA; output a detection signal in response to an open signal of the first LNA and an open signal or a closed signal of a third LNA, wherein there are exactly two LNAs that have detected an open signal; and the logic OR unit is configured to generate a hardware update flag in response to the detection signal output by any one of the at least one LNA detection units.
[0045] Specifically, the first LNA is the LNA corresponding to the PCC, and the third LNA is the LNA corresponding to the SCC. For example, such as Figure 7AThe hardware structure diagram shown illustrates that when LNA0_en=1, the rising and falling edges of LNA1_en through LNAX_en are detected. A logical AND operation is performed on the input followed by a logical OR operation to generate the hw_upd flag, which serves as the trigger signal for AGC gain. Similarly, when LNA1_en=1, the rising and falling edges of LNA0_en, LNA2_en through LNAX_en are detected. A logical AND operation is performed on the input followed by a logical OR operation to generate the hw_upd flag, which also serves as the trigger signal for AGC gain. This process continues, and if different LNAs are turned on first, the rising and falling edges of other LNAs are detected. As soon as any LNA shows a rising or falling edge, a logical AND operation is performed on the input followed by a logical OR operation to generate the hw_upd flag.
[0046] In some embodiments, the hardware update flag is used in conjunction with the path enable signal to control the AGC gain update of the primary carrier and the secondary carrier to be performed simultaneously. In other words, the hardware update flag is synchronously input to the PCC logic synthesis unit and the SCC logic synthesis unit. The logic synthesis module includes the PCC logic synthesis unit and the SCC logic synthesis unit.
[0047] In some embodiments, the automatic gain control device further includes a path enable interface module, which is connected to the logic synthesis module; the path enable interface module is used to receive the PCC path enable signal and the SCC path enable signal.
[0048] Specifically, the path enable interface module is used to inform the logic synthesis module which two RX paths are open by the PCC path enable signal and SCC path enable signal configured in the software. Then, the hardware synthesis module can use the PCC path enable signal and SCC path enable signal to determine whether the hardware update flag is effective.
[0049] Furthermore, the hardware update flag is generated by detecting the status of the LNA, and the path enable signal is used to control whether the hardware update flag is active, so as to trigger the update of the AGC gain when it is active.
[0050] In some embodiments, the path enable signal is configured in software and input to the logic synthesis module through the path enable interface module to generate a synchronization update signal.
[0051] Specifically, the software-configured path enable signals are configured before the third LNA is turned on. That is, before the third LNA is turned on, the PCC path enable signals and SCC path enable signals are effective. Thus, when the third LNA is turned on, accurate synchronous update signal generation can be achieved, ensuring that the AGC gain update meets the gain requirements of the corresponding carrier mode when the path is turned on and off.
[0052] In some embodiments, the path enable signal is used to indicate the mapping relationship between the logical relationship of PCC / SCC and the physical address (RX path number), that is, on which physical RF path the pre-configured AGC configuration is applied. For example, register 1 is applied to physical path 3 (PCC), and register 2 is applied to physical path 2 (SCC).
[0053] For example, such as Figure 7A The hardware structure diagram shown illustrates that the software configures the PCC path enable signal pcc_enable and the SCC path enable signal scc_enable before SCC is enabled. The hardware uses pcc_enable and scc_enable to determine whether hw_upd is effective, implemented using logical AND.
[0054] In some embodiments, the logic synthesis module is configured to: generate a synchronous update signal for PCC in response to both the hardware update flag and the PCC path enable signal being valid; and generate a synchronous update signal for SCC in response to both the hardware update flag and the SCC path enable signal being valid.
[0055] In some embodiments, the logic synthesis module includes an AND unit corresponding to PCC and an AND unit corresponding to SCC.
[0056] Furthermore, in the logic AND unit corresponding to PCC, the hardware update flag and the PCC path enable signal are logically ANDed to generate the PCC synchronization update signal. In the logic AND unit corresponding to SCC, the hardware update flag and the SCC path enable signal are logically ANDed to generate the SCC synchronization update signal.
[0057] Specifically, when the first LNA and the third LNA are turned on, that is, when only two LNAs are turned on, the hardware update flag generates a pulse signal. The hardware update flag is logically ANDed with the valid PCC path enable signal to trigger the PCC to update the AGC gain. The hardware update flag is logically ANDed with the valid SCC path enable signal to trigger the SCC to update the AGC gain.
[0058] Furthermore, when the third LNA is off and only one LNA is on, the hardware update flag generates a pulse signal. The hardware update flag is logically ANDed with the valid PCC path enable signal to trigger the PCC to update the AGC gain. The hardware update flag is logically ANDed with the valid SCC path enable signal to trigger the SCC to update the AGC gain.
[0059] In some embodiments, the gain control module receives the synchronization update signal output by the logic synthesis module, and when the synchronization update signal is active, it synchronously updates the AGC gain corresponding to PCC and the AGC gain corresponding to SCC.
[0060] For example, such as Figure 7A The hardware structure diagram shown indicates that pcc_enable and hw_upd share a common input AND logic, and the output signal is sent to the PCC for AGC update; scc_enable and hw_upd share a common input AND logic, and the output signal is sent to the SCC for AGC update. Ultimately, the PCC and SCC use the signals after the AND logic to update the AGC gain of the PCC and SCC. The entire AGC gain update process is implemented in hardware, ensuring the timing of path opening and closing. The AGC gain meets the requirements of 2CC and 1CC gain, avoiding the degradation of EVM performance.
[0061] In some embodiments, the gain control module is configured to: apply the first AGC gain value corresponding to PCC to the PCC receiving path when the synchronization update signal is active, and apply the second AGC gain value corresponding to SCC to the SCC receiving path.
[0062] Specifically, the synchronization update signals include the PCC synchronization update signal and the SCC synchronization update signal, and the PCC synchronization update signal and the SCC synchronization update signal take effect at the same time, which ensures that the AGC gain update of PCC and SCC can be performed synchronously.
[0063] Furthermore, when the PCC synchronization update signal takes effect, the PCC is triggered to perform an AGC gain update, that is, to update the current AGC gain value to the gain value of the PCC in the AGC gain table at the time of the effect; when the SCC synchronization update signal takes effect, the SCC is triggered to perform an AGC gain update, that is, to update the current AGC gain to the gain value of the SCC in the AGC gain table at the time of the effect.
[0064] In some embodiments, the AGC gain table is a list of gain values pre-configured by software for PCC and SCC in different modes, wherein the gain values of PCC and SCC may be the same or different.
[0065] In some embodiments, the gain control module includes a PCC gain control unit and an SCC gain control unit. The PCC gain control unit is used to apply a first AGC gain value to the PCC receiving path when the PCC synchronization update signal is active. The SCC gain control unit is used to apply a second AGC gain value to the SCC receiving path when the SCC synchronization update signal is active.
[0066] In some embodiments, the gain control module is configured to: read a first AGC gain value from the storage location corresponding to the PCC and apply it to the interface controlling the PCC receiving path; and read a second AGC gain value from the storage location corresponding to the SCC and apply it to the interface controlling the SCC receiving path.
[0067] In some embodiments, when the PCC synchronization update signal triggers the PCC to perform AGC gain update, the corresponding gain control module needs to read the first AGC gain value at the current moment from the storage location corresponding to the PCC; when the SCC synchronization update signal triggers the SCC to perform AGC gain update, the corresponding gain control module needs to read the second AGC gain value at the current moment from the storage location corresponding to the SCC.
[0068] Specifically, when the first synchronization update signal triggers the AGC gain update, i.e., switching from 1cc mode to 2cc mode, the first AGC gain value and the second AGC gain value need to be determined in the AGC table corresponding to 2cc mode; when the second synchronization update signal triggers the AGC gain update, i.e., switching from 2cc mode to 1cc mode, the first AGC gain value and the second AGC gain value need to be determined in the AGC table corresponding to 1cc mode.
[0069] Specifically, the PCC gain control unit reads the first AGC gain value from the storage location of the PCC in the AGC gain table and applies it to the interface controlling the PCC receiving path; the SCC gain control unit reads the second AGC gain value from the storage location of the SCC in the AGC gain table and applies it to the interface controlling the SCC receiving path.
[0070] Furthermore, after reading the gain value that needs to be updated from the storage location, the corresponding gain value needs to be applied to the interface controlling the corresponding carrier receiving path, that is, the first AGC gain value is applied to the interface controlling the PCC receiving path, and the second AGC gain value is applied to the interface controlling the SCC receiving path.
[0071] For example, such as Figure 7B The timing diagram shows that at the rising edge of the first pulse of hw_upd, a logical AND operation is performed with pcc_enable and scc_enable respectively. This updates the AGC control word's configuration at the effective time of hw_upd, from 1cc configuration to 2cc configuration. Before the falling edge of the second pulse of hw_upd, another logical AND operation is performed with pcc_enable and scc_enable respectively. Again, at the effective time of hw_upd, the AGC control word updates its configuration from 2cc configuration to 1cc configuration. Correspondingly, the carrier aggregation operating mode switches from 1cc mode to 2cc mode when the SCC enable switch is set to 1, and switches from 2cc mode to 1cc mode when the SCC enable switch is set to 0, thus achieving synchronization between AGC control and mode switching.
[0072] In summary, the automatic gain control device proposed in this disclosure, in NCCA mode, has a hardware update flag generation module that detects the status of other LNAs after the first LNA is turned on, and generates a hardware update flag when the third LNA is turned on or off. The hardware update flag is then logically ANDed with a pre-configured software path enable signal to determine its validity and generate a synchronization update signal. This synchronization update signal ensures that the PCC and SCC can perform AGC gain updates synchronously, achieving synchronous control of AGC updates for two carriers in NCCA mode. This avoids gain and phase fluctuations, eliminates timing issues in asynchronous software operation, and guarantees signal quality.
[0073] Figure 4 This is a flowchart of an automatic gain control method proposed in an embodiment of this disclosure. Figure 4 As shown, the method includes the following steps: Step 401: In the non-continuous carrier aggregation (NCCA) mode, in response to the first low-noise amplifier (LNA) being turned on, a hardware update flag is generated based on the state of at least one second LNA.
[0074] In some embodiments, in response to the first low-noise amplifier (LNA) being turned on, a hardware update flag is generated based on the state of at least one second LNA, including: generating a hardware update flag in response to an on or off signal of a third LNA in at least one second LNA, wherein there are exactly two LNAs that have detected an on signal.
[0075] In some embodiments, the state of the LNA includes on and off. When an on signal is detected, the corresponding LNA is turned on, and when an off signal is detected, the corresponding LNA is turned off.
[0076] In some embodiments, in NCCA mode, there is no strict correspondence between PCC / SCC and LNA. In response to the first LNA being turned on, the first LNA corresponds to PCC. Rising and falling edges are detected in at least one second LNA other than the first LNA to determine whether there are carriers that are turned on and off. When the turn-on signal of the third LNA is detected, the third LNA corresponds to SCC. The turn-on and turn-off signals of the third LNA will trigger the switching of the carrier aggregation working mode.
[0077] Specifically, when the activation signal of the third LNA is detected, the carrier aggregation operating mode is switched from 1cc mode to 2cc mode; when the deactivation signal of the third LNA is detected, the carrier aggregation operating mode is switched from 2cc mode to 1cc mode.
[0078] Furthermore, when the on and off signals of the third LNA are detected, a hardware update flag will be generated simultaneously. That is, a pulse signal will be output at the time corresponding to the on signal and a pulse signal will be output at the time corresponding to the off signal. Both pulse signals are used to instruct the hardware module to perform AGC update.
[0079] In some embodiments, the hardware update flag can be the hw_upd signal, with the first hw_upd signal generated when the third LNA is turned on and the second hw_upd signal generated when the third LNA is turned off.
[0080] For example, such as Figure 7C The flowchart shown illustrates that when SCC is turned on, the hardware automatically generates the hw_upd signal. When SCC is turned off, the hardware automatically generates the hw_upd signal. When SCC is turned on, the hardware does not generate the hw_upd signal.
[0081] Step 402: Generate a synchronization update signal based on the hardware update flag, the primary carrier PCC path enable signal, and the secondary carrier SCC path enable signal.
[0082] In some embodiments, the PCC path enable signal and the SCC path enable signal can be pre-configured enable signals to inform the hardware of the two RX paths corresponding to NCCA.
[0083] In some embodiments, the PCC path enable signal and the SCC path enable signal are configured before the third LNA is turned on so that a synchronization update signal is generated in a timely manner when the third LNA is turned on.
[0084] In some embodiments, a synchronization update signal is generated based on the hardware update flag, the PCC path enable signal, and the SCC path enable signal. This can be achieved by logically synthesizing the hardware update flag with the PCC path enable signal and the SCC path enable signal to generate the PCC synchronization update signal and the SCC synchronization update signal, respectively.
[0085] Specifically, since the PCC path enable signal and the SCC path enable signal take effect at the same time, it can be guaranteed that the generated synchronous update signal will also take effect at the same time.
[0086] Step 403: Synchronously update the automatic gain control (AGC) gain of PCC and SCC according to the synchronization update signal.
[0087] In some embodiments, the automatic gain control (AGC) gain of PCC and SCC is updated synchronously according to the synchronization update signal. This can be done by updating the AGC gain of PCC based on the effective time of the synchronization update signal of PCC, and updating the AGC gain of SCC based on the effective time of the synchronization update signal of SCC.
[0088] In some embodiments, before the third LNA is turned on and off, the gain tables of PCC and SCC are pre-configured, that is, the AGC configurations of PCC and SCC are stored in their respective registers, wherein the AGC configuration includes the specific AGC gain value required in the current scenario.
[0089] Specifically, the AGC table shows the gain values for PCC and SCC in different operating modes. For example, mode 1cc corresponds to one gain configuration, which typically only includes the gain value of PCC; mode 2cc corresponds to another gain configuration, which includes independent gain values for both PCC and SCC. The gain values for PCC and SCC can be the same or different.
[0090] Furthermore, before turning SCC on or off, the corresponding AGC value is calculated and written to a hardware register or memory area based on the target mode being switched (e.g., switching from 1cc to 2cc). The AGC value to be updated has already been written before the synchronization update signal is triggered. When SCC is turned on, the system switches from 1cc mode to 2cc mode, thus applying the gain value stored in 2cc mode for AGC updates.
[0091] Specifically, before the third LNA is turned off, the PCC's AGC table is configured so that when the SCC is turned off, it switches from 2cc mode to 1cc mode, thereby applying the gain value stored in 1cc mode for AGC update.
[0092] In the above embodiments, the automatic gain control method, in NCCA mode, detects the opening and closing of all LNAs, and generates a hardware update flag when only two LNAs are open. It then generates a synchronous update signal by logically synthesizing the PCC path enable signal and the SCC path enable signal, respectively. This ensures that the AGC gain update meets the gain requirements of both 2cc and 1cc modes when the paths are open and closed, thus avoiding the deterioration of EVM performance.
[0093] Figure 5 This is a flowchart illustrating another automatic gain control method proposed in an embodiment of this disclosure. Based on Figure 4 The embodiment shown, Figure 5 right Figure 4 Step 402 in the text is further defined, such as Figure 5 As shown, the method includes the following steps: Step 501: In response to the hardware update flag and the PCC path enable signal both being valid, a PCC synchronization update signal is generated.
[0094] In some embodiments, the hardware update flag and the PCC path enable signal are logically ANDed to generate a PCC synchronization update signal.
[0095] In some embodiments, when the third LNA is turned on, a first hardware update flag is generated. That is, the pulse signal of the first hardware update flag is logically ANDed with the PCC path enable signal to generate a first PCC synchronization update signal, which triggers the PCC to perform the first AGC gain update.
[0096] In some embodiments, when the third LNA is turned off, a second hardware update flag is generated. That is, the pulse signal of the second hardware update flag is logically ANDed with the PCC path enable signal to generate a second PCC synchronization update signal, which triggers the PCC to perform a second AGC gain update.
[0097] Step 502: In response to the hardware update flag and the SCC path enable signal both being valid, a synchronous update signal for the SCC is generated.
[0098] In some embodiments, the hardware update flag and the SCC path enable signal are logically ANDed to generate a synchronous update signal for the SCC.
[0099] In some embodiments, when the third LNA is turned on, a first hardware update flag is generated. That is, the pulse signal of the first hardware update flag is logically ANDed with the SCC path enable signal to generate a first SCC synchronization update signal, which triggers the SCC to perform the first AGC gain update.
[0100] In some embodiments, when the third LNA is turned off, a second hardware update flag is generated. That is, the pulse signal of the second hardware update flag is logically ANDed with the SCC path enable signal to generate a second SCC synchronization update signal, which triggers the SCC to perform a second AGC gain update.
[0101] In some embodiments, since the PCC path enable signal and the SCC path enable signal are pre-configured, meaning that the two path enable signals take effect at the same time, the synchronous update signal generated by performing a logical AND operation with the hardware update flag also takes effect at the same time. This ensures the synchronization of AGC gain updates when the path is opened and closed, further improving signal reception quality and RF performance. Figure 6 This is a flowchart illustrating another automatic gain control method proposed in an embodiment of this disclosure. Based on Figures 4-5 The embodiment shown, Figure 6 right Figure 4 Step 403 in the text is further defined, such as Figure 6 As shown, it includes the following steps.
[0102] Step 601: When the synchronization update signal of PCC is active, apply the first AGC gain value corresponding to PCC to the PCC receiving path.
[0103] In some embodiments, the effective time of the PCC synchronization update signal is the same as the effective time of the SCC synchronization update signal.
[0104] In some embodiments, the method further includes: determining an AGC gain table; determining a first AGC gain value in the AGC gain table based on the effective time of the PCC synchronization update signal; and determining a second AGC gain value in the AGC gain table based on the effective time of the SCC synchronization update signal.
[0105] In some embodiments, the AGC gain table is pre-configured for PCC and SCC. In different modes, the gain values corresponding to PCC and SCC in the configured AGC gain table may be different or the same, and this disclosure does not limit this.
[0106] Specifically, in 1cc mode, the configured AGC gain table includes the gain value corresponding to PCC and the gain value corresponding to SCC; in 2cc mode, the configured AGC gain table includes the gain value corresponding to PCC and the gain value corresponding to SCC. The gain values of PCC and SCC can be the same or different within the same mode, and this disclosure does not impose any restrictions on this.
[0107] In some embodiments, when the PCC's synchronization update signal triggers the PCC to perform an AGC gain update, the first AGC gain value at the effective time is read from the PCC's storage location; when the SCC's synchronization update signal triggers the SCC to perform an AGC gain update, the second AGC gain value at the effective time is read from the SCC's storage location.
[0108] Specifically, when the first synchronization update signal triggers the AGC gain update, i.e., switching from 1cc mode to 2cc mode, the first AGC gain value and the second AGC gain value need to be determined in the AGC table corresponding to 2cc mode; when the second synchronization update signal triggers the AGC gain update, i.e., switching from 2cc mode to 1cc mode, the first AGC gain value and the second AGC gain value need to be determined in the AGC table corresponding to 1cc mode.
[0109] Specifically, the synchronization update signal of PCC and the synchronization update signal of SCC take effect at the same time, so the first AGC gain value and the second AGC gain value will be determined synchronously.
[0110] Furthermore, after reading the gain value that needs to be updated from the storage location, the corresponding gain value needs to be applied to the interface controlling the corresponding carrier receiving path, that is, the first AGC gain value is applied to the interface controlling the PCC receiving path, so as to apply the first AGC gain value to the PCC receiving path.
[0111] Step 602: When the synchronization update signal of SCC is active, apply the second AGC gain value corresponding to SCC to the SCC receiving path.
[0112] In some embodiments, when the synchronization update signal of the SCC triggers the SCC to perform an AGC gain update, the second AGC gain value at the effective time is read from the storage location of the register corresponding to the SCC.
[0113] Furthermore, after reading the gain value that needs to be updated from the storage location, the corresponding gain value needs to be applied to the interface controlling the corresponding carrier receiving path, that is, the second AGC gain value is applied to the interface controlling the SCC receiving path, so as to apply the second AGC gain value to the SCC receiving path.
[0114] In the above embodiments, by performing a logical AND operation between the hardware update flag and the PCC path enable signal and the SCC path enable signal respectively, a synchronous update signal that takes effect simultaneously can be generated to perform synchronous AGC gain update of PCC and SCC, ensuring that the configuration and enable of PCC and SCC take effect synchronously, thereby improving signal reception quality and RF performance.
[0115] In summary, the automatic gain control method proposed in this disclosure, in NCCA mode, generates a hardware update flag at the moment the third LNA is turned on or off. The activation of the hardware update flag is controlled by a pre-configured path enable signal to generate a synchronous update signal. The synchronous update signal ensures that the PCC and SCC can perform AGC gain updates synchronously, realizing synchronous control of AGC updates of two carriers in NCCA mode, avoiding gain and phase fluctuations, eliminating timing problems of asynchronous software operation, and ensuring signal quality.
[0116] The following is a specific implementation of an AGC gain update method for PCC and SCC in a non-continuous carrier aggregation mode: 1. Software requirements: (1) The software has completed the write operation of the AGC table before opening and closing SCC; (2) Before opening SCC, the software needs to inform the hardware which two RX paths correspond to NCCA.
[0117] 2. In NCCA mode, since there is no strict correspondence between PCC / SCC and LNA, the hardware needs to detect the SCC on and off flags in all LNA scenarios. In the NCCA scenario, there are exactly two LNAs on. The logic is that when one LNA is on, the on and off status of the other LNA is detected. The hw_upd flag serves as the trigger signal for AGC gain. Simultaneously, the software needs to configure pcc_enable and scc_enable before SCC is enabled to inform the hardware which two RX paths are on. The hardware uses pcc_enable and scc_enable to determine whether hw_upd is effective, implemented using logical AND. Finally, PCC and SCC use the signals after the logical AND to update the AGC gain of PCC and SCC. The entire AGC gain update process is automatically implemented by the hardware, ensuring that the AGC gain meets the 2cc and 1cc gain requirements at the time of path opening and closing, thus avoiding EVM performance degradation.
[0118] like Figure 7A The hardware structure diagram shown shows that the digital module is the LNA detection module. Each detection module is for different LNAs that are turned on. For example, the first detection module detects the rising and falling edges of LNAs other than LNA0 when LNA0_en=1, and outputs them to the logic OR module through the logic AND. As long as any detection module outputs a signal of 1, the hw_upd output by the logic OR module is a valid pulse.
[0119] The hw_upd output from the OR module is input into two AND modules, which perform AND operations with scc_enable and pcc_enable respectively, and output to the corresponding SCC AGC update module and PCC AGC update module.
[0120] like Figure 7B The timing diagram shows that at the rising edge of the first pulse of hw_upd, a logical AND operation is performed with the software-configured pcc_enable and scc_enable, respectively. The AGC control word is updated in configuration when hw_upd takes effect, i.e., from 1cc configuration to 2cc configuration. At the falling edge of the second pulse of hw_upd, a logical AND operation is performed with the software-configured pcc_enable and scc_enable, respectively. The AGC control word is updated in configuration when hw_upd takes effect, i.e., from 2cc configuration to 1cc configuration. Correspondingly, the carrier aggregation operating mode switches from 1cc mode to 2cc mode when the SCC enable switch switches from 0 to 1, and from 2cc mode to 1cc mode when the SCC enable switch switches from 1 to 0. This achieves synchronous switching between the AGC control word and the carrier aggregation operating mode, ensuring that the PCC and SCC configurations and enable are synchronously activated.
[0121] Figure 7C The flowchart is shown in the figure, and includes the following steps: 1. Before opening SCC, configure the 2cc AGC table in the software; 2. Before enabling SCC, the software configures the pcc_enable and scc_enable registers, both set to 1; 3. After SCC is enabled, the hardware automatically generates the hw_upd signal; 4. The hardware automatically updates the AGC table for 2cc; 5. Before SCC is shut down, configure the 1cc AGC table in the software; 6. After SCC is turned off, the hardware automatically generates the hw_upd signal; 7. The hardware automatically updates the AGC table of 1cc; after SCC is turned off, the software configures the pcc_enable and scc_enable registers, both set to 0; 8. Determine whether to restart NCCA mode. If yes, return to step 1 to begin execution; otherwise, end the process.
[0122] In summary, under NCCA mode, the above solution ensures that PCC and SCC configuration and enable are effective simultaneously through hardware detection and generation of the hw_upd signal, thereby improving signal reception quality and RF performance, and enhancing EVM.
[0123] This disclosure proposes an automatic gain control device for performing actions such as Figures 4-6 The automatic gain control method shown.
[0124] Figure 8 This is a schematic flowchart of a communication device according to an embodiment of this disclosure. Figure 8 As shown, it includes: The generation module 810 is configured to generate a hardware update flag in response to the opening of the first low-noise amplifier (LNA) and based on the state of at least one second LNA in the non-continuous carrier aggregation (NCCA) mode. Processing module 820 is used to generate a synchronization update signal based on hardware update flag, primary carrier PCC path enable signal, and secondary carrier SCC path enable signal; The control module 830 is used to synchronously update the automatic gain control (AGC) gain of PCC and SCC according to the synchronization update signal.
[0125] In some embodiments, the generation module is configured to generate a hardware update flag in response to an open or closed signal of a third LNA in at least one second LNA, wherein there are exactly two LNAs that detect an open signal.
[0126] In some embodiments, the processing module is configured to: generate a synchronization update signal for the PCC in response to both the hardware update flag and the PCC path enable signal being valid; and generate a synchronization update signal for the SCC in response to both the hardware update flag and the SCC path enable signal being valid.
[0127] In some embodiments, the control module is configured to: apply the first AGC gain value corresponding to the PCC to the PCC receiving path when the PCC synchronization update signal is active; and apply the second AGC gain value corresponding to the SCC to the SCC receiving path when the SCC synchronization update signal is active, wherein the effective time of the PCC synchronization update signal is the same as the effective time of the SCC synchronization update signal.
[0128] In some embodiments, the control module is configured to: determine an AGC gain table; determine a first AGC gain value in the AGC gain table based on the effective time of the PCC synchronization update signal; and determine a second AGC gain value in the AGC gain table based on the effective time of the SCC synchronization update signal.
[0129] Figure 9 This is a schematic diagram of the structure of an electronic device 900 for implementing the above-described automatic gain control method, according to an exemplary embodiment.
[0130] Reference Figure 9 The electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power supply component 906, an input / output (I / O) interface 908, a sensor component 910, and a communication component 912.
[0131] Processing component 902 typically controls the overall operation of electronic device 900, such as operations associated with display, telephone calls, data communication, battery management, and recording. Processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include an equalization module to facilitate interaction between power supply component 906 and processing component 902.
[0132] Memory 904 is configured to store various types of data to support the operation of electronic device 900. Examples of this data include instructions for any application or method operating on electronic device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0133] Power supply component 906 provides power to various components of electronic device 900. Power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 900.
[0134] I / O interface 908 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.
[0135] Sensor assembly 910 includes one or more sensors for providing state assessment of various aspects of electronic device 900. For example, sensor assembly 910 can detect the on / off state of electronic device 900, the relative positioning of components such as the display and keypad of electronic device 900, changes in position of electronic device 900 or a component of electronic device 900, the presence or absence of user contact with electronic device 900, orientation or acceleration / deceleration of electronic device 900, and temperature changes of electronic device 900. Sensor assembly 910 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 910 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications.
[0136] In some embodiments, the sensor assembly 910 may further include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.
[0137] Communication component 912 is configured to facilitate wired or wireless communication between electronic device 900 and other devices. Electronic device 900 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 912 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 912 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
[0138] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.
[0139] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, which can be executed by a processor 920 of an electronic device 900 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.
[0140] This disclosure also provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the steps of the automatic gain control method provided in this disclosure.
[0141] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the automatic gain control method described in the above embodiments of this disclosure.
[0142] Embodiments of this disclosure also provide a chip that includes the communication device described in the above embodiments of this disclosure.
[0143] Figure 10 This is a schematic diagram illustrating the structure of a chip 1000 for implementing the above-described automatic gain control method according to an exemplary embodiment. (Refer to...) Figure 10The chip 1000 includes at least one communication interface 1001 and a processor 1002. The communication interface 1001 is used to receive signals input to the chip 1000 or signals output from the chip 1000. The processor 1002 communicates with the communication interface 1001 and implements the automatic gain control method described in the above embodiments of this disclosure through logic circuits or executing code instructions.
[0144] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.
[0145] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in at least one embodiment or example.
[0146] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.
[0147] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having at least one wiring (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). In addition, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning paper or other media, followed by editing, interpreting or otherwise processing as necessary, and then stored in computer memory.
[0148] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0149] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
[0150] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.
[0151] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. An automatic gain control device, characterized in that, include: Hardware update flag generation module, logic synthesis module, gain control module; The logic synthesis module is connected to the hardware update flag generation module and the gain control module, respectively. The hardware update flag generation module includes at least one low-noise amplifier (LNA) detection unit and a logic OR unit. The LNA detection unit is used to detect the state of at least one LNA. The logic OR unit is used to generate a hardware update flag in response to the turn-on signal of the first LNA and the state switching of the third LNA in at least one second LNA in the non-continuous carrier aggregation (NCCA) mode. The logic synthesis module is used to perform a logical AND operation on the hardware update flag with the main carrier PCC path enable signal and the auxiliary carrier SCC path enable signal respectively to generate a synchronous update signal. The gain control module is used to synchronously update the automatic gain control (AGC) gain of the PCC and the SCC according to the synchronization update signal.
2. The apparatus according to claim 1, characterized in that, The device also includes a path enable interface module. The path enabling interface module is connected to the logic synthesis module; The path enable interface module is used to receive the PCC path enable signal and the SCC path enable signal.
3. The apparatus according to claim 1, characterized in that, The LNA detection unit is used to: in the NCCA mode, in response to the opening signal of the first LNA, detect the status of at least one second LNA; In response to the turn-on signal of the first LNA and the turn-on or turn-off signal of the third LNA, a detection signal is output, and there are exactly two LNAs that detect the turn-on signal; The logic OR unit is used to generate the hardware update flag in response to the detection signal output by any one of the at least one LNA detection units.
4. The apparatus according to claim 3, characterized in that, The logic synthesis module is used for: In response to the hardware update flag and the PCC path enable signal both being valid, a synchronization update signal for the PCC is generated; In response to the hardware update flag and the SCC path enable signal both being valid, a synchronization update signal for the SCC is generated.
5. The apparatus according to any one of claims 1 to 4, characterized in that, The gain control module is used for: When the synchronization update signal is active, the first AGC gain value corresponding to the PCC is synchronously applied to the PCC receiving path, and the second AGC gain value corresponding to the SCC is synchronously applied to the SCC receiving path.
6. The apparatus according to claim 5, characterized in that, The gain control module is used for: The first AGC gain value is read from the storage location corresponding to the PCC and applied to the interface that controls the PCC receiving path; The second AGC gain value is read from the storage location corresponding to the SCC and applied to the interface that controls the SCC receiving path.
7. An automatic gain control method, characterized in that, The method includes: In the discontinuous carrier aggregation (NCCA) mode, in response to the first low-noise amplifier (LNA) being turned on, a hardware update flag is generated based on the state of at least one second LNA. Based on the hardware update flag, the primary carrier PCC path enable signal, and the secondary carrier SCC path enable signal, a synchronization update signal is generated; The automatic gain control (AGC) gain of the PCC and the SCC is updated synchronously according to the synchronization update signal.
8. The method according to claim 7, characterized in that, The response to the first low-noise amplifier (LNA) being turned on, based on the state of at least one second LNA, generates a hardware update flag, including: In response to an open or closed signal of a third LNA in at least one second LNA, the hardware update flag is generated, and there are exactly two LNAs that detect the open signal.
9. The method according to claim 7 or 8, characterized in that, The generation of a synchronization update signal based on the hardware update flag, the primary carrier PCC path enable signal, and the secondary carrier SCC path enable signal includes: In response to the hardware update flag and the PCC path enable signal both being valid, a synchronization update signal for the PCC is generated; In response to the hardware update flag and the SCC path enable signal both being valid, a synchronization update signal for the SCC is generated.
10. The method according to claim 9, characterized in that, The step of synchronously updating the automatic gain control (AGC) gain of the PCC and the SCC according to the synchronization update signal includes: When the synchronization update signal of the PCC is active, the first AGC gain value corresponding to the PCC is applied to the PCC receiving path; When the synchronization update signal of the SCC is active, the second AGC gain value corresponding to the SCC is applied to the SCC receiving path, and the activation time of the synchronization update signal of the PCC is the same as the activation time of the synchronization update signal of the SCC.
11. The method according to claim 10, characterized in that, The method further includes: Determine the AGC gain table; Based on the effective time of the PCC synchronization update signal, the first AGC gain value is determined in the AGC gain table, and... Based on the effective time of the SCC synchronization update signal, the second AGC gain value is determined in the AGC gain table.
12. An electronic device, characterized in that, include: A processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method of any one of claims 7 to 11, or includes the means of any one of claims 1 to 6.
13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 7 to 11.
14. A computer program product comprising a computer program, wherein, When the computer program is executed by a processor, it implements the method of any one of claims 7 to 11.
15. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 7 to 11 through logic circuits or executing code instructions.