Circuits to reduce clock stretch glitches in I2C buffers and I2C buffers

Abstract

This invention discloses a circuit and an I2C buffer for reducing clock stretching glitches in an I2C buffer, belonging to the field of integrated circuit design, and particularly relating to I2C bus communication networks. To address the voltage glitches generated during comparator turn-off and turn-on in clock stretching mode, this invention introduces an auxiliary clamping loop into the traditional comparator structure. This loop presets the comparator's output voltage near the MOSFET threshold voltage when the comparator is off, significantly reducing the voltage swing during state transitions, thereby greatly shortening the response time, effectively suppressing voltage glitches on the SCL line, and avoiding communication errors. This invention does not rely on external filtering or bandwidth enhancement, has good load adaptability and low additional power consumption, and is suitable for various I2C bus expansion and buffering applications.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, specifically to the design of buffer circuits in I2C communication networks, and particularly to a circuit and an I2C buffer for reducing clock extension glitches in I2C buffers. Background Technology

[0002] The I2C (Inter-Integrated Circuit) bus, as a simple and efficient serial communication protocol, is widely used for short-distance communication between various integrated circuits such as microcontrollers, sensors, and memory. It employs an open-drain or open-collector output structure, coupled with pull-up resistors, to implement wired-AND logic, allowing multiple master and slave devices on the bus to communicate bidirectionally.

[0003] However, as system complexity increases, the number of devices connected to the I2C bus leads to a sharp increase in the equivalent load capacitance. According to the RC delay model, excessive load capacitance will delay the rising edge of the bus signal, resulting in decreased signal integrity, insufficient setup / hold time, and communication failure if it exceeds the I2C protocol specification.

[0004] In practical applications, I2C buffers are typically added to the I2C network. Their core function is to divide the heavily loaded bus into two segments with smaller capacitances, achieving load isolation and ensuring that the signal rise time on each segment meets the protocol requirements. Figure 1 This is a typical interface diagram of an I2C buffer. The I2C buffer contains symmetrical input / output channels, namely four interfaces: SDA_IN (data input) / SDA_OUT (data output) and SCL_IN (clock input) / SCL_OUT (clock output). Internally, it uses symmetrical comparator circuits to achieve bidirectional communication.

[0005] The "clock stretching" mechanism in I2C communication is another key feature that allows the slave device to pause the master's clock by actively pulling the SCL line low when it is not yet ready to receive more data, thereby coordinating communication between devices with different speeds.

[0006] However, when the slave device performs clock extension and continuously pulls SCL_OUT low, the internal buffer corresponding to the host-side direction comparator (e.g., the comparator responsible for the SCL_OUT to SCL_IN path) experiences an input offset voltage (V0). offsetThe SCL_IN node is in a shutdown state due to its design, and its output driver transistor is disconnected. If the host releases SCL_IN at this time, the pull-up resistor on the host side cannot quickly discharge the current, and can only charge the load capacitor of the SCL_IN node, causing the SCL_IN voltage to rise. When this voltage exceeds the turn-on threshold of the shutdown comparator, the comparator will be quickly activated, and its output stage will turn on, thereby quickly pulling SCL_IN low. This "rise and fall" process forms a significant glitch on SCL_IN. This glitch is easily misinterpreted by the host controller as a valid clock edge, leading to incorrect data sampling or incorrect start / stop conditions, causing chaos in the entire communication sequence.

[0007] Currently, there are two main solutions to this burr problem:

[0008] Hardware filtering: Integrating digital filters (such as 50ns glitches suppression circuits) within the host or slave device. However, this approach has two drawbacks: First, not all I2C devices have this function built-in, limiting system design; second, the width of the glitches is usually determined by the load capacitance and pull-up resistors, and under heavy load conditions, the glitches can easily exceed 50ns or even hundreds of nanoseconds, far exceeding the filter's suppression capability, leading to filter failure.

[0009] Improving bandwidth: Optimizing the design of the comparator inside the buffer can increase its response speed, thereby discharging current faster to suppress glitches. However, there are drawbacks in engineering practice: the bandwidth of the comparator is usually inversely proportional to the load capacitance. In applications with large load capacitance (which is precisely where I2C buffers are used), improving bandwidth becomes extremely difficult, costly, and even impossible. This inherent contradiction severely limits the effective application range of this solution.

[0010] In summary, neither of the existing technical approaches can reliably solve the clock sputtering problem in all application scenarios. Therefore, there is an urgent need in this field for a circuit structure that is independent of filtering and not constrained by load capacitance to eliminate clock sputtering generated by the I2C buffer in clock sputtering mode and ensure communication reliability. Summary of the Invention

[0011] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows:

[0012] A circuit for reducing clock stretch glitches in an I2C buffer, wherein the I2C buffer includes a comparator circuit for bidirectional signal transmission, and the circuit structure for reducing clock stretch glitches in the I2C buffer includes:

[0013] An auxiliary clamping loop, as part of the comparator circuit, is connected to the output node of the comparator circuit;

[0014] When the comparator circuit is in the off state, the auxiliary clamping loop operates to clamp the output voltage of the output node of the comparator circuit at a preset voltage.

[0015] When the comparator circuit is in the ON state, the auxiliary clamping loop is closed.

[0016] In one embodiment, the auxiliary clamping loop includes MOSFET M7 and MOSFET M8; the gate of MOSFET M7 is connected to the output node of the comparator, the drain of MOSFET M7 is connected to the gate of MOSFET M8, and the source of MOSFET M7 is grounded; the gate of MOSFET M8 is also connected to the output terminal of current source CS4, the source of MOSFET M8 is connected to the second node of the first current mirror in the comparator circuit, and the drain of MOSFET M8 is connected to the output terminal of current source CS3.

[0017] In one embodiment, the value of the preset voltage deviates from the threshold voltage of the pull-down MOS transistor driven by the output node of the comparator circuit, which is in the I2C buffer and outside the comparator circuit, by no more than 10% of the threshold voltage.

[0018] In one embodiment, the output terminal of the current source CS3 is connected to the drain of the MOS transistor M8, and the other terminal is connected to VDD;

[0019] The output terminal of the current source CS4 is connected to the gate of the MOS transistor M8, and the other end is connected to VDD.

[0020] In one embodiment, the differential input pair, consisting of MOSFET M1 and MOSFET M2, is used to receive the input voltage.

[0021] The first current mirror is composed of MOSFET M3 and MOSFET M4, wherein the drain of MOSFET M3 leads to a first node and the drain of MOSFET M4 leads to a second node. The first node and the second node are respectively connected to the two drains of the differential input pair.

[0022] The second current mirror, composed of MOSFETs M5 and M6, serves as the active load of the output stage of the comparator circuit. The source of MOSFET M5 is connected to the first node, and the source of MOSFET M6 is connected to the second node. The output node of the second current mirror is the drain of MOSFET M6, and also serves as the output node of the comparator circuit.

[0023] In one type of embodiment, the comparator circuit includes differential input pairs;

[0024] The aspect ratio of the MOS transistor M1 is greater than that of the MOS transistor M2, so that when the comparator circuit is turned off, the differential input pair generates a non-zero differential current, which is used to start the auxiliary clamping loop.

[0025] In one embodiment, the width-to-length ratio of MOS transistor M3 and MOS transistor M4 is equal; the width-to-length ratio of MOS transistor M5 and MOS transistor M6 is equal.

[0026] In one embodiment, the comparator circuit further includes current source CS1, current source CS2, and current source CS5;

[0027] The current source CS1 is connected between the source of the differential input pair and the power supply voltage VDD.

[0028] The current source CS2 is connected between the drain of the MOS transistor M5 of the second current mirror and VDD.

[0029] The current source CS5 is connected between the drain of the MOS transistor M6 of the second current mirror and VDD, and the drain of the MOS transistor M6 is the output node of the comparator circuit.

[0030] In one embodiment, the MOSFET M7 acts as a loop enable switch, controlled by the output voltage: the auxiliary clamping loop is activated only when the comparator circuit outputs a low level, and automatically shuts down when the comparator circuit outputs a high level.

[0031] The MOSFET M8 serves as a loop sensing and regulation unit, used to sense the current change of the second node and convert the current change into control of the drain current of the MOSFET M8.

[0032] An I2C buffer comprising circuitry for reducing I2C buffer clock stretch glitches as described in any of the preceding claims.

[0033] The technical solution of this invention has one or more of the following beneficial technical effects:

[0034] (1) It can significantly reduce the glitches on the SCL line that are close to the power supply voltage, for example, to within 100mV, thereby reducing the glitches caused by clock delay in principle and eliminating the communication errors caused by them.

[0035] (2) It does not depend on bandwidth improvement, so it is not limited by the size of the load capacitance and has a wide range of applications.

[0036] (3) Adding an auxiliary loop to the existing comparator structure only increases power consumption by almost nothing.

[0037] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0038] Figure 1 This is a typical interface diagram of an I2C buffer;

[0039] Figure 2 This is a schematic diagram of the internal SCL path structure of a typical I2C buffer;

[0040] Figure 3 This is a waveform diagram showing voltage spikes generated during clock extension;

[0041] Figure 4 This is a comparator circuit structure of a specific embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order. It should be clarified that "connection" in this specification refers to electrical connection.

[0044] Terminology Explanation:

[0045] The term "comparator" refers to a circuit used to determine the magnitude of two input voltages and output a corresponding level. In this invention, it is used to control a bidirectional signal path.

[0046] The term "input offset voltage" refers to the input offset voltage (V). offset This refers to the DC voltage difference required between the two input terminals of a comparator or operational amplifier to bring its output to a specified level. In this invention, it is primarily used for direction recognition. When "V+ = V- + V..." offset The flip-flop ensures that the comparators on both sides will not be turned on at the same time, thus preventing a fatal DC path (i.e., "I / O potential is locked") from forming between SCL_IN and SCL_OUT.

[0047] For example, when SCL_IN > SCL_OUT + V offsetIt is assumed that the signal is transmitted from the master to the slave. The comparator on the master side (e.g., comparator 1) is turned on, and the comparator on the slave side is turned off; when SCL_OUT > SCL_IN + V offset It is assumed that the signal is transmitted from the slave device to the master device, the comparator on the slave side is turned on, and the comparator on the master side is turned off.

[0048] The term "clamping" refers to a technique used to limit the voltage of a node in a circuit within a preset range. Specifically, when the comparator is in the off state, an auxiliary clamping loop (composed of MOSFETs M7 and M8) is used to pre-set (i.e., "clamp") its output voltage to a level close to the threshold voltage V of the pull-down MOSFET. TH It is near the preset voltage V_pre.

[0049] The term "width-to-length ratio" (W / L) refers to the ratio of the channel width to the length of a MOSFET, a key parameter determining its on-current and transconductance. For a current mirror to accurately reflect the current, the two paired MOSFETs must have identical W / L ratios. Any mismatch will result in mirroring errors, affecting the comparator's accuracy and function.

[0050] The term "transconductance" refers to the ratio of the change in drain current to the change in gate-source voltage that causes this change. The larger the value, the higher the efficiency of controlling the current with voltage, and the stronger the amplification capability of the transistor.

[0051] For example, in this invention, the transconductance of MOSFET M8 directly determines the "gain" or "sensitivity" of the entire auxiliary clamping loop. This means that even a small change in the gate voltage of MOSFET M8 can generate a large change in drain current. This large change in drain current will rapidly charge the gate capacitance of MOSFET M7, thereby quickly and powerfully controlling the conduction level of MOSFET M7, ultimately controlling the voltage V at the output node. out The voltage is clamped at the preset voltage V_pre. The deviation between the value of the preset voltage V_pre and the threshold voltage of the pull-down MOSFET shall not exceed 10% of the threshold voltage.

[0052] Generally, transconductance is directly proportional to the width-to-length ratio; the wider the channel (the larger W), the greater the transconductance of the tube.

[0053] Figure 2 This is a schematic diagram of the internal SCL path structure of an existing I2C buffer.

[0054] like Figure 2As shown, the I2C buffer uses a symmetrical dual comparator structure to achieve bidirectional signal transmission. Comparator 1 and Comparator 2 are two comparators with identical circuit structures, and pull-down transistors 1 and 2 are two identical pull-down transistors, collectively referred to as pull-down MOS transistors. The I2C buffer operates by utilizing the input offset voltage (V) of the comparators. offset Directional control is achieved when the voltage on one side is approximately V higher than that on the other side. offset When the signal is transmitted in the opposite direction, the comparator in that direction is turned on, activating the pull-down transistor and completing the signal transmission; the comparator in the opposite direction is turned off, blocking the signal path. For example, when SCL_IN transmits a low level to SCL_OUT, the low level of SCL_OUT is clamped at a voltage V higher than SCL_IN through the loop formed by comparator 2 and pull-down transistor 2. offset In terms of numerical value, comparator 2 is in the ON state at this time. At this time, the output V of comparator 1 is OFF. A The voltage is essentially 0V, indicating a shutdown state. This shutdown state blocks the transmission path from SCL_OUT to SCL_IN, thereby preventing SCL_IN and SCL_OUT from forming a loop that could lock the IO potential.

[0055] When clock stretching occurs (slave pulls SCL_OUT low) and master releases SCL_IN, the master-side comparator (comparator 1) is in the off state, and its output is low (V). A When the voltage is essentially 0%, the corresponding pull-down transistor (pull-down transistor 1) is completely off. At this time, there is no discharge path for the current on the host-side pull-up resistor, and the SCL_IN node can only charge the load capacitor through the pull-up resistor, thus increasing the voltage of SCL_IN. When the voltage rises to the comparator's turn-on threshold, the host-side comparator (comparator 1) quickly turns on (turning V...). A (Starting from 0, the voltage is increased) and the voltage of SCL_IN is pulled low. This process generates a positive voltage spike on SCL_IN, such as... Figure 3 As shown. Figure 3 This is a waveform diagram showing voltage spikes generated during clock extension.

[0056] The core of increasing loop bandwidth is to achieve faster system response by improving response speed. This solution shortens the response time by reducing the voltage change range during state transitions. Specifically, in the off state, the comparator output V... A The voltage is V1. After the host releases the SCL signal line, V AThe stable voltage value is V2, where I is the comparator's output current, C is its output equivalent capacitance, and Δt is the settling time. According to circuit characteristics, assuming I and C remain constant, the comparator's settling time Δt is positively correlated with the voltage difference (V2-V1). This relationship means that reducing the difference between V2 and V1 directly shortens Δt, suppressing glitches. Therefore, the core technical solution of this invention is: when the comparator is in the off state, its output voltage V... A (i.e., the voltage V at the output node) out Clamped at threshold voltage V TH Nearby, this design improves V in the off state. A The voltage (i.e., increasing V1) is used to reduce the difference between the "stable voltage V2 after releasing SCL" and the "turn-off voltage V1", ultimately achieving the goal of shortening the settling time and suppressing glitches.

[0057] This invention improves the comparator circuit inside the I2C buffer to reduce the voltage change range during state switching. Figure 4 The core circuit structure of a specific embodiment of the present invention is illustrated. In this embodiment, comparator MOSFETs M1 to M8 and current sources CS1 to CS5 are used. Traditional comparators only have MOSFETs M1 to M6; this invention improves the comparator by adding an auxiliary clamping loop composed of MOSFETs M7 and M8. This loop automatically closes and becomes inactive when the comparator is in the on state, and when the comparator is in the off state, it adjusts the voltage V at the output node. out Clamped at the threshold voltage V of MOS conduction TH A preset voltage V_pre is placed nearby, which significantly reduces the voltage change range during state switching, shortens the response time, and suppresses glitches.

[0058] In this invention, MOS transistors M1 and M2 are both P-channel metal-oxide semiconductors (PMOS), and MOS transistors M3 to M8 are all N-channel metal-oxide semiconductors (NMOS).

[0059] In this embodiment, the comparator section comprises a differential input pair, a first current mirror, a second current mirror, an auxiliary clamping loop (implemented by MOSFETs M1 to M8), and multiple bias current sources (CS1, CS2, CS3, CS4, CS5), and its specific connection method is as follows:

[0060] MOSFETs M1 and M2 form a differential input pair. The gate of MOSFET M1 is the non-inverting input terminal, connected to voltage V+; the gate of MOSFET M2 is the inverting input terminal, connected to voltage V-. The sources of MOSFETs M1 and M2 are connected together and connected to the tail current source CS1. The other end of current source CS1 is connected to VDD, which is the device operating voltage (Voltage Drain-to-Drain, VDD).

[0061] MOSFETs M3 and M4 form the first current mirror. The gate of MOSFET M3 is connected to the gate of MOSFET M4 and to the drain of MOSFET M5; the drain of MOSFET M3 is connected to the drain of MOSFET M1 (defined as the first node); the drain of MOSFET M4 is connected to the drain of MOSFET M2 (defined as the second node); the sources of both MOSFETs M3 and M4 are grounded.

[0062] MOSFETs M5 and M6 form a second current mirror, serving as the active load of the output stage. The gates of MOSFETs M5 and M6 are interconnected; the source of MOSFET M5 is connected to the first node; the source of MOSFET M6 is connected to the second node (the input node of the second current mirror). The drain of MOSFET M5 is connected to one end of current source CS2 (the other end of current source CS2 is connected to VDD), and the drain of MOSFET M6 is connected to one end of current source CS5 (the other end of current source CS5 is connected to VDD), simultaneously serving as the output node of the comparator.

[0063] In the auxiliary clamping loop, the source of MOSFET M7 is grounded, and its drain is connected to the gate of MOSFET M8. The gate of MOSFET M8 is also connected to VDD via a bias current source CS4. The source of MOSFET M8 is connected to the second node, and its drain is connected to a current source CS3, the other end of which is connected to VDD. The gate of MOSFET M7 is connected to the output node.

[0064] Furthermore, to ensure circuit functionality, the width-to-length ratio (W / L) of the critical MOSFETs needs to be designed: MOSFETs M1 and M2 form a differential pair, with the width-to-length ratio of MOSFET M1 set to be slightly larger than that of MOSFET M2, so as to generate a non-zero differential current (I) in the off state. M1 -I M2 This current is crucial for starting the auxiliary clamping loop; MOSFETs M3 and M4 have equal width-to-length ratios, forming a precise current mirror for accurately mirroring the current; MOSFETs M5 and M6 have equal width-to-length ratios, forming another set of precise current mirrors; MOSFETs M7 and M8 form the auxiliary clamping loop.

[0065] The function of MOSFET M7 is as a "loop enable switch controlled by the output voltage," ensuring that the auxiliary loop is activated only when the comparator output needs to be clamped (low level state), and automatically shuts down when the comparator output is normally high, thus avoiding interference with normal operation. The core function of MOSFET M8 is to accurately sense the current change flowing through the second node (i.e., the non-zero differential current I generated by the differential pair). M1 -I M2 This process converts the current change into effective control of its drain current. It is the core sensing and regulation unit in the loop. The aspect ratio of MOSFET M8 needs to be designed in conjunction with the current value of current source CS4, and is determined through precise calculation and simulation based on the required preset voltage V_pre. This allows for precise setting of its transconductance, thereby controlling the loop's gain and response speed, and ultimately controlling the voltage V_pre at the output node. out The voltage is clamped at a preset voltage V_pre, which is set close to the threshold voltage V of the pull-down MOSFET. TH nearby.

[0066] The specific implementation process of this invention is as follows:

[0067] When the comparator is in the ON state, V+ = V- + V offset The condition is that although the width-to-length ratio of MOSFET M1 is greater than that of MOSFET M2, V+ = V- + V. offset The voltage difference offset the effect of the width-to-length ratio difference; simultaneously, the width-to-length ratios of MOSFETs M3 and M4, and M5 and M6 are equal, respectively, and the first and second current mirrors operate normally, ultimately maintaining I. M1 Basically equal to I M2 I M3 =I M4 I M5 =I M6 Based on the node current relationships, we can obtain:

[0068] For the first node: I M3 =I M1 +I M5 For the second node: I M4 =I M2 +I M6 +I M8 .

[0069] By combining the above equations, we can derive I. M8 =I M1 -I M2 I M8Essentially equal to 0. Since the gate of MOSFET M8 is biased by the current source CS4, the gate voltage of MOSFET M8 is pulled to a high potential (close to VDD), causing MOSFET M8 to operate in the linear region or deep transistor region, where its equivalent resistance is extremely small. Therefore, the current I... M8 The voltage drop across MOSFET M8 is extremely small, resulting in a very low source (second node) potential that is insufficient to affect the output node voltage V. out At the same time, the voltage V of the high-level output node... out This causes the gate voltage of MOSFET M7 to be much higher than its threshold voltage, and MOSFET M7 is strongly turned on. However, its drain (i.e., the gate of MOSFET M8) has been clamped to a high level by the current source CS4. Therefore, the entire auxiliary loop does not play a dominant role in this state and does not affect the normal conduction function of the comparator.

[0070] When the comparator is in the off state, since V+ < V-, but because the width-to-length ratio of MOSFET M1 is designed to be greater than that of MOSFET M2, the overall effect is that I... M1 >I M2 , while I M3 =I M4 I M5 =I M6 Remain unchanged. Based on the node current relationships:

[0071] For the first node: I M3 =I M1 +I M5 For the second node: I M4 =I M2 +I M6 +I M8 .

[0072] By combining the equations, we can obtain: I M1 +I M5 =I M2 +I M6 +I M8 Because I M5 =I M6 , that is I M8 =I M1 –I M2 Therefore: I M8 =I M1 –I M2 >0. At this time, the auxiliary clamping loop is activated. Current source CS4 provides a fixed bias voltage to the gate of MOSFET M8, and MOSFET M8 starts to work as a common-source amplifier, with its drain current I... M8 equals I M1 -I M2 . TheI M8Current flows from the drain to the source (second node) of MOSFET M8, affecting the potential of the second node, and subsequently affecting the voltage V of the output node through the second current mirror. out The voltage V at the output node out At this time, it is at a low level, which will output the voltage V of the node. out The change in voltage is fed back to the gate of MOSFET M7, causing MOSFET M7 to turn off. The turn-off of MOSFET M7 means that the gate voltage of MOSFET M8 is completely determined by the current source CS4, providing it with a stable bias. This ensures that MOSFET M8 can operate stably in the amplification region when it is off, establishing an auxiliary clamping loop.

[0073] The entire loop forms a negative feedback loop: "V" out Rise → Second node potential decreases → Gate-source voltage of MOSFET M8 increases → Current I M8 Increase → Inhibit V out The increase in voltage (the symbol "→" connects two changes in physical quantities or circuit states, indicating a causal relationship, i.e., the previous change causes the subsequent change), ultimately increases the voltage V at the output node. out It stabilizes near the preset voltage V_pre. Specifically: if the voltage V_pre at the output node is affected by external interference... out There is an upward trend, and this change affects subsequent circuits, ultimately manifesting as a downward trend in the potential of the second node. The source voltage of MOSFET M8 decreases, while its gate voltage is fixed by the current source CS4, leading to an increase in the gate-source voltage of MOSFET M8, and consequently, an increase in the drain current I of MOSFET M8. M8 Increase (more current flows into the source). I M8 Increasing the voltage at the second node will resist and offset the decrease in the second node potential. The stabilization of the second node potential, through the action of the second current mirror, ultimately suppresses the voltage V at the output node. out The rising trend clamps it to a preset voltage V_pre. During this process, the voltage V_pre of the low-level output node... out By turning off MOSFET M7, the gate voltage of MOSFET M8 is ensured to be entirely determined by the bias current source CS4 and will not be pulled low, thus providing a stable bias condition for the normal operation of the aforementioned negative feedback loop. The value of the preset voltage V_pre is determined by the current value of current source CS4, the transconductance of MOSFET M8, and the output stage impedance.

[0074] Furthermore, by adjusting the current source CS4, the transconductance of MOSFET M8 can be changed, thereby affecting the gain and response speed of the entire loop, and ultimately precisely setting the voltage V of the output node in the off state. out The clamped preset voltage V_pre is brought close to the threshold voltage V of the pull-down MOSFET. TH This minimizes the voltage change during state transitions.

[0075] When the host releases the SCL signal, requesting the comparator to switch from the off state back to the on state, the voltage V at its output node... out The initial value has been clamped at the threshold voltage V by the auxiliary clamping loop. TH The voltage is near the preset voltage V_pre, rather than the traditional 0V. Therefore, the voltage change ΔV required to reach steady state is significantly reduced, and according to the circuit response characteristics, the settling time Δt is also significantly shortened. This allows the comparator to respond quickly and pull down the SCL_IN voltage, effectively suppressing voltage overshoot and oscillation, thereby keeping the glitches at an extremely low level. Essentially, the preset voltage significantly reduces the voltage change (ΔV) required for the output node state to switch, and according to the circuit transient response characteristics, the settling time (Δt) is significantly shortened, thus fundamentally suppressing voltage overshoot (i.e., glitches).

[0076] In one instance, after applying this solution, the glitch amplitude was effectively suppressed and ultimately stabilized below 100mV. Considering the design specifications of the communication system and the signal interference tolerance threshold, a glitch amplitude below 100mV is far below the critical value that would disrupt the integrity of the communication signal. It is insufficient to interfere with signal transmission and data parsing processes in the communication link, thus ensuring that the system communication remains stable and reliable, without communication anomalies or data errors caused by glitches.

[0077] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail, in order to highlight the spirit of the present invention.

[0078] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A circuit for reducing I2C buffer clock stretch glitches, the I2C buffer including a comparator circuit for bidirectional signal transmission, characterized in that, The circuit structure for reducing I2C buffer clock stretch glitch includes: An auxiliary clamping loop, as part of the comparator circuit, connected to the output node of the comparator circuit; When the comparator circuit is in the off state, the auxiliary clamping loop operates to clamp the output voltage of the output node of the comparator circuit at a preset voltage; When the comparator circuit is in the on state, the auxiliary clamping loop is turned off; Wherein, the auxiliary clamping loop includes MOS transistor M7 and MOS transistor M8; The gate of the MOS transistor M7 is connected to the output node of the comparator circuit, the drain of the MOS transistor M7 is connected to the gate of the MOS transistor M8, and the source of the MOS transistor M7 is grounded; The gate of the MOS transistor M8 is also connected to the output terminal of the current source CS4, the source of the MOS transistor M8 is connected to the second node of the first current mirror in the comparator circuit, and the drain of the MOS transistor M8 is connected to the output terminal of the current source CS3; The comparator circuit includes a differential input pair, a first current mirror, and a second current mirror. The source of the MOS transistor M6 in the second current mirror is connected to the second node, and the drain of the MOS transistor M6 is the output node of the comparator circuit.

2. The circuit for reducing I2C buffer clock stretch glitch according to claim 1, wherein: The value of the preset voltage has a deviation from the threshold voltage of the pull-down MOS transistor in the I2C buffer, which is driven by the output node of the comparator circuit and is outside the comparator circuit, not exceeding 10% of the threshold voltage.

3. The circuit for reducing I2C buffer clock stretch glitch according to claim 1, wherein: The output terminal of the current source CS3 is connected to the drain of the MOS transistor M8, and the other end is connected to VDD; The output terminal of the current source CS4 is connected to the gate of the MOS transistor M8, and the other end is connected to VDD.

4. The circuit for reducing I2C buffer clock stretch glitch according to claim 1, characterized in that, The comparator circuit includes: A differential input pair, composed of MOS transistors M1 and M2, for receiving an input voltage; A first current mirror, composed of MOS transistors M3 and M4, wherein the drain of the MOS transistor M3 leads out a first node, the drain of the MOS transistor M4 leads out a second node, and the first node and the second node are respectively connected to the two drains of the differential input pair; A second current mirror, composed of MOS transistors M5 and M6, as the active load of the output stage of the comparator circuit. The source of the MOS transistor M5 is connected to the first node, the source of the MOS transistor M6 is connected to the second node, the output node of the second current mirror is the drain of the MOS transistor M6, and is used as the output node of the comparator circuit.

5. The circuit for reducing I2C buffer clock stretch glitch according to claim 4, wherein: The width-to-length ratio of the MOS transistor M1 is greater than the width-to-length ratio of the MOS transistor M2, so as to generate a non-zero differential current in the differential input pair when the comparator circuit is off, and this differential current is used to start the auxiliary clamping loop.

6. The circuit for reducing I2C buffer clock stretch glitch according to claim 4, wherein: The width-to-length ratios of the MOS transistor M3 and the MOS transistor M4 are equal; The width-to-length ratios of the MOS transistor M5 and the MOS transistor M6 are equal.

7. The circuit for reducing I2C buffer clock stretch glitch according to claim 6, wherein: The comparator circuit further includes a current source CS1, a current source CS2, and a current source CS5; The current source CS1 is connected between the source of the differential input pair and the power supply voltage VDD; The current source CS2 is connected between the drain of the MOS transistor M5 of the second current mirror and VDD; The current source CS5 is connected between the drain of the MOS transistor M6 of the second current mirror and VDD, and the drain of the MOS transistor M6 is the output node of the comparator circuit.

8. The circuit for reducing I2C buffer clock stretch glitch according to claim 7, wherein: In the auxiliary clamping loop, the MOS transistor M7 serves as a loop enable switch and is controlled by the output voltage: the auxiliary clamping loop is activated only when the comparator circuit outputs a low level and is automatically turned off when the comparator circuit outputs a high level; The MOS transistor M8 serves as a loop induction adjustment unit for sensing the current change of the second node and converting the current change into the control of the drain current of the MOS transistor M8.

9. An I2C buffer, wherein: It includes the circuit for reducing I2C buffer clock stretch glitch according to any one of claims 1 to 8.

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