Phase error calibration circuit and method, processor and electronic equipment

Abstract

The invention relates to a phase error calibration circuit and method, a processor and electronic equipment. The phase error calibration circuit comprises a multi-phase adjustment module, a phase error detection module and a control module, the multi-phase adjustment module is used for adjusting the phase of a target phase clock signal in the received N initial phase clock signals; the phase error detection module is used for detecting a first phase difference between the first phase clock signal and the second phase clock signal and a second phase difference between the second phase clock signal and the third phase clock signal, and quantizing the phase difference between the first phase difference and the second phase difference to obtain a quantization result; and the control module is used for controlling the multi-phase adjustment module to adjust the phase of the target phase clock signal according to the quantization result, so that the first phase difference is consistent with the second phase difference. According to the invention, the calibration precision of the phase error calibration of the multi-phase clock can be improved, and the process required by calibration can be simplified.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a phase error calibration circuit, method, processor, and electronic device. Background Technology

[0002] In high-speed interface systems, increasing data transmission speed has become an inevitable trend, which also places higher demands on the transmission rate of high-speed interfaces. As the interface rate continues to increase, the power consumption of the clock system increases accordingly. In order to achieve low power consumption while maintaining high clock performance, traditional single-phase or dual-phase clock schemes are no longer able to achieve the dual goals of high performance and low power consumption. Therefore, multi-phase clock generators are introduced in the transmitting end (TX) and receiving end (RX) for data transmission and processing.

[0003] High-speed interface systems typically employ phase-locked loops (PLLs) or delay-locked loops (DLLs) to generate multi-phase clocks. However, due to systematic and random mismatches, the phase interval between adjacent phases in a multi-phase clock can easily deviate from the ideal value. This type of phase error introduces timing uncertainties in high-speed applications, compressing the system's timing margin and impacting overall performance and stability. To address the phase mismatch problem caused by multi-phase clocks, a phase calibration mechanism is needed to monitor and adjust the phase deviation between each phase. Precise phase calibration can minimize the impact of phase mismatch on timing, thereby ensuring stable and reliable system operation.

[0004] Related technologies are mostly based on PLLs or DLLs to generate multi-phase clock signals. Before performing phase error calibration, it is usually necessary to first calibrate the duty cycle of the multi-phase clock. Then, an XOR operation is performed on the clock signals of adjacent phases, and the XOR results (such as the XOR results of 0 degrees and 90 degrees phases, and the XOR results of 90 degrees and 180 degrees phases) are filtered by a low-pass filter and sent to a differential comparator for comparison. When there is an error between adjacent phases, the logic 0 or 1 result output by the comparator is passed through a digital state machine to control a phase interpolator to adjust the phase error and achieve matching between multiple phases. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a phase error calibration circuit, method, processor, and electronic device to improve the problems of complex calibration process and large calibration error in current multi-phase clock phase error calibration.

[0006] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a phase error calibration circuit, including: a multi-phase adjustment module, a phase error detection module, and a control module; the multi-phase adjustment module is used to adjust the phase of a target phase clock signal among N received initial phase clock signals, wherein N=2 m , m is an integer greater than or equal to 2; the phase error detection module is used to detect the first phase difference between the first phase clock signal and the second phase clock signal, and the second phase difference between the second phase clock signal and the third phase clock signal, and to quantize the phase difference between the first phase difference and the second phase difference to obtain a quantization result; wherein, the first phase clock signal, the second phase clock signal, and the third phase clock signal are three designated phase signals among the N phase clock signals output by the multi-phase adjustment module, and the phase of the second phase clock signal is located between the phase of the first phase clock signal and the phase of the third phase clock signal, and the second phase clock signal is the signal of the target phase clock signal after passing through the multi-phase adjustment module; the control module is used to control the multi-phase adjustment module to adjust the phase of the target phase clock signal according to the quantization result, so that the first phase difference is consistent with the second phase difference.

[0007] In the above implementation scheme, the phase error calibration circuit with the above structure (including a multi-phase adjustment module, a phase error detection module, and a control module) eliminates the need for duty cycle calibration of the N-phase clock signals before phase error calibration. Calibration can be performed directly by acquiring three designated phase signals (the first, second, and third phase clock signals) from the N phase clock signals output by the multi-phase adjustment module and detecting whether the phase difference between any two adjacent signals is consistent. Only N such calibration steps are required to calibrate the phase error of the N-phase clock signals, ensuring that the phase difference between any two adjacent phase clock signals is consistent. Since the duty cycle calibration step required before multi-phase calibration in traditional methods is eliminated, and only N such calibration steps are needed, the complexity of the current multi-phase clock phase error calibration process is simplified. Simultaneously, it avoids the reduction in system calibration accuracy caused by errors introduced by duty cycle calibration. In one possible implementation of the first aspect embodiment, the phase error detection module is specifically used to convert the first phase difference into a first voltage signal, convert the second phase difference into a second voltage signal, compare and quantize the first voltage signal and the second voltage signal to obtain a quantization result.

[0008] In the above implementation scheme, when quantizing the phase difference between the first phase difference and the second phase difference, the phase difference can be converted into a voltage signal first, and then the first voltage signal and the second voltage signal can be compared and quantized, which helps to improve the quantization efficiency.

[0009] In one possible implementation of the first aspect embodiment, the phase error detection module includes: a first detection unit, a second detection unit, a first low-pass filter, a second low-pass filter, and an error quantization unit; the first detection unit is used to detect a first phase difference between the first phase clock signal and the second phase clock signal; the second detection unit is used to detect a second phase difference between the second phase clock signal and the third phase clock signal; the first low-pass filter is used to convert the first phase difference into a corresponding first voltage signal; the second low-pass filter is used to convert the second phase difference into a corresponding second voltage signal; and the error quantization unit is used to compare and quantize the first voltage signal and the second voltage signal to obtain a quantization result.

[0010] In the above implementation scheme, the phase error detection module with the above structure enables the detection of the first phase difference between the first phase clock signal and the second phase clock signal, and the second phase difference between the second phase clock signal and the third phase clock signal, respectively, through two detection units. These two phase differences are converted into voltage signals after passing through low-pass filters. Then, the two voltage signals are compared and quantized by the error quantization unit, thereby enabling the quantization of phase difference differences quickly and accurately without the need to perform duty cycle calibration on the N-phase clock signal.

[0011] In one possible implementation of the first aspect embodiment, the first detection unit includes: a first flip-flop, a second flip-flop, and a first NAND gate; the data input terminal of the first flip-flop is connected to a power supply, the clock input terminal of the first flip-flop is connected to a first phase clock signal, and the data output terminal of the first flip-flop is connected to a first low-pass filter; the data input terminal of the second flip-flop is connected to a power supply, and the clock input terminal of the second flip-flop is connected to a second phase clock signal; the first input terminal of the first NAND gate is connected to the data output terminal of the first flip-flop, the second input terminal of the first NAND gate is connected to the data output terminal of the second flip-flop, and the output terminal of the first NAND gate is connected to the reset terminal of the first flip-flop and the reset terminal of the second flip-flop, respectively.

[0012] In the above implementation scheme, the first detection unit with the above structure and connection method can quickly detect the first phase difference between the first phase clock signal and the second phase clock signal. Since the flip-flops and NAND gates are mature, reliable and relatively inexpensive devices in the field, it is easy to save costs and improve reliability to meet the needs of a wide range of applications, thus achieving an optimal solution in terms of cost, reliability and development efficiency.

[0013] In one possible implementation of the first aspect embodiment, the second detection unit includes: a third flip-flop, a fourth flip-flop, and a second NAND gate; the data input terminal of the third flip-flop is connected to a power supply, the clock input terminal of the third flip-flop is connected to the second phase clock signal, and the data output terminal of the third flip-flop is connected to the second low-pass filter; the data input terminal of the fourth flip-flop is connected to a power supply, and the clock input terminal of the fourth flip-flop is connected to the third phase clock signal; the first input terminal of the second NAND gate is connected to the data output terminal of the third flip-flop, the second input terminal of the second NAND gate is connected to the data output terminal of the fourth flip-flop, and the output terminal of the second NAND gate is connected to the reset terminal of the third flip-flop and the reset terminal of the fourth flip-flop, respectively.

[0014] In the above implementation scheme, the second detection unit with the above structure and connection method can quickly detect the second phase difference between the second phase clock signal and the third phase clock signal. Since the flip-flops and NAND gates are mature, reliable and relatively inexpensive devices in the field, it is easy to save costs and improve reliability to meet the needs of a wide range of applications, thus achieving an optimal solution in terms of cost, reliability and development efficiency.

[0015] In one possible implementation of the first aspect embodiment, the error quantization unit includes: a phase offset selection circuit, an automatic zeroing comparator, and a latch; when the phase offset selection circuit is in a first state, the first voltage signal is output to a first node, and the second voltage signal is output to a second node; when the phase offset selection circuit is in a second state, the second voltage signal is output to the first node, and the first voltage signal is output to the second node; the first input terminal of the automatic zeroing comparator is connected to the first node through a first capacitor, and the second input terminal of the automatic zeroing comparator is connected to the second node through a second capacitor, wherein, when the phase offset selection circuit is in the first state, the loop between the input terminal and the output terminal of the automatic zeroing comparator is in a conducting state, and when the phase offset selection circuit is in the second state, the loop between the input terminal and the output terminal of the automatic zeroing comparator is in a disconnected state; the data input terminal of the latch is connected to the output terminal of the automatic zeroing comparator, and the output terminal of the latch is connected to the control module.

[0016] In the above implementation scheme, the error quantization unit with the above structure, when the phase offset selection circuit is in the first state, ensures that the loop between the input and output terminals of the automatic zeroing comparator is closed. The input and output terminals of the automatic zeroing comparator are directly connected through the loop, making the voltage at the differential input terminals of the comparator consistent, thereby eliminating the influence of the offset voltage of the automatic zeroing comparator and improving subsequent comparison accuracy. When the phase offset selection circuit is in the second state, the automatic zeroing comparator is in the comparison stage. At this time, by exchanging the input voltages of the first and second nodes, since the voltage across the capacitor cannot change abruptly, the difference between the phase difference and the ideal phase difference can be amplified, which helps improve comparison accuracy. Simultaneously, a latch is used to latch the output result of the automatic zeroing comparator to maintain the stability of the comparison result and avoid fluctuations in the output near the correct value due to factors such as noise, offset, or power supply fluctuations in the comparator itself.

[0017] In one possible implementation of the first aspect embodiment, the phase error detection module is specifically used to select three corresponding designated phase signals from the N phase clock signals output by the multi-phase adjustment module according to the selection signal.

[0018] In the above implementation scheme, the three specified phase signals can be quickly selected from the N phase clock signals output by the multi-phase adjustment module by configuring the selection signal, which is beneficial to improve efficiency and has greater flexibility, allowing the selection of the required three specified phase signals as needed.

[0019] Secondly, embodiments of this application also provide a chip, including a phase-locked loop and a phase error calibration circuit as provided in any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment; the phase-locked loop is connected to the phase error calibration circuit, and the phase-locked loop is used to generate N initial phase clock signals.

[0020] Thirdly, embodiments of this application also provide an electronic device, including the chip provided in the second aspect of the embodiments described above.

[0021] Fourthly, embodiments of this application also provide a phase error calibration method, comprising: acquiring N phase clock signals output by a multi-phase adjustment module, where N=2 mm is an integer greater than or equal to 2; N phase error calibration operations are performed to make the phase difference between any two adjacent phase clock signals among the N phase clock signals consistent; wherein, each phase error calibration operation includes: detecting the first phase difference between the first phase clock signal and the second phase clock signal, and the second phase difference between the second phase clock signal and the third phase clock signal, and quantizing the phase difference between the first phase difference and the second phase difference to obtain a quantization result; wherein, the first phase clock signal, the second phase clock signal, and the third phase clock signal are three designated phase signals among the N phase clock signals, and the phase of the second phase clock signal is located between the phase of the first phase clock signal and the phase of the third phase clock signal; according to the quantization result, the multi-phase adjustment module is controlled to adjust the phase of the second phase clock signal to make the first phase difference consistent with the second phase difference; wherein, at least one of the three designated phase signals selected from the N phase clock signals is different during each phase error calibration operation.

[0022] The technical effects of any of the implementation methods in the second to fourth aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0023] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0025] Figure 1a A schematic diagram of a phase error calibration circuit provided in an embodiment of this application is shown.

[0026] Figure 1b This illustration shows a schematic diagram of another phase error calibration circuit connected to a PLL / DLL according to an embodiment of this application.

[0027] Figure 2 This illustration shows a schematic diagram of the principle of a phase error calibration operation for an 8-phase clock provided in an embodiment of this application.

[0028] Figure 3A schematic diagram of the structure of a phase error detection module provided in an embodiment of this application is shown.

[0029] Figure 4 A schematic diagram of the structure of a first detection unit provided in an embodiment of this application is shown.

[0030] Figure 5 A schematic diagram of another phase error detection module provided in an embodiment of this application is shown.

[0031] Figure 6 A circuit diagram of a quantization error unit provided in an embodiment of this application is shown.

[0032] Figure 7 This illustration shows a schematic diagram of the principle of connecting a first detection unit and a first phase selection circuit, as well as a second detection unit and a second phase selection circuit, according to an embodiment of this application.

[0033] Figure 8 This illustration shows a timing diagram of a 4-phase clock and the phase difference between adjacent clocks provided in an embodiment of this application.

[0034] Figure 9 This illustration shows a timing diagram of an 8-phase clock and the phase difference between adjacent clocks provided in an embodiment of this application.

[0035] Figure 10 for Figure 2 A timing diagram illustrating the phase clock signal, phase difference, and corresponding voltage involved in step 1.

[0036] Figure 11 for Figure 10 The timing diagram of the main signals in the quantization error unit under the given signal is shown.

[0037] Figure 12 for Figure 2 Another timing diagram of the phase clock signal, phase difference, and corresponding voltage involved in step 1.

[0038] Figure 13 for Figure 12 The timing diagram of the main signals in the quantization error unit under the given signal is shown.

[0039] Figure 14 A schematic flowchart of a phase error calibration method provided in an embodiment of this application is shown.

[0040] Figure 15 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0042] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0043] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0044] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0045] Given that current phase error calibration for multi-phase clocks suffers from complex calibration processes and large calibration errors, for example, in conventional solutions, duty cycle calibration is required before phase error calibration. However, during duty cycle calibration, due to the influence of the duty cycle calibration circuit itself and calibration accuracy, the actual output duty cycle often fails to reach the ideal 50%, and there will always be a certain error. This error information will be introduced into the subsequent phase error calibration stage, further causing the result after multi-phase calibration to have an error introduced by duty cycle calibration between it and the ideal value, thereby reducing the calibration accuracy of the system.

[0046] This application provides a phase error calibration circuit, method, processor, and electronic device. This application eliminates the duty cycle calibration step required before multi-phase calibration in traditional methods. Calibration is performed by detecting whether the phase difference between the rising or falling edges of multiple phases is consistent. Only N phase error calibration operations as specified in this application are required, ultimately achieving phase calibration of N phase clock signals to ensure that the phase difference between any two adjacent phase clock signals among the N phase clock signals is consistent. Here, the phase difference in this application refers to the time offset between two periodic signals of the same frequency. For clock signals in digital circuits, the phase difference can be the time difference between any point of two clock signals of the same frequency, typically represented by the time difference between the conventional edges (such as the rising edge) of these two signals.

[0047] In this application, N=2 of the N phase clock signals. m m is an integer greater than or equal to 2. For example, when m=2, N=4; when m=3, N=8; and when m=4, N=16. In the following examples, we will mainly use N=8 as an example.

[0048] The following is combined Figure 1a The phase error calibration circuit provided in this application embodiment will be described. This phase error calibration circuit includes a multi-phase adjustment module, a phase error detection module, and a control module. The multi-phase adjustment module is connected to the phase error detection module, and the phase error detection module is connected to the control module. In some possible implementations, such as... Figure 1b As shown, a clock driver (containing multi-level clock buffers) is also provided between the multi-phase adjustment module and the phase error detection module to enhance the clock driving capability, optimize timing, and maintain signal integrity. Figure 1b Only the case where the control module is a Finite State Machine (FSM) is shown, but it cannot be shown that... Figure 1b The FSM shown is understood as the only way to implement the control module.

[0049] These N initial phase clock signals can be generated by a phase-locked loop (PLL) or a delay-locked loop (DLL). For example, a PLL or DLL outputs 8-phase clock signals: clock0, clock45, clock90, clock135, clock180, clock225, clock270, and clock315. It's understandable that if the PLL or DLL outputs a 4-phase clock signal, it would be clock0, clock90, clock180, and clock270; or if the PLL or DLL outputs a 16-phase clock signal, it would be clock0, clock22.5, clock45, clock67.5, clock90, clock112.5, clock135, clock157.5, clock180, clock202.5, clock225, clock247.5, clock270, clock292.5, clock315, and clock337.5.

[0050] For example, the 8-phase clock signal output by a PLL or DLL corresponds to phases 0, 45, 90, 135, 180, 225, 270, and 315. These 8-phase clock signals first pass through a multi-phase adjustment module, and then are sent to a remote end for use by the transmitter or receiver via a clock driver. Due to the influence of manufacturing processes and physical implementation, the skew between the clock phases is not an ideal 45-degree phase difference. Therefore, phase error calibration is required before normal application. Specifically, the 8-phase clock signals (phase0, 45, 90, 135, 180, 225, 270, and 315) are sent to a phase error detection module. Each time, the phase error detection module detects the first phase difference between the first and second phase clock signals, and the second phase difference between the second and third phase clock signals, and quantizes the phase differences between the first and second phase differences to obtain the quantization result. Subsequently, based on the quantization results, the control module controls the multi-phase adjustment module to adjust the phase of the target phase clock signal (corresponding to the second phase clock signal, where the second phase clock signal is the signal after the target phase clock signal has passed through the multi-phase adjustment module) so that the first phase difference is consistent with the second phase difference. After multiple rounds (or multiple steps) of similar operations, the phase difference between any two adjacent phase clock signals among the eight phase clock signals can be made consistent.

[0051] A multi-phase adjustment module is used to adjust the phase of a target phase clock signal from among N received initial phase clock signals. The target phase clock signal can be any one of the N initial phase clock signals. For example... Figure 1b As shown, the multi-phase adjustment module can include N phase adjustment units, each used to adjust the phase of a single phase clock signal. Each phase adjustment unit can include multiple delay-adjustable inverters (INVs). Alternatively, the phase adjustment units can employ related technologies, such as phase interpolators. The phase error detection module detects the first phase difference between the first and second phase clock signals, and the second phase difference between the second and third phase clock signals, and quantizes the phase differences between the first and second phase differences to obtain the quantization result.

[0052] Among them, the first phase clock signal, the second phase clock signal, and the third phase clock signal are three designated phase signals among the N phase clock signals output by the multi-phase adjustment module, and the phase of the second phase clock signal is located between the phase of the first phase clock signal and the phase of the third phase clock signal. The second phase clock signal is the signal after the target phase clock signal has passed through the multi-phase adjustment module.

[0053] The phase error detection module requires a multi-step operation similar to the one described above. In each step, at least one of the three selected specified phase signals is different, and the target control signal adjusted in each step is different. For example, ... Figure 2As shown, the first step selects phase0, phase90, and phase180; the second step selects phase180, phase270, and phase0; the third step selects phase90, phase180, and phase270; and the fourth step selects phase270, phase0, and phase90. After these four steps, the phase difference between these four clock signals can be guaranteed to be 90 degrees. However, it cannot be guaranteed that the phase difference between phase 0 and phase 45 is equal to the phase difference between phase 45 and phase 90; the phase difference between phase 90 and phase 135 is equal to the phase difference between phase 135 and phase 180; the phase difference between phase 180 and phase 225 is equal to the phase difference between phase 225 and phase 270; and the phase difference between phase 270 and phase 315 is equal to the phase difference between phase 315 and phase 0. Further calibration is required. For example, in step five, select phase 0, phase 45, and phase 90; in step six, select phase 90, phase 135, and phase 180; in step seven, select phase 180, phase 225, and phase 270; and in step eight, select phase 270, phase 315, and phase 0. Phase calibration is completed after these eight steps. It can be understood that for a 4-phase clock signal, only the first four calibration steps of the eight-phase calibration are needed to complete the corresponding phase calibration.

[0054] For an 8-phase clock, it can be done as described above. Figure 2The steps shown are performed sequentially for eight calibrations to achieve phase difference consistency among the eight phases. Step 1: Move the phase adjustment unit corresponding to phase 90 so that the phase difference between phase 90 and phase 0 equals the phase difference between phase 90 and phase 180. Step 2: Move the phase adjustment unit corresponding to phase 270 so that the phase difference between phase 270 and phase 180 equals the phase difference between phase 270 and phase 0. Step 3: Move the phase adjustment unit corresponding to phase 180 so that the phase difference between phase 180 and phase 90 equals the phase difference between phase 180 and phase 270. Step 4: Move the phase adjustment unit corresponding to phase 0 so that the phase difference between phase 270 and phase 0 equals the phase difference between phase 0 and phase 90. These four calibration steps achieve phase difference consistency among phases 0, 90, 180, and 270, ideally equal to 90 degrees.

[0055] After the 90-degree calibration is completed, execute steps 5, 6, 7, and 8. Step 5 moves the phase adjustment unit corresponding to phase 45 so that the phase difference between phase 0 and phase 45 is equal to the phase difference between phase 45 and phase 90. Step 6 moves the phase adjustment unit corresponding to phase 135 so that the phase difference between phase 90 and phase 135 is equal to the phase difference between phase 135 and phase 180. Step 7 moves the phase adjustment unit corresponding to phase 225 so that the phase difference between phase 180 and phase 225 is equal to the phase difference between phase 225 and phase 270. Step 8 moves the phase adjustment unit corresponding to phase 315 so that the phase difference between phase 270 and phase 315 is equal to the phase difference between phase 315 and phase 0. Through the above 8 steps, phase calibration between the 8 phases is achieved.

[0056] Understandable, Figure 2 In the example shown, the order of step1 and step2 can be swapped, the order of step3 and step4 can be swapped, and the order of step1 to step4 can also be reversed, for example, to step4 to step1; similarly, there is no order between step5 to step8.

[0057] The control module, based on the quantization results, controls the multi-phase adjustment module to adjust the phase of the target phase clock signal so that the first phase difference matches the second phase difference. When the phase error detection module performs N-step phase error calibration operations, it generates N quantization results. Correspondingly, the control module controls the multi-phase adjustment module to adjust the phase of the target phase clock signal based on each quantization result. It is understandable that the target phase clock signal adjusted in each step is different.

[0058] In some possible implementations, the control module may include a controller. Alternatively, the control module may be other modules that implement the above functions; for example, the control module may be a Finite State Machine (FSM). The FSM_OUT output of the FSM controls the drive strength or load of the phase adjustment units INV0, INV1, INV2, INV3, INV4, INV5, INV6, or INV7 in the multi-phase adjustment module to achieve phase calibration.

[0059] In some possible implementations, the phase error detection module may include a time-digital converter (TDC). After obtaining the first phase difference and the second phase difference, the TDC can be used to quantize the phase difference between the first phase difference and the second phase difference to obtain the quantization result.

[0060] In some possible implementations, when the phase difference between the first phase difference and the second phase difference is quantized to obtain the quantization result, the phase error detection module specifically converts the first phase difference into a first voltage signal, converts the second phase difference into a second voltage signal, and compares and quantizes the first and second voltage signals to obtain the quantization result. Furthermore, an automatic zero-calibration technique can be introduced in the phase error comparison to eliminate errors introduced by the comparator's own offset, thereby improving calibration accuracy.

[0061] In some possible implementations, such as Figure 3 As shown, the phase error detection module includes: a first detection unit, a second detection unit, a first low-pass filter (LPF), a second low-pass filter, and an error quantization unit. If the phase error detection module is implemented based on a TDC, then the phase error detection module may include the first detection unit, the second detection unit, and the TDC.

[0062] The first detection unit is used to detect a first phase difference between a first phase clock signal and a second phase clock signal. The input signals of the first detection unit are the first phase clock signal and the second phase clock signal, and the output signal is the first phase difference.

[0063] The second detection unit is used to detect the second phase difference between the second phase clock signal and the third phase clock signal. The input signals of the second detection unit are the second phase clock signal and the third phase clock signal, and the output signal is the second phase difference.

[0064] A first low-pass filter is connected to a first detection unit. The first low-pass filter is used to convert the first phase difference into a corresponding first voltage signal.

[0065] The second low-pass filter is connected to the second detection unit and is used to convert the second phase difference into a corresponding second voltage signal.

[0066] The error quantization unit is connected to the first low-pass filter and the second low-pass filter respectively. The error quantization unit is used to compare and quantize the first voltage signal and the second voltage signal to obtain the quantization result.

[0067] The structures of the first detection unit and the second detection unit can be different. However, to simplify the design process, the structures of the first detection unit and the second detection unit can be the same. This application only illustrates the case where the structures of the first detection unit and the second detection unit are the same. In some possible implementations, such as... Figure 4 As shown, the first detection unit includes: a first flip-flop (DFF0), a second flip-flop (DFF1), and a NAND gate (NAND0). Optionally, the first detection unit may also include buffers (buffer0 and buffer1). Furthermore, the first and second detection units may also be detection units used for detecting phase differences in related technologies.

[0068] The data input terminal (e.g., D terminal) of the first flip-flop is connected to the power supply, the clock input terminal (e.g., Clk terminal) of the first flip-flop is connected to the first phase clock signal, and the data output terminal (e.g., Q terminal) of the first flip-flop is connected to the first low-pass filter. In some possible implementations, the data output terminal (e.g., Q terminal) of the first flip-flop is connected to the first low-pass filter through a buffer. Figure 4 In this context, clk represents the first phase difference.

[0069] The data input terminal (e.g., D terminal) of the second flip-flop is connected to the power supply, and the clock input terminal (e.g., Clk terminal) of the second flip-flop is connected to the second phase clock signal.

[0070] The first input of the first NAND gate is connected to the data output of the first flip-flop, the second input of the first NAND gate is connected to the data output of the second flip-flop, and the output of the first NAND gate is connected to the reset terminals (e.g., Rb terminals) of the first and second flip-flops respectively.

[0071] The structure of the second detection unit is the same as that of the first detection unit, for example, as follows: Figure 5 As shown, the second detection unit includes a third flip-flop (DFF2), a fourth flip-flop (DFF3), and a second NAND gate (NAND1). The data output terminal of the third flip-flop in the second detection unit is connected to the second low-pass filter. Figure 5 The clk output by the second detection unit is the second phase difference.

[0072] In some possible implementations, the error quantization unit includes a comparator for comparing a first voltage signal and a second voltage signal. Alternatively, the error quantization unit includes a comparator and a latch, with the latch connected to the output of the comparator.

[0073] In some other possible implementations, such as Figure 6 As shown, the error quantization unit includes: a phase offset selection circuit and an automatic zeroing comparator. Additionally, the error quantization unit may also include a latch.

[0074] The phase offset selection circuit has two states (first state and second state). When the phase offset selection circuit is in the first state, the first voltage signal is output to the first node (VIP0), and the second voltage signal is output to the second node (VIN0). When the phase offset selection circuit is in the second state, the second voltage signal is output to the first node, and the first voltage signal is output to the second node. The state of the phase offset selection circuit is controlled by clock_reset and clock_latch. The control signals of SW0, SW1 and SW2, SW3 are non-overlapping clocks, meaning that there is no interval in which SW0, SW1 and SW2, SW3 are simultaneously turned on. SW2, SW3 will only turn on after SW0, SW1 is completely turned off; conversely, SW0, SW1 will only turn on after SW2, SW3 is completely turned off.

[0075] The first input terminal of the automatic zeroing comparator is connected to the first node via a first capacitor (C0), and the second input terminal is connected to the second node via a second capacitor (C1). When the phase offset selection circuit is in the first state, the loop between the input and output terminals of the automatic zeroing comparator is in a conducting state; when the phase offset selection circuit is in the second state, the loop between the input and output terminals of the automatic zeroing comparator is in a disconnected state. The state of the loop can be controlled by adjusting the conduction of SW4 and SW5.

[0076] The latch has its data input terminal connected to the output terminal of the automatic zeroing comparator, and its output terminal connected to the control module.

[0077] Optionally, when the phase error detection module selects three specified phase signals from the N phase clock signals output by the multi-phase adjustment module, the phase error detection module is specifically configured to select the corresponding three specified phase signals from the N phase clock signals output by the multi-phase adjustment module according to the selection signal. In some possible implementations, the phase error detection module further includes a selection circuit, for example, it can... Figure 5 Based on the above, a phase selection circuit is further added to select the phase clock signal input to the first detection unit and the second detection unit. For example... Figure 7 As shown, the first phase selection circuit is used to select the first phase clock signal and the second phase clock signal, and the second phase selection circuit is used to select the second phase clock signal and the third phase clock signal.

[0078] By controlling the control signals sel<1:0> of the first and second phase selection circuits, the two detected adjacent phases are sent to the first and second detection units according to the following steps. After the second detection unit detects the phase error, it outputs corresponding signals clk0 and clk1, which are then filtered by a low-pass filter to output DC levels V0 and V1. These are then output to VIP0 and VIN0 via non-overlapping clock control switches SW0, SW1, SW2, and SW3. VIP0 and VIN0 are compared by an automatic zeroing comparator via capacitors C0 and C1. The comparison result is then processed by a finite state machine (FSM) to control the corresponding phase adjustment unit, achieving consistent skew between adjacent phases.

[0079] To better understand the phase error calibration process shown in this application, the following explanation is provided with examples.

[0080] If the phase difference between phase 0, phase 90, phase 180, and phase 270 is an ideal 90 degrees, then the output results of the first and second detection units are as follows: Figure 8 As shown, the skew output between the rising edges of phase 0 and phase 90 is clk0, the skew output between the rising edges of phase 90 and phase 180 is clk1, the skew output between the rising edges of phase 180 and phase 270 is clk2, and the skew output between the rising edges of phase 270 and phase 0 is clk3. The duty cycle of the output signals clk0, clk1, clk2, and clk3 is an ideal 25%.

[0081] Similarly, if it is an 8-phase clock, and the phase difference between phase 0, phase 45, phase 90, phase 135, phase 180, phase 225, phase 270, and phase 315 is an ideal 45 degrees, then the output results of the first and second detection units are as follows: Figure 9 As shown, the skew output between the rising edges of phase 0 and phase 45 is clk0, the skew output between the rising edges of phase 45 and phase 90 is clk1, the skew output between the rising edges of phase 90 and phase 135 is clk2, the skew output between the rising edges of phase 135 and phase 180 is clk3, the skew output between the rising edges of phase 180 and phase 225 is clk4, the skew output between the rising edges of phase 225 and phase 270 is clk5, the skew output between the rising edges of phase 270 and phase 315 is clk6, and the skew output between the rising edges of phase 315 and phase 0 is clk7. The duty cycle of outputs clk0, clk1, clk2, clk3, clk4, clk5, clk6, and clk7 is the ideal 12.5%.

[0082] However, due to the influence of process and physical implementation, the skew between clock phases of multi-phase clocks is not an ideal angle, so the phase error needs to be calibrated before normal application.

[0083] for Figure 7 The 8-phase clock shown can be configured as described above. Figure 2 The steps shown are performed sequentially for eight calibrations to ensure consistent phase difference between the eight phases.

[0084] In step 1, the phase selection signal of the first phase selection circuit is sel<1:0>=00. MUX0 and MUX1 select input signals phase0 and phase90 respectively as the clocks for DFF0 and DFF1 within the first detection unit. Simultaneously, the phase selection signal of the second phase selection circuit is sel<1:0>=00, and MUX2 and MUX3 select input signals phase90 and phase180 respectively as the clocks for DFF2 and DFF3 within the second detection unit. The first and second detection units detect the time difference between the rising edges of the clocks phase0 and phase90, and phase90 and phase180 respectively. If the phase difference between phase0 and phase90 is greater than the phase difference between phase90 and phase180, the outputs p0, p1, p2, and p3 of DFF0, DFF1, DFF2, and DFF3 are the same as the outputs after passing through buffer0, buffer1, buffer2, and buffer3. Initially, the p0 signal output by DFF1 is 0. When the rising edge of phase 0 arrives, the p0 output by DFF0 equals the result of clk0, which is 1. At this time, the p1 signal output by DFF1 is 0. When the rising edge of phase 90 arrives, p1 changes from 0 to 1. The output result of p0 and p1 through the NAND gate NAND0 changes from 1 to 0. After the delay of NAND0, DFF0 and DFF1 output clk0.

[0085] Meanwhile, the second detection unit is responsible for checking the phase difference between phase 90 and phase 180. When the rising edge of phase 90 arrives, the output of DFF2, p2, equals the result of clk1, which is 1. At this time, the output of DFF3, p3, is 0. When the rising edge of phase 180 arrives, p3 changes from 0 to 1. The output of p2 and p3, after passing through the NAND gate NAND1, changes from 1 to 0. After a delay by NAND1, the output of DFF2, clk1, changes from 1 to 0. At this time, the duty cycle of clk0 is greater than that of clk1. Figure 10 As shown, after the outputs of clk0 and clk1 are low-pass filtered by low-pass filters LPF0 and LPF1, the output signals V0 and V1 are equal to VDD / 4+deltava (where deltava is the phase difference between the actual 0 degrees and 90 degrees and the phase error between the ideal 90 degrees) and VDD / 4-deltavb (where deltavb is the phase difference between the actual 90 degrees and 180 degrees and the phase error between the ideal 90 degrees), respectively. The voltage of V0 is greater than that of V1.

[0086] for Figure 6 The error quantization unit shown is as follows: Figure 11As shown, during the period when clock_reset is 1, SW0, SW1, SW4, and SW5 are simultaneously turned on, while SW2 and SW3 are turned off. At this time, the voltage of VIP0 is VDD / 4 + deltava, and the voltage of VIN0 is VDD / 4 - deltavab. The output terminals VOUTP and VOUTN of the auto-zero comparator (hereinafter referred to as the comparator) are connected to the input terminals VIP and VIN, making the voltages at the differential input terminals of the comparator consistent, both equal to Vol_cm + offset / 2, where vol_cm represents the common-mode voltage of the differential input, and offset is the offset voltage of the auto-zero comparator. The voltage difference across capacitors C0 and C1 is: V_C0 = Vol_cm+offset / 2-(VDD / 4+deltava); V_C1 = Vol_cm+offset / 2-(VDD / 4-deltavb).

[0087] At this point, the latch retains the previous comparator output of 0. When the non-overlapping clock `clock_reset` becomes 0 and `clock_latch` becomes 1, the VIP0 voltage switches from VDD / 4+deltava to VDD / 4-deltava, and the VIN0 voltage switches from VDD / 4-deltava to VDD / 4+deltava. Because the voltages across capacitors C0 and C1 cannot change abruptly, the voltages of VIP and VIN at this time are respectively: VIP= Vol_cm+offset / 2-(deltava+ deltavb); VIN= Vol_cm+offset / 2+(deltava+ deltavb).

[0088] At this point, the comparator is in the comparison phase. Since VIP is less than VIN, the output is 0. The latch sends the comparator's output to the digital state machine, and the digital state machine's output decreases. Figure 1b The load on the phase adjustment unit INV2 in the circuit reduces the phase difference between phase 0 and phase 90, while increasing the phase difference between phase 90 and phase 180. Through the above process, the load of INV2 is continuously adjusted. When the comparator's output first changes from 0 to 1, the calibration in step 1 is completed, making the phase difference between phase 0 and phase 90 equal to the phase difference between phase 90 and phase 180. In step 1, if the phase difference between phase 0 and phase 90 is less than the phase difference between phase 90 and phase 180, then... Figure 12As shown, at this time, the duty cycle of clk0 is less than the duty cycle of clk1. After the output results of clk0 and clk1 are low-pass filtered by low-pass filters LPF0 and LPF1, the output signals V0 and V1 are equal to VDD / 4-deltava and VDD / 4+deltavab, respectively, and the voltage of V0 is less than that of V1.

[0089] During the period when clock_reset is 1, SW0, SW1, SW4, and SW5 are simultaneously turned on, while SW2 and SW3 are turned off. At this time, the voltage at VIP0 is VDD / 4 - deltava, and the voltage at VIN0 is VDD / 4 + deltavab. The comparator outputs VOUTP and VOUTN are connected to the inputs VIP and VIN, making the voltages at the differential inputs of the comparator identical, both equal to Vol_cm + offset / 2. The voltage difference across capacitors C0 and C1 is: V_C0 = Vol_cm+offset / 2-(VDD / 4-deltava); V_C1 = Vol_cm+offset / 2-(VDD / 4+deltavb).

[0090] At this point, the latch retains the previous comparator output result of 1. When the non-overlapping clock_reset becomes 0 and clock_latch becomes 1, the VIP0 voltage switches from VDD / 4-deltava to VDD / 4+deltava, and the VIN0 voltage switches from VDD / 4+deltava to VDD / 4-deltava. Because the voltages across capacitors C0 and C1 cannot change abruptly, the voltages of VIP and VIN at this time are respectively: VIP= Vol_cm+offset / 2+(deltava+ deltavb); VIN= Vol_cm+offset / 2-(deltava+ deltavb).

[0091] At this point, the comparator is in the comparison phase. Since VIP is greater than VIN, the output is 1. The latch sends the comparator's output to the digital state machine, and the digital state machine's output decreases. Figure 1b The load on the phase adjustment unit INV2 increases the phase difference between phase 0 and phase 90, while decreasing the phase difference between phase 90 and phase 180. Through this process, the load on INV2 is continuously adjusted. When the comparator's output first changes from 1 to 0, the calibration in step 1 is complete, making the phase difference between phase 0 and phase 90 equal to the phase difference between phase 90 and phase 180.

[0092] After Step 1 is completed, proceed to Step 2. At this stage, compare the phase difference between phase 180 and phase 270 with the phase difference between phase 270 and phase 0. If the phase difference between phase 180 and phase 270 is greater than the phase difference between phase 270 and phase 0, then the process is the same as in Step 1. Figure 10 In this context, phase0, phase90, and phase180 are replaced by phase180, phase270, and phase0, respectively. Therefore, the duty cycle of clk0 is greater than that of clk1. After passing through the low-pass filter, the output voltage V0 is VDD / 4 + deltava (where deltava is the actual phase difference from 180 degrees to 270 degrees and the phase error from the ideal 90 degrees), and V1 is VDD / 4 - deltavab (where deltava is the actual phase difference from 270 degrees to 0 degrees and the phase error from the ideal 90 degrees).

[0093] While clock_reset is 1, SW0, SW1, SW4, and SW5 are simultaneously turned on, while SW2 and SW3 are turned off. At this time, the voltage information of VIP0, VIN0, VIP, and VIN is as follows: Figure 11 As shown, at this time, the voltage of VIP0 is VDD / 4 + deltava, and the voltage of VIN0 is VDD / 4 - deltavab. The output terminals VOUTP and VOUTN of the comparator are connected to the input terminals VIP and VIN, making the voltages at the differential input terminals of the comparator consistent, both equal to Vol_cm + offset / 2. The voltage difference across capacitors C0 and C1 is: V_C0 = Vol_cm+offset / 2-(VDD / 4+deltava); V_C1 = Vol_cm+offset / 2-(VDD / 4-deltavb).

[0094] At this point, the latch retains the previous comparator output of 0. When the non-overlapping clock `clock_reset` becomes 0 and `clock_latch` becomes 1, the VIP0 voltage switches from VDD / 4+deltava to VDD / 4-deltava, and the VIN0 voltage switches from VDD / 4-deltava to VDD / 4+deltava. Because the voltages across capacitors C0 and C1 cannot change abruptly, the voltages of VIP and VIN at this time are respectively: VIP= Vol_cm+offset / 2-(deltava+ deltavb); VIN= Vol_cm+offset / 2+(deltava+ deltavb).

[0095] At this point, the comparator is in the comparison phase. Since VIP is less than VIN, the output is 0. The latch sends the comparator's output to the digital state machine, and the digital state machine's output decreases. Figure 1b The load on the phase adjustment unit INV6 reduces the phase difference between phase 180 and phase 270, while increasing the phase difference between phase 270 and phase 0.

[0096] In step 2, the phase selection signals sel<1:0>=22 for the first phase selection circuit and the second phase selection circuit. If the phase difference between phase 180 and phase 270 is less than the phase difference between phase 270 and phase 0, then... Figure 12 In step 1, phase 0, phase 90, and phase 180 are replaced by phase 180, phase 270, and phase 0, respectively. The process is the same as in step 1. Then, the duty cycle of clk0 is less than the duty cycle of clk1. After passing through the low-pass filter, the output voltage V0 is VDD / 4 - deltava, and V1 is VDD / 4 + deltavab.

[0097] While clock_reset is 1, SW0, SW1, SW4, and SW5 are simultaneously turned on, while SW2 and SW3 are turned off. At this time, the voltage information of VIP0, VIN0, VIP, and VIN is as follows: Figure 13 As shown, the voltage at VIP0 is VDD / 4 - deltava, and the voltage at VIN0 is VDD / 4 + deltavab. At this time, the comparator's outputs VOUTP and VOUTN are connected to the inputs VIP and VIN, respectively. The differential input voltages are the same, equal to Vol_cm + offset / 2. The voltage difference across capacitors C0 and C1 is: V_C0 = Vol_cm+offset / 2-(VDD / 4-deltava); V_C1 = Vol_cm+offset / 2-(VDD / 4+deltavb).

[0098] At this point, the latch retains the previous comparator output result of 1. When the non-overlapping clock_reset becomes 0 and clock_latch becomes 1, the VIP0 voltage switches from VDD / 4-deltava to VDD / 4+deltava, and the VIN0 voltage switches from VDD / 4+deltava to VDD / 4-deltava. Because the voltages across capacitors C0 and C1 cannot change abruptly, the voltages of VIP and VIN at this time are respectively: VIP= Vol_cm+offset / 2+(deltava+ deltavb); VIN= Vol_cm+offset / 2-(deltava+ deltavb).

[0099] At this point, the comparator is in the comparison phase. Since VIP is greater than VIN, the output is 1. The latch sends the comparator's output to the digital state machine, and the digital state machine's output increases. Figure 1b The load on the phase adjustment unit INV6 increases the phase difference between phase 180 and phase 270, while decreasing the phase difference between phase 270 and phase 0.

[0100] Through the above process, the load size in INV6 is continuously adjusted until the phase difference between phase 180 and phase 270 is equal to the phase difference between phase 270 and phase 0, and the calibration in step 2 is completed.

[0101] After completing steps 1 and 2, the phase difference from phase 0 to phase 90 is equal to the phase difference from phase 90 to phase 180, and the phase difference from phase 180 to phase 270 is equal to the phase difference from phase 270 to phase 0. However, at this point, the phase difference from phase 0 to phase 90, or the phase difference from phase 90 to phase 180, is not equal to the phase difference from phase 180 to phase 270, or the phase difference from phase 270 to phase 0. To achieve the same phase difference, steps 3 and 4 are required.

[0102] Step 3 follows the same process as Step 1 or Step 2. The phase selection signals sel<1:0>=11 for the first and second phase selection circuits. Step 3 compares the phase difference between phase 90 and phase 180 with the phase difference between phase 180 and phase 270. If the phase difference between phase 90 and phase 180 is greater than the phase difference between phase 180 and phase 270, the digital state machine outputs a decrease in the load of the phase adjustment unit INV4, thus reducing the phase difference between phase 90 and phase 180 while increasing the phase difference between phase 180 and phase 270. Conversely, if the phase difference between phase 90 and phase 180 is less than the phase difference between phase 180 and phase 270, the digital state machine outputs an increase in the load of the phase adjustment unit INV4, thus increasing the phase difference between phase 90 and phase 180 while decreasing the phase difference between phase 180 and phase 270. Through this process, the load size in INV4 is continuously adjusted until the phase difference between phase 90 and phase 180 is equal to the phase difference between phase 180 and phase 270, and the calibration in step 3 is completed.

[0103] After step 3 is completed, proceed to step 4. At this point, the phase selection signals sel<1:0>=33 for both the first and second phase selection circuits, and the process is consistent with steps 1, 2, or 3 above. Step 4 compares the phase difference between phase 270 and phase 0 with the phase difference between phase 0 and phase 90. If the phase difference between phase 270 and phase 0 is greater than the phase difference between phase 0 and phase 90, the digital state machine output decreases. Figure 1b The load on the phase adjustment unit INV0 reduces the phase difference between phase 270 and phase 0, while increasing the phase difference between phase 0 and phase 90. Conversely, if the phase difference between phase 270 and phase 0 is less than the phase difference between phase 0 and phase 90, the digital state machine output increases. Figure 1b The load on the phase adjustment unit INV0 increases the phase difference between phase 270 and phase 0, while decreasing the phase difference between phase 0 and phase 90. Through this process, the load in INV0 is continuously adjusted until the phase difference between phase 270 and phase 0 equals the phase difference between phase 0 and phase 90, thus completing the calibration in step 4.

[0104] After completing steps 1, 2, 3, and 4, the calibration between the four orthogonal phases of phase 0, phase 90, phase 180, and phase 270 can be achieved. After the calibration of the four orthogonal phases of phase 0, phase 90, phase 180, and phase 270 is completed, the calibration between the eight phases continues. At this point, it cannot be guaranteed that the phase difference between phase 0 and phase 45 is equal to the phase difference between phase 45 and phase 90; the phase difference between phase 90 and phase 135 is equal to the phase difference between phase 135 and phase 180; the phase difference between phase 180 and phase 225 is equal to the phase difference between phase 225 and phase 270; and the phase difference between phase 270 and phase 315 is equal to the phase difference between phase 315 and phase 0. Further steps 5, 6, 7, and 8 are required.

[0105] Steps 5, 6, 7, and 8 are similar to steps 1, 2, 3, and 4, except for the selection of sel<1:0> in the first and second phase selection circuits. In step 5, the sel in the first phase selection circuit... <0> =0, sel <1> =4; sel in the second phase selection circuit <0> =4, sel <1> =3, adjust the load size of INV1 according to the FSM output so that the phase difference between phase0 and phase45 is equal to the phase difference between phase45 and phase90.

[0106] In step 6, the sel in the first phase selection circuit <0> =1, sel <1> =5; sel in the second phase selection circuit <0> =5, sel <1> =0, adjust the load of INV3 according to the FSM output so that the phase difference between phase 90 and phase 135 is equal to the phase difference between phase 135 and phase 180.

[0107] In step 7, the sel in the first phase selection circuit <0> =2, sel <1> =6; sel in the second phase selection circuit <0> =6, sel <1> =1, adjust the load of INV5 according to the FSM output so that the phase difference between phase180 and phase225 is equal to the phase difference between phase225 and phase270.

[0108] In step 8, the sel in the first phase selection circuit <0> =3, sel <1> =7; sel in the first phase selection circuit <0> =7, sel <1> =2, adjust the load size of INV7 according to the FSM output so that the phase difference between phase270 and phase315 is equal to the phase difference between phase315 and phase0.

[0109] The above 8 steps achieve a 45-degree phase difference between adjacent signals in the 8 phases. Understandably, for applications requiring 16-phase clock signal calibration, after the above 8-phase calibration, 8 additional phase calibration steps are needed: Adjusting the phase adjustment unit corresponding to phase 22.5 so that the phase difference between phase 0 and phase 22.5 equals the phase difference between phase 22.5 and phase 45; adjusting the phase adjustment unit corresponding to phase 67.5 so that the phase difference between phase 45 and phase 67.5 equals the phase difference between phase 67.5 and phase 90; adjusting the phase adjustment unit corresponding to phase 112.5; adjusting the phase adjustment unit corresponding to phase 157.5; adjusting the phase adjustment unit corresponding to phase 202.5; adjusting the phase adjustment unit corresponding to phase 247.5; adjusting the phase adjustment unit corresponding to phase 292.5; and adjusting the phase adjustment unit corresponding to phase 337.5. These 16 phase calibration steps achieve a 22.5-degree phase calibration across 16 phases.

[0110] This application also provides a phase error calibration method, such as... Figure 14 As shown below, in conjunction with Figure 14 The principle behind this method is explained. This phase error calibration method can be applied to the phase error calibration circuit shown in any of the aforementioned embodiments, as well as to other modules, chips, and devices that implement this method.

[0111] S1: Obtain N phase clock signals output by the multi-phase adjustment module.

[0112] For example, the N phase clock signals generated by a PLL or DLL are obtained and processed by a multi-phase adjustment module to obtain N phase clock signals. The multi-phase adjustment module contains N phase adjustment units, each corresponding to a phase clock signal and responsible for adjusting the phase of that phase clock signal.

[0113] S2: Perform N-step phase error calibration to make the phase difference between any two adjacent phase clock signals in the N phase clock signals consistent.

[0114] After acquiring N phase clock signals output by the multi-phase adjustment module, three specified phase signals (the first, second, and third phase clock signals) can be selected from the N phase clock signals to perform phase error calibration. This ensures that the first phase difference between the first and second phase clock signals is consistent with the second phase difference between the second and third phase clock signals. N similar phase error calibration steps are performed to ensure that the phase difference between any two adjacent phase clock signals among the N phase clock signals is consistent.

[0115] In each phase error calibration operation, at least one of the three specified phase signals selected from N phase clock signals must be different, such as at least the second phase clock signal being different. Each phase error calibration operation includes: The system detects the first phase difference between the first and second phase clock signals, and the second phase difference between the second and third phase clock signals. It then quantizes the phase differences between the first and second phase differences to obtain a quantization result. Based on the quantization result, it controls a multi-phase adjustment module to adjust the phase of the second phase clock signal so that the first phase difference matches the second phase difference. The first, second, and third phase clock signals are three designated phase signals from N phase clock signals, and the phase of the second phase clock signal lies between the phases of the first and third phase clock signals.

[0116] The phase error calibration method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned phase error calibration circuit embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned phase error calibration circuit embodiment. This application also provides a chip including a phase-locked loop (PLL) and a phase error calibration circuit as provided in any of the above embodiments; the PLL is connected to the phase error calibration circuit and is used to generate N initial phase clock signals. The PLLs shown in this application include, but are not limited to, delay phase-locked loops (DLLs).

[0117] The chip shown in this application can be a clock generator or clock synchronizer, or a high-speed interface chip, such as a transceiver chip. Furthermore, the chip shown in this application can also be an integrated circuit chip with signal processing capabilities. The aforementioned chip can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit (ACCU), a Multimedia Application Processor (MAP), a microprocessor, etc.; the aforementioned chip can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, the chip can also be any conventional processor.

[0118] This application also provides an electronic device that includes the aforementioned chip. In some possible implementations, such as... Figure 15 As shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor. The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, including at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor executes the software functional module or computer program stored in the memory. For example, the processor executes the phase error calibration method described above.

[0119] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0120] The processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, the processor can be any conventional processor.

[0121] The electronic devices provided in this application may include, but are not limited to, mobile phones, tablets, personal computers (PCs), netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other devices equipped with parallel processors.

[0122] This application also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which, when run by a computer such as the electronic device described above, executes the phase error calibration method described above.

[0123] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0124] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0125] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0126] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0127] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A phase error calibration circuit, characterized in that, include: A multi-phase adjustment module is used to adjust the phase of the target phase clock signal from N received initial phase clock signals, where N=2. m m is an integer greater than or equal to 2; A phase error detection module is used to detect a first phase difference between a first phase clock signal and a second phase clock signal, and a second phase difference between the second phase clock signal and a third phase clock signal, and to quantize the phase differences between the first phase difference and the second phase difference to obtain a quantization result; wherein, the first phase clock signal, the second phase clock signal, and the third phase clock signal are three designated phase signals among N phase clock signals output by the multi-phase adjustment module, and the phase of the second phase clock signal is located between the phase of the first phase clock signal and the phase of the third phase clock signal; the second phase clock signal is the signal of the target phase clock signal after passing through the multi-phase adjustment module. The control module is used to control the multi-phase adjustment module to adjust the phase of the target phase clock signal according to the quantization result, so that the first phase difference is consistent with the second phase difference.

2. The phase error calibration circuit according to claim 1, wherein the phase error detection module is specifically used to convert the first phase difference into a first voltage signal, convert the second phase difference into a second voltage signal, compare and quantize the first voltage signal and the second voltage signal to obtain a quantization result.

3. The phase error calibration circuit according to claim 2, characterized in that, The phase error detection module includes: The first detection unit is used to detect the first phase difference between the first phase clock signal and the second phase clock signal; The second detection unit is used to detect the second phase difference between the second phase clock signal and the third phase clock signal; A first low-pass filter is used to convert the first phase difference into a corresponding first voltage signal; A second low-pass filter is used to convert the second phase difference into a corresponding second voltage signal; An error quantization unit is used to compare and quantize the first voltage signal and the second voltage signal to obtain a quantization result.

4. The phase error calibration circuit according to claim 3, characterized in that, The first detection unit includes: The first flip-flop has its data input terminal connected to a power supply, its clock input terminal connected to the first phase clock signal, and its data output terminal connected to the first low-pass filter. The second flip-flop has its data input terminal connected to a power supply and its clock input terminal connected to the second phase clock signal. The first NAND gate has its first input connected to the data output of the first flip-flop, its second input connected to the data output of the second flip-flop, and its output connected to the reset terminals of the first and second flip-flops, respectively.

5. The phase error calibration circuit according to claim 3, characterized in that, The second detection unit includes: The third flip-flop has its data input terminal connected to a power supply, its clock input terminal connected to the second phase clock signal, and its data output terminal connected to the second low-pass filter. The fourth flip-flop has its data input terminal connected to a power supply and its clock input terminal connected to the third phase clock signal. The second NAND gate has its first input connected to the data output of the third flip-flop, its second input connected to the data output of the fourth flip-flop, and its output connected to the reset terminals of the third and fourth flip-flops.

6. The phase error calibration circuit according to claim 3, characterized in that, The error quantization unit includes: The phase offset selection circuit, when in a first state, outputs the first voltage signal to a first node and the second voltage signal to a second node; when in a second state, the second voltage signal is output to the first node and the first voltage signal is output to the second node. An automatic zeroing comparator is provided, wherein the first input terminal of the automatic zeroing comparator is connected to the first node through a first capacitor, and the second input terminal of the automatic zeroing comparator is connected to the second node through a second capacitor. When the phase offset selection circuit is in the first state, the loop between the input terminal and the output terminal of the automatic zeroing comparator is in the conducting state, and when the phase offset selection circuit is in the second state, the loop between the input terminal and the output terminal of the automatic zeroing comparator is in the open state. A latch, the data input terminal of which is connected to the output terminal of the automatic zeroing comparator, and the output terminal of the latch is connected to the control module.

7. The phase error calibration circuit according to any one of claims 1-6, characterized in that, The phase error detection module is specifically used to select three specified phase signals from the N phase clock signals output by the multi-phase adjustment module according to the selection signal.

8. A chip, characterized in that, It includes a phase-locked loop and a phase error calibration circuit as described in any one of claims 1-7; the phase-locked loop is connected to the phase error calibration circuit, and the phase-locked loop is used to generate N initial phase clock signals.

9. An electronic device, characterized in that, Including the chip as described in claim 8.

10. A phase error calibration method, characterized in that, include: Obtain N phase clock signals output by the multi-phase adjustment module, where N=2 m m is an integer greater than or equal to 2; Perform N-step phase error calibration operations to make the phase difference between any two adjacent phase clock signals among the N phase clock signals consistent; Each phase error calibration operation includes: The first phase difference between the first phase clock signal and the second phase clock signal, and the second phase difference between the second phase clock signal and the third phase clock signal are detected, and the phase differences between the first phase difference and the second phase difference are quantized to obtain a quantization result; wherein the first phase clock signal, the second phase clock signal, and the third phase clock signal are three designated phase signals among the N phase clock signals, and the phase of the second phase clock signal is located between the phase of the first phase clock signal and the phase of the third phase clock signal; Based on the quantization result, the multi-phase adjustment module is controlled to adjust the phase of the second phase clock signal so that the first phase difference is consistent with the second phase difference; In each phase error calibration operation, at least one of the three designated phase signals selected from the N phase clock signals is different.

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