Logic gate circuit of hybrid memristor CMOS and complex logic circuit

Abstract

The invention relates to the technical field of micro-nano electronic complex logic circuits, and provides a logic gate circuit of a hybrid memristor CMOS (Complementary Metal Oxide Semiconductor) and a complex logic circuit, the memristor is integrated with the rear end of the CMOS, the additional substrate area is not occupied, and the data density is improved by 1.58 times compared with that of a traditional CMOS binary circuit. A CMOS complementary circuit structure is adopted, static power consumption is remarkably reduced, signal attenuation during cascading is restrained, reliable transmission of a multi-stage logic chain is ensured, compared with a traditional design, the number of devices is reduced, power consumption is lower, the integration degree is high, and a practical logic unit with high performance and low power consumption is achieved. According to the memristor adopting the standard CMOS process and post-integration, an additional mask layer is not needed in preparation of the memristor, the memristor can be directly imported into an existing integrated circuit production line, the industrialization cost is reduced, and the memristor is compatible with an existing EDA tool and has the practical tape-out potential.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronic complex logic circuit technology, and relates to a logic gate circuit and complex logic circuit of hybrid memristor CMOS. Background Technology

[0002] As Moore's Law approaches its physical limits, traditional binary CMOS circuits face the memory wall problem caused by the von Neumann bottleneck and interconnect latency challenges, making it difficult to meet the high-performance requirements of massive data processing in fields such as the Internet of Things and artificial intelligence. In the post-Moore's Law era, Multiple-Valued Logic (MVL), especially ternary logic, has attracted widespread attention due to its ability to improve information density and reduce the number of interconnects. Existing ternary logic circuits are mainly divided into two categories: unbalanced ternary logic (such as {0,1,2} or {0,-1,-2}) and balanced ternary logic (such as {-1,0,1}). Balanced ternary logic has significant advantages: it can represent the range of integers without a sign bit, multiplication does not produce a carry, and addition only produces a carry in 2 out of 9 input combinations, thus giving it superior performance in arithmetic operations.

[0003] Memristors, as passive devices with non-volatility, nanoscale size, and back-end process operability (BEOL) integration characteristics, provide an ideal carrier for realizing high-density ternary logic. By integrating memristors into the back-end interconnect layer of CMOS processes, complex logic functions can be implemented without occupying substrate silicon area. However, existing pure memristor-based logic gates (such as memristor ratio logic (MRL) voltage divider structures) suffer from static current problems, severe signal attenuation during cascading, and require additional buffer circuits. Existing designs are mostly focused on unbalanced ternary logic, with insufficient research on systematic circuit design methods for balanced ternary logic systems. There is a lack of collaborative design methods that take into account both the variable resistance characteristics of memristors and the switching characteristics of MOSFETs (metal-oxide-semiconductor field-effect transistors), making it difficult to achieve high-performance and low-power practical logic units. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional methods, this invention proposes a hybrid memristor CMOS logic gate circuit and a complex logic circuit, which have the advantages of fewer devices, lower power consumption, higher integration, and better compatibility with CMOS technology, and can realize practical logic units with high performance and low power consumption.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a logic gate circuit of hybrid memristor CMOS is provided, including a series MOSFET transistor voltage divider network and a memristor voltage divider network. The power supply terminal of the MOSFET transistor voltage divider network is used to connect to a single power supply VDD. The input terminals of the MOSFET transistor voltage divider network are respectively used to connect to a first input signal and a second input signal. The output terminal of the memristor voltage divider network is used as the output terminal of the logic gate circuit. Among them, the balanced three-value logic -1 of the logic gate circuit corresponds to a voltage level of -VDD, the balanced three-value logic 0 of the logic gate circuit corresponds to a voltage level of 0, and the balanced three-value logic 1 of the logic gate circuit corresponds to a voltage level of VDD.

[0006] In one embodiment, the logic gate is a balanced ternary NAND gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Parallel connection, transistor T n1 and transistor T n2 Series connection, transistor T p1 The drain of transistor T is used to connect to a single power supply VDD. n2 The source of transistor T is used to connect to a single power supply -VDD. p2 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of the balanced ternary NAND gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

[0007] In one embodiment, the logic gate is a balanced ternary NOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Series connection, transistor T n1 and transistor T n2 Parallel connection, transistor T p2 The drain of transistor T is used to connect to a single power supply VDD. n2 The source of transistor T is used to connect to a single power supply -VDD. p1 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n2 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced ternary OR gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

[0008] In one embodiment, the logic gate is a balanced ternary XOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 P-type MOSFET transistor T p3 P-type MOSFET transistor T p4 N-type MOSFET transistor T n1 N-type MOSFET transistor T n2 N-type MOSFET transistor T n3 and N-type MOSFET transistor T n4 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Series connection, transistor T p3 With transistor T p4 Series connection, transistor T n1 and transistor T n2 Series connection, transistor T n3 and transistor T n4 Series connection, transistor T p2 The drain and transistor T p4 The drains of both transistors are used to connect to a single power supply VDD. n2 The source and transistor T n4 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p1 The source and transistor T p3The sources of all transistors are connected to transistor T via a memristor voltage divider network. n1 The drain of the transistor T n3 Drain-connected transistor T n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced ternary XOR gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the inverted signal of the second input signal. p3 The gate of transistor T is used to receive the inverted signal of the first input signal. p4 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate of transistor T is used to receive the second input signal. n3 The gate of transistor T is used to receive the inverted signal of the first input signal. n4 The gate is used to receive the inverted signal of the second input signal.

[0009] In one embodiment, the logic gate is a balanced three-valued XOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 P-type MOSFET transistor T p3 P-type MOSFET transistor T p4 N-type MOSFET transistor T n1 N-type MOSFET transistor T n2 N-type MOSFET transistor T n3 and N-type MOSFET transistor T n4 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Series connection, transistor T p3 With transistor T p4 Series connection, transistor T n1 and transistor T n2 Series connection, transistor T n3 and transistor T n4 Series connection, transistor T p2 The drain and transistor T p4 The drains of both transistors are used to connect to a single power supply VDD. n2 The source and transistor T n4 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p1The source and transistor T p3 The sources of all transistors are connected to transistor T via a memristor voltage divider network. n1 The drain of the transistor T n3 Drain-connected transistor T n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced three-valued XNOR gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. p3 The gate of transistor T is used to receive the inverted signal of the first input signal. p4 The gate of transistor T is used to receive the inverted signal of the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate of transistor T is used to receive the inverted signal of the second input signal. n3 The gate of transistor T is used to receive the inverted signal of the first input signal. n4 The gate is used to receive the second input signal.

[0010] In one embodiment, the logic gate is a balanced ternary non-uniform gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Parallel connection, transistor T n1 and transistor T n2 Parallel connection, transistor T p1 The drain and transistor T p2 The drains of both transistors are used to connect to a single power supply VDD. n1 The source and transistor T n2 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p2 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n2 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of the balanced ternary non-uniform gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

[0011] In one embodiment, the memristor in the logic gate circuit adopts the ASU model, with a low impedance state of 10kΩ and a high impedance state of 3MΩ.

[0012] In one embodiment, the MOSFET transistors in the logic gate circuit adopt a 65nm BSIM model, with a channel length of 65nm and a width of 65nm.

[0013] In one embodiment, the power supply voltage of the single power supply VDD is 0.5V, and the voltages corresponding to the logic states of the logic gate circuits are as follows: The voltage level corresponding to -1 in balanced ternary logic is -0.5V, the voltage level corresponding to 0 in balanced ternary logic is 0V, and the voltage level corresponding to +1 in balanced ternary logic is 0.5V.

[0014] On the other hand, a complex logic circuit is also provided, including at least one of an encoder, a decoder, a half-adder, and a multiplier constructed using the logic gate circuit of the aforementioned hybrid memristor CMOS.

[0015] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned hybrid memristor CMOS logic gates and complex logic circuits integrate memristors with the CMOS back-end, without occupying additional substrate area, and achieve a data density 1.58 times higher than traditional CMOS binary circuits. Employing a complementary CMOS circuit structure significantly reduces static power consumption, solves the impedance matching problem encountered when using two memristors in series to form a TAND or TOR gate, suppresses signal attenuation during cascading, and ensures reliable transmission of multi-level logic chains. Compared to traditional designs, this results in fewer devices, lower power consumption, and higher integration density, realizing a high-performance and low-power practical logic unit. Using standard CMOS processes and back-end integrated memristors, memristor fabrication requires no additional mask layer and can be directly integrated into existing integrated circuit production lines, reducing industrialization costs. It is compatible with existing EDA (Electronic Design Automation) tools and has the potential for practical tape-out. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1The diagram below shows a circuit diagram of a balanced ternary NAND gate in one embodiment, wherein... Figure 1 (a) is a schematic diagram of the TNAND symbol. Figure 1 (b) is the circuit structure diagram of TNAND; Figure 2 This is a circuit diagram of a balanced ternary NOR gate (TNOR) in one embodiment, wherein, Figure 2 (a) is a schematic diagram of the TNOR symbol. Figure 2 (b) is the circuit structure diagram of TNOR; Figure 3 The diagram below shows a circuit diagram of a balanced ternary XOR gate (TXOR) in one embodiment, wherein... Figure 3 (a) is a schematic diagram of the TXOR symbol. Figure 3 (b) is the circuit diagram of TXOR; Figure 4 The diagram below shows a circuit diagram of a balanced ternary XNOR gate (TXNOR) in one embodiment, wherein... Figure 4 (a) is a schematic diagram of the TXNOR symbol. Figure 4 (b) is the circuit structure diagram of TXNOR; Figure 5 The diagram below shows a circuit diagram of a balanced ternary non-uniform gate (NCONS) in one embodiment, wherein... Figure 5 (a) is a schematic diagram of the NCONS symbol. Figure 5 (b) is the circuit structure diagram of NCONS; Figure 6 The following is a transient simulation waveform diagram of a balanced ternary NAND gate, a balanced ternary NOR gate, and a balanced ternary non-uniform gate in one embodiment. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0019] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0020] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] In one embodiment, such as Figures 1 to 5 As shown, a hybrid memristor CMOS logic gate circuit is provided, including a series-connected MOSFET transistor voltage divider network and a memristor voltage divider network. The power supply terminal of the MOSFET transistor voltage divider network is used to connect to a single power supply VDD, and the input terminals of the MOSFET transistor voltage divider network are respectively used to connect to a first input signal (i.e., V in1 ) and the second input signal (i.e. V in2 The output of the memristor voltage divider network is used as the output of the logic gate circuit. The balanced ternary logic -1 corresponds to a voltage level of -VDD, the balanced ternary logic 0 corresponds to a voltage level of 0, and the balanced ternary logic 1 corresponds to a voltage level of VDD.

[0022] It is understood that the core design principle of this embodiment is: based on the balanced three-valued logic {-1,0,+1} corresponding to the voltage levels {-VDD,0,VDD}, a hybrid integrated architecture of memristor voltage divider network and MOSFET transistor voltage divider network is adopted. In this way, the logic state representation of the logic gate circuit can be realized by utilizing the resistive switching characteristics of the memristor, and the signal driving and noise suppression can be optimized by the switching control of the MOSFET.

[0023] The aforementioned hybrid memristor CMOS logic gate circuit integrates memristors with the CMOS back-end, without occupying additional substrate area, and achieves a data density 1.58 times higher than traditional CMOS binary circuits. Employing a complementary CMOS circuit structure significantly reduces static power consumption, solves the impedance matching problem encountered when using two memristors in series to form a TAND or TOR gate, suppresses signal attenuation during cascading, and ensures reliable transmission of multi-level logic chains. Compared to traditional designs, it reduces the number of devices, lowers power consumption, and increases integration density, realizing a high-performance and low-power practical logic unit. Using standard CMOS technology and back-end integrated memristors, memristor fabrication requires no additional mask layer and can be directly integrated into existing integrated circuit production lines, reducing industrialization costs. It is compatible with existing EDA (Electronic Design Automation) tools and has the potential for practical tape-out.

[0024] In one embodiment, the logic gate is a balanced ternary NAND gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network consists of memristors X1 and X2 connected in series. Transistor T p1 With transistor T p2 Parallel connection, transistor T n1 and transistor T n2 Series connection, transistor T p1 The drain of transistor T is used to connect to a single power supply VDD. n2 The source of transistor T is used to connect to a single power supply -VDD. p2 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced ternary NAND gate (i.e., V out Transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

[0025] It is understandable that the circuit symbol and circuit structure of a balanced ternary NAND gate are as follows: Figure 1 (a) and Figure 1As shown in (b), by adopting the hybrid integrated architecture of memristor voltage divider network and MOSFET transistor voltage divider network in this embodiment, the logic state representation of the logic gate TNAND can be realized by utilizing the resistive switching characteristics of memristors.

[0026] In one embodiment, the logic gate is a balanced ternary NOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network consists of memristors X1 and X2 connected in series. Transistor T p1 With transistor T p2 Series connection, transistor T n1 and transistor T n2 Parallel connection, transistor T p2 The drain of transistor T is used to connect to a single power supply VDD. n2 The source of transistor T is used to connect to a single power supply -VDD. p1 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n2 The drain of transistor T, and the tap between memristors X1 and X2, serve as the output of a balanced ternary NOR gate. p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

[0027] It is understandable that the circuit symbol and circuit structure of a balanced three-valued NOR gate (TNOR) are as follows: Figure 2 (a) and Figure 2 As shown in (b), by adopting the hybrid integrated architecture of memristor voltage divider network and MOSFET transistor voltage divider network in this embodiment, the logic state characterization of the logic gate TNOR can be realized by utilizing the resistive switching characteristics of the memristor.

[0028] In one embodiment, the logic gate is a balanced ternary XOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 P-type MOSFET transistor T p3 P-type MOSFET transistor T p4 N-type MOSFET transistor T n1N-type MOSFET transistor T n2 N-type MOSFET transistor T n3 and N-type MOSFET transistor T n4 The memristor voltage divider network consists of memristors X1 and X2 connected in series. Transistor T p1 With transistor T p2 Series connection, transistor T p3 With transistor T p4 Series connection, transistor T n1 and transistor T n2 Series connection, transistor T n3 and transistor T n4 Series connection, transistor T p2 The drain and transistor T p4 The drains of both transistors are used to connect to a single power supply VDD. n2 The source and transistor T n4 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p1 The source and transistor T p3 The sources of all transistors are connected to transistor T via a memristor voltage divider network. n1 The drain of the transistor T n3 Drain-connected transistor T n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced ternary XOR gate.

[0029] transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate is used to receive the inverted signal of the second input signal (i.e., ), transistor T p3 The gate is used to receive the inverted signal of the first input signal (i.e., ), transistor T p4 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate of transistor T is used to receive the second input signal. n3 The gate of transistor T is used to receive the inverted signal of the first input signal. n4 The gate is used to receive the inverted signal of the second input signal.

[0030] It is understandable that the circuit symbol and circuit structure of a balanced ternary XOR gate (TXOR) are as follows: Figure 3 (a) and Figure 3As shown in (b), by adopting the hybrid integrated architecture of memristor voltage divider network and MOSFET transistor voltage divider network in this embodiment, the logic state representation of the logic gate TXOR can be realized by utilizing the resistive switching characteristics of the memristor.

[0031] In one embodiment, the logic gate is a balanced three-valued XOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 P-type MOSFET transistor T p3 P-type MOSFET transistor T p4 N-type MOSFET transistor T n1 N-type MOSFET transistor T n2 N-type MOSFET transistor T n3 and N-type MOSFET transistor T n4 The memristor voltage divider network consists of memristors X1 and X2 connected in series.

[0032] transistor T p1 With transistor T p2 Series connection, transistor T p3 With transistor T p4 Series connection, transistor T n1 and transistor T n2 Series connection, transistor T n3 and transistor T n4 Series connection, transistor T p2 The drain and transistor T p4 The drains of both transistors are used to connect to a single power supply VDD. n2 The source and transistor T n4 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p1 The source and transistor T p3 The sources of all transistors are connected to transistor T via a memristor voltage divider network. n1 The drain of the transistor T n3 Drain-connected transistor T n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced three-valued XNOR gate.

[0033] transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. p3 The gate of transistor T is used to receive the inverted signal of the first input signal. p4 The gate of transistor T is used to receive the inverted signal of the second input signal. n1The gate of transistor T is used to receive the first input signal. n2 The gate of transistor T is used to receive the inverted signal of the second input signal. n3 The gate of transistor T is used to receive the inverted signal of the first input signal. n4 The gate is used to receive the second input signal.

[0034] It is understandable that the circuit symbol and circuit structure of a balanced three-valued XNOR gate (TXNOR) are as follows: Figure 4 (a) and Figure 4 As shown in (b), by adopting the hybrid integrated architecture of memristor voltage divider network and MOSFET transistor voltage divider network in this embodiment, the logic state characterization of the logic gate TXNOR can be realized by utilizing the resistive switching characteristics of memristor.

[0035] In one embodiment, the logic gate is a balanced ternary non-uniform gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network consists of memristors X1 and X2 connected in series. Transistor T p1 With transistor T p2 Parallel connection, transistor T n1 and transistor T n2 Parallel connection, transistor T p1 The drain and transistor T p2 The drains of both transistors are used to connect to a single power supply VDD. n1 The source and transistor T n2 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p2 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n2 The drain of transistor T, and the tap between memristors X1 and X2, serve as the output of a balanced ternary non-uniform gate. p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

[0036] It is understandable that the circuit symbol and circuit structure of a balanced ternary non-uniform gate (NCONS) are as follows: Figure 5 (a) and Figure 5As shown in (b), by adopting the hybrid integrated architecture of memristor voltage divider network and MOSFET transistor voltage divider network in this embodiment, the logic state characterization of logic gate NCONS can be realized by utilizing the resistive switching characteristics of memristor.

[0037] It should be noted that in the above-mentioned balanced three-value NAND gate (TNAND), balanced three-value NOR gate (TNOR), balanced three-value XOR gate (TXOR), balanced three-value XNOR gate (TXNOR), and balanced three-value non-uniform gate (NCONS), the absolute values ​​of the voltage threshold values ​​of the N-type MOSFET transistor (i.e., NMOS) and the P-type MOSFET transistor (i.e., PMOS) are all lower than VDD. For the devices used in the logic gate circuits of the above embodiments, devices with the same reference numerals indicate the same devices used in different logic gate circuits.

[0038] All the device units in the above logic gate circuits are powered by a single power supply (VDD) to avoid the design complexity caused by additional voltage sources. The truth table of balanced ternary logic is shown in Table 1: Table 1

[0039] Transient simulation waveforms of balanced ternary NAND gates (TNAND), balanced ternary NOR gates (TNOR), and balanced ternary non-uniform gates (NCONS) are shown below. Figure 6 As shown, v(n_vin1) represents V in1 Terminal voltage in V, v(n_vin2) represents V. in2 Terminal voltage in V, v(n_vout) represents V out Terminal voltage, in volts (V).

[0040] In one embodiment, the memristor in the logic gate circuit adopts the ASU model, with a low impedance state of 10kΩ and a high impedance state of 3MΩ.

[0041] It is understood that, in this embodiment, for the device model and parameter selection of the logic gate circuit of the above-mentioned hybrid memristor CMOS, the memristor can be designed using the ASU model, with a low resistance state (LRS) of 10kΩ and a high resistance state (HRS) of 3MΩ. The ASU model is an existing threshold bipolar memristor model for SPICE simulation, suitable for modeling metal oxide RRAM devices, and can accurately characterize the given resistance state switching characteristics of LRS 10kΩ and HRS 3MΩ.

[0042] In one embodiment, the MOSFET transistors in the logic gate circuit adopt a 65nm BSIM model, with a channel length of 65nm and a width of 65nm.

[0043] It is understood that, in this embodiment, for the device model and parameter selection of the logic gate circuit of the above-mentioned hybrid memristor CMOS, the MOSFET transistor can adopt a 65nm BSIM model with a channel length of 65nm and a width of 65nm. The BSIM model is an existing MOSFET simulation model, such as, but not limited to, third-generation or fourth-generation MOSFET simulation models, applied to the modeling and circuit simulation of CMOS process semiconductor devices. The model can support DC, transient and AC analysis, and has the technical characteristics of accuracy and scalability, which can meet the device modeling requirements of nanometer-level process nodes.

[0044] In one embodiment, the power supply voltage of the single power supply VDD is 0.5V, and the voltages corresponding to the logic states of the logic gate circuits are as follows: the voltage level corresponding to the balanced three-valued logic -1 is -0.5V, the voltage level corresponding to the balanced three-valued logic 0 is 0V, and the voltage level corresponding to the balanced three-valued logic +1 is 0.5V.

[0045] It is understood that, in this embodiment, for the power supply and logic state design of the logic gate circuit of the above-mentioned hybrid memristor CMOS, the power supply voltage can be selected as VDD=0.5V, and the logic state corresponding voltages are: -1→-0.5V, 0→0V and +1→0.5V, so as to achieve more flexible and fine logic state representation through the resistive switching characteristics of memristors, and further optimize noise suppression through low voltage design.

[0046] In one embodiment, a complex logic circuit is also provided, including at least one of an encoder, a decoder, a half-adder, and a multiplier constructed using the logic gate circuits of the aforementioned hybrid memristor CMOS.

[0047] Each circuit module in the aforementioned complex logic circuit can be a corresponding module circuit existing in the field. The logic gate circuit of the aforementioned hybrid memristor CMOS can be used to replace the original corresponding logic gates, thereby building a new complex logic circuit and achieving a comprehensive improvement in circuit performance.

[0048] The aforementioned complex logic circuits are constructed using hybrid memristor CMOS logic gates, resulting in a 1.58-fold increase in data density compared to traditional CMOS binary circuits. This effectively suppresses signal attenuation during cascading and ensures reliable transmission across multi-level logic chains. Complex logic circuits such as encoders, decoders, half-adders, and multipliers are implemented through basic unit combinations, combining non-volatile storage with logical operation capabilities, making them suitable for various application scenarios such as in-memory computing and neuromorphic computing. Balanced ternary encoding simplifies the carry logic of adders, and multipliers do not require carry chains, significantly reducing the latency and power consumption of complex arithmetic circuits. This makes them suitable for the design of artificial intelligence accelerators and high-density arithmetic logic units (ALUs).

[0049] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A logic gate circuit for hybrid memristor CMOS, characterized in that, It includes a series-connected MOSFET transistor voltage divider network and a memristor voltage divider network. The power supply terminal of the MOSFET transistor voltage divider network is used to connect to a single power supply VDD. The input terminals of the MOSFET transistor voltage divider network are used to connect to the first input signal and the second input signal, respectively. The output terminal of the memristor voltage divider network serves as the output terminal of the logic gate circuit. Among them, the voltage level corresponding to the balanced three-value logic -1 of the logic gate circuit is -VDD, the voltage level corresponding to the balanced three-value logic 0 of the logic gate circuit is 0, and the voltage level corresponding to the balanced three-value logic 1 of the logic gate circuit is VDD.

2. The logic gate circuit of the hybrid memristor CMOS according to claim 1, characterized in that, The logic gate circuit is a balanced three-valued NAND gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Parallel connection, transistor T n1 and transistor T n2 Series connection, transistor T p1 The drain of transistor T is used to connect to a single power supply VDD. n2 The source of transistor T is used to connect to a single power supply -VDD. p2 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of the balanced ternary NAND gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

3. The logic gate circuit of the hybrid memristor CMOS according to claim 1, characterized in that, The logic gate circuit is a balanced three-valued NOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Series connection, transistor T n1 and transistor T n2 Parallel connection, transistor T p2 The drain of transistor T is used to connect to a single power supply VDD. n2 The source of transistor T is used to connect to a single power supply -VDD. p1 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n2 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced ternary OR gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

4. The logic gate circuit of hybrid memristor CMOS according to claim 1, characterized in that, The logic gate circuit is a balanced three-valued XOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 P-type MOSFET transistor T p3 P-type MOSFET transistor T p4 N-type MOSFET transistor T n1 N-type MOSFET transistor T n2 N-type MOSFET transistor T n3 and N-type MOSFET transistor T n4 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Series connection, transistor T p3 With transistor T p4 Series connection, transistor T n1 and transistor T n2 Series connection, transistor T n3 and transistor T n4 Series connection, transistor T p2 The drain and transistor T p4 The drains of both transistors are used to connect to a single power supply VDD. n2 The source and transistor T n4 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p1 The source and transistor T p3 The sources of all transistors are connected to transistor T via a memristor voltage divider network. n1 The drain of the transistor T n3 Drain-connected transistor T n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced ternary XOR gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the inverted signal of the second input signal. p3 The gate of transistor T is used to receive the inverted signal of the first input signal. p4 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate of transistor T is used to receive the second input signal. n3 The gate of transistor T is used to receive the inverted signal of the first input signal. n4 The gate is used to receive the inverted signal of the second input signal.

5. The logic gate circuit of the hybrid memristor CMOS according to claim 1, characterized in that, The logic gate circuit is a balanced three-valued XOR gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 P-type MOSFET transistor T p3 P-type MOSFET transistor T p4 N-type MOSFET transistor T n1 N-type MOSFET transistor T n2 N-type MOSFET transistor T n3 and N-type MOSFET transistor T n4 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Series connection, transistor T p3 With transistor T p4 Series connection, transistor T n1 and transistor T n2 Series connection, transistor T n3 and transistor T n4 Series connection, transistor T p2 The drain and transistor T p4 The drains of both transistors are used to connect to a single power supply VDD. n2 The source and transistor T n4 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p1 The source and transistor T p3 The sources of all transistors are connected to transistor T via a memristor voltage divider network. n1 The drain of the transistor T n3 Drain-connected transistor T n1 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of a balanced three-valued XNOR gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. p3 The gate of transistor T is used to receive the inverted signal of the first input signal. p4 The gate of transistor T is used to receive the inverted signal of the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate of transistor T is used to receive the inverted signal of the second input signal. n3 The gate of transistor T is used to receive the inverted signal of the first input signal. n4 The gate is used to receive the second input signal.

6. The logic gate circuit of the hybrid memristor CMOS according to claim 1, characterized in that, The logic gate circuit is a balanced three-valued non-uniform gate, and the MOSFET transistor voltage divider network includes P-type MOSFET transistors T. p1 P-type MOSFET transistor T p2 N-type MOSFET transistor T n1 and N-type MOSFET transistor T n2 The memristor voltage divider network includes memristors X1 and X2 connected in series; transistor T p1 With transistor T p2 Parallel connection, transistor T n1 and transistor T n2 Parallel connection, transistor T p1 The drain and transistor T p2 The drains of both transistors are used to connect to a single power supply VDD. n1 The source and transistor T n2 The sources of both transistors are used to connect to a single power supply -VDD, transistor T p2 The source of the transistor is connected to the transistor T via a memristor voltage divider network. n2 The drain of the memristor, and the tap between memristor X1 and memristor X2, serve as the output of the balanced ternary non-uniform gate. transistor T p1 The gate of transistor T is used to receive the first input signal. p2 The gate of transistor T is used to receive the second input signal. n1 The gate of transistor T is used to receive the first input signal. n2 The gate is used to receive the second input signal.

7. The logic gate circuit of hybrid memristor CMOS according to any one of claims 1 to 6, characterized in that, The memristors in the logic gate circuit adopt the ASU model, with a low impedance of 10kΩ and a high impedance of 3MΩ.

8. The logic gate circuit of the hybrid memristor CMOS according to claim 7, characterized in that, The MOSFET transistors in the logic gate circuit adopt the 65nm BSIM model, with a channel length of 65nm and a width of 65nm.

9. The logic gate circuit of the hybrid memristor CMOS according to claim 7, characterized in that, The power supply voltage of the single power supply VDD is 0.5V. The voltages corresponding to the logic states of the logic gate circuits are as follows: The voltage level corresponding to -1 in balanced ternary logic is -0.5V, the voltage level corresponding to 0 in balanced ternary logic is 0V, and the voltage level corresponding to +1 in balanced ternary logic is 0.5V.

10. A complex logic circuit, characterized in that, Includes at least one of an encoder, decoder, half-adder, and multiplier constructed using logic gates of the hybrid memristor CMOS as described in any one of claims 1 to 9.

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