Alternating-current coupling broadband high-performance flip input buffer circuit applied to high-speed high-precision analog-to-digital converter

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to an alternating-current coupling broadband high-performance flip input buffer. The alternating-current coupling broadband high-performance flip input buffer mainly comprises an alternating-current coupling flip source follower core module, a nonlinear parasitic capacitance compensation module, a bias network and a current mirror. The alternating current coupling flip source follower core module mainly comprises a main source follower tube for realizing a source follower basic function, a CASCODE tube for improving the overall linearity of a circuit, and a current mirror tube for providing main path current and constructing a negative feedback loop with a coupling capacitor and a coupling resistor. The output impedance of the input buffer under the concern frequency can be effectively reduced, the wider bandwidth and better linearity are realized, and meanwhile, the input signal range is greatly widened; the nonlinear stray capacitance compensation module compensates the nonlinear stray capacitance of a main source follower tube through an accumulation type MOS varactor, and the overall linearity is further improved; the bias network and the current mirror provide bias which is not affected by process temperature change for the core module, provide wider drain-source voltage and realize better linearity.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to an AC-coupled broadband high-performance flip-flop input buffer. Background Technology

[0002] In high-speed, high-precision applications, the input of an analog-to-digital converter (ADC) needs to adapt to increasingly higher input signal frequencies. This often necessitates an input buffer to isolate the ADC input from the sampling network, preventing charge injection from the sampling switch and kickback noise from the sampling capacitor, thus ensuring signal transmission integrity. Simultaneously, the input buffer provides a high input impedance and a low output impedance, enabling better driving by the signal source and better driving of the sampling network.

[0003] In existing technologies, to improve the linearity of input buffers, the industry has adopted techniques such as emitter degradation feedforward attenuation, cascaded structures, and source followers with feedforward compensation. Among these, source followers with feedforward compensation offer the advantage of low power consumption, but the additional cascaded components raise the output common-mode voltage, and the compensation capacitor not only increases the chip area but also increases the signal source load and limits the input bandwidth. Traditional flip-flop source followers achieve high linearity and low output impedance through internal parallel negative feedback, but their DC-coupled feedback method results in an extremely narrow input signal range, which cannot meet the application requirements of high-speed analog-to-digital converters.

[0004] In summary, developing an input buffer that combines high linearity, low output impedance, wide signal range, wide bandwidth, and the ability to compensate for parasitic capacitance nonlinearity has become a pressing technical problem to be solved in the field of high-speed, high-precision analog-to-digital converters. Summary of the Invention

[0005] To address the aforementioned issues of limited input bandwidth, narrow input signal range, and overall performance limitations in meeting the requirements of analog-to-digital converters in high-speed and high-precision applications, this invention proposes an AC-coupled broadband high-performance flip-flop input buffer. This buffer achieves the technical goals of high linearity, low output impedance, and a wide input signal range. Furthermore, the linearity of the buffer is further improved through parasitic capacitance compensation design.

[0006] The AC-coupled broadband high-performance flip-type input buffer circuit mainly includes an AC-coupled flip-type source follower core module, a nonlinear parasitic capacitance compensation module, a bias network, and a current mirror. The AC-coupled flip-type source follower core module includes a main source follower transistor, a Cascode transistor, and a flip-type negative feedback loop implemented by a current mirror transistor, feedback capacitors, and resistors. The nonlinear parasitic capacitance compensation module includes an accumulator-type MOS varactor transistor to compensate for input nonlinearity. The bias network and current mirror provide appropriate voltage bias and main circuit current for the source follower body to ensure the correct DC operating point of the source follower.

[0007] The core module of the AC-coupled flip-over source follower mainly includes a second resistor, a third resistor, a fourth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a coupling capacitor CFT, and a feedback capacitor CFB. The first NMOS transistor acts as the main source follower to ensure basic functionality. Its gate is connected to the input signal, and its source is connected to the output signal and the subsequent load, providing a voltage drop of VGS from input to output. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor. Its gate is connected to the sixth NMOS transistor in the current mirror circuit through the second resistor to determine the main current. Simultaneously, the gate is connected to one end of the fourth resistor through the feedback capacitor CFB, forming a negative feedback network. The source of the third NMOS transistor is connected to the drain of the first NMOS transistor to form a CASCODE structure. Its gate is connected to the gate of the first NMOS transistor through the coupling capacitor CFT, making it follow the input and ensuring that the drain-source voltage of the first NMOS transistor remains relatively constant, avoiding nonlinearity issues caused by the device. Its gate is also connected to the bias circuit through the third resistor to obtain the correct DC bias.

[0008] The nonlinear parasitic capacitance compensation module includes an accumulator MOS varactor (CVAR) and a first resistor. The gate of the accumulator MOS is connected to the gate of the first NMOS transistor in the core module. After the source and drain are shorted, it is connected to a fixed level VC through a resistor. Its substrate is grounded, so that the variable capacitor CSDB compensates for the nonlinear parasitic capacitance of the first NMOS transistor, thereby compensating for the nonlinearity of the input terminal.

[0009] The bias network and current mirror circuit mainly includes a bandgap reference voltage VBG, an operational amplifier, a fifth resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The bandgap reference voltage VBG is externally provided and connected to the positive input terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the gate of the seventh NMOS transistor, and the negative input terminal is connected to the source terminal of the seventh NMOS transistor, forming a negative feedback loop that clamps the source voltage of the seventh NMOS transistor at the bandgap reference voltage VBG. The voltage at the reference point and the fifth resistor together form the reference current; the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor constitute a current mirror to reflect the reference current; the fifth NMOS transistor is connected as a diode, and its drain voltage is connected to the gate of the third NMOS transistor in the source follower body to provide it with the correct DC bias; the fourth NMOS transistor is connected as a diode to provide the correct DC bias for the current branch; the sixth NMOS transistor is connected as a diode, and its gate terminal is connected to the gate of the second NMOS transistor in the source follower body through the second resistor, forming a current mirror structure to provide current to the source follower body.

[0010] The operational amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a Miller capacitor Cc, and a zero-adjustment resistor Rz. The sources of the first, fourth, and fifth PMOS transistors are all connected to the power supply voltage. The gates of the first and fourth PMOS transistors are connected to the gate of the fifth PMOS transistor to form a current mirror, providing the main current for the first and second stages of the operational amplifier. The drain of the fifth PMOS transistor is connected to an externally provided reference voltage. The second and third PMOS transistors are connected to the source of the first PMOS transistor, and their gates are connected to the positive and negative input terminals, respectively. The first NMOS transistor is connected as a diode, and its gate is connected to the second NMOS transistor as the drain load of the second and third PMOS transistors. The drain of the second NMOS transistor is the output terminal of the first stage of the op-amp and is connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor serves as the single-ended output terminal of the entire op-amp. The Miller capacitor Cc and the zero-adjustment resistor Rz are connected in series between the output terminals of the first and second stages of the op-amp for overall Miller compensation.

[0011] The beneficial effects of this invention are as follows: It adopts an AC-coupled flip-type source follower architecture and constructs a feedback loop through a coupling capacitor, retaining the advantages of high linearity and low output impedance of traditional flip-type source followers, while significantly widening the input signal range; it sets an accumulator-type MOS varactor at the gate of the input MOS to compensate for the nonlinear parasitic capacitance of the input MOS, further improving the linearity of the buffer; and it combines low-threshold transistor selection, bandgap reference bias circuit, and baseboard sampling technology to achieve high reliability and wide bandwidth of the circuit. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the front-end function of the analog-to-digital converter applied to this invention.

[0013] Figure 2 This is a schematic diagram of the AC-coupled broadband high-performance flip-in input buffer circuit described in this invention.

[0014] Figure 3 This is a schematic diagram illustrating the principle of nonlinear parasitic capacitance compensation for the input tube in this invention.

[0015] Figure 4 This is a circuit diagram of the operational amplifier described in this invention. Detailed Implementation

[0016] The present invention will now be further described with reference to the accompanying drawings.

[0017] The basic application scenarios and functions of this invention are as follows: Figure 1As shown, in high-speed, high-precision analog-to-digital converter (ADC) applications, the input buffer, as the front-end circuit of the pipeline stage, isolates the ADC input from the back-end sampling network, reducing the impact of charge injection on the input from the subsequent kickback and sampling switches. Simultaneously, it provides high input impedance and low output impedance, enhancing the input's driving capability for the subsequent sampling network and reducing the overall distortion of the ADC. Linearity is one of the most important design parameters of the input buffer, limiting the linearity of the entire ADC. Its input / output signal range and bandwidth also determine the signal amplitude range and overall bandwidth of the ADC.

[0018] The AC-coupled broadband high-performance flip-in input buffer circuit structure of the present invention is as follows: Figure 2 As shown. Figure 2 The right-hand frame shows the core module of the AC-coupled flip-source follower. This circuit abandons the DC-coupled feedback method of traditional flip-source followers and adopts an AC-coupled feedback architecture: an auxiliary MOSFET, the third NMOS, is stacked on top of the first NMOS input MOSFET. The input signal is coupled to the gate of the third NMOS via a third resistor and a coupling capacitor CFT. The drain of the third NMOS is connected to the gate of the feedback MOSFET, the second NMOS, through an AC coupling capacitor CFB, forming a parallel negative feedback path equivalent to that of a traditional flip-source follower. This architecture retains the core advantage of traditional flip-source followers—the drain current of the first NMOS is provided by the current source, the first PMOS, and is independent of the signal current drawn by the load capacitor CL, achieving high linearity in driving the sampling capacitor of the analog-to-digital converter. At the same time, AC coupling frees the DC voltage of the drain of the third NMOS from the constraint of the gate-source voltage of the second NMOS, significantly widening the input signal range to 1.4Vpp, meeting the signal transmission requirements of high-speed, high-precision analog-to-digital converters. Furthermore, the inherent negative feedback of this architecture significantly reduces the output impedance of the input buffer at the frequency of interest, effectively mitigating bandwidth attenuation and crosstalk issues caused by parasitic capacitance at the back end of analog-to-digital converters with complex wiring configurations.

[0019] Figure 2 The box below the right-hand input terminal contains the nonlinear parasitic capacitance compensation module. This circuit uses a cumulant varactor (CVAR) at the gate of the first NMOS transistor in the input MOSFET to compensate for the nonlinear parasitic capacitance present in the first NMOS transistor. For example... Figure 3 As shown in (a), the first NMOS transistor in the actual circuit is a deep N-well NMOS transistor. The capacitances of the reverse-biased drain body and body DNW diodes DDB and DBN are nonlinear loads relative to the input. Therefore, when the input is set as shown... Figure 3(b) shows an accumulation-type MOS (also known as a varactor) CVAR, in which the capacitance between the source / drain short circuit and the substrate is a varactor capacitor. The substrate is grounded to ensure that the diode between the source / drain and the substrate is reverse biased. The source / drain is connected to a relatively low bias voltage VC through a first resistor, thereby ensuring that the device operates in the accumulation state. Its gate is connected to the input terminal. The size design and the adjustment of the bias VC can compensate for the nonlinear capacitance through the reverse capacitance change.

[0020] Figure 2 The left frame contains the bias network and current mirror module. The overall bias circuit current is determined by the leftmost branch. An external bandgap reference voltage VBG is provided, and the reference current is generated through the clamping of the operational amplifier and the fifth resistor. The operational amplifier structure used is as follows: Figure 4 As shown, this is a two-stage operational amplifier structure. The first stage is a standard five-transistor OTA (Optical Transistor Overload), and the second stage is a common-source amplifier. Miller compensation is used between stages to split the dominant and secondary poles of the operational amplifier, ensuring its stability. The fifth resistor is the same type as the fourth resistor in the core module, ensuring that the drain voltage of the third NMOS transistor in the core module is not affected by PVT (Programmable Voltage Transformation). The first, second, and third PMOS transistors form a proportional current mirror to provide bias voltage and bias current for the second and third NMOS transistors in the core module. The bias voltage can be precisely adjusted by changing the current source flowing through the NMOS transistor connected to the corresponding branch diode.

[0021] In summary, this invention is an AC-coupled broadband high-performance input buffer circuit that adopts an AC-coupled flip-flop source follower structure to achieve performance advantages such as high linearity, large input signal range, large bandwidth, and low output impedance. It can be widely used in the front end of future high-speed and high-precision analog-to-digital converters.

Claims

1. A high-performance AC-coupled broadband flip-in input buffer circuit applied at the front end of a high-speed, high-precision analog-to-digital converter, characterized in that, The system includes an AC-coupled flip-type source follower core module, a nonlinear parasitic capacitance compensation module, a bias network, and a current mirror. The AC-coupled flip-type source follower core module includes a main source follower transistor, a Cascode transistor, and a flip-type negative feedback loop implemented with a current mirror transistor, feedback capacitors, and resistors. The nonlinear parasitic capacitance compensation module includes an accumulator-type MOS varactor transistor to compensate for input nonlinearity. The bias network and current mirror provide appropriate voltage bias and main circuit current for the source follower body to ensure the correct DC operating point of the source follower.

2. The core module of the AC-coupled flip source follower as described in claim 1, characterized in that... The circuit includes a second resistor, a third resistor, a fourth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a coupling capacitor CFT, and a feedback capacitor CFB. The first NMOS transistor acts as the main source follower, ensuring basic functionality. Its gate is connected to the input signal, and its source is connected to the output signal and the subsequent load, providing a voltage drop of VGS from input to output. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor. Its gate is connected to the sixth NMOS transistor in the current mirror circuit through the second resistor to determine the main current. Simultaneously, its gate is connected to one end of the fourth resistor through the feedback capacitor CFB, forming a negative feedback network. The source of the third NMOS transistor is connected to the drain of the first NMOS transistor to form a CASCODE structure. Its gate is connected to the gate of the first NMOS transistor through the coupling capacitor CFT, making it follow the input and ensuring that the drain-source voltage of the first NMOS transistor remains relatively constant, avoiding nonlinearity issues caused by the device. Its gate is also connected to the bias circuit through the third resistor to obtain the correct DC bias.

3. The nonlinear parasitic capacitance compensation module as described in claim 1, characterized in that... Includes a cumulant MOSFET (CVAR) and a first resistor; In the core module of the accumulator MOS, the gate of the first NMOS transistor is connected to the source and drain. After the source and drain are shorted, the fixed level VC is connected through a resistor. Its substrate is grounded, so that the variable capacitor CSDB compensates for the nonlinear parasitic capacitance of the first NMOS, thereby compensating for the nonlinearity of the input.

4. The bias network and current mirror circuit as described in claim 2, characterized in that... The circuit includes a bandgap reference voltage VBG, an operational amplifier, a fifth resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The bandgap reference voltage VBG is externally provided and connected to the positive input of the operational amplifier. The output of the operational amplifier is connected to the gate of the seventh NMOS transistor, and the negative input is connected to the source of the seventh NMOS transistor, forming a negative feedback loop that clamps the source voltage of the seventh NMOS transistor at the bandgap reference voltage VBG. This clamping voltage, together with the fifth resistor, forms a reference current. The first, second, and third PMOS transistors form a current mirror to reflect the reference current. The fifth NMOS transistor is connected as a diode, and its drain voltage is connected to the gate of the third NMOS transistor in the source follower body, providing it with the correct DC bias. The fourth NMOS transistor is also connected as a diode, providing the correct DC bias for the current branch. The sixth NMOS transistor is also connected as a diode, and its gate is connected to the gate of the second NMOS transistor in the source follower body through a second resistor, forming a current mirror structure to provide current to the source follower body.

5. The operational amplifier as described in claim 4, characterized in that... The amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a Miller capacitor Cc, and a zero-adjustment resistor Rz. The sources of the first, fourth, and fifth PMOS transistors are all connected to the power supply voltage. The gates of the first and fourth PMOS transistors are connected to the gate of the fifth PMOS transistor to form a current mirror, providing the main current for the first and second stages of the operational amplifier. The drain of the fifth PMOS transistor is connected to an externally supplied reference current. The sources of the second and third PMOS transistors are both connected to the source of the first PMOS transistor, and their gates are connected to the positive and negative input terminals, respectively. The first NMOS transistor is connected as a diode, and its gate is connected to the second NMOS transistor as the drain load for the second and third PMOS transistors. The drain of the second NMOS transistor is the output terminal of the first stage of the operational amplifier and is connected to the gate of the third NMOS transistor, serving as the single-ended output terminal of the entire operational amplifier. The Miller capacitor Cc and the zero-adjustment resistor Rz are connected in series between the output terminals of the first and second stages of the operational amplifier for overall Miller compensation.

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