Frame aggregation-based fault-tolerant communication method for high-voltage cascade energy storage system

Abstract

The invention relates to a cascading energy storage communication technology, in particular to a high-voltage cascading energy storage system fault-tolerant communication method based on frame aggregation and a storage medium. The method comprises the following steps of: serially connecting and aggregating a control frame sent to a sub-controller by a main controller and control instruction frames sent to all subordinate unit bodies into an aggregation packet, and redundantly sending the aggregation packet; the aggregation packet is divided into a data packet and a synchronous packet; the sub-controller carries out three-level receiving caching and processing on the aggregated packet sent redundantly, and executes different logics on the data packet and the synchronous packet; wherein the main controller sends serial control information of each unit body to the sub-controller, which is called as high-speed downlink; and the sub-controller sends control information to each unit body, namely low-speed downlink. According to the invention, while stable operation of the system is ensured, efficient data transmission and an intelligent control strategy are realized so as to adapt to increasingly complex power system requirements.

Description

Technical Field

[0001] This invention relates to cascaded energy storage communication technology, specifically a fault-tolerant communication method for high-voltage cascaded energy storage systems based on frame aggregation. Background Technology

[0002] With the rapid development and widespread application of new energy technologies, high-voltage cascaded energy storage systems have become the mainstream topology in large-scale energy storage due to their ease of expansion and high voltage levels. In such systems, stable and reliable communication between the main controller and numerous power converter units (PCS) is crucial for the safe and efficient operation of the system. Traditional communication schemes typically employ one-to-one serial communication between the main controller and each PCS; however, as the system scales up and the number of PCS increases dramatically, the number of communication cables required from the main controller becomes enormous, leading to complex system wiring and high costs. Furthermore, the number of main controller ports becomes a bottleneck for system expansion, limiting the system's scalability.

[0003] To improve system scalability, some have proposed introducing a "sub-controller" communication architecture between the main controller and the unit cells, where the high-speed downlink between the main controller and the sub-controllers uses high-speed fiber optic communication. However, under high-voltage electromagnetic interference, if data packets are discarded due to CRC check failure, all unit cells under the corresponding sub-controller will lose control commands within the same control cycle. Furthermore, existing communication schemes based on this architecture lack deterministic timing constraints, which may negatively impact the overall system performance and stability. Summary of the Invention

[0004] To address the problems of existing communication architectures based on main controller-sub-controller-unit systems, this invention proposes a fault-tolerant communication method and storage based on frame aggregation for high-voltage cascaded energy storage systems. This method can achieve efficient data transmission and intelligent control strategies while ensuring stable system operation, thus adapting to the increasingly complex demands of power systems.

[0005] This invention proposes a fault-tolerant communication method for a high-voltage cascaded energy storage system based on frame aggregation. The communication architecture of the high-voltage cascaded energy storage system includes a main controller, sub-controllers, and unit cells. The fault-tolerant communication method includes the following steps: The control frames sent by the main controller to the sub-controller itself, as well as the control command frames sent to all subordinate units, are concatenated and aggregated into an aggregate packet, and the aggregate packet is sent redundantly; the aggregate packet is divided into data packets and synchronization packets; The sub-controller performs three-level receive buffering and processing on redundantly transmitted aggregated packets, and executes different logic on data packets and synchronization packets; In this process, the main controller sends serial control information from each unit to the sub-controllers, which is called high-speed downlink; the sub-controllers send control information to each unit, which is called low-speed downlink.

[0006] Preferably, the concatenation and aggregation into an aggregated package, and the redundant transmission of the aggregated package, specifically includes: At the start of a fixed control cycle, the main controller sends control instruction frames for all subordinate units to the sub-controllers, as well as control frames for the sub-controllers themselves; multiple control frames and control instruction frames are concatenated and aggregated into an aggregate packet; the data packet includes a frame header, timestamp, packet sequence number, sub-controller instructions, and control instructions for multiple units, and the synchronization packet includes a frame header, timestamp, packet sequence number, and sub-controller instructions; In the main controller, the same aggregated packet is repeatedly sent multiple times within a control cycle, with only the packet sequence number changing each time, and an idle packet is sent between the two transmissions of the aggregated packet; where the same aggregated packet refers to an aggregated packet with the same timestamp and instruction content; One control cycle consists of several system clock cycles.

[0007] Furthermore, in the main controller, the same aggregation packet is repeatedly sent three times in one control cycle; the sending sequence is: first send - first idle - second send - second idle - third send - third idle - synchronization packet - fourth idle - next control cycle.

[0008] Preferably, the sub-controller performs three-level receive buffering and processing on the redundantly transmitted aggregated packets, including: On the high-speed downlink of the main controller, the sub-controller continuously monitors the received aggregated packets and performs CRC verification on each received aggregated packet; After the verification is successful, the sub-controller determines whether the aggregated packet is a synchronization packet or a data packet based on the frame header of the aggregated packet, and executes different logic accordingly.

[0009] This invention also provides a storage medium storing computer instructions, which, when executed by a processor, implement the steps of the fault-tolerant communication method.

[0010] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention adopts a three-tier architecture of main controller-sub-controller-unit, and realizes communication between the main controller and sub-controllers through the high-speed Aurora 8B / 10B protocol, effectively improving the system's anti-interference capability. Even in environments with strong electromagnetic interference such as high voltage and high current, data packets can reliably transmit down, avoiding data loss and communication failures caused by electromagnetic interference, and greatly enhancing the system's reliability and stability.

[0011] 2. This invention features an ingenious design for the sub-controller, achieving triple fault tolerance through a CRC check and selection mechanism for three redundant data replicas. When all three data replicas of a unit fail the CRC check, the successfully executed instruction data cached in the previous control cycle is used as a degradation strategy to ensure that the unit will not lose control due to communication failure, further improving the system's fault tolerance and reliability.

[0012] 3. This invention introduces a receiving data buffer and timestamp synchronization mechanism in the sub-controllers, which effectively solves the problem of asynchronous receiving and execution times caused by differences in communication paths, ensuring synchronous communication and collaborative work between the sub-controllers, and avoiding problems such as large AC output harmonics in high-voltage cascaded energy storage systems caused by asynchrony.

[0013] 4. The communication method of the present invention adopts a fusion architecture of high-speed and low-speed links. Through reasonable frame aggregation and redundant transmission mechanisms, it effectively reduces the system wiring complexity and equipment cost, while solving the problem that the number of main controller ports becomes a bottleneck for system expansion, thus meeting the expansion needs of large-scale energy storage systems.

[0014] 5. The communication method of this invention has good maintainability and scalability. By reserving FPGA chip pads and fiber optic communication channels in the main controller, and selecting an appropriate number of chips and optical modules according to project requirements, and by adopting standardized communication protocols and modular architecture design, system maintenance and upgrades become more convenient, and it can quickly adapt to future technological developments and changes in market demands. Attached Figure Description

[0015] Figure 1 This is a topology diagram of high-speed communication between the main controller and the sub-controllers; Figure 2 This is a topology diagram of low-speed communication between the controller and its subordinate units; Figure 3 It is a logical timing diagram of data packets, idle packets, and synchronization packets in a single control cycle; Figure 4 It is a frame structure diagram of the data packet; Figure 5 This is a frame structure diagram of the synchronization packet; Figure 6 This is a flowchart of the high-speed downlink data processing in the controller. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto. Example

[0017] The technical terms and abbreviations involved in this invention include: Power Conversion System (PCS); Cyclic Redundancy Check (CRC); and Field Programmable Gate Array (FPGA).

[0018] The communication architecture of the high-voltage cascaded energy storage system involved in this invention includes a main controller, sub-controllers, and unit modules, with the physical layer connections of each module as follows: As shown. The FPGA chip on the main controller is used to generate control signals for the unit cells and to parse the status signals uploaded by the unit cells.

[0019] In general, the main controller has only one FPGA chip installed, configured with 12 high-speed fiber optic communication interfaces, each communicating with a sub-controller. When a high-voltage cascaded energy storage system has a high number of stages, the main controller can be expanded to two FPGA chips and 24 high-speed fiber optic communication interfaces. A pair of synchronization signals is designed between the two FPGA chips to synchronize the control information of the control system. The first FPGA chip is responsible for channels 00 to 11, and the second FPGA chip is responsible for channels 12 to 23. Channels 00 to 23 are respectively connected to sub-controllers 0 to 23.

[0020] like As shown, a sub-controller can connect to multiple units simultaneously, such as units 0 through 17. The sub-controller receives control signals from multiple units from the main controller, distributes them to each unit via optical fiber, and sends status signals of each unit to the main controller. In this invention, the main controller sending serial control information of each unit to the sub-controller is called high-speed downlink; the sub-controller sending serial status information of each unit to the main controller is called high-speed uplink; the sub-controller sending control information to each unit is called low-speed downlink; and each unit sending status information to the sub-controller is called low-speed uplink.

[0021] This invention provides a fault-tolerant communication method for a high-voltage cascaded energy storage system based on frame aggregation, comprising the following steps: S1, Downlink signals of the two FPGA chips in the synchronous main controller.

[0022] When the main controller is configured with two FPGA chips, after each FPGA chip is successfully initialized, it sends a reset success signal to the other FPGA chip.

[0023] After each FPGA chip detects the reset success signal of another FPGA chip, it performs a logical AND operation between its own reset success signal and the reset success signal of the other FPGA chip, and immediately starts the high-speed downlink signal transmission counter.

[0024] The transmit counter starts from 0, increments with each system clock cycle, and is reset to zero after one control cycle. In this embodiment, one control cycle is several (e.g., 550) system clock cycles.

[0025] S2. Frame aggregation and redundant transmission: The control frames sent by the main controller to the sub-controller itself, as well as the control command frames sent to all subordinate units, are concatenated and aggregated into an aggregated packet, and the aggregated packet is transmitted redundantly.

[0026] This step specifically includes: S21. Aggregate multiple frames sent by the main controller at high speed downlink to form an aggregated packet.

[0027] At the start of a fixed control cycle, the main controller sends control command frames for all subordinate units to the sub-controllers, as well as control frames to the sub-controllers themselves; multiple control frames and control command frames are concatenated and aggregated into a large high-speed downlink data packet, also called an aggregated packet.

[0028] The aggregate packet consists of various types of data frames, specifically including a frame header, timestamp, packet sequence number, sub-controller instructions, and control instructions for multiple unit bodies. The control instructions for multiple unit bodies are essentially the data for those multiple unit bodies, such as... Figure 3 , Figure 4 As shown. The logic timing and structure of a single control cycle are as follows. Figure 3 As shown. The aggregated packet can be divided into data packets and synchronization packets, and their frame structures are as follows: Figure 4 , Figure 5 As shown, the data packet includes a frame header, timestamp, packet sequence number, sub-controller instructions, and control instructions for multiple units. The synchronization packet includes a frame header, timestamp, packet sequence number, and sub-controller instructions.

[0029] S22, Redundant transmission of aggregated packets.

[0030] In the main controller, the same aggregated packet is repeatedly sent three times in one control cycle, with only the packet sequence number changing each time. An idle packet is sent between the two transmissions of the aggregated packet. The transmission sequence is: first transmission - first idle - second transmission - second idle - third transmission - third idle - synchronization packet - fourth idle - next control cycle. Here, the same aggregated packet refers to a high-speed downlink data packet with the same timestamp and instruction content.

[0031] S3, the sub-controller performs three-level receive buffering and processing on redundantly transmitted aggregated packets. Specifically, this includes: S31. In this embodiment, in the three-level communication architecture of the high-voltage cascaded energy storage system, the Aurora 8B / 10B protocol is used on the high-speed downlink of the main controller to realize communication between the main controller and the sub-controller. The sub-controller continuously listens to the received aggregate packets and performs CRC verification on each received aggregate packet.

[0032] S32. After the verification is passed, the sub-controller determines whether the aggregated packet is a synchronization packet or a data packet based on the frame header of the aggregated packet, and executes different logic accordingly.

[0033] S321. If it is a data packet and the packet sequence number is 1, clear all data in the receive data buffer, write the data to the corresponding position in the buffer according to the packet sequence number, and start the low-speed downlink counter to accumulate.

[0034] S322. If it is a data packet and the packet sequence number is 2, determine whether the timestamp of the current aggregate packet is equal to any timestamp in the received data buffer. If they are equal, it means that the aggregate packet with packet sequence number 1 was successfully received. Write the data into the corresponding position in the buffer according to the packet sequence number and keep the low-speed downlink counter accumulating. If they are not equal, it means that the aggregate packet with packet sequence number 1 failed to be received. Clear all the data in the received data buffer and write the data into the corresponding position in the buffer according to the packet sequence number, and start the low-speed downlink counter accumulating.

[0035] S323. If it is a data packet and the packet sequence number is 3, determine whether the timestamp of the current aggregate packet is equal to any timestamp in the received data buffer. If they are equal, it means that the aggregate packet with packet sequence number 1 or 2 has been successfully received. Write the data into the corresponding position in the buffer according to the packet sequence number and keep the low-speed downlink counter accumulating. If they are not equal, it means that the aggregate packets with packet sequence numbers 1 and 2 have both failed to be received. Clear all the data in the received data buffer and write the data into the corresponding position in the buffer according to the packet sequence number, and start the low-speed downlink counter accumulating.

[0036] S324. If it is a synchronous packet, it indicates that all sub-controllers should execute the low-speed downlink logic at this moment, triggering the low-speed downlink logic.

[0037] It should be noted that if the sub-controller fails to receive the synchronization packet during a control cycle, the low-speed downlink logic is also triggered when the low-speed downlink counter reaches the preset value. From the absolute time perspective of a control cycle, the execution time of the low-speed downlink counter is only one system clock cycle longer than the time from the start of the first data packet transmission to the end of the synchronization packet transmission.

[0038] After the low-speed downlink logic is successfully executed, the sub-controller returns to the state of continuously monitoring the aggregated packets.

[0039] S4. The sub-controller determines whether there is a situation where all three data packets fail to be received, but the synchronization packet is received successfully; if so, it executes the degradation protection logic.

[0040] This step specifically includes: S41. The sub-controller executes low-speed downlink logic, sending data that is the content of the received data buffer to ensure that the unit will not lose control due to communication failure.

[0041] S42. When the timestamp of the synchronization packet is different from the timestamp of the received data buffer, the high-speed downlink error counter is incremented by one; after the high-speed downlink error counter reaches the pre-designed value, the sub-controller sends a communication fault alarm to the main controller, and the main controller executes the relevant protection logic.

[0042] Based on the same inventive concept, this invention also proposes a storage medium storing computer instructions, which, when executed by a processor, implement steps S1-S4 of the fault-tolerant communication method described in this embodiment. The storage medium includes various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0043] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A fault-tolerant communication method for a high-voltage cascaded energy storage system based on frame aggregation, wherein the communication architecture of the high-voltage cascaded energy storage system includes a main controller, sub-controllers, and unit bodies, characterized in that, The fault-tolerant communication method includes the following steps: The control frames sent by the main controller to the sub-controller itself, as well as the control command frames sent to all subordinate units, are concatenated and aggregated into an aggregate packet, and the aggregate packet is sent redundantly; the aggregate packet is divided into data packets and synchronization packets; The sub-controller performs three-level receive buffering and processing on redundantly transmitted aggregated packets, and executes different logic on data packets and synchronization packets; In this process, the main controller sends serial control information from each unit to the sub-controllers, which is called high-speed downlink; the sub-controllers send control information to each unit, which is called low-speed downlink.

2. The fault-tolerant communication method according to claim 1, characterized in that, The process of concatenating and aggregating data into an aggregated packet, and then redundantly sending the aggregated packet, specifically includes: At the start of a fixed control cycle, the main controller sends control instruction frames for all subordinate units to the sub-controllers, as well as control frames for the sub-controllers themselves; multiple control frames and control instruction frames are concatenated and aggregated into an aggregate packet; the data packet includes a frame header, timestamp, packet sequence number, sub-controller instructions, and control instructions for multiple units, and the synchronization packet includes a frame header, timestamp, packet sequence number, and sub-controller instructions; In the main controller, the same aggregated packet is repeatedly sent multiple times within a control cycle, with only the packet sequence number changing each time, and an idle packet is sent between the two transmissions of the aggregated packet; where the same aggregated packet refers to an aggregated packet with the same timestamp and instruction content; One control cycle consists of several system clock cycles.

3. The fault-tolerant communication method according to claim 2, characterized in that, In the main controller, the same aggregation packet is repeatedly sent three times in one control cycle; the sending sequence is: first send - first idle - second send - second idle - third send - third idle - synchronization packet - fourth idle - next control cycle.

4. The fault-tolerant communication method according to claim 1, characterized in that, The sub-controller performs three-level receive buffering and processing on the redundantly transmitted aggregated packets, including: On the high-speed downlink of the main controller, the sub-controller continuously monitors the received aggregated packets and performs CRC verification on each received aggregated packet; After the verification is successful, the sub-controller determines whether the aggregated packet is a synchronization packet or a data packet based on the frame header of the aggregated packet, and executes different logic accordingly.

5. The fault-tolerant communication method according to claim 4, characterized in that, Execute different logics, specifically including: If it is a data packet and the packet sequence number is 1, clear all data in the receive data buffer, write the data to the corresponding position in the buffer according to the packet sequence number, and start the low-speed downlink counter to accumulate; If it is a data packet and the packet sequence number is 2, check if the timestamp of the current aggregated packet is equal to any timestamp in the received data buffer. If they are equal, it means that the aggregated packet with packet sequence number 1 was successfully received. Write the data to the corresponding position in the buffer according to the packet sequence number and keep the low-speed downlink counter accumulating. If they are not equal, it means that the aggregated packet with packet sequence number 1 failed to be received. Clear all the data in the received data buffer and write the data to the corresponding position in the buffer according to the packet sequence number, and start the low-speed downlink counter accumulating. If it is a data packet and the packet sequence number is 3, check if the timestamp of the current aggregated packet is equal to any timestamp in the received data buffer. If they are equal, it means that the aggregated packet with sequence number 1 or 2 was successfully received. Write the data into the corresponding position in the buffer according to the packet sequence number and keep the low-speed downlink counter accumulating. If they are not equal, it means that the aggregated packets with sequence numbers 1 and 2 failed to be received. Clear all the data in the received data buffer and write the data into the corresponding position in the buffer according to the packet sequence number, and start the low-speed downlink counter accumulating. If it is a synchronous packet, it triggers the low-speed downlink logic.

6. The fault-tolerant communication method according to claim 5, characterized in that, Executing different logic also includes: If the sub-controller fails to receive the synchronization packet during a control cycle, the low-speed downlink logic is triggered when the low-speed downlink counter reaches the preset value.

7. The fault-tolerant communication method according to claim 1, characterized in that, The fault-tolerant communication method further includes the following steps: The sub-controller determines whether there is a situation where all data packets fail to be received, but the synchronization packets are received successfully; if so, it executes the degradation protection logic.

8. The fault-tolerant communication method according to claim 7, characterized in that, The degradation protection logic is executed, specifically including: The sub-controller executes low-speed downlink logic, and the data sent is the content of the receive data buffer. When the timestamp of the synchronization packet differs from the timestamp of the received data buffer, the high-speed downlink error counter is incremented by one; after the high-speed downlink error counter reaches the pre-designed value, the sub-controller sends a communication fault alarm to the main controller, and the main controller executes the relevant protection logic.

9. The fault-tolerant communication method according to claim 1, characterized in that, The main controller is configured with two FPGA chips; the fault-tolerant communication method further includes the following steps before serially aggregating the data into an aggregated packet and redundantly sending the aggregated packet: Downlink signals of two FPGA chips in the synchronous main controller.

10. A storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed by the processor, they implement the steps of the fault-tolerant communication method according to any one of claims 1-9.

Images