Capacitor module detection circuit, chip and optical lens movement detection device

Abstract

The invention provides a capacitor module detection circuit, a chip and an optical lens movement detection device, and belongs to the technical field of integrated circuits. The capacitor module detection circuit comprises a charging and discharging circuit, a control circuit and a measuring circuit, the charging and discharging circuit charges and discharges a target capacitor, and the control circuit detects the capacitor voltage of the target capacitor in real time in the charging process of the target capacitor and compares the capacitor voltage with a preset voltage to output a first control signal and a second control signal with opposite levels. Therefore, the first capacitor and the second capacitor are alternately in a charging or discharging state. Because the time required for charging the target capacitor to the preset voltage is related to the capacitance value, the change of the capacitance values of the first capacitor and the second capacitor caused by the movement of the lens can be directly reflected as the change of the pulse width and duty ratio characterization information of the first control signal and the second control signal. And the measuring circuit extracts the first duty ratio characterization information and the second duty ratio characterization information and calculates the current position of the lens according to the first duty ratio characterization information and the second duty ratio characterization information.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a capacitor module detection circuit, a chip, and an optical lens movement detection device. Background Technology

[0002] With the improvement of imaging capabilities in smart terminals, camera modules commonly integrate functions such as autofocus (AF) and optical image stabilization (OIS). To achieve closed-loop control of lens position, the camera driver typically needs to detect and provide feedback on lens displacement in real time. In capacitive position detection schemes, a capacitor pair is often formed by setting up an electrode that moves with the lens and a fixed electrode. The capacitance value changes with the lens movement, thereby converting displacement information into changes in capacitance parameters and further estimating the lens position.

[0003] In related technologies, dedicated capacitance detection chips for OIS / AF camera drivers (such as Chipsemi's CHM9500) typically employ a charge-balance-based capacitance detection approach: based on the charge-balance formula, the target capacitor is charged and discharged, and the charge is transferred to a reference capacitor. The target capacitor is detected by sampling the voltage difference generated on the reference capacitor. However, this type of charge-balance scheme usually requires multiple reference voltage sources (e.g., Vref1, Vref2) and active switching / excitation control of these sources. It also requires a separate clock oscillator or controller to complete the charge transfer and balancing process. During the transition phase of charge balancing, the voltage change on the reference capacitor also needs to be sampled and judged, thus placing high demands on sampling accuracy and response speed. Furthermore, this scheme involves relatively many peripheral devices and internal functional units, which can easily lead to increased circuit implementation costs and an increase in error sources and cumulative errors.

[0004] Therefore, in the position detection of autofocus / optical image stabilization lenses in camera modules, the increased complexity and cost brought about by multiple reference voltage sources and active excitation control, the dependence on high-precision and high-speed sampling, and the error accumulation caused by the increase in the number of devices have become technical problems that urgently need to be solved. Summary of the Invention

[0005] This application provides a capacitor module detection circuit, chip, and optical lens movement detection device to solve the problems of increased implementation complexity and cost caused by multiple reference voltage sources and active excitation control in existing capacitor detection circuits, strong dependence on high-precision and high-speed sampling, and error accumulation caused by the increase in the number of devices.

[0006] In a first aspect, this application provides a capacitor module detection circuit, wherein the capacitor module includes a first capacitor and a second capacitor, the first plate of the first capacitor and the first plate of the second capacitor are both disposed on a lens, the positions of the second plates of the first capacitor and the second capacitor are fixed, and the capacitance value of the first capacitor and the capacitance value of the second capacitor change with the movement of the lens. The capacitor module detection circuit includes a charging / discharging circuit, a control circuit, and a measurement circuit. The charging and discharging circuit is used to charge or discharge the target capacitor, which is either the first capacitor or the second capacitor. The control circuit is used to detect the capacitor voltage of the target capacitor during the charging and discharging process of the charging and discharging circuit, and output a first control signal and a second control signal based on the capacitor voltage and a preset voltage. The first control signal is used to control the charging and discharging circuit to charge or discharge the first capacitor, and the second control signal is used to control the charging and discharging circuit to charge or discharge the second capacitor. The level of the first control signal is opposite to the level of the second control signal. The measurement circuit is used to determine the first duty cycle characterization information corresponding to the first control signal and the second duty cycle characterization information corresponding to the second control signal based on the first control signal and the second control signal, and to determine the current position of the lens based on the first duty cycle characterization information and the second duty cycle characterization information.

[0007] In one possible design, the first terminal of the charging and discharging circuit is electrically connected to the first terminal of the first capacitor, the second terminal of the charging and discharging circuit is electrically connected to the first terminal of the second capacitor, the third terminal of the charging and discharging circuit is electrically connected to the first terminal of the control circuit, and the fourth terminal of the charging and discharging circuit is electrically connected to the second terminal of the control circuit; the second terminals of the first capacitor and the second terminal of the second capacitor are both grounded. The third terminal of the control circuit is electrically connected to the fifth terminal of the charging and discharging circuit and the first terminal of the measuring circuit, respectively. The fourth terminal of the control circuit is electrically connected to the sixth terminal of the charging and discharging circuit and the second terminal of the measuring circuit, respectively.

[0008] In one possible design, the charging and discharging circuit includes a charging circuit, a discharging circuit, a first switch, and a second switch; The first terminal of the charging circuit is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the control circuit, respectively; the second terminal of the charging circuit is electrically connected to the second terminal of the control circuit. The first terminal of the discharge circuit is electrically connected to the second terminal of the first switch and the second terminal of the second switch, respectively, and the second terminal of the discharge circuit is grounded. The third terminal of the first switch is electrically connected to the first terminal of the first capacitor, and the fourth terminal of the first switch is electrically connected to the third terminal of the control circuit. The third terminal of the second switch is electrically connected to the first terminal of the second capacitor, and the fourth terminal of the second switch is electrically connected to the fourth terminal of the control circuit. Wherein, when the charging circuit charges the first capacitor, the discharging circuit discharges the second capacitor; when the charging circuit charges the second capacitor, the discharging circuit discharges the first capacitor.

[0009] In one possible design, the charging circuit includes a voltage source and a first resistor; The positive terminal of the voltage source is electrically connected to the first end of the first resistor and the second end of the control circuit, respectively, and the negative terminal of the voltage source is grounded. The second end of the first resistor is electrically connected to the first end of the first switch, the first end of the second switch, and the first end of the control circuit, respectively. When the first control signal is a high-level signal, the voltage source charges the first capacitor through the first resistor; when the second control signal is a high-level signal, the voltage source charges the second capacitor through the first resistor.

[0010] In one possible design, the discharge circuit includes a second resistor, the first end of which is electrically connected to the second end of the first switch and the second end of the second switch, respectively, and the second end of the second resistor is grounded. Specifically, when the first control signal is a low-level signal, the first capacitor discharges through the second resistor; when the second control signal is a low-level signal, the second capacitor discharges through the second resistor.

[0011] In one possible design, the control circuit includes a voltage divider circuit, a voltage comparator, and a trigger. The first terminal of the voltage divider circuit is electrically connected to the positive terminal of the voltage source, and the second terminal of the voltage divider circuit is electrically connected to the inverting input terminal of the voltage comparator. The non-inverting input terminal of the voltage comparator is electrically connected to the second terminal of the first resistor, and the output terminal of the voltage comparator is electrically connected to the first terminal of the flip-flop. The second and third terminals of the trigger are both electrically connected to the output terminal of the high-level output circuit. The fourth terminal of the trigger is electrically connected to the fourth terminal of the first switch and the first terminal of the measurement circuit, respectively. The fifth terminal of the trigger is electrically connected to the fourth terminal of the second switch and the second terminal of the measurement circuit, respectively. The high-level output circuit is used to output a high-level signal. The voltage divider circuit is used to output the preset voltage to the voltage comparator, the voltage comparator is used to compare the capacitor voltage and the preset voltage to obtain a comparison result, and the trigger is used to output the first control signal and the second control signal based on the comparison result.

[0012] In one possible design, the measurement circuit includes a first low-pass filter, a second low-pass filter, and a subtractor; The input terminal of the first low-pass filter is electrically connected to the third terminal of the control circuit, and the output terminal of the first low-pass filter is electrically connected to the first terminal of the subtractor. The input terminal of the second low-pass filter is electrically connected to the fourth terminal of the control circuit, and the output terminal of the second low-pass filter is electrically connected to the second terminal of the subtractor. The first low-pass filter is used to determine the first duty cycle characterization information based on the first control signal, the second low-pass filter is used to determine the second duty cycle characterization information based on the second control signal, and the subtractor is used to determine the current position of the lens based on the difference between the first duty cycle characterization information and the second duty cycle characterization information, and a preset calibration relationship.

[0013] Secondly, this application provides a chip, the chip including the capacitor module detection circuit described in the first aspect and any possible design of the first aspect.

[0014] Thirdly, this application provides an optical lens movement detection device, including a capacitor module and the chip described in the second aspect above, the chip having a first detection pin and a second detection pin; The capacitor module includes a first capacitor and a second capacitor. The first plates of the first capacitor and the second capacitor are both disposed on the lens. The positions of the second plates of the first capacitor and the second capacitor are fixed. The capacitance values ​​of the first capacitor and the second capacitor change as the lens moves. The first detection pin is electrically connected to the first plate of the first capacitor, and the second detection pin is electrically connected to the first plate of the second capacitor.

[0015] Fourthly, this application provides a camera module, including the optical lens movement detection device described in the third aspect above.

[0016] Fifthly, this application provides an electronic device including the camera module described in the fourth aspect above.

[0017] This application provides a capacitor module detection circuit, a chip, and an optical lens movement detection device. The capacitor module detection circuit includes a charging / discharging circuit, a control circuit, and a measurement circuit. The charging / discharging circuit charges and discharges a target capacitor, which may be a first capacitor or a second capacitor. The control circuit detects the capacitor voltage in real time during the charging process and outputs a first control signal and a second control signal by comparing the capacitor voltage with a preset voltage. The first control signal and the second control signal have opposite levels, so that the first capacitor and the second capacitor alternately enter the charging or discharging state under the same set of control logic. Since the time required for the target capacitor to charge to the preset voltage is related to the capacitance value, the change in the capacitance value of the first capacitor and the second capacitor caused by lens movement will be directly reflected in the changes in the pulse width and duty cycle characterization information of the first control signal and the second control signal. The measurement circuit extracts the first duty cycle characterization information and the second duty cycle characterization information accordingly and calculates the current position of the lens. This application converts capacitance changes into duty cycle changes of the first and second control signals to complete lens position detection. It can complete threshold determination and output the first and second control signals with a single preset voltage in the detection link, avoiding the dependence of existing charge balancing schemes on multiple reference voltage sources and their active switching / excitation control. At the same time, the current lens position is calculated based on the first and second duty cycle characterization information, rather than high-precision high-speed sampling of the transition voltage change of the reference capacitor. This helps to reduce the stringent requirements on sampling accuracy and response speed, and reduce the number of related functional units and peripheral devices, thereby reducing implementation complexity and cost and suppressing error accumulation caused by the increase of error sources. Attached Figure Description

[0018] Figure 1 A circuit block diagram of a capacitor module detection circuit provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the connection relationship between the capacitive module and the lens in an optical image stabilization application scenario provided in this application embodiment; Figure 3 A schematic diagram illustrating the connection relationship between the capacitive module and the lens in an autofocus scenario provided in this application embodiment; Figure 4 A circuit block diagram of another capacitor module detection circuit provided in an embodiment of this application; Figure 5 A circuit diagram of a voltage source, voltage divider circuit, and voltage comparator provided for embodiments of this application; Figure 6An output waveform diagram of a first control signal, a second control signal, and a capacitor voltage provided in an embodiment of this application; Figure 7 The waveform of the difference data output by the measurement circuit provided in the embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0021] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B can exist simultaneously, and B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0023] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0024] In the description of this application, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0025] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, "connected" or "linked" can refer not only to a physical connection, but also to an electrical connection or a signal connection. For instance, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected. It can also refer to the internal connection between two components. A signal connection can refer not only to a signal connection through a circuit, but also to a signal connection through a medium, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, different technical features in this application can be combined with each other.

[0027] In related technologies, in order to meet the requirements of camera module autofocus and optical image stabilization closed-loop control for lens displacement detection, a capacitive position detection method is usually adopted. That is, by forming a capacitor pair between an electrode plate that moves with the lens and an electrode plate that is fixed in position, the capacitance value changes with the lens displacement. Then, the capacitance detection circuit converts the capacitance change into a processable signal such as voltage, frequency or digital quantity, so as to drive the camera to estimate and control the lens position.

[0028] Based on the conversion mechanism of "capacitance to electrical signal", existing capacitance detection methods can be broadly classified into the following three categories: oscillation / timing circuit schemes based on discrete devices, integrated circuit schemes for capacitance detection based on LC resonance measurement, and dedicated capacitance detection chip schemes based on charge balance. These will be explained in detail below.

[0029] The first type is the capacitance detection circuit scheme based on discrete components. It typically employs a multivibrator or timer structure, such as the traditional 555 timer like the LM555 / NE555. An external charging / discharging resistor network, voltage divider resistors, etc., periodically charges and discharges the capacitor under test, outputting a pulse width modulation (PWM) square wave signal or oscillation frequency signal related to the capacitor under test. Specifically, the capacitor under test is connected as a timing capacitor to the timer's charging / discharging circuit, causing its voltage to fluctuate within a preset threshold range, thus forming a PWM waveform at the timer output with a duty cycle or frequency related to the RC time constant. To obtain the capacitance or displacement characteristic, a main control chip such as a Digital Signal Processor (DSP) or Microcontroller Unit (MCU) typically performs edge detection, frequency counting, or pulse width measurement on the PWM signal. Combined with a pre-calibrated lookup table or fitting relationship, a "frequency / pulse width - capacitance value" conversion is performed, thereby enabling the detection of changes in the target capacitance.

[0030] Such solutions typically do not include a reference capacitor for error calibration, and the output frequency is often inversely proportional to the capacitance value, resulting in limited linearity and measurement accuracy. Furthermore, the relatively large number of external components increases implementation costs and introduces more sources of error. Moreover, when the capacitance under test is extremely small (e.g., in the fF range) and the control / sampling frequency of the main control device is low, a large external resonant resistor is often required to obtain a measurable oscillation signal, thereby introducing greater thermal noise and amplifying measurement errors, affecting detection stability and reliability.

[0031] The second type is the capacitance sensing integrated circuit solution, such as Texas Instruments' FDC2X1X series chips, which typically uses the inductor-capacitor resonance measurement principle to achieve capacitance detection. This type of solution uses an external inductor L to form a resonant circuit with the capacitor C under test. The chip excites the resonant circuit and samples its resonant frequency or oscillation signal, then infers the capacitance value based on the correspondence between the resonant frequency and the capacitor under test. Because the measurement results of this type of solution are significantly affected by the nominal error of the external inductor, temperature drift, and parasitic wiring parameters, and typically do not have an independent reference capacitor for calibrating system errors, its measurement accuracy and stability are easily affected by deviations in external device parameters and environmental changes. While a certain level of accuracy can be obtained after calibration, it is highly sensitive to device consistency and layout parasitics.

[0032] This type of solution generally does not include a reference capacitor for error calibration, and the measurement results are still based on frequency-based capacitance deduction. Linearity and accuracy are easily limited, and it is quite sensitive to the nominal error of the external inductor, temperature drift, and wiring parasitic parameters. Especially when the capacitance value under test is extremely small (e.g., in the fF range) and the control / sampling frequency is limited, a large external inductor is often required to create usable resonant conditions. However, a larger inductor is more likely to introduce noise and errors, thereby reducing measurement stability and consistency.

[0033] The third type is a dedicated capacitance detection chip solution for OIS / AF camera drivers. Its internal capacitance detection circuit usually adopts a detection approach based on charge balance: during the measurement process, the target capacitor is charged and discharged, and the amount of charge generated by the target capacitor during the charging and discharging process is transferred to the reference capacitor. The voltage difference or voltage change formed on the reference capacitor due to the charge transfer is sampled to characterize the size of the target capacitor. Furthermore, the target capacitor can be detected and converted by multiple charging and discharging and charge transfer operations combined with the charge balance relationship, thereby completing the measurement of capacitance change.

[0034] Such solutions typically require multiple reference voltage sources (e.g., Vref1, Vref2), increasing power and control resource investment. Furthermore, active excitation / switching control of these multiple reference voltage sources is necessary, often requiring a separate clock oscillator or controller to complete the charge transfer and balancing process, further increasing system cost and implementation complexity. In addition, the voltage change on the reference capacitor needs to be sampled during the charge balancing transition phase, placing high demands on sampling accuracy and response speed, thus increasing implementation difficulty and cost. Simultaneously, the large number of related functional units and peripheral devices increases the sources of error and easily leads to cumulative errors, affecting detection accuracy and reliability.

[0035] Based on the problems existing in related technologies, this application provides a capacitor module detection circuit. Addressing the issues of existing charge-balance capacitor detection schemes relying on multiple reference voltage sources and their active excitation control, and requiring high-precision, high-speed sampling during the charge-balance transition phase, leading to increased circuit complexity and error accumulation, this application proposes a detection path that directly converts capacitance value changes into duty cycle representation information of digital control signals. Specifically, a charging and discharging circuit alternately charges and discharges a first and a second capacitor. During the charging process of the target capacitor, the control circuit generates complementary first and second control signals based solely on the comparison between the capacitor voltage and a single preset voltage. This allows capacitance changes to be naturally mapped to duty cycle changes in the first and second control signals. The measurement circuit then extracts the first and second duty cycle representation information and combines it with a preset calibration relationship to obtain the current position of the lens. This allows lens position detection to be completed without introducing multiple reference voltage sources and complex excitation control, reducing reliance on high-speed, high-precision voltage sampling, reducing the number of components and functional units, thereby lowering implementation complexity and cost, and suppressing error accumulation.

[0036] Next, through some specific embodiments and accompanying drawings, this application will describe in detail how it solves the problems of increased implementation complexity and cost, strong dependence on high-precision and high-speed sampling, and error accumulation caused by the increase in the number of devices in the existing capacitance detection circuits.

[0037] Figure 1 This is a circuit block diagram illustrating the principle of a capacitor module detection circuit provided in an embodiment of this application. Figure 1 As shown, the capacitor module detection circuit 10 provided in this embodiment includes a charging and discharging circuit 11, a control circuit 12, and a measurement circuit 13.

[0038] The capacitor module detection circuit 10 detects the capacitor module 40, which includes a first capacitor 41 and a second capacitor 42. The first plate of the first capacitor 41 and the first plate of the second capacitor 42 are both mounted on the lens. The positions of the second plates of the first capacitor 41 and the second plates of the second capacitor 42 are fixed. The capacitance value of the first capacitor 41 and the capacitance value of the second capacitor 42 change as the lens moves.

[0039] Figure 2 This diagram illustrates the connection relationship between the capacitive module and the lens in an optical image stabilization application scenario provided in this application embodiment. Figure 2 As shown, in one embodiment, the capacitor module includes a first capacitor 21 and a second capacitor 22. The first electrode plate 211 of the first capacitor 21 and the first electrode plate 221 of the second capacitor 22 are both disposed on the lens 200. The positions of the second electrode plate 212 of the first capacitor 21 and the second electrode plate 222 of the second capacitor 22 are fixed.

[0040] In the application of optical image stabilization in a lens, the lens 200 moves along the x-axis, that is, the lens 200 moves between the second plate 212 of the first capacitor 21 and the second plate 222 of the second capacitor 22; when the lens 200 moves along the x-axis, the distance between the first plate 211 and the second plate 212 of the first capacitor 21... and the distance between the first plate 221 and the second plate 222 of the second capacitor 22 As the lens 200 moves, the capacitance values ​​of the first capacitor 21 and the second capacitor 22 change.

[0041] The capacitance between the first plate 211 and the second plate 212 is the first capacitor 21, which is also the first capacitor 41. The first capacitor 41 is also called the first capacitor. The capacitance between the first plate 221 and the second plate 222 is the second capacitor 22, which is also the second capacitor 42, and is also called the second capacitor. .

[0042] The overlap area between the first electrode plate 211 and the second electrode plate 212, and the overlap area between the first electrode plate 221 and the second electrode plate 222 are designed to be the same, and the overlap areas between the first electrode plate 211 and the second electrode plate 212, and the overlap areas between the first electrode plate 221 and the second electrode plate 222 are all equal. .

[0043] It should be noted that, , , Where is the dielectric constant. and The sum is a constant.

[0044] Figure 3 This is a schematic diagram illustrating the connection relationship between the capacitive module and the lens in an autofocus scenario provided in an embodiment of this application. Figure 3 As shown, in another embodiment, the capacitor module includes a first capacitor 31 and a second capacitor 32. The first electrode plate 311 of the first capacitor 31 and the first electrode plate 321 of the second capacitor 32 are the same electrode plate, and the first electrode plate 311 is disposed on the lens 300. The positions of the second electrode plate 312 of the first capacitor 31 and the second electrode plate 322 of the second capacitor 32 are fixed.

[0045] In the autofocus application of the lens, the lens 300 moves along the z-axis, that is, the lens 300 moves along the direction in which the second electrode 312 and the second electrode 322 are positioned; when the lens 300 moves along the z-axis, the overlap area between the first electrode 311 and the second electrode 312 of the first capacitor 31... and the overlapping area between the first plate 321 and the second plate 322 of the second capacitor 32. As the lens 300 moves, the capacitance values ​​of the first capacitor 31 and the second capacitor 32 change.

[0046] The capacitance between the first plate 311 and the second plate 312 is the first capacitor 31, which is also the first capacitor 41. The capacitance between the first plate 321 and the second plate 322 is the second capacitor 32, which is also the second capacitor 42.

[0047] The distances between the first electrode plate 311 and the second electrode plate 312, and between the first electrode plate 321 and the second electrode plate 322, are designed to be the same, and the distances between the first electrode plate 311 and the second electrode plate 312, and between the first electrode plate 321 and the second electrode plate 322, are all equal. .

[0048] It should be noted that, , , and The sum is a constant.

[0049] like Figure 1 As shown, the first terminal of the charging and discharging circuit 11 is electrically connected to the first terminal of the first capacitor C1, the second terminal of the charging and discharging circuit 11 is electrically connected to the first terminal of the second capacitor C2, the third terminal of the charging and discharging circuit 11 is electrically connected to the first terminal of the control circuit 12, and the fourth terminal of the charging and discharging circuit 11 is electrically connected to the second terminal of the control circuit 12; the second terminals of the first capacitor C1 and the second terminals of the second capacitor C2 are both grounded.

[0050] The charging and discharging circuit 11 is used to charge or discharge the target capacitor, which is either the first capacitor C1 or the second capacitor C2.

[0051] It should be noted that while charging the first capacitor C1, the charging / discharging circuit 11 simultaneously discharges the second capacitor C2. This ensures that the second capacitor C2 returns to its preset initial potential before being selected as the target capacitor and starting charging again. This guarantees that the initial voltage across the second capacitor C2 remains at the preset initial potential during subsequent charging operations, ensuring that the determination of the second capacitor C2's charging from the preset initial potential to the preset voltage in each charging cycle is based on the same initial voltage. This avoids time deviations caused by differences in the residual voltage of the second capacitor C2. Similarly, when the charging / discharging circuit 11 charges the second capacitor C2, it simultaneously discharges the first capacitor C1, restoring it to its preset initial potential. By alternating charging / discharging of the first capacitor C1 and the second capacitor C2, complementary switching between them can be achieved in the charging / discharging cycle, improving the stability and consistency of the detection process.

[0052] In this embodiment, the initial potential is preset to 0V, which is the ground potential.

[0053] The third terminal of the control circuit 12 is electrically connected to the fifth terminal of the charging and discharging circuit 11 and the first terminal of the measuring circuit 13, respectively. The fourth terminal of the control circuit 12 is electrically connected to the sixth terminal of the charging and discharging circuit 11 and the second terminal of the measuring circuit 13, respectively.

[0054] The control circuit 12 is used to detect the capacitor voltage of the target capacitor during the charging and discharging circuit 11 charging the target capacitor, and output a first control signal and a second control signal based on the capacitor voltage and a preset voltage. The first control signal is used to control the charging and discharging circuit 11 to charge or discharge the first capacitor 41, and the second control signal is used to control the charging and discharging circuit 11 to charge or discharge the second capacitor 42. The level of the first control signal is opposite to the level of the second control signal.

[0055] It should be noted that both the first control signal and the second control signal are PWM signals, and the first control signal and the second control signal are complementary. When the first control signal is a high-level signal, the second control signal is a low-level signal; when the first control signal is a low-level signal, the second control signal is a high-level signal.

[0056] The control circuit 12 can drive the first capacitor C1 and the second capacitor C2 to alternately become the target capacitor in the same detection process by outputting complementary first and second control signals. During the charging process of the target capacitor, it can determine whether the capacitor voltage has reached the preset voltage, thereby providing a control basis for extracting duty cycle characterization information based on the first and second control signals and determining the current position of the lens.

[0057] The measurement circuit 13 is used to determine the first duty cycle characterization information corresponding to the first control signal and the second duty cycle characterization information corresponding to the second control signal based on the first control signal and the second control signal, and to determine the current position of the lens based on the first duty cycle characterization information and the second duty cycle characterization information.

[0058] It should be noted that the first control signal is used to characterize the alternating charging and discharging process of the first capacitor C1, and the second control signal is used to characterize the alternating charging and discharging process of the second capacitor C2. The change in capacitance value of the first capacitor C1 and the second capacitor C2 caused by lens movement can be reflected as a change in duty cycle characterization information corresponding to the first control signal and the second control signal. Therefore, the measurement circuit 13 can determine the current position of the lens based on the first duty cycle characterization information and the second duty cycle characterization information.

[0059] This application provides a capacitor module detection circuit, which includes a charging / discharging circuit, a control circuit, and a measurement circuit. The charging / discharging circuit charges and discharges a target capacitor, which may be a first capacitor or a second capacitor. The control circuit detects the capacitor voltage in real time during the charging process and outputs a first control signal and a second control signal by comparing the capacitor voltage with a preset voltage. The first control signal and the second control signal have opposite levels, so that the first capacitor and the second capacitor alternately enter the charging or discharging state under the same set of control logic. Since the time required for the target capacitor to charge to the preset voltage is related to the capacitance value, the change in the capacitance value of the first capacitor and the second capacitor caused by lens movement will be directly reflected in the change of the pulse width and duty cycle characterization information of the first control signal and the second control signal. The measurement circuit extracts the first duty cycle characterization information and the second duty cycle characterization information accordingly and calculates the current position of the lens. This application converts capacitance changes into duty cycle changes of the first and second control signals to complete lens position detection. It can complete threshold determination and output the first and second control signals with a single preset voltage in the detection link, avoiding the dependence of existing charge balancing schemes on multiple reference voltage sources and their active switching / excitation control. At the same time, the current lens position is calculated based on the first and second duty cycle characterization information, rather than high-precision high-speed sampling of the transition voltage change of the reference capacitor. This helps to reduce the stringent requirements on sampling accuracy and response speed, and reduce the number of related functional units and peripheral devices, thereby reducing implementation complexity and cost and suppressing error accumulation caused by the increase of error sources.

[0060] Figure 4 This is a circuit diagram of a charging / discharging circuit and a capacitor module provided for an embodiment of this application. Figure 4 As shown, in one possible embodiment, the charging and discharging circuit 11 includes a charging circuit 111, a discharging circuit 112, a first switch SW1, and a second switch SW2.

[0061] Among them, the first switch SW1 and the second switch SW2 are both single-pole double-throw switches, and the single-pole double-throw switch has a first switching terminal, a second switching terminal, a common terminal and a control terminal.

[0062] The first terminal of the charging circuit 111 is electrically connected to the first terminal of the first switch SW1, the first terminal of the second switch SW2 and the first terminal of the control circuit 12, respectively, and the second terminal of the charging circuit 111 is electrically connected to the second terminal of the control circuit 12.

[0063] The first terminal of the discharge circuit 112 is electrically connected to the second terminal of the first switch SW1 and the second terminal of the second switch SW2, respectively, and the second terminal of the discharge circuit 112 is grounded.

[0064] The third terminal of the first switch SW1 is electrically connected to the first terminal of the first capacitor C1, and the fourth terminal of the first switch SW1 is electrically connected to the third terminal of the control circuit 12.

[0065] The third terminal of the second switch SW2 is electrically connected to the first terminal of the second capacitor C2, and the fourth terminal of the second switch SW2 is electrically connected to the fourth terminal of the control circuit 12.

[0066] Specifically, the third terminal of the first switch SW1 is the first terminal of the charging and discharging circuit 11, the third terminal of the second switch SW2 is the second terminal of the charging and discharging circuit 11, the first terminal of the charging circuit 111 is the third terminal of the charging and discharging circuit 11, the second terminal of the charging circuit 111 is the fourth terminal of the charging and discharging circuit 11, the fourth terminal of the first switch SW1 is the fifth terminal of the charging and discharging circuit 11, and the fourth terminal of the second switch SW2 is the sixth terminal of the charging and discharging circuit 11.

[0067] Specifically, when the charging circuit 111 charges the first capacitor C1, the discharging circuit 112 discharges the second capacitor C2; when the charging circuit 111 charges the second capacitor C2, the discharging circuit 112 discharges the first capacitor C1.

[0068] It should be noted that when the charging circuit 111 charges the first capacitor C1 and the discharging circuit 112 discharges the second capacitor C2, the duration of a single charging of the first capacitor C1 by the charging circuit 111 is longer than the duration of a single discharging of the second capacitor C2 by the discharging circuit 112, so that the capacitor being discharged (the second capacitor C2) is released to 0V before the switching. Similarly, when the charging circuit 111 charges the second capacitor C2 and the discharging circuit 112 discharges the first capacitor C1, the duration of a single charging of the second capacitor C2 by the charging circuit 111 is longer than the duration of a single discharging of the first capacitor C1 by the discharging circuit 112, so that the capacitor being discharged (the first capacitor C1) is released to 0V before the switching.

[0069] In this embodiment, by releasing the capacitor to be discharged to 0V before switching, the charging start offset caused by the residual voltage in the capacitor to be discharged can be reduced, thereby improving the stability and consistency of the subsequent duty cycle characterization information.

[0070] Wherein, the first end of the first switch SW1 is the first switching end of the first switch SW1, the second end of the first switch SW1 is the second switching end of the first switch SW1, the third end of the first switch SW1 is the common end of the first switch SW1, and the fourth end of the first switch SW1 is the control end of the first switch SW1.

[0071] It should be noted that, under the control of the third terminal of the control circuit 12, the common terminal of the first switch SW1 is selectively connected to either the first switching terminal or the second switching terminal of the first switch SW1. When the common terminal of the first switch SW1 is connected to the first switching terminal of the first switch SW1, the first capacitor C1 is connected to the charging circuit 111, and the charging circuit 111 performs a charging operation on the first capacitor C1; when the common terminal of the first switch SW1 is connected to the second switching terminal of the first switch SW1, the first capacitor C1 is connected to the discharging circuit 112, and the discharging circuit 112 performs a discharging operation on the first capacitor C1.

[0072] Wherein, the first end of the second switch SW2 is the first switching end of the second switch SW2, the second end of the second switch SW2 is the second switching end of the second switch SW2, the third end of the second switch SW2 is the common end of the second switch SW2, and the fourth end of the second switch SW2 is the control end of the second switch SW2.

[0073] It should be noted that, under the control of the fourth terminal of the control circuit 12, the common terminal of the second switch SW2 is selectively connected to either the first switching terminal or the second switching terminal of the second switch SW2. When the common terminal of the second switch SW2 is connected to the first switching terminal, the second capacitor C2 is connected to the charging circuit 111, and the charging circuit 111 performs a charging operation on the second capacitor C2. When the common terminal of the second switch SW2 is connected to the second switching terminal, the second capacitor C2 is connected to the discharging circuit 112, and the discharging circuit 112 performs a discharging operation on the second capacitor C2.

[0074] like Figure 4 As shown, in one possible embodiment, the charging circuit 111 includes a voltage source VD1 and a first resistor R1.

[0075] The positive terminal of voltage source VD1 is electrically connected to the first end of the first resistor R1 and the second end of the control circuit 12, respectively, and the negative terminal of voltage source VD1 is grounded; the second end of the first resistor R1 is electrically connected to the first end of the first switch SW1, the first end of the second switch SW2 and the first end of the control circuit 12, respectively.

[0076] Specifically, the positive terminal of voltage source VD1 is the second terminal of charging circuit 111, that is, the positive terminal of voltage source VD1 is the fourth terminal of charging and discharging circuit 11; the second terminal of the first resistor R1 is the first terminal of charging circuit 111, that is, the second terminal of the first resistor R1 is the third terminal of charging and discharging circuit 11.

[0077] Specifically, when the first control signal is a high-level signal, the voltage source VD1 charges the first capacitor C1 through the first resistor R1; when the second control signal is a high-level signal, the voltage source VD1 charges the second capacitor C2 through the first resistor R1.

[0078] It should be noted that when the first control signal is a high-level signal, the common terminal of the first switch SW1 is connected to the first switching terminal of the first switch SW1, and the voltage source VD1 charges the first capacitor C1 through the first resistor R1; when the second control signal is a high-level signal, the common terminal of the second switch SW2 is connected to the first switching terminal of the second switch SW2, and the voltage source VD1 charges the second capacitor C2 through the first resistor R1.

[0079] In this embodiment, the first resistor R1 is composed of a standard resistor and an adjustable resistor. The standard resistor provides the main reference resistance value, and the adjustable resistor is used to fine-tune the resistance value of the equivalent charging resistance (e.g., connected in series and / or in parallel with the standard resistor to form the equivalent resistance). By setting the adjustable resistor, when the equivalent charging resistance deviates from the design value due to factors such as device manufacturing tolerances, temperature drift, and switch on-resistance, the equivalent charging resistance can be compensated and calibrated. This makes the charging current of the target capacitor and the RC time constant closer to the preset value, thereby making the charging time of the target capacitor from 0V to the preset voltage more stable and consistent. This reduces the zero-point offset and dispersion of the duty cycle characterization information caused by resistance deviation, improves the consistency and accuracy of lens position detection results, and helps reduce the accumulation of system errors.

[0080] like Figure 4 As shown, in one possible embodiment, the discharge circuit 112 includes a second resistor R2, the first end of which is electrically connected to the second end of the first switch SW1 and the second end of the second switch SW2, respectively, and the second end of the second resistor R2 is grounded.

[0081] Specifically, the first end of the second resistor R2 is the first end of the discharge circuit 112, and the second end of the second resistor R2 is the second end of the discharge circuit 112.

[0082] Specifically, when the first control signal is a low-level signal, the first capacitor C1 discharges through the second resistor R2; when the second control signal is a low-level signal, the second capacitor C2 discharges through the second resistor R2.

[0083] It should be noted that when the second control signal is a high-level signal, the first control signal is a low-level signal. At this time, the common terminal of the first switch SW1 is connected to the second switching terminal of the first switch SW1, and the first capacitor C1 discharges through the second resistor R2. When the first control signal is a high-level signal, the second control signal is a low-level signal. At this time, the common terminal of the second switch SW2 is connected to the second switching terminal of the second switch SW2, and the second capacitor C2 discharges through the second resistor R2.

[0084] In this embodiment, the resistance value of the second resistor R2 is less than that of the first resistor R1 to reduce the discharge time constant of the capacitor being discharged, thereby achieving rapid discharge of the capacitor being discharged during the charging of the target capacitor. This ensures that the initial voltage across the capacitor being discharged is 0V when it starts charging as the target capacitor in the next round, improving the consistency of subsequent threshold determination and duty cycle characterization information extraction.

[0085] like Figure 5 As shown, in one possible embodiment, the control circuit 12 includes a voltage divider circuit 121, a voltage comparator 122, and a trigger 123.

[0086] The first terminal of the voltage divider circuit 121 is electrically connected to the positive terminal of the voltage source VD1, the second terminal of the voltage divider circuit 121 is electrically connected to the inverting input terminal of the voltage comparator 122, the non-inverting input terminal of the voltage comparator 122 is electrically connected to the second terminal of the first resistor R1, and the output terminal of the voltage comparator 122 is electrically connected to the first terminal of the flip-flop 123.

[0087] The second and third terminals of the trigger 123 are electrically connected to the output terminal of the high-level output circuit 50. The fourth terminal of the trigger 123 is electrically connected to the fourth terminal of the first switch SW1 and the first terminal of the measurement circuit 13, respectively. The fifth terminal of the trigger 123 is electrically connected to the fourth terminal of the second switch SW2 and the second terminal of the measurement circuit 13, respectively.

[0088] Specifically, the first terminal of the voltage divider circuit 121 is the second terminal of the control circuit 12, the non-inverting input terminal of the voltage comparator 122 is the first terminal of the control circuit 12, the fourth terminal of the flip-flop 123 is the third terminal of the control circuit, and the fifth terminal of the flip-flop 123 is the fourth terminal of the control circuit 12.

[0089] The voltage divider circuit 121 is used to output a preset voltage to the voltage comparator 122.

[0090] Figure 5 This is a circuit diagram of a voltage source, voltage divider circuit, and voltage comparator provided for embodiments of this application. Figure 5 As shown, in one possible embodiment, the voltage divider circuit 121 includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first terminal of the third resistor R3 is electrically connected to the positive terminal of the voltage source VD1, the second terminal of the third resistor R3 is electrically connected to the first terminal of the fourth resistor R4, the second terminal of the fourth resistor R4 is electrically connected to the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is grounded. The connection terminal of the third resistor R3 and the fourth resistor R4 is electrically connected to the inverting input terminal of the voltage comparator 122.

[0091] Among them, the first end of the third resistor R3 is the first end of the voltage divider circuit 121, and the connection end of the third resistor R3 and the fourth resistor R4 is the second end of the voltage divider circuit 121.

[0092] It should be noted that when the resistance values ​​of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are the same, the preset voltage is 2 / 3VCC, where VCC is the output voltage of the voltage source VD1.

[0093] The preset voltage is used as a threshold voltage to compare with the capacitor voltage of the target capacitor to trigger the subsequent switching of the first and second control signals; and the preset voltage can be set by configuring the resistance ratio of the third resistor R3, the fourth resistor R4 and the fifth resistor R5, so as to adapt to different target capacitor ranges and charging and discharging speed requirements.

[0094] The comparator 122 is used to compare the capacitor voltage with a preset voltage to obtain a comparison result.

[0095] It should be noted that the inverting input of voltage comparator 122 is electrically connected to the second terminal of voltage divider circuit 121 to receive a preset voltage; the non-inverting input of voltage comparator 122 is electrically connected to the second terminal of first resistor R1 to receive the capacitor voltage corresponding to the target capacitor currently in the charging state.

[0096] When the target capacitor is charged, causing the capacitor voltage to rise and reach the preset voltage, the output of voltage comparator 122 outputs a high-level signal; when the capacitor voltage is lower than the preset voltage, the output of voltage comparator 122 outputs a low-level signal.

[0097] The high-level output circuit 50 is used to output a high-level signal. The flip-flop 123 is used to output a first control signal and a second control signal based on the comparison result.

[0098] It should be noted that flip-flop 123 is a JK flip-flop. The first terminal of flip-flop 123 is the trigger terminal of the JK flip-flop, the second terminal of flip-flop 123 is the J input terminal of the JK flip-flop, the third terminal of flip-flop 123 is the K input terminal of the JK flip-flop, the fourth terminal of flip-flop 123 is the output terminal of the JK flip-flop, and the fifth terminal of flip-flop 123 is the inverted output terminal of the JK flip-flop.

[0099] The high-level output circuit 50 continuously outputs a high-level signal to the J and K input terminals of the JK flip-flop, causing the JK flip-flop to operate in Toggle mode. In Toggle mode, when both the J and K input terminals of the JK flip-flop are high (J=K=1), and the trigger terminal of the JK flip-flop receives a trigger edge, the output state of the JK flip-flop flips. During the charging process of the target capacitor, when the capacitor voltage reaches the preset voltage, the comparison result output by comparator 122 is a high-level signal. The JK flip-flop flips its output state according to the high-level signal output by comparator 122, causing the first control signal and the second control signal to change alternately under a complementary relationship, thereby realizing the alternating charging / discharging control of the first capacitor C1 and the second capacitor C2.

[0100] like Figure 4 As shown, in one possible embodiment, the measurement circuit 13 includes a first low-pass filter 131, a second low-pass filter 132, and a subtractor 133.

[0101] The input terminal of the first low-pass filter 131 is electrically connected to the third terminal of the control circuit 12, and the output terminal of the first low-pass filter 131 is electrically connected to the first terminal of the subtractor 133; the input terminal of the second low-pass filter 132 is electrically connected to the fourth terminal of the control circuit 12, and the output terminal of the second low-pass filter 132 is electrically connected to the second terminal of the subtractor 133.

[0102] Specifically, the input terminal of the first low-pass filter 131 is the first terminal of the measurement circuit 13, and the input terminal of the second low-pass filter 132 is the second terminal of the measurement circuit 13.

[0103] The first low-pass filter 131 is used to determine the first duty cycle characterization information according to the first control signal, the second low-pass filter 132 is used to determine the second duty cycle characterization information according to the second control signal, and the subtractor 133 is used to determine the current position of the lens based on the difference between the first duty cycle characterization information and the second duty cycle characterization information, as well as the preset calibration relationship.

[0104] It should be noted that the first control signal and the second control signal are complementary pulse signals. The high-level duration of the first control signal and the second control signal is related to the charging time of the target capacitor from 0V to the preset voltage during the charging process, and this charging time is further related to the capacitance value of the corresponding capacitor. Therefore, the change in the duty cycle of the first control signal and the second control signal can characterize the capacitance change of the first capacitor C1 and the second capacitor C2 as the lens moves.

[0105] The first low-pass filter 131 can convert the duty cycle change of the first control signal into a relatively stable first DC characteristic quantity, thereby obtaining the first duty cycle characteristic information, and output the first duty cycle characteristic information to the subtractor 133. The second low-pass filter 132 can convert the duty cycle change of the second control signal into a relatively stable second DC characteristic quantity, thereby obtaining the second duty cycle characteristic information, and output the second duty cycle characteristic information to the subtractor 133.

[0106] It should be noted that the first duty cycle characterization information is used to characterize the duty cycle of the first control signal. This information can be the DC component voltage (or a duty cycle-related parameter equivalent to this DC component) obtained after low-pass filtering the first control signal. The second duty cycle characterization information is used to characterize the duty cycle of the second control signal. This information can also be the DC component voltage (or a duty cycle-related parameter equivalent to this DC component) obtained after low-pass filtering the second control signal. Since the first and second control signals are pulse-width modulated signals, when the high-level amplitude of the first and second control signals is constant, the DC component output by the low-pass filter is approximately proportional to the duty cycle. Therefore, the change in the capacitance values ​​of the first and second capacitors caused by lens movement can be reflected as a change in the DC component (i.e., the duty cycle characterization information). Furthermore, the current position of the lens can be determined based on the first and second duty cycle characterization information, combined with a preset calibration relationship.

[0107] Furthermore, the subtractor 133 performs a difference operation on the first duty cycle representation information and the second duty cycle representation information to obtain difference data; and determines the current position of the lens based on the difference data and a preset calibration relationship. By using the difference between the first duty cycle representation information and the second duty cycle representation information as the basis for position representation, the common-mode effects of voltage source fluctuations and device consistency differences can be effectively offset, thereby improving the stability and consistency of the lens position detection results.

[0108] It should be noted that the preset calibration relationship is used to characterize the correspondence between the difference data and the current position of the lens. This calibration relationship can be pre-obtained and stored in the measurement circuit or a processing unit communicating with the measurement circuit. Specifically, during the factory calibration or assembly calibration stage, the lens can be moved sequentially to multiple known position points. At each position point, first duty cycle characterization information and second duty cycle characterization information are acquired, and the difference data between the first duty cycle characterization information and the second duty cycle characterization information is calculated, thereby establishing the correspondence between the difference data and the lens position.

[0109] Specifically, in the application of lens autofocus, the high-level duration of the first control signal is... , The high-level duration in the second control signal is... , Where k is related to the threshold of the voltage comparator and is a fixed constant.

[0110] Based on the above lens autofocus applications and From the calculation formula, we can see that... , Therefore, the duty cycle of the first control signal , Duty cycle of the second control signal .

[0111] It is a fixed constant, based on the duty cycle of the first control signal. Duty cycle of the second control signal The calculation formula shows that the duty cycle of the first control signal... The overlap area between the first plate 311 and the second plate 312 of the first capacitor 31 (first capacitor C1) The duty cycle of the second control signal is in a perfectly linear proportional relationship. The overlap area between the first plate 321 and the second plate 322 of the second capacitor 32 (first capacitor C2) They are in a perfectly linear proportional relationship.

[0112] The duty cycle of the first control signal Duty cycle of the second control signal Input subtractor 133, and you will get This allows us to obtain the amount of movement of lens 300 along the z-axis, and ultimately the current position of lens 300.

[0113] In optical image stabilization applications of lenses, the high-level duration of the first control signal is... , The high-level duration in the second control signal is... , .

[0114] Based on the optical image stabilization applications of the aforementioned lenses and From the calculation formula, we can see that... , Therefore, the duty cycle of the first control signal The calculation formula is The duty cycle of the second control signal .

[0115] It is a fixed constant, based on the duty cycle of the first control signal. Duty cycle of the second control signal The calculation formula shows that the duty cycle of the first control signal... The distance between the first plate 221 and the second plate 222 of the second capacitor 22 (first capacitor C1) The duty cycle of the second control signal is in a perfectly linear proportional relationship. The distance between the first plate 211 and the second plate 212 of the first capacitor 21 (first capacitor C2) They are in a perfectly linear proportional relationship.

[0116] The duty cycle of the first control signal Duty cycle of the second control signal Input subtractor 133, and you will get This allows us to obtain the amount of movement of lens 300 along the x-axis, and ultimately the current position of lens 300.

[0117] Figure 6 An output waveform diagram of a first control signal, a second control signal, and a capacitor voltage signal provided in an embodiment of this application is shown below. Figure 6 As shown, waveform 1 is the output waveform of the first control signal, waveform 2 is the output waveform of the second control signal, and waveform 3 is the output waveform of the capacitor voltage signal. The output waveforms of the first and second control signals are inverses of each other and alternately flip: when the first control signal is a high-level signal, it indicates that the first capacitor C1 is selected as the target capacitor and connected to the charging circuit; at the same time, the second control signal is a low-level signal, causing the second capacitor C2 to be connected to the discharging circuit; when the voltage of the target capacitor rises to a preset voltage and triggers the flip, the first and second control signals synchronously switch in opposite directions, causing the second capacitor C2 to be connected to the charging circuit and the first capacitor C1 to be connected to the discharging circuit, thereby realizing the alternating charging and discharging process of charging one capacitor while discharging another capacitor.

[0118] The pulse width (duty cycle) of the first control signal and the second control signal varies with the time required to reach the preset voltage each time the charge is applied, providing a basis for extracting the duty cycle characterization information through low-pass filtering and determining the lens position in combination with the calibration relationship.

[0119] As shown in waveform 3, the target capacitor starts from 0V and rises exponentially during the charging phase (RC charging curve). When it reaches the preset voltage, it switches and quickly returns to a low level before rising again, forming a periodic sawtooth / charge-discharge waveform.

[0120] Figure 7 The waveform diagram of the difference data output by the measurement circuit provided in the embodiments of this application is shown below. Figure 7 As shown, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are in the fF range, and their original capacitance changes are relatively small, making them unsuitable for direct output as a lens position representation. Based on the duty cycle representation and differential processing method of this application, the duty cycle representation information corresponding to the first control signal and the second control signal can be combined (e.g., by subtracting and normalizing) to map the fF-level capacitance change into a dimensionless calculation result with an amplitude in the range of [-1, 1]. This calculation result can show a clear trend and periodic response with the capacitance values ​​of the first capacitor C1 and the second capacitor C2, and has good monotonicity and approximately linear relationship with the changes of the first capacitor C1 and the second capacitor C2, which is convenient for subsequent position conversion in combination with preset calibration relationships. Through the above mapping and normalization processing, this application can achieve high-sensitivity representation of small capacitance changes without relying on direct high-precision measurement of small capacitance values, thereby improving the effective dynamic range and usability of the position detection signal.

[0121] In summary, the capacitor module detection circuit provided in this application only requires a single voltage source VD1 to operate and can share power supply with integrated circuits, reducing power supply and peripheral configuration costs. This application does not require actively generating excitation signals; the control signals of the single-pole double-throw switch (first switch and second switch) are automatically generated by the comparator and JK flip-flop based on the capacitor voltage threshold, eliminating the need for additional oscillators or controllers, thus further reducing implementation complexity and cost. This application does not require a reference capacitor or high-speed sampling of frequency or rising edge; duty cycle characterization information can be obtained simply by extracting the DC component of the PWM signal through low-pass filtering, resulting in stable and clean detection results. Furthermore, this application does not rely on external components such as resonant inductors, requiring fewer components and achieving higher integration. It also exhibits strong robustness to fluctuations in parameters such as voltage source VD1 and resistance, which helps suppress error accumulation and improve measurement consistency. In addition, this invention is applicable to capacitive position sampling scenarios for various camera drivers, including autofocus and optical image stabilization, making it widely applicable.

[0122] This application also provides a chip that includes the capacitor module detection circuit described in the above embodiments.

[0123] This application also provides an optical lens movement detection device, which includes a capacitor module and the chip in the above embodiment, the chip having a first detection pin and a second detection pin; The capacitor module includes a first capacitor and a second capacitor. The first plates of the first capacitor and the second capacitor are both mounted on the lens. The positions of the second plates of the first capacitor and the second capacitor are fixed. The capacitance values ​​of the first capacitor and the second capacitor change as the lens moves. The first detection pin is electrically connected to the first plate of the first capacitor, and the second detection pin is electrically connected to the first plate of the second capacitor.

[0124] This application also provides a camera module, which includes the optical lens movement detection device in the above embodiments.

[0125] This application also provides an electronic device that includes the camera module described in the above embodiments.

[0126] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A capacitor module detection circuit, characterized in that, The capacitor module includes a first capacitor and a second capacitor. The first plates of the first capacitor and the second capacitor are both disposed on the lens. The positions of the second plates of the first capacitor and the second capacitor are fixed. The capacitance values ​​of the first capacitor and the second capacitor change as the lens moves. The capacitor module detection circuit includes a charging / discharging circuit, a control circuit, and a measurement circuit. The charging and discharging circuit is used to charge or discharge the target capacitor, which is either the first capacitor or the second capacitor. The control circuit is used to detect the capacitor voltage of the target capacitor during the charging and discharging process of the charging and discharging circuit, and output a first control signal and a second control signal based on the capacitor voltage and a preset voltage. The first control signal is used to control the charging and discharging circuit to charge or discharge the first capacitor, and the second control signal is used to control the charging and discharging circuit to charge or discharge the second capacitor. The level of the first control signal is opposite to the level of the second control signal. The measurement circuit is used to determine the first duty cycle characterization information corresponding to the first control signal and the second duty cycle characterization information corresponding to the second control signal based on the first control signal and the second control signal, and to determine the current position of the lens based on the first duty cycle characterization information and the second duty cycle characterization information.

2. The circuit according to claim 1, characterized in that, The first terminal of the charging and discharging circuit is electrically connected to the first terminal of the first capacitor, the second terminal of the charging and discharging circuit is electrically connected to the first terminal of the second capacitor, the third terminal of the charging and discharging circuit is electrically connected to the first terminal of the control circuit, and the fourth terminal of the charging and discharging circuit is electrically connected to the second terminal of the control circuit; the second terminals of the first capacitor and the second terminal of the second capacitor are both grounded. The third terminal of the control circuit is electrically connected to the fifth terminal of the charging and discharging circuit and the first terminal of the measuring circuit, respectively. The fourth terminal of the control circuit is electrically connected to the sixth terminal of the charging and discharging circuit and the second terminal of the measuring circuit, respectively.

3. The circuit according to claim 2, characterized in that, The charging and discharging circuit includes a charging circuit, a discharging circuit, a first switch, and a second switch. The first terminal of the charging circuit is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the control circuit, respectively; the second terminal of the charging circuit is electrically connected to the second terminal of the control circuit. The first terminal of the discharge circuit is electrically connected to the second terminal of the first switch and the second terminal of the second switch, respectively, and the second terminal of the discharge circuit is grounded. The third terminal of the first switch is electrically connected to the first terminal of the first capacitor, and the fourth terminal of the first switch is electrically connected to the third terminal of the control circuit. The third terminal of the second switch is electrically connected to the first terminal of the second capacitor, and the fourth terminal of the second switch is electrically connected to the fourth terminal of the control circuit. Specifically, when the charging circuit charges the first capacitor, the discharging circuit discharges the second capacitor; when the charging circuit charges the second capacitor, the discharging circuit discharges the first capacitor.

4. The circuit according to claim 3, characterized in that, The charging circuit includes a voltage source and a first resistor; The positive terminal of the voltage source is electrically connected to the first end of the first resistor and the second end of the control circuit, respectively, and the negative terminal of the voltage source is grounded. The second end of the first resistor is electrically connected to the first end of the first switch, the first end of the second switch, and the first end of the control circuit, respectively. Specifically, when the first control signal is a high-level signal, the voltage source charges the first capacitor through the first resistor; when the second control signal is a high-level signal, the voltage source charges the second capacitor through the first resistor.

5. The circuit according to claim 3, characterized in that, The discharge circuit includes a second resistor, the first end of which is electrically connected to the second end of the first switch and the second end of the second switch, and the second end of the second resistor is grounded. Specifically, when the first control signal is a low-level signal, the first capacitor discharges through the second resistor; when the second control signal is a low-level signal, the second capacitor discharges through the second resistor.

6. The circuit according to claim 4, characterized in that, The control circuit includes a voltage divider circuit, a voltage comparator, and a trigger. The first terminal of the voltage divider circuit is electrically connected to the positive terminal of the voltage source, and the second terminal of the voltage divider circuit is electrically connected to the inverting input terminal of the voltage comparator. The non-inverting input terminal of the voltage comparator is electrically connected to the second terminal of the first resistor, and the output terminal of the voltage comparator is electrically connected to the first terminal of the flip-flop. The second and third terminals of the trigger are both electrically connected to the output terminal of the high-level output circuit. The fourth terminal of the trigger is electrically connected to the fourth terminal of the first switch and the first terminal of the measurement circuit, respectively. The fifth terminal of the trigger is electrically connected to the fourth terminal of the second switch and the second terminal of the measurement circuit, respectively. The high-level output circuit is used to output a high-level signal. The voltage divider circuit is used to output the preset voltage to the voltage comparator. The voltage comparator is used to compare the capacitor voltage and the preset voltage to obtain a comparison result. The trigger outputs the first control signal and the second control signal based on the comparison result.

7. The circuit according to claim 2, characterized in that, The measurement circuit includes a first low-pass filter, a second low-pass filter, and a subtractor; The input terminal of the first low-pass filter is electrically connected to the third terminal of the control circuit, and the output terminal of the first low-pass filter is electrically connected to the first terminal of the subtractor. The input terminal of the second low-pass filter is electrically connected to the fourth terminal of the control circuit, and the output terminal of the second low-pass filter is electrically connected to the second terminal of the subtractor. The first low-pass filter is used to determine the first duty cycle characterization information based on the first control signal, the second low-pass filter is used to determine the second duty cycle characterization information based on the second control signal, and the subtractor is used to determine the current position of the lens based on the difference between the first duty cycle characterization information and the second duty cycle characterization information, and a preset calibration relationship.

8. A chip, characterized in that, The chip includes the capacitor module detection circuit according to any one of claims 1 to 7.

9. An optical lens movement detection device, characterized in that, It includes a capacitor module and a chip as described in claim 8, the chip having a first detection pin and a second detection pin; The capacitor module includes a first capacitor and a second capacitor. The first plates of the first capacitor and the second capacitor are both disposed on the lens. The positions of the second plates of the first capacitor and the second capacitor are fixed. The capacitance values ​​of the first capacitor and the second capacitor change as the lens moves. The first detection pin is electrically connected to the first plate of the first capacitor, and the second detection pin is electrically connected to the first plate of the second capacitor.

10. A camera module, characterized in that, Includes the optical lens movement detection device as described in claim 9.

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