Imaging system and method of operating image sensor

Abstract

The invention relates to an imaging system and a method of operating an image sensor. The imaging system may include an image sensor having an array of pixels arranged in rows and columns. A row driver circuit may be coupled to the pixel and may address a given row of the pixel based on a row address. Row randomization circuitry may be coupled to the row driver circuitry to dither the row address and thus randomize the order of reading out rows of a given column through column lines to sample and hold circuitry, the sample and hold circuitry including a plurality of capacitors for each column. The imaging system may include a multiplexer that de-randomizes the order of the row after passing through the sample and hold circuit. Alternatively or additionally, the order in which the signals from each column are stored using the plurality of capacitors may be randomized. In this manner, fixed pattern noise in the output image may be reduced or eliminated.

Description

Technical Field

[0001] This disclosure relates generally to image sensors, and more specifically to imaging systems and methods of operating image sensors. Background Technology

[0002] Image sensors are commonly used in electronic devices such as mobile phones, cameras, computers, and automobiles to capture images. In a typical arrangement, an image sensor comprises an array of image pixels arranged in rows and columns. Circuitry can be coupled to each pixel column to read out image signals from the image pixels.

[0003] The implementation scheme described in this article emerged in this context. Summary of the Invention

[0004] According to one embodiment, an imaging system is provided. The imaging system includes: an image sensor including a pixel array arranged in rows and columns; a row driver coupled to the pixel array, wherein the row driver is configured to address rows of the pixel array based on row addresses; a row randomization circuit coupled to the row driver, wherein the row randomization circuit is configured to jitter the row addresses; and column lines coupled to the columns of the pixel array, wherein signals from the pixel array are configured to be read out via the column lines based on the jittered row addresses.

[0005] According to another embodiment, an imaging system is provided. The imaging system includes: an image sensor comprising a pixel array arranged in rows and columns; column lines coupled to columns of the pixel array, wherein signals from the pixel array are configured to be read out through the column lines; sample-and-hold circuitry coupled to the column lines, wherein the sample-and-hold circuitry includes at least three capacitors configured to store signals and reset values ​​for each column line; and sample-and-hold control circuitry coupled to the sample-and-hold circuitry, wherein the sample-and-hold circuitry is configured to randomize, frame-by-frame, a pattern using at least three capacitors to store signals and reset values.

[0006] According to another embodiment, a method for operating an image sensor is provided, the image sensor including a pixel array arranged in rows and columns. The method includes: reading a signal from a given column of the pixel array, wherein the rows of the given column are randomized; sampling and holding the signal; storing the signal in a column memory group; and reading the signal from the column memory group, wherein the rows of the given column are derandomized. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an exemplary electronic device with an image sensor according to some implementation schemes.

[0008] Figure 2 This is a schematic diagram of an exemplary pixel array and associated row and column control circuitry for reading image signals from an image sensor, according to some implementation schemes.

[0009] Figure 3 This is a schematic diagram of an exemplary imaging system according to some implementation schemes, including a line randomization circuit coupled to a line driver and an image sensor.

[0010] Figure 4 This is a schematic diagram of an exemplary sampling and holding circuit for an imaging system according to some implementation schemes.

[0011] Figure 5 This is a schematic diagram of an exemplary imaging system including a sampling and holding control circuit according to some implementation schemes, the sampling and holding control circuit being configured to randomize the pattern of the capacitor used for sampling and holding pixel signals.

[0012] Figure 6 This is a schematic diagram of an exemplary sample-and-hold circuit with a capacitor according to some implementation schemes, which can sample and control pixel signals in a random mode.

[0013] Figure 7 It is a table of exemplary randomization patterns for sampling and maintaining pixel signals according to some implementation schemes. Detailed Implementation

[0014] Embodiments of the present invention relate to image sensors. Those skilled in the art will understand that exemplary embodiments of the invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0015] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include image sensors that collect incoming light to capture images. Image sensors may include pixel arrays. Pixels in an image sensor may include photosensitive elements, such as photodiodes, that convert incoming light into image signals. Image sensors may have any number of pixels (such as hundreds, thousands, or more). Typical image sensors may, for example, have hundreds, thousands, or millions of pixels. One million pixels may be referred to as one megapixel. Image sensors may include control circuitry (such as circuitry for operating the pixels) and readout circuitry for reading out image signals corresponding to the charges generated by the photosensitive elements.

[0016] The signal generated by the pixel can be read out via the column lines. A sample-and-hold circuit samples and holds this signal, which can be converted into a digital signal and output from the readout circuit. The sample-and-hold circuit can be shared between pixel columns and may include multiple capacitors for storing and reading out the signal and reset for each column. Due to parasitic differences in these multiple capacitors, if pixels are read out in the same manner in each image frame, row-fixed pattern noise may be present in the output image. Therefore, to reduce or eliminate row-fixed pattern noise, the rows can be randomized (e.g., pseudo-randomized) according to the readout order, and / or the capacitors used to store the signal and reset value can be randomized (e.g., pseudo-randomized).

[0017] Figure 1 This is a schematic diagram of an exemplary imaging and response system, which includes an imaging system that captures images using an image sensor. As an example, Figure 1 System 8 can be an electronic device, such as a camera, cellular phone, video camera, or other electronic device that captures digital image data; it can be a vehicle safety system (e.g., an active braking system or other vehicle safety system); or it can be a surveillance system.

[0018] like Figure 1 As shown, system 8 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 may include camera module 12. Camera module 12 may include one or more image sensors 14, such as those in an image sensor array integrated circuit, and one or more lenses. During image capture operation, each lens may focus light onto its associated image sensor 14. Image sensor 14 may include photosensitive elements (e.g., image sensor pixels) that convert light into analog data. Image sensors may have any number (such as hundreds, thousands, millions, or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., megapixels).

[0019] Each image sensor in camera module 12 may be identical, or different types of image sensors may exist in a given image sensor array integrated circuit. In some examples, image sensor 14 may also include bias circuitry (e.g., source follower load circuitry), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), and / or addressing circuitry.

[0020] Still and video image data from image sensor 14 can be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 can be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, or face detection. Image processing and data formatting circuitry 16 can additionally or alternatively be used to compress raw camera image files when needed, such as compressing raw camera image files to Joint Photographic Experts Group (JPEG) format.

[0021] In one example arrangement (such as a system-on-a-chip (SoC) arrangement), the image sensor 14 and the image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (such as a common silicon image sensor integrated circuit die). However, if desired, the image sensor 14 and the image processing and data formatting circuitry 16 can be formed on a separate semiconductor substrate. For example, the image sensor 14 and the image processing and data formatting circuitry 16 can be formed on separate, stacked substrates.

[0022] Imaging system 10 can transmit acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include input-output devices 22 and storage and processing circuitry 24. Host subsystem 20 may include processing software for detecting objects in the image, detecting motion of objects between image frames, determining distances to objects in the image, or filtering or otherwise processing the image provided by imaging system 10. For example, image processing and data formatting circuitry 16 of imaging system 10 can transmit acquired image data to storage and processing circuitry 24 of host subsystem 20.

[0023] If needed, system 8 can provide users with many advanced functions. For example, in a computer or mobile phone, it can provide users with the ability to run user applications. For these functions, the input-output devices 22 of the host subsystem 20 may include a keyboard, input-output ports, buttons, and a display, as well as storage and processing circuitry 24. The storage and processing circuitry 24 of the host subsystem 20 may include volatile memory and / or non-volatile memory (e.g., random access memory, flash memory, hard disk drive, and / or solid-state drive, etc.). The storage and processing circuitry 24 may additionally or alternatively include a microprocessor, microcontroller, digital signal processor, and / or application-specific integrated circuit.

[0024] Figure 2 It shows Figure 1 An example of the arrangement of the image sensor 14. For example... Figure 2 As shown, the image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44 (sometimes referred to herein as control and processing logic) may be... Figure 1The image sensor 14 may be part of or separate from the image processing and data formatting circuitry 16. The image sensor 14 may include a pixel array, such as an array 32 of pixels 34 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels). The control and processing circuitry 44 may be coupled to the row control circuitry 40 via control path 27 and to the column control and readout circuitry 42 via data path 26.

[0025] The line control circuit 40 can receive a line address from the control and processing circuit 44 and can provide the corresponding line control signal to the image pixel 34 through one or more control paths 36. The line control signal may include a pixel reset control signal, a charge transfer control signal, an overflow control signal, a line selection control signal, a double conversion gain control signal, and / or any other desired pixel control signal.

[0026] Column control and readout circuitry 42 may be coupled to one or more columns of pixel array 32 via one or more wires (such as column lines 38). A given column line 38 may be coupled to a column of image pixels 34 in image pixel array 32 and may be used to read image signals from image pixels 34 and to provide bias signals (e.g., bias current or bias voltage) to image pixels 34. Alternatively, a single column line 38 may be coupled to multiple columns of pixel array 32, or multiple column lines 38 may be coupled to a single column of pixel array 32. In some examples, each pixel column may be coupled to a corresponding column line 38. For image pixel readout operations, row control circuitry 40 may be used to select a pixel row in image pixel array 32, and image data associated with the image pixels 34 of that pixel row may be read out by column control and readout circuitry 42 on column line 38. The column control and readout circuit 42 may include column circuitry, such as a column amplifier for amplifying the signal read from array 32, a sample-and-hold circuit for sampling and storing the signal read from array 32, an analog-to-digital converter circuit for converting the read analog signal into a corresponding digital signal, and / or a column memory for storing the readout signal and any other desired data. The column control and readout circuit 42 can output the digital pixel readout value to the control and processing circuit 44 via data path 26.

[0027] Array 32 may have any number of rows and columns. Generally, the size of array 32 and the number of rows and columns in array 32 will depend on the specific implementation of image sensor 14. Although rows and columns are generally described herein as horizontal and vertical, respectively, rows and columns may refer to any grid-like structure. Features described herein as rows may be arranged vertically, and features described herein as columns may be arranged horizontally.

[0028] Pixel array 32 may include a color filter array with multiple color filter elements, which allows a single image sensor to sample different colors of light. For example, image sensor pixels (such as image pixels in array 32) may include a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels. The red, green, and blue image sensor pixels may be arranged in a Bayer mosaic pattern. A Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite each other and adjacent to a red image pixel diagonally opposite a blue image pixel. In another example, wideband image pixels with wideband color filter elements (e.g., transparent color filter elements) may be used instead of green pixels in the Bayer pattern. These examples are merely illustrative, and in general, color filter elements of any desired color (e.g., cyan, yellow, red, green, or blue) and any desired pattern can be formed on any desired number of image pixels 34. Alternatively or additionally, image pixel 34 may be sensitive to infrared wavelengths (or other suitable wavelengths) and may be provided with color filter elements corresponding to those wavelengths.

[0029] The sample-and-hold circuitry in column control and readout circuitry 42 may include multiple capacitors (e.g., six capacitors) for each pair of columns in pixel array 32. For example, column control and readout circuitry 42 may include three capacitors for even-numbered output columns and three capacitors for odd-numbered output columns. Including three capacitors (or another suitable number of capacitors) for each column readout allows sampling and holding of reset and signals for each column on two of the capacitors, while pre-charging the remaining capacitors to a fixed level to remove any residual charge from the previous row. By reading columns in this manner, signals from multiple rows can be serially read out via a single parallel readout.

[0030] However, if the sample-and-hold cycle uses a pattern that repeats every three rows (e.g., due to a repeating pattern of sample-and-hold for three capacitors per column), any mismatch (e.g., non-idealities) between capacitors (e.g., parasitic effects of capacitors) can lead to gain and bias errors between row readouts. As a result, there may be row-fixed pattern noise that repeats every three rows in the output image.

[0031] To reduce or eliminate fixed-pattern noise, row selection can be jittered during readout. In other words, rows can be read out randomly instead of sequentially. Therefore, any repetitive cycles of fixed-pattern noise can be larger (e.g., more than once every three rows) and less noticeable to the viewer of the output image, or the fixed-pattern noise can be eliminated. An illustrative example of a camera module that includes row randomization circuitry to reduce or eliminate fixed-pattern noise is as follows: Figure 3 As shown.

[0032] like Figure 3 As shown, the imaging system 10 may include a row randomization circuit 46. The row randomization circuit 46 may be coupled to a row address adjustment circuit 48, which may also (e.g., from...) Figure 2 The control and processing circuit 44) receives the row address 47. The row driver 50 is coupled to the row address adjustment circuit 48 and is coupled to the row of the pixel array 32 via line 52.

[0033] The columns of pixel array 32 are coupled to column lines 38. Column lines 38 are coupled to column bias circuit 54, which in turn is coupled to sample and hold circuit 56. Sample and hold circuit 56 is coupled to multiplexer (MUX) 58. The output of MUX 58 is coupled to amplifier 60 and analog-to-digital converter (ADC) 62. The output of ADC 62 is coupled to demultiplexer (DEMUX) 64, and the output of DEMUX 64 is coupled to column memory bank 66.

[0034] The column memory bank 66 can be coupled to the MUX 68. The row randomization circuitry 46 can also be coupled to the MUX 68 via the MUX control circuitry 70. The output 72 of the MUX 68 can be a digital signal corresponding to the signal generated by the pixel array 32, and the output 72 can be output to a digital data path (e.g., ...). Figure 1 (Path 18 or another suitable data path).

[0035] although Figure 3The pixel array 32 is not shown, but can be read out through the cut-out columns. In other words, column lines 38 can carry half of the output of array 32 (e.g., the lower half of array 32). A second set of column lines, column bias circuitry, sample-and-hold circuitry, MUX, amplifier, ADC, DEMUX, column memory bank, and MUX can be used to read out the output from the other half of array 32 (e.g., the upper half of array 32). However, this is merely illustrative. In some embodiments, column lines 38 can carry the entire output of array 32. Alternatively, column lines 38 can carry one-quarter of the output of array 32, and the output can be read out from the other quarter of array 32 using three additional sets of column lines, column bias circuitry, sample-and-hold circuitry, MUX, amplifier, ADC, DEMUX, column memory bank, and MUX. In general, array 32 can be divided into any desired number of sections, which are read out using column line sets, column bias circuitry, sample-and-hold circuitry, MUX, amplifier, ADC, DEMUX, column memory bank, and MUX.

[0036] In operation, the row randomization circuit 46 can generate random codes (e.g., pseudo-random codes) on a per-frame basis (or at another suitable interval). In some embodiments, for example, the row randomization circuit 46 can be a pseudo-random binary sequence (PRBS) generator. The random code can be input to the row address adjustment circuit 48 along with the row address 47. Based on the random code, the row address adjustment circuit 48 can jitter the row address (e.g., jitter the original value of the row address 47). The random code generated by the row randomization circuit 46 and the jitter performed by the row address adjustment circuit 48 can be of a suitable length such that they do not repeat on a per-frame basis. For example, the random code and the jitter can have at least 10 least significant bits (LSBs), at least 15 LSBs, at least 20 LSBs, a length between 10 and 30 LSBs, or another suitable length. As an example, the row randomization circuit 46 can randomize all rows using a two-row set (e.g., two consecutive rows), a four-row set (e.g., four consecutive rows), an eight-row set (e.g., eight consecutive rows), or a 16-row set (e.g., 16 consecutive rows). However, this is merely illustrative. Dithering can be repeated within an image frame if desired. Generally, the dithering of row addresses can be long enough to avoid short rows with fixed noise patterns.

[0037] A jittered row address can be provided to row driver 50, which can then select rows for reading via line 52. In other words, row driver 50 can address rows of array 32 based on row addresses. Due to the jittered row address provided to row driver 50, the read will be jittered.

[0038] The output of the pixels of array 32 can be read through column lines 38 (e.g., where the rows of the columns are randomized based on jittered row addresses) and passed through column bias circuitry 54, which supplies a bias signal (e.g., bias current or bias voltage) to the columns. The output of column bias circuitry 54 can be passed to sample-and-hold circuitry 56. Sample-and-hold circuitry 56 may include multiple capacitors for even and odd columns of column lines 38, and a shared amplifier and ADC for the multiple column lines 38. The capacitors in sample-and-hold circuitry 56 sample and store the output of the pixels of array 32. Figure 4 An exemplary example of the sample-and-hold circuit 56 is shown.

[0039] like Figure 4 As shown, a portion of the sample-and-hold circuit 56 receives input along column line 74A from the first column (e.g., even column) of array 32 and along column line 74B from the second column (e.g., odd column) of array 32. Column line 74A can be coupled to three capacitors: capacitor Ce0 76A, capacitor Ce1 78A, and capacitor Ce2 80A. Switches 82A, 84A, and 86A can control the sample-and-hold operation of capacitors Ce0 76A, Ce1 78A, and Ce2 80A, respectively.

[0040] Similarly, line 74B can be coupled to three capacitors: capacitor Co0 76B, capacitor Co1 78B, and capacitor Co2 80B. Switches 82B, 84B, and 86B can control the sampling and holding operations of capacitors Co0 76B, Co1 78B, and Co2 80B, respectively.

[0041] The outputs of capacitors 76, 78, and 80 can be coupled to amplifier 92, which in turn can be coupled to switch 94, and this switch is coupled to output lines 97A and 97B via switches 96A and 96B, respectively. The base plates of capacitors 76, 78, and 80 can be coupled to ground.

[0042] The sample and hold circuit 56 may also include bypass lines 88A and 88B, respectively coupled to column lines 74A and 74B. Each bypass line 88A and 88B may include one or more corresponding switches, such as switches 90A and 90B, and may be coupled to output lines 97A and 97B.

[0043] In operation, the sample-and-hold circuit 56 samples and holds row readouts for the column associated with column line 74A and the column associated with column line 74B. Specifically, for each row read out, each capacitor 76, 78, and 80 holds one of a presampled signal, a reset value, or a signal associated with a reset in the same row or a reset from the next row. The sample-and-hold circuit 56 cyclically uses each capacitor 76, 78, and 80 for each of the presampled signal, the reset value, and the signal associated with a reset in the current row or a reset from the next row. In some embodiments, this cycle (e.g., a pattern) may repeat once every three rows within a given image frame.

[0044] Sample and hold circuit 56 may include Figure 4 The portion shown represents each set of two columns (e.g., each set of odd and even columns) of array 32. However, the shared sample-and-hold circuitry 56 between each set of odd and even columns of array 32 is merely illustrative. In some embodiments, for example, the sample-and-hold circuitry 56 may be shared among four columns, at least one column, at least two columns, or any other suitable number of columns, where each column has three (or more) capacitors. Furthermore, if array 32 has a cutout, the sample-and-hold circuitry 56 may be replicated for the top portion of array 32.

[0045] although Figure 4 A sample-and-hold circuit 56 with three capacitors for each column of array 32 is shown, but this is merely illustrative. In some embodiments, as an example, the sample-and-hold circuit 56 may have at least two, at least three, at least four, or at least five capacitors for each column.

[0046] Back Figure 3 The output of the sample-and-hold circuit 56 can be passed to a MUX 58, which can multiplex the output of the sample-and-hold circuit 56. For example, the output lines 97A and 97B of the sample-and-hold circuit 56... Figure 4 The signal can be passed to a single amplifier 60 and ADC 62 via MUX 58. The multiplexed output can be amplified by amplifier 60 and converted from an analog signal to a digital signal by ADC 62. DEMUX 64 can then demultiplex the digital signal from ADC 62.

[0047] Column memory group 66 can store digital signals. For example, as an example, column memory group 66 may include four groups of column memories to store four rows of digital signals, or eight groups of column memories to store eight rows of digital signals. Generally, column memory group 66 may include any suitable number of groups of column memories, such as at least two groups, at least three groups, at least four groups, at least eight groups, or another suitable number of groups of column memories. In some embodiments, the number of column memory groups 66 may correspond to the number of rows randomized by row randomization circuit 46 (e.g., a set of four rows, a set of eight rows, or a set of 16 rows, as an example).

[0048] The storage of column memory bank 66 can be selected by multiplexer (MUX) control circuitry 70 (via MUX 68) in response to a signal from row randomization circuitry 46. Specifically, MUX control circuitry 70 can control MUX 68 to read signals from column memory bank 66 based on the jittered row address from row randomization circuitry 46. In other words, row randomization circuitry can control MUX 68 to read the correct signal from column memory bank 66 for the currently jittered row (e.g., signals from column memory bank 66 can be read based on inputs from row randomization circuitry 46, where rows are derandomized in each column). The output of MUX 68 can be read via output line 72 to the digital data path.

[0049] By randomizing the output of the rows of pixel array 32, any row noise caused by the sequential readout of sample-and-hold circuit 56 (e.g., row noise repeated every three rows due to the three-capacitor set in sample-and-hold circuit 56) can be prevented from being repeated in the resulting output image (or reduced). In other words, due to the randomization of the row readout, even due to capacitors 76, 78, and 80 ( Figure 4 Due to the non-ideal nature of the output image, some noise exists, which will not appear in a fixed pattern. This randomization also corrects for mismatches between column circuits, thus reducing or eliminating column fixed-pattern noise.

[0050] although Figure 3 Row readouts have been shown and described using jitter with row randomization circuit 46, but this is merely illustrative. In some implementations, a counter, a shift register with randomization mode, or other suitable randomizer may be used to randomize row readouts and reduce or eliminate row fixed-mode noise.

[0051] although Figure 3An imaging system 10 is shown, including a MUX 58 coupled to an amplifier 60, which is coupled to an ADC 62, which is coupled to a DEMUX 64; however, this arrangement is merely illustrative. In some embodiments, the MUX 58 and DEMUX 64 may be omitted from the imaging system 10. Alternatively, the MUX 58 may be incorporated between the array 32 and the sample-and-hold circuitry 56. Generally, the imaging system 10 may include any suitable readout components arranged in any suitable order.

[0052] although Figure 3 An imaging system 10 with row randomization circuitry 46 is shown to randomize the output of rows within pixel array 32 and reduce or eliminate row fixed-pattern noise, but this is merely illustrative. If desired, the output of columns within pixel array 32 can be randomized instead of the row outputs or in addition to the row outputs to reduce or eliminate column fixed-pattern noise.

[0053] In some implementations, it may be necessary to read the odd and even rows of array 32 sequentially. In these implementations, row readouts may be jittered (e.g., two rows may be jittered at a time).

[0054] If necessary, other correction methods may be performed in addition to row readout randomization. For example, black level correction (bias) and / or sample-and-hold calibration (e.g., gain and bias) may be performed concurrently with row readout randomization.

[0055] Row read randomization can be disabled and enabled as needed during or between reads of array 32. For example, row randomization circuitry 46 can (e.g., via...) Figure 2 The control and processing circuit 44) controls and switches to the form of non-jittering row address 47.

[0056] Instead of randomizing the row readouts of array 32, or in addition to randomizing the row readouts of the array, the sample and hold circuit capacitors can be randomized (e.g., pseudo-randomized) to reduce or eliminate fixed-pattern noise. Figure 5 An exemplary example of an imaging system with a sample-and-hold circuit controller for randomizing the sample-and-hold cycle is shown.

[0057] like Figure 5 As shown, the imaging system 10 may include a sample and hold control circuit 100 coupled to the sample and hold circuit 101. The imaging system 10 may have an output 102 directly from the DEMUX 64, or the imaging system 10 may have a column memory group 66 between the DEMUX 64 and the output 102, such as... Figure 3 As shown.

[0058] The sample-and-hold control circuit 100 may randomly (e.g., pseudo-randomly) change the capacitor cycle of the sample-and-hold circuit 101 frame by frame (or at another suitable interval). Specifically, the sample-and-hold circuit 101 may include a capacitor on which signals from column line 38 are sampled and stored. Figure 6 An illustrative example of a portion of the sample and hold circuit 101 is shown.

[0059] like Figure 6 As shown, the sample-and-hold circuit 101 may include an input 103 coupled to a multiplexer (MUX) 104. The input 103 may be coupled to one or more column lines 38. Figure 5 For example, input 103 can be coupled to a column line 38 (e.g., an odd column line or an even column line). Although Figure 6 Not shown, but the sample and hold circuit 101 may include a total of six (or more) capacitors, with three (or more) capacitors per column line 38 (e.g., as shown in Figure 1). Figure 4 (As shown). In these embodiments, the sample-and-hold circuit 101 may have a portion shared across the column output lines 38 (e.g., shared between odd and even column output lines 38, such as...). Figure 4 (As shown).

[0060] The MUX 104 can be coupled to capacitors C1 106A, C2 106B, and C3 106C, which in turn can be coupled to the DEMUX 108. The base plates of capacitors C1 106A, C2 106B, and C3 106C can be coupled to ground. The output of the DEMUX 108 can be coupled to output line 110.

[0061] After multiplexing using MUX 104, the signal received via input line 103 can be passed to one or more of capacitors C1106A, C2106B, and / or C3106C. Specifically, two of capacitors C1106A, C2106B, and C3106C can hold the pre-sampled signal and reset value, while the remaining capacitor samples the signal associated with the reset in the current line or from the reset in the next line. If the capacitors used for reset and signal values ​​are reused (e.g., every three lines) and repeated line readouts are performed, line fixed-pattern noise will be seen in the output image. Therefore, the use of capacitor 106 can be changed frame-by-frame (or on another suitable basis) randomly (e.g., pseudo-randomly) to reduce or eliminate fixed-pattern noise. An illustrative example of changing the use of capacitor 106 is provided in [the original text]. Figure 7 As shown in the chart.

[0062] like Figure 7As shown, in frame M, the reset (R) of line N can be stored on capacitor C3 106C, while the signal (S) of line N can be stored on capacitor C1 106A. The reset of line N+1 can be stored on capacitor C2 106B, while the signal of line N+1 can be stored on capacitor C3 106C. The reset of line N+2 can be stored on capacitor C1 106A, while the signal of line N+2 can be stored on capacitor C2 106B. The reset of line N+3 can be stored on capacitor C3 106C, while the signal of line N+3 can be stored on capacitor C1 106A. The reset of line N+4 can be stored on capacitor C2 106B, while the signal of line N+4 can be stored on capacitor C3 106C. The reset of line N+5 can be stored on capacitor C1 106A, while the signal of line N+5 can be stored on capacitor C2 106B. This mode can continue for each line N of frame M. In other words, the capacitor 106 storing the reset and signal values ​​in frame M can be changed between each line N, and this pattern can be repeated every three lines.

[0063] Relative to frame M, for each line of frame M+1, the capacitors storing the signal and reset value can be changed randomly (e.g., pseudo-randomly). Figure 7 In the example, in frame M+1, the reset of line N can be stored on capacitor C2 106B, while the signal of line N can be stored on capacitor C1 106A. The reset of line N+1 can be stored on capacitor C3 106C, while the signal of line N+1 can be stored on capacitor C2 106B. The reset of line N+2 can be stored on capacitor C1 106A, while the signal of line N+2 can be stored on capacitor C3 106C. The reset of line N+3 can be stored on capacitor C2 106B, while the signal of line N+3 can be stored on capacitor C1 106A. The reset of line N+4 can be stored on capacitor C3 106C, while the signal of line N+4 can be stored on capacitor C2 106B. The reset of line N+5 can be stored on capacitor C1 106A, while the signal of line N+5 can be stored on capacitor C3 106C. This mode can continue for each line N of frame M+1. In other words, the capacitor 106 storing the reset and signal values ​​in frame M+1 can be changed between each row N, and this pattern can be repeated every three rows. However, the pattern of frame M+1 can be changed randomly (e.g., pseudo-randomly) relative to the pattern of the capacitor used in frame M.

[0064] Similarly, relative to frames M and M+1, for each line of frame M+2, the capacitors storing the signal and reset value can be changed randomly (e.g., pseudo-randomly). Figure 7In the example, in frame M+2, the reset of line N can be stored on capacitor C3106C, while the signal of line N can be stored on capacitor C2106B. The reset of line N+1 can be stored on capacitor C1106A, while the signal of line N+1 can be stored on capacitor C3106C. The reset of line N+2 can be stored on capacitor C2106B, while the signal of line N+2 can be stored on capacitor C1106A. The reset of line N+3 can be stored on capacitor C3106C, while the signal of line N+3 can be stored on capacitor C2106B. The reset of line N+4 can be stored on capacitor C1106A, while the signal of line N+4 can be stored on capacitor C3106C. The reset of line N+5 can be stored on capacitor C2106B, while the signal of line N+5 can be stored on capacitor C1106A. This mode can continue for each line N of frame M+2. In other words, the capacitor 106 storing the reset and signal values ​​in frame M+2 can be changed between each row N, and this pattern can be repeated every three rows. However, the pattern of the capacitor used in frames M and M+1 can be changed randomly (e.g., pseudo-randomly).

[0065] The mode of the capacitors used to store the signals and reset values ​​in each row can be changed randomly (e.g., pseudo-randomly) between frames. By changing the mode between frames, the line-fixed pattern noise that would otherwise be caused by using capacitors C1, C2, and C3 in a rotating mode (e.g., the same mode for each frame) can be reduced or eliminated. Specifically, as Figure 7 As shown, for row N of frame M, the difference between the row value and the signal value is dC1-dC3; for row N of frame M+1, the difference is dC1-dC2; and for row N of frame M+2, the difference is dC2-dC3. Adding these differences together yields a multi-frame average of zero. For... Figure 7 This applies to all the rows shown. In other words, by randomly changing the capacitor storage pattern between image frames, row fixed-pattern noise can be reduced or eliminated. In some implementations, for example, fixed-pattern noise can be reduced to below thermal / temporal noise, such as below 20 dB. However, this is merely illustrative. In general, fixed-pattern noise can be reduced below any suitable threshold.

[0066] Back Figure 6 MUX 104 and DEMUX 108 can be used to randomize capacitor modes between frames. Specifically, MUX 104 can multiplex signals and reset signals to capacitor 106, and DEMUX 108 can demultiplex signals and reset signals, which can be passed to output 110.

[0067] although Figure 6 and 7A sample-and-hold circuit 101, including three capacitors 106 for a single column line, is shown and described, but this is merely illustrative. In some embodiments, the sample-and-hold circuit may include more capacitors, such as four or five capacitors per column line. Therefore, the randomization of capacitor usage between frames can be increased to further reduce fixed-pattern line noise.

[0068] although Figure 6 and 7 The capacitor storage pattern in the randomized sample-and-hold circuit 101 is shown and described to reduce or eliminate row fixed-pattern noise, but this is merely illustrative. If needed, the capacitors used to store the column outputs within the pixel array 32 can be randomized instead of the row outputs or in addition to the row outputs to reduce or eliminate column fixed-pattern noise.

[0069] In some implementation schemes, Figure 3 Row randomization (using Figure 4 The associated sample and hold circuit 56) can be connected with Figure 5 and Figure 6 The capacitor mode randomization combination. In other words, a single imaging system 10 may include a row randomization circuit 46, a row address adjustment circuit 48, and a MUX control circuit 70. Figure 3 ) and sampling and holding control circuit 100 ( Figure 5 In this way, fixed-mode noise can be further reduced.

[0070] The above description is merely illustrative and various modifications can be made to the described implementation scheme. The above implementation scheme can be implemented individually or in any combination.

Claims

1. An imaging system, characterized in that, The imaging system includes: An image sensor comprising a pixel array arranged in rows and columns; A row driver coupled to the pixel array, wherein the row driver is configured to address rows of the pixel array based on row addresses; A row randomization circuit, coupled to the row driver, wherein the row randomization circuit is configured to jitter the row address; and Column lines, which are coupled to columns of the pixel array, wherein signals from the pixel array are configured to be read out via the column lines based on jittered row addresses.

2. The imaging system according to claim 1, characterized in that, The imaging system also includes: A column memory group, the column memory group being coupled to the column lines; A multiplexer, the multiplexer being coupled to the output of the column memory group; and A multiplexer control circuit is coupled between the multiplexer and the row randomization circuit, wherein the multiplexer control circuit is configured to control the multiplexer to read the signal based on a jittered row address.

3. The imaging system according to claim 2, characterized in that, The imaging system also includes: A sampling and holding circuit coupled to the column lines between the pixel array and the column memory group, wherein the sampling and holding circuit includes at least three capacitors coupled to each of the column lines.

4. The imaging system according to claim 3, wherein, The column memory group comprises four column memory groups.

5. The imaging system according to claim 4, characterized in that, The imaging system also includes: An amplifier, the amplifier being coupled to the sample and hold circuit; and An analog-to-digital converter (ADC) coupled to the amplifier, wherein each amplifier in the amplifier and each ADC in the ADC are shared between two column lines in the column lines.

6. The imaging system according to claim 1, wherein, The row randomization circuit includes a pseudo-random binary sequence generator.

7. The imaging system according to claim 6, characterized in that, The imaging system also includes: A row address adjustment circuit is configured to jitter the row address based on a random code generated by the pseudo-random binary sequence generator.

8. The imaging system according to claim 1, wherein, The row randomization circuit is configured to randomize the order in which rows in each set of four rows are read.

9. The imaging system according to claim 1, characterized in that, The imaging system also includes: A sample-and-hold circuit coupled to the column lines, wherein the sample-and-hold circuit includes at least three capacitors configured to store the signal and reset value for each of the column lines; and A sample and hold control circuit coupled to the sample and hold circuit, wherein the sample and hold control circuit is configured to randomize the pattern of storing the signal and the reset value using the at least three capacitors frame by frame.

10. The imaging system according to claim 9, wherein, The mode of using the at least three capacitors to store the signal and the reset value is configured to repeat once every three lines within a given image frame.

11. An imaging system, characterized in that, The imaging system includes: An image sensor comprising a pixel array arranged in rows and columns; Column lines, which are coupled to columns of the pixel array, wherein signals from the pixel array are configured to be read out through the column lines; A sample-and-hold circuit coupled to the column lines, wherein the sample-and-hold circuit includes at least three capacitors configured to store the signal and reset value for each of the column lines; and A sample and hold control circuit coupled to the sample and hold circuit, wherein the sample and hold circuit is configured to randomize the pattern of storing the signal and the reset value using the at least three capacitors frame by frame.

12. The imaging system according to claim 11, wherein, The sample-and-hold control circuit is configured to pseudo-randomly randomize the pattern of storing the signal and the reset value using the at least three capacitors.

13. The imaging system according to claim 11, wherein, The sample and hold circuit includes at least four capacitors configured to store the signal and the reset value for each of the column lines, and the sample and hold circuit is configured to randomize the pattern of storing the signal and the reset value using the at least four capacitors frame by frame.

14. The imaging system according to claim 11, characterized in that, The imaging system also includes: A row driver circuit coupled to the pixel array, wherein the row driver circuit is configured to address rows of the pixel array based on row addresses; and A row randomization circuit coupled to the row driver circuit, wherein the row randomization circuit is configured to jitter the row address, and the signal from the pixel array is configured to be read out through the column lines based on the jittered row address.

15. The imaging system according to claim 14, characterized in that, The imaging system also includes: A column memory group, the column memory group being coupled to the column lines; A multiplexer, the multiplexer being coupled to the output of the column memory group; and A multiplexer control circuit is coupled between the multiplexer and the row randomization circuit, wherein the multiplexer control circuit is configured to control the multiplexer to read the signal based on a jittered row address.

16. A method of operating an image sensor, said image sensor comprising a pixel array arranged in rows and columns, characterized in that, The method includes: The signal is read from a given column of the pixel array, wherein the rows of the given column are randomized; Sample and hold the signal; The signal is stored in a column memory group; and The signal is read from the column memory group, wherein the row of the given column is derandomized.

17. The method according to claim 16, characterized in that, The method further includes: Using a row randomization circuit, the row address used to address the rows of the pixel array is jittered to randomize the row of the given column.

18. The method according to claim 17, characterized in that, The method further includes: The row randomization circuit is used to control the reading of the signal from the column memory group.

19. The method of claim 17, wherein, Sampling and holding the signal includes sampling and holding the signal from the given column on at least three capacitors, as well as a reset value for the given column.

20. The method according to claim 19, characterized in that, The method further includes: The pattern of storing the signal and the reset value using the at least three capacitors is randomized frame by frame.

Images