Image sensor and signal processing method

Abstract

The embodiment of the invention provides an image sensor and a signal processing method, and the image processor comprises a pixel array module which comprises a pixel array composed of a plurality of pixel units arranged in an array, and each pixel unit is used for converting incident light into photo-generated charges and accumulating the photo-generated charges; the memristor calculation array module comprises a memristor calculation array formed by a plurality of memristor rows, and each memristor row comprises a plurality of memristors; the analog calculation and reading module is connected to the output end of the memristor row and is used for converting the charge signal into a voltage signal and outputting the voltage signal; the analog calculation and reading modules are in one-to-one correspondence with the memristor rows; and the time sequence and control module is used for generating a control signal so as to coordinate the operation of the pixel array module and the memristor calculation array module. According to the image sensor in the embodiment of the invention, the operation power consumption of the image sensor can be reduced, and the processing time delay is reduced.

Description

Technical Field

[0001] This application belongs to the field of image processing technology, and in particular relates to an image sensor and a signal processing method. Background Technology

[0002] Image sensors, especially CMOS (Complementary Metal Oxide Semiconductor) image sensors, are key devices for acquiring visual information. They convert incident light into an analog voltage signal. This analog voltage signal is then converted into a digital signal by an analog-to-digital converter and transmitted to a digital signal processor for a series of image processing operations, such as noise reduction, white balance, and sharpening.

[0003] However, the aforementioned traditional architecture has inherent performance bottlenecks. First, the analog-to-digital conversion process itself consumes a lot of power, especially in high-resolution, high-frame-rate applications, becoming one of the main contributors to system power consumption and introducing a significant signal readout delay. Second, subsequent signal processing in the digital domain, particularly matrix operations (such as convolution filtering), requires extensive computation in the digital signal processor, further increasing the overall system power consumption and processing latency. This serial, separate "sensing-conversion-processing-output" architecture limits the application of image sensing systems in power-sensitive and real-time-critical edge computing scenarios. Summary of the Invention

[0004] This application provides an image sensor and a signal processing method that can reduce the operating power consumption of the image sensor and reduce processing latency.

[0005] In a first aspect, embodiments of this application provide an image sensor, including: The pixel array module includes a pixel array consisting of multiple pixel units arranged in an array, each pixel unit being used to convert incident light into photogenerated charge and accumulate it; The memristor computing array module includes a memristor computing array consisting of multiple rows of memristors. Each row of memristors includes multiple memristors, and the conductance value of each memristor can be programmed and retained. The analog calculation and readout module is connected to the output terminal of the memristor row and is used to convert the charge signal into a voltage signal and output it; the analog calculation and readout module corresponds one-to-one with the memristor row; The timing and control module generates control signals to coordinate the exposure and charge transfer operations of the pixel array module and the computational operations of the memristor computation array module. In this module, each column output of the pixel array module is connected to the corresponding column of the memristor computing array module through a column line. Under the control of the timing and control module, the charge accumulated in the pixel array module can be transferred to the memristor computing array module, and the simulation calculation is completed in the memristor computing array module through charge redistribution.

[0006] In one feasible implementation, the pixel unit includes: A photodiode, wherein its first electrode is connected to a first voltage terminal and its second electrode is connected to a first node; The first capacitor has its first terminal connected to the first node and its second terminal connected to the second voltage terminal. A row selection switch, with its first end connected to the first node and its second end connected to the column line, and its control end used to receive the row selection signal; The reset switch has its first terminal connected to the power supply voltage terminal, its second terminal connected to the column line, and its control terminal used to receive the reset signal. Among them, the photodiode is used to accumulate photogenerated charge at the first node during exposure, and the row selection switch is used to turn on during the charge transfer stage, so that the first node is coupled to the memristor computing array module through the column line.

[0007] In one feasible implementation, the image processor further includes a plurality of column line capacitors; a first end of each column line capacitor is electrically connected to the column line of the column in which it resides, and a second end is electrically connected to a first fixed potential node; wherein, during the charge transfer phase, the charge on the first capacitor within the pixel unit is shared with the column line capacitor.

[0008] In one feasible implementation, the image processor has a charge transfer isolation switch on each column line; The first terminal of the charge transfer isolation switch is electrically connected to the column line capacitor of the column, the second terminal is electrically connected to the column line of the column, and the control terminal is connected to the timing and control module to receive the charge transfer isolation signal. The charge transfer isolating switch is used to turn on when charge transfer is isolated and to turn off when charge transfer is on.

[0009] In one feasible implementation, the sum of the conductance values ​​of all memristors in each column of the memristor computing array module is equal to the sum of the conductance values ​​of all memristors in any different column.

[0010] In one feasible implementation, the first terminal of the memristor in each row is electrically connected to the column line capacitor of the column containing the memristor, and the second terminal is electrically connected to the input terminal of the analog calculation and readout module of the row containing the memristor.

[0011] In one feasible implementation, the analog calculation and readout module includes a second capacitor and an amplifier connected across the output of the memristor row, the amplifier being in virtual ground mode; The simulation calculation and readout module includes: The amplifier has its non-inverting input terminal electrically connected to the second fixed potential node, its inverting input terminal electrically connected to the second terminal of the memristor in the row where the analog calculation and readout module is located, and its output terminal serves as the voltage signal output terminal of the analog calculation and readout module. The second capacitor has its first end electrically connected to the inverting input terminal and its second end electrically connected to the output terminal of the amplifier. The amplifier is configured in virtual ground mode, making the inverting input terminal and the non-inverting input terminal at the same potential. The second capacitor is used to accumulate the charge flowing into the corresponding output row of the memristor calculation array module and generate a voltage signal at its second terminal that is proportional to the amount of accumulated charge.

[0012] Secondly, embodiments of this application provide a signal processing method based on an image sensor, wherein the image sensor is any one of the image sensors described above, and the method includes: The pixel array is controlled to expose the light, converting the incident light into photocharge and accumulating it. After exposure, a charge transfer path is established between the pixel array and the memristor computing array to transfer the accumulated charge from the pixel array to the memristor computing array. Disconnect the charge transfer path to electrically isolate the pixel array from the memristor computing array; The charge temporarily stored on each column line is discharged and redistributed through a memristor computing array; wherein, the memristor computing array includes multiple memristors with pre-programmed conductance values, and the charge is accumulated on each output row according to the conductance value. The accumulated charge signals on each output row of the memristor computing array are converted into voltage signals and output.

[0013] In one feasible implementation, the pixel unit includes: A photodiode, wherein its first electrode is connected to a first voltage terminal and its second electrode is connected to a first node; The first capacitor has its first terminal connected to the first node and its second terminal connected to the second voltage terminal. A row selection switch, with its first end connected to the first node and its second end connected to the column line, and its control end used to receive the row selection signal; The reset switch has its first terminal connected to the power supply voltage terminal, its second terminal connected to the column line, and its control terminal used to receive the reset signal. The image sensor also includes multiple column line capacitors; the first end of each column line capacitor is electrically connected to the column line of the column in which it is located, and the second end is electrically connected to a fixed potential node; A charge transfer isolation switch is provided on each column line. The first end of the charge transfer isolation switch is electrically connected to the column line capacitor of the column, the second end is electrically connected to the column line of the column, and the control end is connected to the timing and control module to receive the charge transfer isolation signal. The first terminal of each memristor in each row is electrically connected to the column line capacitor of the column containing the memristor, and the second terminal is electrically connected to the input terminal of the analog calculation and readout module of the row containing the memristor. Establishing a charge transfer path between the pixel array and the memristor computing array includes: The row selection signal is received through the row selection switch in the pixel array to connect the first node of the corresponding row and the column line of the column in the pixel array. The charge transfer isolation signal is received through the charge transfer isolation switch to turn on the isolation switch connected to the column line of the column to connect the column line of the column to the corresponding column of the memristor computing array.

[0014] In one feasible implementation, after cutting off the charge transfer path to electrically isolate the pixel array from the memristor computing array, the method further includes: The reset signal is used to turn on the reset switch of the pixel unit in the pixel array to clear the residual charge on the first capacitor in the pixel array.

[0015] In one feasible implementation, converting the charge signals accumulated on each output row of the memristor computing array into voltage signals and outputting them includes: Multiply the charge matrix formed by the charge of each memristor in the same row with the matrix formed by the conductance of the corresponding memristor to determine the voltage signal of the corresponding output row and output it.

[0016] The image sensor and signal processing method of this application embodiment realize a complete analog domain processing link by unifying the exposure and charge transfer of the pixel array module and the calculation operation of the memristor computing array module through a timing and control module. The photogenerated charge accumulated by the pixel array module is directly transferred to the memristor computing array module through the column lines, and the analog calculation is completed by redistributing the charge within the array using the programmable memristor that maintains the conductance value. Finally, the corresponding analog calculation and readout module converts the result charge signal into a voltage signal for output. The entire information processing process from the light signal to the final voltage output is realized entirely within the analog charge domain through the physical transfer and redistribution of charge, without the need for the analog-to-digital conversion and digital processing steps required in traditional architectures, thus systematically avoiding the power consumption and delay of related links in principle. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a CMOS image sensor provided in an embodiment of this application; Figure 2 This is a structural diagram of an image sensor provided in an embodiment of this application; Figure 3 This is a structural diagram of a pixel array module in an image sensor provided in an embodiment of this application; Figure 4 This is a diagram of a column line capacitor structure in an image sensor provided in an embodiment of this application; Figure 5 This is a structural diagram of a memristor computing array module in an image sensor provided in an embodiment of this application; Figure 6 This is a structural diagram of an analog calculation and readout module in an image sensor provided in an embodiment of this application; Figure 7 This is a schematic flowchart of a signal processing method based on an image sensor provided in an embodiment of this application; Figure 8 This is a schematic diagram of a simulation calculation provided in an embodiment of this application. Detailed Implementation

[0019] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0020] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0021] Based on the background technology, image sensors, especially CMOS image sensors, are currently key devices for acquiring visual information. Their typical architecture is as follows: Figure 1 As shown, it typically includes a pixel array composed of photodiodes 1101, an analog-to-digital converter 120, and a digital signal processor 130. The pixel array can convert incident light into an analog voltage signal through the photodiodes 1101. After the analog voltage signal is converted into a digital signal by the analog-to-digital converter 120, it is transmitted to the digital signal processor 130 for a series of image processing operations, such as noise reduction, white balance, and sharpening.

[0022] However, the aforementioned traditional architecture has inherent performance bottlenecks. First, the analog-to-digital conversion process itself consumes a lot of power, especially in high-resolution, high-frame-rate applications, becoming one of the main contributors to system power consumption and introducing a significant signal readout delay. Second, subsequent signal processing in the digital domain, particularly matrix operations, requires extensive computation in the digital signal processor, further increasing the overall system power consumption and processing latency. This serial, separate "sensing-conversion-processing-output" architecture limits the application of image sensing systems in power-sensitive and real-time-critical edge computing scenarios.

[0023] To address the problems in the prior art, this application provides an image sensor and a signal processing method.

[0024] The present invention is conceived as follows: a timing and control module generates control signals to control a pixel array module to convert incident light into photogenerated charges and accumulate them, thus completing exposure. A memristor computation array module controls the redistribution of charges to perform analog calculations, obtaining a charge signal characterizing the calculation result. The analog calculation and readout module then converts the charge signal into a voltage signal and outputs it. With light signal input and voltage signal output, no unnecessary signal conversions are performed during processing. Image processing is completed entirely in the analog domain, significantly reducing computational power consumption and processing latency.

[0025] The image sensor provided in the embodiments of this application will be described first below.

[0026] Figure 2 A schematic diagram of the structure of an image sensor provided in one embodiment of this application is shown. Figure 2 As shown, the image sensor may include the following structure: pixel array module 110, memristor computing array module 220, analog computing and readout module 240, and timing and control module 230.

[0027] Each column output of the pixel array module 110 is connected to the corresponding column of the memristor computing array 202 module through a column line 370. Under the control of the timing and control module 230, the charge accumulated in the pixel array module 110 can be transferred to the memristor computing array module 220, and the simulation calculation is completed in the memristor computing array module 220 through charge redistribution.

[0028] The pixel array module 110 includes a pixel array consisting of multiple pixel units 360 arranged in an array, each pixel unit 360 being used to convert incident light into photogenerated charge and accumulate it.

[0029] The pixel array module 110 consists of multiple pixel units 360 arranged in an array. Its core function is to directly convert the incident light signal into the corresponding photogenerated charge and complete the charge accumulation during the exposure process. As the photosensing and signal generation part of the image sensor, this module realizes the efficient conversion from optical information to analog charge signals, providing the original charge domain input for subsequent processing.

[0030] In this embodiment, the image sensor coordinates the exposure and charge transfer of the pixel array module and the computational operations of the memristor computation array module through a timing and control module, realizing a complete analog domain processing chain. The photogenerated charge accumulated by the pixel array module is directly transferred to the memristor computation array module via column line 370. Using a programmable memristor that maintains its conductivity, the analog calculation is completed through charge redistribution within the array. Finally, the corresponding analog calculation and readout modules convert the resulting charge signal into a voltage signal for output. The entire information processing process, from the optical signal to the final voltage output, is achieved entirely within the analog charge domain through the physical transfer and redistribution of charge, eliminating the need for analog-to-digital conversion and digital processing steps required in traditional architectures. This systematically avoids power consumption and latency in related stages from a fundamental perspective.

[0031] As an example of this application, such as Figure 3 As shown, pixel unit 360 may include: The photodiode 1101 has its first terminal connected to the first voltage terminal 380 and its second terminal connected to the first node 340. The reset switch 310 has its first terminal connected to the power supply voltage terminal 350 and its second terminal connected to the column line 370. The control terminal is used to receive the reset signal. The row selection switch 320 has its first end connected to the first node 340 and its second end connected to the column line 370. The control end is used to receive the row selection signal. The first capacitor 330 has its first terminal connected to the first node 340 and its second terminal connected to the second voltage terminal 390. Among them, photodiode 1101 is used to accumulate photogenerated charge at the first node 340 during exposure, and row selection switch 320 is used to turn on during the charge transfer stage, so that the first node 340 is coupled to memristor computing array module 220 through column line 370.

[0032] It should be noted that the first capacitor 330 is used to accumulate the charge converted from the light signal by the photodiode 1101 during the exposure stage. The first node 340 is a connection node used to illustrate the connection relationship.

[0033] The photodiode 1101 can also be any other photoelectric sensor that uses charge as a signal carrier. The reset switch 310 and the row selection switch 320 can be transistors.

[0034] As an example, pixel unit 360 includes a photodiode 1101, a reset switch 310, a row selection switch 320, and a first capacitor 330. The photodiode 1101 has its first terminal connected to a first voltage terminal 380 and its second terminal connected to a first node 340, used to accumulate photogenerated charge at the first node 340 during exposure. The first capacitor 330 has its first terminal connected to the first node 340 and its second terminal connected to a second voltage terminal 390, used to temporarily store charge and stabilize the node potential. The row selection switch 320 has its first terminal connected to the first node 340 and its second terminal connected to a column line 370; its control terminal receives a row selection signal to turn on the pixel unit 360 during the charge transfer phase, thereby coupling the first node 340 to the memristor computing array module 220 via the column line 370. The reset switch 310 has its first terminal connected to a power supply voltage terminal 350 and its second terminal connected to the column line 370; its control terminal receives a reset signal to reset the pixel unit 360. This achieves the accumulation and controlled transfer of photogenerated charge.

[0035] In this way, by connecting the photodiode 1101, the first capacitor 330, the row selection switch 320, and the reset switch 310 to the first node 340 and the column line 370 in the aforementioned manner, an efficient and controllable charge management path is constructed. During exposure, the photogenerated charge generated by the photodiode 1101 is effectively collected and temporarily stored in the first node 340 (stabilized by the first capacitor 330); during the charge transfer stage, the controlled conduction of the row selection switch 320 enables direct, low-loss coupling of the accumulated charge to the column line 370, ensuring high signal integrity transmission; the reset switch 310 provides the controllable zeroing capability of the node charge. This structure realizes full-process analog domain management of photogenerated charge from generation, temporary storage, transfer, and reset, providing high-quality and timing-accurate charge input for subsequent high-efficiency analog calculations in the memristor computing array module 220, and is a fundamental unit guarantee for achieving the system's low power consumption and low latency goals.

[0036] In some embodiments, such as Figure 4 As shown, the image sensor may also include a column line capacitor module 430, which includes a plurality of column line capacitors 410; the first end of each column line capacitor 410 is electrically connected to the column line 370 of the column in which it is located, and the second end is electrically connected to the first fixed potential node 440; wherein, during the charge transfer stage, the charge on the first capacitor 330 in the pixel unit 360 is shared with the column line capacitors 410.

[0037] The charge of the integral of the line capacitance is shown in formula (1): In the formula, Q C-CLMN The charge on the line capacitor is denoted as . Let be the charge of the first capacitor. Let be the capacitance value of the first capacitor. This represents the capacitance value of the column line capacitor.

[0038] The column line capacitor 410 can be any type of capacitor, used to temporarily store and buffer the charge transferred from the pixel, and participate in charge sharing.

[0039] As an example, during the charge transfer stage, when the row selection switch of pixel unit 360 is turned on, the photogenerated charge accumulated on the first capacitor 330 in pixel unit 360 will share the charge with the column line capacitor 410 on the same column line 370.

[0040] By adding the column line capacitor module 430 and enabling it to share charge with the first capacitor 330 within the pixel unit 360 during the charge transfer stage, this structure achieves efficient buffering and signal conditioning during the charge transfer process from the pixel unit 360 to the computing array. The column line capacitor 410, acting as an intermediate storage unit, significantly improves the charge transfer capacity and charge packet integrity, effectively reducing charge loss and noise introduction during transmission. Simultaneously, its second terminal is connected to the first fixed potential node 440, providing a stable voltage reference for charge sharing and ensuring the determinism of the signal level. This optimizes the charge transfer efficiency and signal-to-noise ratio from the photosensitive unit to the computing unit, providing a stable and high-quality charge input for the subsequent high-precision analog calculations performed by the memristor computing array module 220, thereby consolidating the technical advantages of low-power, low-latency processing at the system level.

[0041] In some embodiments, such as Figure 4 As shown, a charge transfer isolation switch 420 can be installed on each column line 370; The first terminal of the charge transfer isolation switch 420 is electrically connected to the column line capacitor 410 of the column, the second terminal is electrically connected to the column line 370 of the column, and the control terminal is connected to the timing and control module 230 to receive the charge transfer isolation signal. The charge transfer isolating switch 420 is used to turn on during charge transfer isolation and turn off during charge transfer conduction.

[0042] It should be noted that the charge transfer isolation switch 420 can be a transistor.

[0043] As an example, each column line 370 is equipped with a charge transfer isolation switch 420 controlled by a TRANS signal. The first terminal of this switch is electrically connected to the column line capacitor 410 of its respective column, and the second terminal is connected to the column line 370. Its control terminal receives the TRANS signal from the timing and control module 230. The TRANS signal is briefly set high at the beginning of the charge transfer phase, causing the switch to quickly turn on, allowing the charge on the first capacitor 330 within the pixel unit 360 to quickly share charge with the column line capacitor 410. Subsequently, within a very short time, such as less than 10 nanoseconds, the TRANS signal is set low, causing the switch to immediately turn off, thereby electrically isolating the column line capacitor 410 from the column line 370, and also achieving physical isolation between the pixel array and the memristor computing array. This design ensures high efficiency in charge transfer and independence in subsequent computational stages through the precise and rapid switching of the TRANS signal.

[0044] By setting charge transfer isolation switches 420 controlled by charge transfer isolation signals on each column line 370, this structure achieves precise timing control and electrical isolation of the charge transfer path. When the charge transfer isolation signal is valid, the switch is turned on, establishing a charge path between the column line capacitor 410 and the column line 370, ensuring efficient sharing of the charge accumulated after exposure. After charge transfer is completed, the signal is quickly deactivated, the switch is turned off, and the pixel array module 110 and the memristor computing array module 220 are completely electrically isolated. This mechanism not only ensures the efficiency and integrity of the charge transfer stage, but more importantly, it prevents subsequent calculation operations from interfering with the front-end photosensitive and charge sampling process, achieving strict decoupling of the three core stages of exposure, transfer, and calculation in terms of timing and electrical aspects. This design ensures the reliability of the system operation and the purity of signal processing at the hardware level, and is a key control node supporting the stable operation of the full analog processing flow, thereby achieving the goals of low power consumption and low latency.

[0045] The memristor computing array module 220 may include a memristor computing array consisting of multiple rows of memristors, each row of memristors including multiple memristors 520, and the conductance value of each memristor 520 can be programmed and retained.

[0046] The memristor computing array module 220 includes a memristor computing array consisting of multiple rows of memristors, each row containing multiple memristors 520. The conductance value of each memristor 520 can be independently programmed and maintained, enabling the array to function as a configurable analog computing unit, providing the underlying hardware support for subsequent parallel analog signal processing in the charge domain.

[0047] The memristor 520 can be a non-volatile memory or a programmable resistor.

[0048] Different types of memristors 520 can be used in memristor arrays, such as resistive random access memory, phase change memory, magnetic random access memory, etc.

[0049] The memristor computing array module 220 can adopt different in-memory computing architectures or units, such as 1T1R, 2T2R, 2T1R, etc.

[0050] Specifically, it can be constrained that the sum of the conductance values ​​of all memristors in each column of the memristor calculation array module is equal to the sum of the conductance values ​​of all memristors in any different column.

[0051] In this way, the sum of the conductivities of all memristors 520 in each column of the memristor computation array module is configured to be equal, meaning that the total conductivity of all memristors in any two columns remains consistent. This design ensures that each column has consistent equivalent load characteristics during charge redistribution, thereby providing a basis for accurate and stable vector calculations in the analog domain. Matrix multiplication provides the necessary circuitry.

[0052] Specifically, such as Figure 5 As shown, the first terminal of the memristor 520 in each row of memristors can be electrically connected to the column line capacitor 410 of the column where the memristor is located, and the second terminal can be electrically connected to the input terminal of the analog calculation and readout module of the row where the memristor is located.

[0053] As an example, the memristors 520 in each row are connected as follows: their first terminal is electrically connected to the column line capacitor 410 of their respective column to receive the charge temporarily stored in that column; their second terminal is electrically connected to the input terminal of the analog calculation and readout module of their respective row to output the charge distributed by the memristors 520 to the corresponding readout circuit. This constructs a directional charge transfer path from the column line capacitor 410 to the output module.

[0054] By connecting the first terminal of each row of memristors 520 to the column line capacitor 410 of its respective column, and the second terminal to the input terminal of the analog computing and readout module 240 of its respective row, this structure constructs a directional and structured charge transfer and convergence path from the charge storage node to the analog computing and readout unit. This defined connection provides a physically clear and electrically controllable channel for charge to be discharged from the column line capacitor 410 to the memristor network and finally accumulated at the output node of the corresponding row. This not only ensures that the charge redistribution process based on the pre-programmed conductance value can be carried out accurately and predictably according to circuit laws, realizing high-precision analog vector-matrix multiplication operations; at the same time, the regular wiring reduces signal crosstalk and improves the signal-to-noise ratio and integrity of the calculated signal. This design is key to achieving efficient and parallel coupling between the memristor computing array module 220 and the analog computing and readout module 240, laying the core circuit structure foundation for the entire image sensor to complete low-power, low-latency near-sensing calculations in the analog domain.

[0055] In addition, a memristor calculation switch 510 can be set between each column line capacitor 410 and the corresponding column memristor 520 to receive the memristor calculation signal. The core function of this switch is to precisely manage the calculation timing: during the charge transfer and exposure stages, the memristor calculation signal remains off, thereby electrically isolating the charge temporarily stored on the column line capacitor 410 from the memristor calculation array, preventing the calculation operation from interfering with the charge acquisition and temporary storage process at the front end; when the charge transfer isolation signal has physically isolated the pixel array from the memristor array and the charge transfer is completed, the memristor calculation signal is controlled to turn on, allowing the charge temporarily stored on the column line capacitor 410 to be discharged and redistributed through the memristor array with pre-programmed conductance values, thereby initiating the analog matrix operation. This design achieves clear decoupling of the exposure, transfer, and calculation stages in terms of timing and electrical aspects, ensuring the stability of the system operation and the accuracy of the analog calculation.

[0056] The analog calculation and readout module 240 is connected to the output terminal of the memristor row and is used to convert the charge signal into a voltage signal and output it; the analog calculation and readout module 240 corresponds one-to-one with the memristor row.

[0057] The analog calculation and readout module 240 serves as the system's back-end output interface. Each module is directly connected to one row of the memristor calculation array's output terminals, forming a one-to-one correspondence. The core function of this module is to efficiently and linearly convert the analog calculation results, represented in the form of charges, output from the memristor rows into voltage signals that are easy for subsequent circuit processing and then output.

[0058] Specifically, such as Figure 6 As shown, the analog calculation and readout module 240 may include a second capacitor 620 connected across the output of the memristor row and an amplifier 610, wherein the amplifier 610 is in virtual ground mode. It should be noted that amplifier 610 can be an operational amplifier. In virtual ground mode, amplifier 610 is configured in a specific circuit so that its inverting input potential is forced to be maintained at zero potential (ground potential), but the node is not physically grounded.

[0059] The simulation calculation and readout module 240 may include: Amplifier 610 has its non-inverting input terminal electrically connected to the second fixed potential node 630, and its inverting input terminal electrically connected to the second terminal of the memristor in the row where the analog calculation and readout module 240 is located. The output terminal of amplifier 610 serves as the voltage signal output terminal of analog calculation and readout module 240. The second capacitor 620 has its first end electrically connected to the inverting input terminal and its second end electrically connected to the output terminal of the amplifier 610. The amplifier 610 is configured in virtual ground mode, so that the inverting input terminal and the non-inverting input terminal are at the same potential. The second capacitor 620 is used as an integrating capacitor to accumulate the charge flowing into the corresponding output row of the memristor calculation array module 220, and generates a voltage signal at its second terminal that is proportional to the amount of accumulated charge.

[0060] As an example, the non-inverting input of amplifier 610 is connected to a fixed reference potential node, its inverting input is directly electrically connected to the second terminal of the corresponding row of memristors 520, and its output serves as the voltage signal output of the module. A second capacitor 620 is connected between the inverting input and the output of amplifier 610. Since amplifier 610 is configured in virtual ground mode, the potential of its inverting input is forced to be clamped to the same reference potential as the non-inverting input, thus providing a stable virtual ground node for the charge flowing in from the memristor row. The flowing charge is integrated by the second capacitor 620 and generates an output voltage signal proportional to the accumulated charge at the output of amplifier 610, thereby achieving a high linearity and high precision conversion from charge to voltage.

[0061] In this way, by connecting the virtual-ground mode amplifier 610 and the second capacitor 620, which serves as the integrating capacitor, across the output of the memristor row, this structure constructs a high-precision, high-linearity charge-to-voltage conversion interface. The virtual-ground mode of amplifier 610 provides a stable and reliable reference potential for its inverting input, allowing the charge flowing in from each row of the memristor calculation array to be accurately integrated without loss by the second capacitor 620. This integration process directly and linearly maps the charge quantity to the voltage signal at the amplifier output, achieving distortion-free readout of the analog calculation results. This conversion method eliminates the need for traditional multi-stage amplification and sample-and-hold circuits, resulting in a simple structure and low static power consumption. At the same time, the one-time charge integration output avoids the delay and dynamic power consumption caused by periodic signal conversion. This design is crucial to ensuring the integrity and accuracy of the analog calculation results are maintained at the final output port, thus fully realizing a fully analog, low-latency signal link from optical sensing to information processing.

[0062] The timing and control module 230 is used to generate control signals to coordinate the exposure and charge transfer operations of the pixel array module 110 and the calculation operations of the memristor calculation array module 220.

[0063] The timing and control module 230, acting as the command center of the entire image sensor system, is responsible for generating and outputting a series of precise control signals. Its core function is to coordinate the exposure and charge transfer operations of the pixel array module 110 and the analog calculation operations of the memristor computation array module 220, ensuring that these three key stages are tightly linked in timing and electrically isolated from each other. Through this centralized timing scheduling and control, the module achieves efficient and reliable operation of the photosensing, signal transfer, and analog processing workflows, providing fundamental timing guarantees for the entire system to achieve low-power and low-latency image sensing and processing.

[0064] Based on the image processor described above, this application also provides a signal processing method.

[0065] Figure 7A schematic flowchart of a signal processing method provided in one embodiment of this application is shown. Figure 7 As shown, the method may include the following steps S710-S750: S710 controls the pixel array to expose in order to convert incident light into photocharge and accumulate it.

[0066] As an example, the timing and control module 230 sends an exposure control signal, causing all pixel units 360 in the pixel array module 110 to synchronously enter the photosensitive state. The photodiode 1101 in each pixel unit 360 converts the incident light into photogenerated charge, which continuously accumulates on the first capacitor 330 inside. The amount of accumulation is determined by both the light intensity and the exposure time. This step completes the initial conversion and temporary storage from optical information to analog charge signal, providing an accurate charge domain input signal for subsequent charge transfer and simulation calculations.

[0067] After exposure, the S720 establishes a charge transfer path between the pixel array and the memristor computing array, allowing the accumulated charge to be transferred from the pixel array to the memristor computing array.

[0068] As an example, the timing and control module 230 first sets the row selection signal, turning on the row selection switch 320 in the target row pixel unit 360, so that the charge nodes accumulated on the first capacitor 330 in each pixel unit 360 are connected to the corresponding column line 370. At the same time, the timing and control module 230 sets the TRANS signal to active (e.g., high level), turning on the charge transfer isolation switch 420 on each column line 370, thereby connecting the column line capacitor 410 to the path. At this time, the charge on the first capacitor 330 of each pixel unit 360 is rapidly shared with its corresponding column line capacitor 410 through the column line 370, completing the charge transfer from the pixel array to the column line capacitor 410. Subsequently, the TRANS signal is set to inactive (e.g., low level) in a very short time, turning off the charge transfer isolation switch 420, electrically isolating the pixel array module 110 from the memristor computing array module 220, preparing for the next step of calculation. This step realizes the efficient and controllable transfer of photogenerated charge from the photosensitive unit to the computing unit.

[0069] Specifically, based on the pixel array structure in pixel array module 110, a charge transfer path is established between the pixel array and the memristor computing array, including steps A and B: A. Receives a row selection signal through a row selection switch in the pixel array to connect the first node 340 of the corresponding row in the pixel array to the column line 370 of the column. B, receives charge transfer isolation signal through charge transfer isolation switch, so as to turn on the isolation switch connected to column line 370 of the column to connect column line 370 of the column to the corresponding column of the memristor calculation array.

[0070] As an example, the timing and control module 230 sends a row selection signal to the target row, which turns on the row selection switches 320 in all pixel units 360 of the row, thereby connecting the first node 340 in each pixel unit 360 with the column line 370 of the corresponding column; at the same time, the timing and control module 230 sets the TRANS signal to be active, controls the charge transfer isolation switch 420 on each column line 370 to be turned on, thereby connecting the column line capacitor 410 with the column line 370, so that the column line 370 further forms a charge path with the corresponding column of the memristor computing array module 220.

[0071] In step A, the row selection switch 320 of the pixel array module 110 receives the row selection signal and accurately connects the first node 340 of the corresponding row pixel unit 360 to the column line 370 of the column, thereby achieving the directional screening and output of the target row charge and avoiding interference from non-target row signals. In step B, the charge transfer isolation switch 420 receives the charge transfer isolation signal and reliably connects the column line 370 to the corresponding column of the memristor computing array module 220, thus constructing a complete and dedicated charge transfer path from the first node 340 of the pixel unit 360 through the column line 370 to the memristor computing array. The two-step collaborative process enables the directional and precise transfer of charge from the pixel array module 110 to the memristor computing array module 220. This ensures the directness and integrity of charge transfer, reduces signal attenuation and loss during transmission, and achieves controllable timing of charge transfer by relying on the controlled conduction characteristics of the switch. This provides a precise and clean charge input foundation for subsequent charge redistribution and simulation calculations of the memristor array based on pre-programmed conductance values, while also ensuring the timing coordination of the charge transfer process with other operational steps.

[0072] S730 cuts off the charge transfer path to electrically isolate the pixel array from the memristor computing array.

[0073] As an example, after the charge transfer is completed, the timing and control module 230 sends a charge transfer isolation signal to turn off the charge transfer isolation switch, thereby controlling the charge transfer isolation switch 420 on each column line 370 to turn off quickly.

[0074] This operation disconnects the column line capacitor 410 from the column line 370, thereby completely blocking the electrical path between the column output of the pixel array module 110 and the corresponding column of the memristor calculation array module 220. Through this step, the two core functional modules are reliably isolated, creating the necessary electrical environment for the next step of independently performing analog calculations in the memristor array.

[0075] S740 allows the charge temporarily stored on each column line 370 to be discharged and redistributed through a memristor computing array; wherein the memristor computing array includes multiple memristors with pre-programmed conductance values, and the charge is accumulated on each output row according to the conductance value.

[0076] As an example, the timing and control module 230 sets the CALC signal to a valid high level, thereby turning on the memristor calculation switch 510 located between each column line capacitor 410 and the corresponding memristor 520. This allows the charge temporarily stored on each column line capacitor 410 to be discharged through all memristors 520 in their respective columns that have pre-programmed conductance values. According to Ohm's law and the principle of charge conservation, the charge is redistributed in the conductive path formed by the memristor network, and according to the conductance weight ratio of each memristor cell, it is directionally accumulated at the output node of its respective row, i.e., the input terminal of the analog calculation and readout module 240. This process directly realizes the parallel multiplication operation of the input charge vector and the memristor conductance matrix in the analog charge domain.

[0077] The S750 converts the accumulated charge signals on each output row of the memristor computing array into voltage signals and outputs them.

[0078] The core function is to convert the analog calculation results, represented by charges on each output row of the memristor computing array, into standard voltage signals and finally output them. This conversion process serves as the signal output interface for the entire near-sensing computing architecture, enabling seamless integration between the analog computing domain and the back-end voltage processing domain.

[0079] Specifically, the S750 may include: Multiply the charge matrix formed by the charge of each memristor in the same row with the matrix formed by the conductance of the corresponding memristor to determine the voltage signal of the corresponding output row and output it.

[0080] As an example, suppose the memristor computing array has a 3x4 structure—the 3 rows correspond to 3 analog computing and readout modules, and the 4 columns correspond to 4 column line capacitors, with the sum of the conductance values ​​of the memristors in each column being G. 总 , i.e. G 11 +G 21 +G 31 =G 12 +G 22 +G 32 =G 13 +G 23 +G 33 =G 14 +G 24 +G 34 =G 总The charge temporarily stored on the four column capacitors forms a 4×1 charge matrix [Q1,Q2,Q3,Q4], and the pre-programmed conductance values ​​of the three rows and four columns of memristors form a 3×4 conductance matrix [[G 11 G 12 G 13 G 14 ],[G 21 G 22 G 23 G 24 ],[G 31 G 32 G 33 G 34 According to the principle of charge domain calculation for memristor arrays, the charge in each column is allocated to the target row according to the proportion of the memristor conductance value in the corresponding row to the total conductance of the column. For example, the charge Q1 in the first column is allocated to the first row as Q1×G. 11 / G 总 The charge Q2 in the second column is allocated to the charge in the first row as Q2 × G. 12 / G 总 And so on, the total accumulated charge in the first row is Q1G 11 +Q2G 12 +Q3G 13 +Q4G 14 Divide by G 总 The total charge flows into the second capacitor (with a capacity of C) of the corresponding simulation calculation and readout module. F In the amplifier's virtual ground mode, the output voltage Vout1 generated by the integration of the second capacitor is (Q1G) 11 +Q2G 12 +Q3G 13 +Q4G 14 ) / (G 总 ×C F Similarly, we can obtain the output voltage Vout2 of the second row as Vout2 = (Q1G) 21 +Q2G 22 +Q3G 23 +Q4G 24 ) / (G 总 ×C F ), the output voltage Vout3 in the third row = (Q1G 31 +Q2G 32 +Q3G 33 +Q4G 34 ) / (G 总 ×C F The three output voltages correspond to the results of multiplying the charge matrix and the conductance matrix, respectively, and are output synchronously through the amplifier output terminal.

[0081] In this way, by directly multiplying the charge matrix formed by the charge values ​​of the memristors in the same row with the matrix formed by their corresponding conductance values ​​in the analog domain, the parallel architecture of the memristor array enables the synchronous matching and accumulation of multiple sets of charge-conductance weights, significantly improving the parallelism and efficiency of the operation. The direct interaction between the charge matrix and the conductance matrix avoids intermediate steps in the signal conversion between different domains, reducing signal attenuation and noise introduction, and ensuring the original accuracy of the calculation results. At the same time, combined with the synergistic effect of the virtual ground mode amplifier and the second capacitor in the analog calculation and readout module, the accumulated charge signal after matrix multiplication is linearly converted into a voltage signal. The conversion process and the calculation process are seamlessly connected, which not only ensures the high linearity and high signal-to-noise ratio of the voltage output, but also, relying on the programmable characteristics of the memristor conductance values, allows for flexible adjustment of matrix weights to adapt to different calculation scenarios. While achieving accurate calculation, it simplifies the signal processing link and further reduces the power consumption of the operation process.

[0082] In addition, such as Figure 8 As shown, the principle of the charge domain calculation method for a memristor array is as follows: The core principle of the charge domain calculation method for a memristor array is: by taking advantage of the virtual short characteristic of the output operational amplifier, the potential of the row lines in the array is clamped to zero, so that the voltage across each memristor in the same column remains consistent; according to Ohm's law, the current on the row line is proportional to the conductance of the corresponding memristor, and thus the charge flowing through the memristor in that row is also proportional to the conductance. Therefore, the charge distribution formula of the Rth row of a certain column can be derived as shown in formula (2) (taking the first column as an example): Provided that the sum of the conductivities of all memristors in each column of the memristor array is equal, the op-amp output voltage can accurately characterize the charge value (Q) on the line capacitance of each column. C1 -Q CN The vector formed by ) and the pre-programmed conductance value (G) in the memristor array 11 -G KN The result of multiplying the matrices formed by these matrices enables efficient simulation calculations within the charge domain.

[0083] The signal processing method of this application embodiment achieves direct conversion and accumulation of incident light into photogenerated charge by controlling the exposure of the pixel array, providing a pure original charge signal for subsequent processing; after exposure, a dedicated charge transfer path is established, so that the accumulated charge is directly transferred to the memristor computing array, avoiding signal loss during conversion between different carriers; cutting off the path achieves electrical isolation between the pixel array and the memristor computing array, ensuring the independence of the charge calculation process and signal stability; relying on the memristor array with pre-programmed conductance values, the temporarily stored charge is discharged and redistributed according to the conductance weight ratio and directionally accumulated in the output row, and the physical characteristics of the memristor are used to realize parallel operation of multiple sets of signals, which greatly improves the computing efficiency; finally, the accumulated charge signal is directly converted into voltage output, so that the signal flow is based on charge as the core carrier and there are no redundant links. It shortens the processing cycle by relying on the parallel operation characteristics, reduces power consumption by relying on the directness of signal transmission and conversion, and achieves flexible adaptation to computing needs through the programmability of conductance values. It can also ensure high signal-to-noise ratio and accuracy of output signal through isolation design and linear conversion.

[0084] In some embodiments, after cutting off the charge transfer path to electrically isolate the pixel array from the memristor computing array, the method further includes: The reset signal is used to turn on the reset switch of the pixel unit 360 in the pixel array to clear the residual charge on the first capacitor in the pixel array.

[0085] As an example, after the timing and control module 230 achieves electrical isolation between the pixel array module 110 and the memristor computing array module 220 by turning off the charge transfer isolation switches 420 of each column line, it immediately generates and outputs a high-level reset signal. This signal is transmitted to the control terminal of the reset switch 310 of the pixel unit 360 in the pixel array module 110. After receiving the signal, the reset switch 310 quickly turns on, and the power supply voltage terminal connected to its first terminal applies a stable reset potential to the column line 370. Through the coupling path between the column line 370 and the first node 340 of the pixel unit 360, the residual charge on the first capacitor 330 that has not been completely transferred to the column line capacitor 410 is completely conducted away and cleared to zero. After the residual charge is cleared, if it lasts for 5 ns, the timing and control module 230 pulls the reset signal low, the reset switch 310 turns off, and the first capacitor 330 returns to the initial standby state, ensuring that the pixel array module 110 can accurately accumulate new photogenerated charge without being disturbed by residual charge in the next exposure process.

[0086] In this way, after the timing and control module 230 achieves electrical isolation between the pixel array module 110 and the memristor computing array module 220 by turning off the charge transfer isolation switch 420, it immediately turns on the reset switch 310 of the pixel unit 360 through the reset signal. This can completely remove the residual charge that has not been completely transferred on the first capacitor 330, avoid the residual charge from interfering with the accumulation of photogenerated charge in the next exposure, and ensure that the charge signal accumulated in each exposure can accurately reflect the intensity of the incident light. At the same time, this reset operation is seamlessly connected with the re-exposure timing of the subsequent pixel array module 110. While ensuring the purity and accumulation accuracy of the charge signal, it maintains the continuity and efficiency of the entire signal processing flow, and further improves the consistency, stability and signal-to-noise ratio of the image sensor output signal.

[0087] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0088] The functional blocks shown in the above block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (ROM), flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0089] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0090] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0091] It should be noted that the acquisition, storage, use, and processing of data in this application embodiment all comply with the relevant provisions of national laws and regulations.

[0092] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0093] It should be noted that the acquisition, storage, use, and processing of data in this application embodiment all comply with the relevant provisions of national laws and regulations.

[0094] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0095] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An image sensor, characterized in that, include: A pixel array module includes a pixel array consisting of multiple pixel units arranged in an array, each of which is used to convert incident light into photogenerated charge and accumulate it; A memristor computing array module includes a memristor computing array consisting of multiple rows of memristors, each row of the memristors including multiple memristors, and the conductance value of each memristor can be programmed and retained; An analog calculation and readout module is connected to the output terminal of the memristor row and is used to convert the charge signal into a voltage signal and output it; the analog calculation and readout module corresponds one-to-one with the memristor row; The timing and control module is used to generate control signals to coordinate the exposure and charge transfer operations of the pixel array module and the calculation operations of the memristor calculation array module. Each column output of the pixel array module is connected to the corresponding column of the memristor computing array module via a column line. Under the control of the timing and control module, the charge accumulated in the pixel array module can be transferred to the memristor computing array module, and the simulation calculation is completed in the memristor computing array module through charge redistribution.

2. The image sensor according to claim 1, characterized in that, The pixel unit includes: A photodiode, wherein its first electrode is connected to a first voltage terminal and its second electrode is connected to a first node; The first capacitor has its first terminal connected to the first node and its second terminal connected to the second voltage terminal. A row selection switch, with its first end connected to the first node and its second end connected to the column line, and its control end used to receive the row selection signal; A reset switch has a first terminal connected to the power supply voltage terminal, a second terminal connected to the column line, and a control terminal used to receive a reset signal. The photodiode is used to accumulate photogenerated charge at the first node during exposure, and the row selection switch is used to turn on during the charge transfer phase, so that the first node is coupled to the memristor computing array module through the column line.

3. The image sensor according to claim 2, characterized in that, It also includes multiple column line capacitors; the first end of each column line capacitor is electrically connected to the column line of the column in which it is located, and the second end is electrically connected to the first fixed potential node; wherein, during the charge transfer stage, the charge on the first capacitor in the pixel unit is shared with the column line capacitor.

4. The image sensor according to claim 3, characterized in that, A charge transfer isolation switch is provided on each of the column lines; The first terminal of the charge transfer isolation switch is electrically connected to the column line capacitor of the column, the second terminal is electrically connected to the column line of the column, and the control terminal is connected to the timing and control module to receive the charge transfer isolation signal. The charge transfer isolation switch is used to turn on when the charge transfer is isolated and to turn off when the charge transfer is on.

5. The image sensor according to claim 4, characterized in that, The sum of the conductance values ​​of all memristors in each column of the memristor calculation array module is equal to the sum of the conductance values ​​of all memristors in any different column.

6. The image sensor according to any one of claims 1-5, characterized in that, The first terminal of the memristor in each row is electrically connected to the column line capacitor of the column containing the memristor, and the second terminal is electrically connected to the input terminal of the analog calculation and readout module of the row containing the memristor.

7. The image sensor according to claim 1, characterized in that, The analog calculation and readout module includes a second capacitor and an amplifier connected across the output of the memristor row, wherein the amplifier is in virtual ground mode; The simulation calculation and readout module includes: An amplifier, whose non-inverting input is electrically connected to a second fixed potential node, and whose inverting input is electrically connected to the second terminal of the memristor in the row where the analog calculation and readout module is located, and whose output is used as the voltage signal output of the analog calculation and readout module; The second capacitor has its first end electrically connected to the inverting input terminal and its second end electrically connected to the output terminal of the amplifier. The amplifier is configured in virtual ground mode, such that the inverting input terminal and the non-inverting input terminal are at the same potential. The second capacitor is used to accumulate the charge flowing into the corresponding output row of the memristor calculation array module and generate a voltage signal at its second terminal that is proportional to the amount of accumulated charge.

8. A signal processing method based on an image sensor, characterized in that, The image sensor is the image sensor as described in any one of claims 1-7, and the method includes: The pixel array is controlled to expose itself in order to convert incident light into photogenerated charge and accumulate it; After exposure, a charge transfer path is established between the pixel array and the memristor computing array, so that the accumulated charge is transferred from the pixel array to the memristor computing array; The charge transfer path is cut off to electrically isolate the pixel array from the memristor computing array; The charge temporarily stored on each column line is discharged and redistributed through the memristor computing array; wherein, the memristor computing array includes multiple memristors with pre-programmed conductance values, and the charge is accumulated on each of its output rows according to the conductance values; The accumulated charge signals on each output row of the memristor computing array are converted into voltage signals and output.

9. The signal processing method according to claim 8, characterized in that, The pixel unit includes: A photodiode, wherein its first electrode is connected to a first voltage terminal and its second electrode is connected to a first node; The first capacitor has its first terminal connected to the first node and its second terminal connected to the second voltage terminal. A row selection switch, with its first end connected to the first node and its second end connected to the column line, and its control end used to receive the row selection signal; A reset switch has a first terminal connected to the power supply voltage terminal, a second terminal connected to the column line, and a control terminal used to receive a reset signal. The image sensor also includes multiple column line capacitors; the first end of each column line capacitor is electrically connected to the column line of the column in which it is located, and the second end is electrically connected to a first fixed potential node; A charge transfer isolation switch is provided on each of the column lines. The first end of the charge transfer isolation switch is electrically connected to the column line capacitor of the column, the second end is electrically connected to the column line of the column, and the control end is connected to the timing and control module to receive the charge transfer isolation signal. The first terminal of the memristor in each row is electrically connected to the column line capacitor of the column where the memristor is located, and the second terminal is electrically connected to the input terminal of the analog calculation and readout module of the row where the memristor is located. The establishment of the charge transfer path between the pixel array and the memristor computing array includes: The row selection signal is received through the row selection switch in the pixel array to connect the first node of the corresponding row in the pixel array to the column line of the column where it is located; A charge transfer isolation signal is received via a charge transfer isolation switch to activate the isolation switch connected to the column line of the column to connect the column line of the column to the corresponding column of the memristor computing array.

10. The signal processing method according to claim 9, characterized in that, After cutting off the charge transfer path to electrically isolate the pixel array from the memristor computing array, the method further includes: The reset signal is used to activate the reset switch of the pixel unit in the pixel array to clear the residual charge on the first capacitor in the pixel array.

11. The signal processing method according to any one of claims 8-10, characterized in that, The step of converting the accumulated charge signals on each output row of the memristor computing array into voltage signals and outputting them includes: Multiply the charge matrix formed by the charge amount of each memristor in the same row with the matrix formed by the conductance value of the corresponding memristor to determine the voltage signal of the corresponding output row and output it.

Images