Component carrier and method for manufacturing same

Abstract

The invention provides a component carrier and a method of manufacturing the same. The component carrier (100) comprises a stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), where the at least one electrically insulating layer structure (106) has a first main surface (108) and an opposite second main surface (110), and at least one cavity (116), the at least one cavity (116) is formed in a first main surface (108) of the at least one electrically insulating layer structure (106) and is delimited by a bottom wall (112) and a side wall (114), a surface of the bottom wall (112) and a surface of the side wall (114) of the at least one cavity (116) have a roughness Ra different from a roughness of the first main surface (108) and / or a roughness of the second main surface (110) of the at least one electrically insulating layer structure (106).

Description

Technical Field

[0001] The present invention relates to component carriers and to methods for manufacturing component carriers. Background Technology

[0002] Against the backdrop of increasing product functionality and miniaturization of component carriers equipped with one or more parts, and a growing number of components to be connected to component carriers such as printed circuit boards, increasingly robust array-shaped components or packages with multiple parts having multiple contacts or connections, wherein the spacing between these contacts is becoming smaller and smaller. In particular, the component carrier should be mechanically robust and electrically reliable to enable operation, even under harsh conditions. Summary of the Invention

[0003] It may be necessary to form component carriers with precisely defined cavities in a simple manner.

[0004] According to an exemplary embodiment of the present invention, a component carrier is provided, the component carrier including a stack and at least one cavity, the stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein the at least one electrically insulating layer structure has a first main surface and an opposite second main surface, the at least one cavity is formed in the first main surface of the at least one electrically insulating layer structure and is defined by a bottom wall and a side wall, wherein the surface of the bottom wall and the surface of the side wall of the at least one cavity have a roughness Ra that is different from the roughness of the first main surface and / or the roughness of the second main surface of the at least one electrically insulating layer structure.

[0005] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, wherein the method includes: providing a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein the at least one electrically insulating layer structure has a first main surface and an opposite second main surface; forming at least one cavity in the first main surface of the at least one electrically insulating layer structure, and the at least one cavity being defined by a bottom wall and a side wall; and forming the at least one cavity such that the surfaces of the bottom wall and the side wall of the at least one cavity have a roughness Ra different from the roughness of the first main surface and / or the roughness of the second main surface of the at least one electrically insulating layer structure.

[0006] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components on and / or within a component carrier to provide mechanical support and / or electrical and / or thermal connections. In other words, a component carrier can be configured as a mechanical and / or electronic and / or thermal support for a component. A component carrier may include laminated stacks such as laminated stacks. Specifically, a component carrier may be one of the following: a printed circuit board, an organic interposer and / or an inorganic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different types of component carriers of the above types.

[0007] In the context of this application, the term "stack" may specifically refer to a flat or planar sheet-like body. For example, a stack can be a layered stack or a laminate, and more particularly, a laminated layered stack. Such a laminate can be formed by joining multiple layers together by applying mechanical pressure and / or heat. Preferably, the multiple layers are arranged parallel to each other vertically. The stack may include at least one electrically conductive structure and at least one electrically insulating structure.

[0008] In the context of this application, the term "layer structure" may specifically refer to a continuous layer, a patterned layer, or a plurality of discontinuous islands in a common plane, and the "layer structure" may perform the functions of electrical conduction and / or electrical insulation.

[0009] In the context of this application, the term "cavity" may specifically refer to a blind or through-hole (e.g., a stepped through-hole) in a stack of component carriers. For example, the shape and size of a cavity may be designed to accommodate electronic components (e.g., semiconductor chips), heat sinks (e.g., copper or ceramic blocks), or another component carrier, wholly or partially within the cavity.

[0010] In the context of this application, the term "roughness" can specifically refer to the average height Ra of the centerline of a surface. Ra is the arithmetic mean of all distances from the centerline to the profile. For example, the measurement or determination of roughness Ra as mentioned in the context of this application can be performed according to DIN EN ISO 4287:2010 (this is an industry standard). Ra can be the arithmetic mean of the absolute values ​​of the deviations of the surface from the average surface profile. The unit of roughness parameter Ra is length, and roughness parameter Ra can be measured in micrometers or nanometers. The average surface profile can be selected from the original surface profile, i.e., the measured surface profile, for example, by eliminating the waviness component of the surface deviation from the original surface profile, i.e., the measured surface profile.

[0011] In the context of this application, the term "main surface of a body" may specifically refer to one or more of the largest, generally flat surface areas or the outermost opposing surfaces of a body (e.g., a stack). Typically, a generally cubic body may have two opposing main surfaces in the form of two horizontal surface areas on the top and bottom of the body. Thus, the main surfaces may differ from the sidewalls of the body.

[0012] According to an exemplary embodiment of the invention, a component carrier (e.g., a printed circuit board or integrated circuit substrate) has a (preferably laminated) stack comprising an electrically insulating layer structure (e.g., a glass core) wherein a cavity is formed in the main surface of the electrically insulating layer structure. The cavity may be defined by bottom and sidewalls having a roughness Ra different from the roughness Ra of the main surface of the electrically insulating layer structure. Advantageously, the component carrier design and corresponding manufacturing method allow for selective adjustment of the roughness Ra of the surface defining the cavity in a manner different from the roughness Ra of one or more defining main surfaces of the electrically insulating layer structure in which the cavity is formed. For example, when a component (e.g., a semiconductor chip) is to be embedded in a cavity, a relatively rough cavity may be required to ensure proper adhesion between the cavity walls and the component. However, when the cavity is used, for example, in high-frequency applications (e.g., for designing hollow waveguides), a cavity with relatively smooth walls may be required to suppress losses. Therefore, selective adjustment of the roughness Ra of the cavity may have the greatest advantage for various component carrier applications. Preferably, forming a cavity by combining laser processing of the material for locally altering the structure of the electrical insulating layer with subsequent selective etching of the altered material has proven to be an effective method for adjusting local roughness Ra, because the laser light can be flexibly altered by adjusting the depth and / or length of light propagation into the material, where the depth of light penetration into the material may affect the roughness of the material.

[0013] Detailed description of exemplary embodiments

[0014] Further exemplary embodiments of the component carrier and method will be described below.

[0015] For example, the roughness Ra of the bottom wall and / or sidewall of the cavity and / or the roughness Ra of the main surface of the glass core can be in the range of 300 nm to 5000 nm, particularly in the range of 500 nm to 1000 nm.

[0016] In one embodiment, the roughness Ra of the bottom wall and / or sidewall in the at least one cavity is defined by peaks and valleys. Peaks can represent locally protruding structures, while valleys can represent locally recessed structures of the corresponding walls. Alternating sequences of peaks and valleys can result in a rough or contoured surface structure corresponding to a specific roughness Ra value. Such contours can typically be determined by the material composition of the component carrier, taking into account whether the material is inorganic, particularly glass, the depth of laser penetration into the glass, and the compressive stress of the glass.

[0017] Throughout the base or sidewalls, the glass surface can have a uniform or substantially uniform roughness. This texture improves adhesion to the encapsulation material, and the adhesion can be the same or similar in all areas. There are no gaps or delamination between the two layers. Furthermore, the stress in the altered areas can also be the same or similar, which prevents the glass from cracking. The laser emitted onto the glass surface can also be uniform. The compressive stress at the main surface of the glass substrate can be balanced by the tensile stress (also known as "central tension") within the glass substrate.

[0018] In one embodiment, at least a portion of the valleys is arranged along a straight valley section in a plan view on at least one cavity. The straight valley section may correspond to a surface portion of the corresponding cavity wall, wherein the elongated valley section between the surrounding peaks has a linear or generally linear appearance. Such a straight valley section can serve as an anchoring line for anchoring adhesive attachment films and / or (e.g., resin-based) encapsulation materials between the electrical insulation layer structure and the embedded component.

[0019] In one embodiment, the roughness Ra of the bottom wall in the at least one cavity is defined by peaks and valleys, wherein most of the valleys are arranged along straight valley segments extending substantially parallel to each other in a plan view of the at least one cavity. "Most" can specifically mean more than 50% of the valleys. However, in other embodiments, approximately 50% of the valleys have the aforementioned characteristics. The valleys can be arranged substantially parallel to each other and can therefore serve as adhesion-enhancing structures that strengthen the mechanical anchoring between the embedded component, the cavity wall, and the connecting material between the embedded component and the cavity wall. Due to precise alterations achieved through the laser beam, material composition, and the balanced distribution of the combined stress on the material, these valleys arranged at the bottom can all have uniform or substantially uniform depth or size, ultimately altering the material properties in a uniform manner.

[0020] In one embodiment, most of the valleys extend in an inclined direction relative to the sidewalls; for example, most of the valleys extend diagonally relative to the sidewalls. Therefore, the aforementioned anchoring effect can be achieved along the spatial contribution of both of the two mutually perpendicular sidewalls. The valleys can extend in an inclined direction relative to the sidewalls in a uniform manner. This means that adhesion between the edge region and the encapsulation material can be good. Furthermore, the combined stress at the edges can be balanced, and breakage of the component carrier can be avoided.

[0021] In one embodiment, the roughness Ra of the bottom wall and / or sidewall in the at least one cavity is defined by peaks and valleys, wherein the thickness extensions of at least a plurality of peaks form undercuts along the thickness direction of the stack. Such undercuts allow for excellent anchoring of bonding materials (e.g., attachment films and / or encapsulating resins) within the cavity and between the embedded component and the electrical insulating layer structure. In this context, the attachment film can be an adhesive material to bond the component to the bottom wall of the cavity via adhesive properties, or it can be a non-adhesive material that is a filler material to be filled in openings or recesses in the bottom wall of the cavity so that the attachment film serves as an intermediate layer between the bottom wall of the cavity and the component as a bonding joint; such openings or recesses in the bottom wall of the cavity can be obtained by roughness formation at the bottom wall of the cavity.

[0022] In one embodiment, the roughness Ra of the bottom wall and / or sidewall in the at least one cavity is defined by peaks and valleys, wherein the thickness extensions of at least a plurality of peaks on the bottom wall follow different directions relative to the thickness extensions of at least a plurality of peaks on the sidewall. For example, valleys may extend into the bottom wall in a generally vertical direction or thickness extension, while valleys may extend into the sidewall in a generally horizontal direction or thickness extension. The depth or size of the valleys disposed on the sidewalls may differ from the depth or size of the valleys disposed on the bottom wall, and / or, the height or size of the peaks disposed on the sidewalls may differ from the height or size of the peaks disposed on the bottom wall. This structure can provide different levels of adhesion based on the actual requirements of the component carrier application. This may be due to the fact that in some applications, the component placed in the cavity may require stronger adhesion to the bottom wall to prevent delamination between the component and the component carrier due to a mismatch in the CTE (coefficient of thermal expansion) between the materials of the component and the component carrier.

[0023] In one embodiment, the roughness Ra of the bottom wall and / or sidewall in the at least one cavity is defined by peaks and valleys, wherein undercuts are provided in the at least one cavity along the thickness direction of the stack through different extensions of the peaks. Specifically, the peaks may have vertical and horizontal segments that together form the undercuts. The undercuts can significantly improve the adhesion-promoting effect of the cavity walls because they can provide anchoring points for the edges of the cavity to improve adhesion at the bonding joints between the bottom wall and / or sidewall and the encapsulation material.

[0024] In one embodiment, the roughness Ra of the bottom wall and / or sidewall in the at least one cavity is defined by peaks and valleys, wherein the valleys divide the peaks into islands (preferably adjacent islands), each island comprising at least one peak, for example, each island comprising multiple peaks. Each island may be surrounded by valleys to form a rock-like profile. This can serve as an effective adhesion promoter. Furthermore, such profiles may have been configured at a distance or precision such that the material can be modified and later removed without causing breakage or damage to the component carrier.

[0025] In one embodiment, in a plan view of the at least one cavity, at least a portion of the island-shaped portion has a length in at least one horizontal direction ranging from 0.2 μm to 15 μm; for example, in a plan view of the at least one cavity, at least a portion of the island-shaped portion has a length in at least one horizontal direction ranging from 0.5 μm to 5 μm. Island-shaped portions of this shape can be used excellently as anchoring structures.

[0026] In one embodiment, the peaks at the bottom wall or sidewall have the same height or size, and the valleys at the bottom wall or sidewall have the same depth or size. This means that the contours throughout the bottom wall or sidewall can be arranged in a uniform manner. Therefore, good encapsulation within the cavity can be ensured. Furthermore, air bubbles or voids in the encapsulation material can be avoided. In addition, this can result in a flat surface on the dielectric layer surface of the stacked components. Simultaneously, the distribution of central strength of the component carrier is uniformly distributed during and after laser processing, thus avoiding the risk of breakage or damage, particularly at the glass component carrier.

[0027] In one embodiment, the peaks at the bottom wall and the peaks at the side walls have the same height or size, and the valleys at the bottom wall and the valleys at the side walls have the same depth or size. This can result in the bottom and side walls of the cavity having the same roughness, caused by material modification by laser at the same level, and can lead to a uniform distribution of internal or combined stress throughout the cavity. Ultimately, it can control the cracking and damage of the inorganic layer structure, or even the warping of the entire component's support structure.

[0028] In another embodiment, the peaks at the bottom wall and the peaks at the side walls have different heights or dimensions, while the valleys at the bottom wall and the valleys at the side walls have different depths or dimensions. This results in different roughnesses on the bottom and side walls of the cavity, caused by different levels of laser modification of the material. As long as the surface roughness of the cavity is controlled within tolerances, the entire component carrier will not be damaged, and these different surface textures can be used for different applications. This structure and method can provide manufacturing flexibility for the component carrier and the end application.

[0029] In one embodiment, at least one of the valleys is configured as a pathway adjacent to multiple islands in the island segments. Furthermore, this pathway-type structure, which demarcates the different island segments of the peak, can contribute to a more defined surface profile and an effective increase in roughness. This pathway-type structure may be due to precise control of laser-induced material modification (change in properties) for cavity formation, particularly precise control of laser-induced glass modification.

[0030] In one embodiment, the bottom wall and the side walls are connected to each other by a transition wall, for example, a rounded wall. For example, the bottom wall may be generally horizontal, while the outer portion of the side wall may be generally vertical or inclined. A rounded joint may be provided between these generally straight segments. The rounded joint at the transition wall may receive less laser treatment during laser-modified materials, and therefore the degree of cracking may be much smaller. The rounded joint can provide a buffer for the diffusion of central stress from the center outwards. Furthermore, the rounded joint can reduce the risk of breakage of the entire component support, particularly the glass component support.

[0031] In one embodiment, the transition wall (which may be an arcuate wall) has a roughness different from that of the bottom wall and sidewalls; specifically, the transition wall (which may be an arcuate wall) has a roughness smaller than that of the bottom wall and sidewalls. The arcuate characteristic of this region can form a buffer zone for stress diffusion from the bottom and sidewalls to the edges. Therefore, cracking at the corners of the cavity, which could potentially damage or break the entire component's support structure, can be reliably avoided.

[0032] In one embodiment, the roughness Ra of the bottom wall and / or the side wall and / or the transition wall in the at least one cavity is defined by peaks and valleys, wherein the thickness extension of the peaks on the transition wall differs from the thickness extension of the peaks on the bottom wall and / or the side wall. Therefore, the transition wall can provide a continuous transition between the thickness extensions of the peaks in the corresponding wall portions on both sides of the transition wall. In another embodiment, the thickness extensions in the bottom wall, side wall, and transition wall can also be identical.

[0033] In one embodiment, the thickness extension of the peak on the transition wall changes from the thickness extension of the peak on the bottom wall toward the thickness extension of the peak on the side wall; for example, the thickness extension of the peak on the transition wall gradually changes from the thickness extension of the peak on the bottom wall toward the thickness extension of the peak on the side wall. Therefore, the transition wall can provide a smooth transition between the bottom wall and the side wall, which can improve the mechanical integrity of the entire component carrier.

[0034] In one embodiment, the sidewalls of the at least one cavity are substantially perpendicular to the first main surface and / or the second main surface. For example, the sidewalls of the at least one cavity are perpendicular to the first main surface and / or the second main surface within a deviation of ±10°, or within a deviation of ±5°. It is highly advantageous that a combination of modified glass material in a predefined space by a controlled laser beam and subsequent selective removal of the modified glass material by wet etching alone can produce nearly vertical sidewalls. A deviation of ±10° can be significantly smaller than that obtained using conventional methods for forming cavities in electrically insulating structures. The steeply slanted or even nearly vertical sidewalls obtained through exemplary embodiments offer the advantage that electronic components with rectangular cross-sections can be embedded in the cavity in a controlled and space-saving manner. This accuracy of the deviation allows for the formation of substantially straight cavity sidewalls, enabling cavity dimensions to be matched to component dimensions in various applications. Furthermore, this accuracy avoids occupying surface area of ​​the component carrier, thus allowing for minimal use of surface area in the cavity and enabling the arrangement of more wiring or wiring structures on the surface. Therefore, this is advantageous for, for example, high-density and fine-line structured component carriers used in high-performance computing.

[0035] In one embodiment, the first main surface and / or the second main surface are planar. In particular, the electrically insulating layer structure having the at least one cavity may be plate-like. Preferably, the electrically insulating layer structure may be an inorganic plate, such as a glass plate, ceramic plate, or semiconductor plate.

[0036] In one embodiment, the surface of the bottom wall has a different roughness Ra than the surface of the side wall. However, the bottom wall and side wall may also have the same roughness. Different roughness or the same roughness can be precisely controlled by modifying the material with a laser. With this embodiment, the roughness can be flexibly adjusted based on final product requirements and / or manufacturing process requirements.

[0037] In one embodiment, the surface of the bottom wall has a higher roughness Ra than the surface of the sidewalls. This can result in excellent adhesion between the particularly rough bottom wall and an adhesive attachment film, which can be formed on the bottom main surface of the component to be embedded in the cavity. Since the gap between the cavity sidewalls and the component can be filled with a flowable resin or the like, lateral adhesion may be less of a problem than adhesion of the component to the bottom side of the cavity.

[0038] In one embodiment, the roughness Ra of the surface of the bottom wall and / or the roughness Ra of the surface of the sidewall provides an anchoring boundary region for anchoring the attachment film and / or encapsulation material at the bottom wall and / or sidewall of the at least one cavity. Therefore, this exemplary embodiment allows for highly reliable and precise embedding of components into cavities.

[0039] In one embodiment, a plurality of cavities are formed in the first main surface of the at least one electrically insulating layer structure, each cavity being defined by a corresponding bottom wall and a corresponding side wall. Different cavities can be arranged side-by-side, for example, different cavities can be arranged at the same vertical level. Different cavities can also be formed at different vertical levels; for example, at least one cavity can be formed in the first main surface of the electrically insulating layer structure and at least one cavity can be formed in the second main surface. Different cavities can have the same or different shapes and / or sizes.

[0040] In one embodiment, the different cavities within the cavity have different dimensions, specifically, the different cavities have different dimensions in the horizontal plane and / or in the vertical direction. This embodiment of the invention allows for precise implementation of different dimensions and allows for variations in material levels. Therefore, cavities with different horizontal regions and / or different depths can be formed within the same electrical insulating layer structure. For example, different lateral extensions of the different cavities can be defined by laser scanning regions of different sizes on corresponding main surfaces of the electrical insulating layer structure. Different depths of the different cavities can be defined by adjusting the different focusing depths of the laser beam impacting the electrical insulating layer structure. This defines the depth to which the glass material is altered by laser impact, such that the corresponding altered glass material reaching said depth can subsequently be removed by wet etching.

[0041] In one embodiment, the component carrier includes at least one component embedded in the at least one cavity. In the context of this application, the term "component embedded in the at least one cavity" may specifically refer to a component that is fully housed or only partially housed in the cavity. In a fully housed embodiment, the entire vertical space between the upper and lower ends of the component lies within the cavity. In a partially housed embodiment, only a portion of the vertical space between the upper and lower ends of the component lies within the cavity; for example, the component may protrude upwards and / or downwards beyond the cavity. In one embodiment, the upper end of the at least partially housed component may be aligned with the upper main surface of the electrical insulating layer structure, and / or the lower end of the component may be aligned with the lower main surface of the electrical insulating layer structure. For example, the component may be an electrical component for providing electrical functions (e.g., a semiconductor chip), a thermal component for providing cooling functions (e.g., a copper or ceramic block), and / or an optical component for providing optical functions. For example, the shape and size of the cavity can be designed to house electronic components (such as semiconductor chips), heat sinks (such as copper blocks or ceramic blocks), or other component carriers, either completely or partially, within the cavity.

[0042] Preferably, filling the gap between the component and the cavity wall with an encapsulation material and laminating another (preferably organic) electrical insulating layer structure (e.g., a sheet comprising a curable resin) onto the cavity-containing (preferably inorganic) electrical insulating layer structure can be performed using the same laminating material in a single common lamination process, which partially flows into the gap and partially remains on the top main surface of the cavity-containing electrical insulating layer structure.

[0043] In one embodiment, the component carrier includes an attachment film located within the at least one cavity, wherein the at least one component is attached via the attachment film. In one embodiment, the attachment film is pre-attached to the bottom side of the component, such that only one body needs to be inserted into the cavity. Therefore, the component can be firmly bonded to the bottom wall after the curing process. In another embodiment, the attachment film can be formed at the bottom wall of the cavity (e.g., by inserting solid adhesive tape into the cavity or by dispensing adhesive to the bottom of the cavity) before the component is inserted onto the attachment film.

[0044] In one embodiment, the electrically insulating layer structure comprises or is composed of glass. Typically, the electrically insulating layer structure may comprise, or be composed of, glass, ceramics, semiconductors, quartz, or metals. Therefore, suitable materials for the electrically insulating layer structure are glass (especially silicon-based glass), ceramics (e.g., aluminum nitride and / or alumina), and materials including semiconductors (e.g., silicon oxide, silicon, silicon carbide, gallium nitride, etc.). Inorganic layer structures may also be made of metallic materials, such as copper.

[0045] In one embodiment, the electrical insulating layer structure comprises or is composed of glass. Specifically, the electrical insulating layer structure can be a glass core or a glass plate. Most preferably, it comprises or is composed of glass. Such an electrical insulating layer structure may comprise or be composed of silicon dioxide. In particular, the electrical insulating layer structure may have glass as a major component. For example, the electrical insulating layer structure may be block-shaped, strip-shaped, or plate-shaped. The main material component of the electrical insulating layer structure (particularly the material component providing the highest weight percentage of the electrical insulating layer structure) is glass, particularly silicon-based glass. For example, at least 90 weight percent of the electrical insulating layer structure may be glass. For example, the electrical insulating layer structure may consist solely of glass. However, the electrical insulating layer structure may also include one or more additional other materials. Advantageously, the electrical insulating layer structure can have a very flat surface, allowing the planarization stage during processing to be omitted, and enabling fine-line processing on or above a very flat surface to be fully supported. Furthermore, the electrical insulation layer structure can possess high thermal stability, ensuring that undesirable thermal phenomena such as thermal stress, shrinkage, warpage, and delamination do not significantly affect the component carrier. This makes the entire component carrier stable and its dimensional variations controllable (e.g., less shrinkage), thus improving the alignment of all components associated with the component carrier (e.g., layer-to-layer alignment, via-to-pad alignment, pad-to-via alignment, protrusion-to-opening alignment, etc.). In addition, it improves the coplanarity of components assembled on the component carrier (e.g., protrusions, capacitors, etc.). Moreover, glass materials can exhibit low Dk and low Df behavior and good dielectric properties, thus supporting low-loss, high-frequency (especially improved RF) and high-speed applications, as well as high-performance computing applications with good signal integrity and low loss.

[0046] In one embodiment, the surfaces of the bottom wall and the sidewalls have a roughness Ra that is higher than the roughness of the first main surface and / or the roughness of the second main surface. This is advantageous for applications where components are to be assembled and attached in a cavity, as the locally increased roughness Ra can promote adhesion of such components in the cavity and thus improve the accuracy and reliability of the embedding process.

[0047] In one embodiment, the minimum horizontal distance between the first main surface and the bottom wall is no greater than 50 μm, for example, no greater than 15 μm, and preferably no greater than 10 μm. Therefore, the sidewalls of the cavity can be very steep, allowing for a cavity with an almost rectangular cross-section. This allows components to be assembled in the cavity with low space consumption and high spatial accuracy. Significantly steeper sidewalls can be achieved compared to conventional methods due to the combination of laser modification of the glass material and subsequent wet etching. This structure improves the alignment between components and component carriers, as well as layer-to-layer alignment. Furthermore, the cavity can be well-encapsulated without gaps.

[0048] In one embodiment, the depth of the at least one cavity is in the range of 10 μm to 200 μm, for example, the depth of the at least one cavity is in the range of 30 μm to 100 μm, and preferably, the depth of the at least one cavity is in the range of 40 μm to 80 μm. For example, the cavity depth can be about 60 μm. Such cavity dimensions are compatible with modern semiconductor chip dimensions.

[0049] In another embodiment, the cavity has a depth of at least 500 μm, and more particularly, the cavity has a depth of at least 700 μm. Advantageously, this large cavity depth enables many high-tech applications, such as optical packages that include at least one optical component embedded in the cavity.

[0050] In one embodiment, the method includes forming the at least one cavity using laser processing. Specifically, the method includes forming the cavity by processing the stacked material using a laser beam, particularly a Bessel beam. Single-beam or multi-beam processing can be performed. The laser beam can be specifically configured to attack the bonds of the material in the electrically insulating layer structure. For example, when the electrically insulating layer structure comprises glass, the laser beam can be particularly well-suited to attack Si-O bonds. This can be achieved by adjusting the laser wavelength, laser pulse length, and / or laser energy. A green picosecond laser, particularly a green picosecond laser with a Bessel beam, is preferred, where the Bessel beam can be a non-diffractive beam. Therefore, the beam distribution can remain constant in the horizontal direction during propagation toward the object. Simultaneously, the main diameter of the beam can be as small as a few micrometers, but the focusing depth can reach several millimeters. Utilizing this advantageous Bessel beam emitted by a picosecond laser, glass can be precisely altered or cut without causing breakage, and surface roughness control can be effectively achieved by precisely controlling the beam propagation distance.

[0051] In one embodiment, the method includes forming the at least one cavity using etching after the laser treatment, for example, wet etching. Wet etchants are particularly suitable for dissolving materials whose electrical insulating layer structure has been selectively altered by a previous laser treatment. HF has proven to be very suitable as a wet etchant for removing altered glass materials with pre-attacked Si-O bonds. In other embodiments, other etching processes besides wet etching can also be used. With etching methods, the altered material in the cavity region can be easily removed without cracking or damage to the glass. Since lasers do not remove material while etching does, there are no foreign objects generated by cutting. This is a significant advantage (in terms of high throughput and high reliability) for the manufacture of component carriers, particularly for high-density and fine-line structured component carriers used in fields such as high-performance computing.

[0052] In one embodiment, the method includes performing the laser processing using a laser beam having a wavelength in the range of 520 nm to 580 nm, particularly using a green laser. For example, the method includes forming a cavity by processing with a laser beam having a wavelength below 600 nm, for example, in the range of 520 nm to 580 nm, such as 550 nm. The laser beam having these characteristics allows for the formation of a cavity with a locally roughened cavity surface.

[0053] In one embodiment, the cavity can be formed by a CO2 laser. The laser beam can facilitate complete separation around the perforation line. Then, the following laser method can produce through-hole cuts in various types of glass in a single pass with minimal subsurface damage.

[0054] In one embodiment, the high-pressure assist gas can be mixed with CO2. The beam is extruded collinearly through nozzles to provide additional force to expel the glass material from the larger glass piece.

[0055] In one embodiment, the method includes performing the laser processing using a pulsed laser, for example, a picosecond pulsed laser. Preferably, the method includes forming a pulsed laser beam using laser pulses with a duration and / or time interval not exceeding 1 ps. For example, a picosecond laser or a femtosecond laser can be used to form the cavity. In another embodiment, a nanosecond laser can also be used.

[0056] In one embodiment, the method includes, for the purpose of the laser processing, scanning a surface region of the at least one electrically insulating layer structure where the at least one cavity is to be formed with a laser beam. In one embodiment, the electrically insulating layer structure or panel can be spatially fixed while the laser source scans the surface of the electrically insulating layer structure or panel. In another embodiment, the electrically insulating layer structure or panel can be moved while the laser source is spatially fixed for scanning.

[0057] In one embodiment, the method includes focusing a laser beam to a desired depth for the laser processing of the at least one cavity to be formed in the at least one electrically insulating layer structure. Advantageously, the laser beam can be focused to a depth below a first main surface of the electrically insulating layer structure. For example, the laser beam can be focused to a depth in the range of 30 μm to 100 μm, preferably in the range of 40 μm to 80 μm, below the main surface. This allows for precise definition of the cavity depth. In another embodiment, the laser beam can be varied with the diameter of the central main lobe and the non-diffraction propagation distance of the laser beam. For example, by reducing the diameter of the central main lobe and shortening the non-diffraction propagation distance, the taper of the laser beam can be increased, which can improve the results.

[0058] In one embodiment, the method includes: configuring a laser to alter the properties of the glass on which the at least one electrically insulating layer structure with the at least one cavity is to be formed, for the purpose of the laser processing. The laser for depth control can be generated by a laser using one or more lenses, which may have long beam and short focal length characteristics, allowing the laser to alter the properties of the glass for chemical removal of the altered glass. Overlapping focal points may exist.

[0059] However, other exemplary embodiments may use an etching method other than desiccation etching. Furthermore, other exemplary embodiments may use a continuous (rather than pulsed) laser beam and / or a laser with a different wavelength range compared to the green laser described above.

[0060] In one embodiment, the cavity extends vertically over only a single layer structure. However, in another embodiment, the cavity extends vertically over multiple layer structures of the stack. For example, the multiple layer structures over which the cavity extends vertically can be at least two layer structures, particularly at least three layer structures, preferably at least four layer structures, or even more than four layer structures, such as at least ten layer structures. A corresponding deep cavity can be formed without structural artifacts, particularly by using a pulsed laser source, for example, with a pulse length of no more than picoseconds, particularly no more than femtoseconds.

[0061] In one embodiment, multiple cavities can be formed from the second main surface and the first main surface within a single layer (e.g., a core). Furthermore, components can be embedded in two (or more) sides of the cavities. Advantageously, this allows for increased density and also enables heterogeneous packaging.

[0062] In one embodiment, the cavity may be formed in the central portion of the electrically insulating layer structure or stack. Alternatively, the cavity may be cut out at the edge of the electrically insulating layer structure or stack. Thus, there may be only three sidewalls, and there may be side portions with lateral openings. With this structure, external connection elements can be easily inserted into the component carrier (e.g., optical plugs and / or pull-out elements), and connected to and / or disconnected from the component carrier (e.g., optical plugs and / or pull-out elements).

[0063] In one embodiment, the component carrier includes electronic components mounted on or above an electrically insulating layer structure. One or more electronic components may be surface-mounted. In the context of this application, the term "electronic component" may specifically refer to a component that performs an electronic task. Such an electronic component may be an active component, such as a semiconductor chip comprising semiconductor materials, particularly semiconductor materials as primary or basic materials. Electronic components may also be passive components, such as capacitors or inductors. Preferably, the electronic component comprises a semiconductor chip. The semiconductor chip may be made, for example, based on a type IV semiconductor, such as silicon or germanium, or the semiconductor chip may be a type III-V semiconductor material, such as gallium arsenide. In particular, the semiconductor component may be a semiconductor chip such as a bare wafer or a molded wafer. A bare wafer may be an unpackaged (particularly, unmolded) semiconductor material (e.g., silicon) piece having at least one monolithic integrated circuit element (e.g., a diode or transistor). Furthermore, semiconductor materials suitable for photonic packages are also possible. For example, the electronic component to be surface-mounted onto the package may be an HBM (High Bandwidth Memory) or a silicon interposer.

[0064] In one embodiment, the component carrier includes a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the aforementioned one or more electrically insulating layer structures and one or more electrically conductive layer structures, particularly a laminate of the aforementioned one or more electrically insulating layer structures and one or more electrically conductive layer structures formed by applying mechanical pressure and / or thermal energy. The aforementioned stack can provide a plate-like component carrier that provides a large mounting surface for other components while remaining very thin and compact.

[0065] In one embodiment, the component carrier is shaped as a plate. This contributes to a compact design, whereby the component carrier still provides a large base for mounting components on the component carrier. In particular, a bare die, as an example of an electronic component, can be surface-mounted on a thin plate such as a printed circuit board.

[0066] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0067] In the context of this application, the term "printed circuit board (PCB)" may specifically refer to a plate-shaped component carrier formed by laminating multiple electrically conductive layer structures with multiple electrically insulating layer structures, for example, by applying pressure and / or by supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may include resin and / or glass fiber, so-called prepreg, or FR4 material. The various electrically conductive layer structures can be connected to each other in a desired manner by forming holes through the laminate, for example, by laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material (particularly copper), thereby forming vias or any other through-hole connections. The filled holes connect the entire stack (i.e., through-hole connections extending through multiple layers or the entire stack), or the filled holes connect at least two electrically conductive layers, i.e., so-called vias. Similarly, optical interconnects may be formed through the various layers of the stack to receive electro-optical circuit boards (EOCBs). Printed circuit boards (PCBs) are typically configured to house one or more components on one or both opposite surfaces of a board-shaped PCB. The one or more components can be soldered to their respective main surfaces. The dielectric portions of the PCB may include resin with reinforcing fibers (e.g., glass fiber).

[0068] In the context of this application, the term "substrate" can specifically refer to a small component carrier, particularly an IC substrate. An IC substrate can be a relatively small component carrier relative to a PCB, on which one or more components can be mounted, and which can serve as a connection medium between one or more chips and another PCB. For example, an IC substrate can have approximately the same size as the components (particularly electronic components) to be mounted on it (e.g., in the case of chip-scale packages (CSP)). More specifically, an IC substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier with a relatively high density of lateral and / or vertical connections, comparable to a printed circuit board (PCB). Lateral connections are, for example, conductive paths, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connections can be particularly arranged within the IC substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated or unaccommodated components (e.g., bare wafers), particularly IC chips, and printed circuit boards or intermediate printed circuit boards. In the context of this application, the term "substrate" is particularly advantageous for electrical connectivity and / or heat dissipation and / or providing mechanical strength. Therefore, the term "substrate" is specifically used as a synonym for "IC substrate" in the context of this application. It must be noted that the term "substrate" should not be confused with the term "base," as "base" is typically used in a wafer context, where it generally refers to the substrate material used in wafer fabrication as the basic material for constructing devices or circuits and forming the foundational layer supporting the electronic or photonic structures integrated into the wafer. This is not the meaning of "substrate" in the context of this application.

[0069] The substrate or interlayer may include or be composed of at least one of the following: glass; silicon (Si) and / or photoimageable or dry-etchable organic materials, such as epoxy-based stacked materials (e.g., epoxy-based stacked films); or polymer compounds (polymer compounds may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0070] In one embodiment, the at least one electrically insulating layer structure comprises at least one of the following: a resin or polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, melamine derivative, poly(p-phenylenebenzodioxazole) (PBO), bismaleimide-triazine resin, polyphenylene derivative (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing structures, such as meshes, fibers, spheres, or other types of filler particles made of glass (multilayer glass), may also be used to form the composite. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is called a prepreg. These prepregs are typically named according to their properties, such as FR4 or FR5, which describe their flame-retardant properties. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, especially epoxy-based stacked materials (e.g., stacked films) or photosensitive dielectrics, can also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins are preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0071] In one embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, and magnesium. Although copper is generally preferred, other materials or coating variations thereof, particularly those coated with superconducting materials or conductive polymers, are also possible, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0072] The at least one component may be selected from at least one of the following: non-electrically conductive inlays, electrically conductive inlays (e.g., metallic inlays, preferably copper or aluminum), heat transfer units (e.g., heat pipes), optical guiding elements (e.g., optical waveguides or optical conductor connectors), electronic components, or combinations thereof. The inlay may be, for example, a metal block (IMS-inlay) with or without an insulating material coating, which may be surface-mounted to facilitate heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to improve heat exchange capacity. In addition, components can be active electronic components (implemented with at least one pn junction), passive electronic components such as resistors, inductors, or capacitors, electronic chips, storage devices (e.g., DRAM or other data memories), filters, integrated circuits (e.g., field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, junction field-effect transistors (JFETs), or insulated-gate field-effect transistors). These include transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound; optoelectronic interface elements; light-emitting diodes; optocouplers; voltage converters (e.g., DC / DC converters or AC / DC converters); cryptographic components; transmitters and / or receivers; electromechanical transducers; sensors; actuators; microelectromechanical systems (MEMS); microprocessors; capacitors; resistors; inductors; batteries; switches; cameras; antennas; logic chips; and energy harvesting units. However, other components can also be surface-mounted onto component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnetic elements (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, the component can also be an IC substrate, an interposer, or another component carrier, such as a board-in-board configuration. The component can be surface-mounted onto the component carrier. In addition, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, may be used as components.

[0073] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayer composite structure that is stacked and connected together by applying pressure and / or heat.

[0074] After the internal layer structure of the component carrier has been treated, one or more additional electrically insulating and / or electrically conductive layer structures (particularly, through lamination) can be used to symmetrically or asymmetrically cover one main surface or two opposite main surfaces of the treated layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0075] After the formation of the stacked component with an electrically insulating layer structure and an electrically conductive layer structure is completed, the obtained layer structure or component carrier can be surface treated.

[0076] Specifically, in terms of surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, such a solder resist can be formed across the entire main surface and then the solder resist layer can be patterned to expose one or more electrically conductive surface portions, which will be used to electrically connect the component carrier to electronic peripherals. The surface portions of the component carrier covered by the solder resist, particularly those containing copper, can be effectively protected against oxidation or corrosion.

[0077] In terms of surface treatment, a surface finish can be selectively applied to the exposed electrically conductive surface portion of the component carrier. This surface finish can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or composed of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) will oxidize, resulting in lower reliability of the component carrier. Furthermore, the surface finish can be formed, for example, as a joint between a surface mount component and the component carrier. The surface finish functions to protect the exposed electrically conductive layer structure (especially copper circuitry), and the surface finish can achieve bonding processing with one or more components, for example, by soldering. Examples of suitable materials for the surface finish are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0078] The foregoing limitations and other aspects of the present invention will become apparent by way of examples of embodiments described below and will be explained with reference to these examples. Attached Figure Description

[0079] Figure 1 and Figure 2 A cross-sectional view of a structure obtained during the execution of a method for manufacturing a component carrier according to an exemplary embodiment of the present invention is shown.

[0080] Figure 3 A cross-sectional view of a component carrier according to an exemplary embodiment of the present invention is shown.

[0081] Figure 4 A three-dimensional image of a component carrier manufactured according to an exemplary embodiment of the present invention is shown.

[0082] Figure 5 Different cross-sectional views of various parts of a component carrier manufactured according to an exemplary embodiment of the present invention are shown.

[0083] Figures 6 to 9 Plan views of various parts of a component carrier manufactured according to an exemplary embodiment of the present invention are shown at different zoom levels. Detailed Implementation

[0084] The illustrations in the accompanying drawings are schematic. In different drawings, similar or identical elements are provided with the same reference numerals.

[0085] Before describing the exemplary embodiments in more detail with reference to the accompanying drawings, some basic considerations on which the exemplary embodiments of the present invention are based will be summarized.

[0086] To meet the trend of miniaturization in advanced packaging interconnects, glass core substrates may be superior to organic core substrates in terms of finer spacing or feature formation, and have good material properties.

[0087] To achieve high-density advanced packaging of multiple chips, it may be necessary to embed some chips into a glass core panel. Since removing the tape from the glass panel can be difficult, blind-via cavities may be a good choice for the glass core.

[0088] Current glass cavity formation is accomplished through etching following an ink printing process. However, this method may be insufficient to achieve precisely designed cavities due to challenges in ink thickness and alignment, as well as the chemical isotropic etching process. Therefore, improved methods for glass cavity formation may be needed to address current glass core fabrication issues.

[0089] According to an exemplary embodiment of the invention, a component carrier (e.g., a PCB or IC substrate) may be provided with a stack of preferably laminated layers having one or more (preferably, blind via) cavities. Advantageously, the bottom and sidewalls of the cavities may be formed with roughness Ra values ​​different from the roughness of the main surfaces of the electrically insulating layer structure (e.g., an inorganic carrier such as a glass carrier). This provides the advantage that the component carrier design can be specifically tailored, through appropriate manufacturing methods combined with appropriate material selection for the electrically insulating layer structure, to set the roughness Ra of the cavity boundary surfaces to be different from the roughness Ra of at least one of the main surfaces of the corresponding electrically insulating layer structure. By taking this approach, the roughness of the cavity can be locally adjusted according to the desired application. By way of example only, such an application could be embedding a component in the cavity, which can be facilitated by a relatively rough cavity due to the good adhesion of the component generated in the cavity. In another example, if the cavity forms part of a high-frequency component, such as a waveguide, for guiding high-frequency waves in an efficient manner, it may be desirable for the cavity walls to have a low roughness Ra. Advantageously, the cavity can be formed by selectively weakening defined portions of the electrically insulating layer material through laser processing, followed by etching to ultimately form the cavity. By appropriately defining the parameters and characteristics of this manufacturing method, the roughness Ra of the cavity can be designed in a desired manner.

[0090] According to an exemplary embodiment, a method is provided for forming a blind cavity in an electrically insulating layer structure of a stacked component, particularly on a glass core panel. Specifically, a Bessel beam laser application can be provided to ensure accurate depth of glass property modification, thereby precisely adjusting the cavity depth. Therefore, components can be embedded into the electrically insulating layer structure, preferably electronic components such as semiconductor wafers, which can preferably be implemented as a glass core.

[0091] Exemplary applications of exemplary embodiments of the present invention include glass interposers or substrates, high-performance computing (HPC) devices, and elevated fan-out bridge (EFB) glass interposer products.

[0092] In a preferred embodiment, a cavity with a characteristically defined roughness Ra in the electrical insulation layer structure of the component carrier can be formed by laser irradiation followed by wet etching. The laser type (in particular, the laser wavelength, pulse length, etc.) and laser processing parameters can be used to fine-tune the cavity surface characteristics, for example, for the formation of large-sized cavities.

[0093] According to an exemplary embodiment, a component carrier is provided, the component carrier including a stack and at least one cavity (e.g., an opening or a recess), the stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure, wherein the at least one electrically insulating layer structure has a first main surface and an opposite second main surface, the at least one cavity is formed at the first main surface of the at least one electrically insulating layer structure and is defined by a bottom wall and a side wall, wherein the surfaces of the bottom wall and the side wall in the cavity have a roughness different from the roughness of the main surface of the at least one electrically insulating layer structure.

[0094] Advantageously, the roughness of the bottom wall and / or sidewalls in the cavity is defined by peaks and valleys, which are distributed in a planar and linear manner along a partially straight direction (in particular, another portion may be non-straight). In one embodiment, the thickness extensions of the peaks (in particular, at least a plurality of peaks) follow the direction in which undercuts are formed along the thickness direction of the stack. For example, the thickness extensions of the peaks on the bottom wall follow a different direction than the thickness extensions of the peaks on the sidewall. For example, undercuts are provided in the cavity along the thickness direction of the stack by different extensions of the peaks. According to one embodiment, the overall planar and linear distribution of a plurality of valleys follows the same planar direction (in particular, more than 50% of the valleys follow the same planar direction). For example, the planar direction may be a diagonal direction. In one embodiment, the valley distribution divides the surface into adjacent island-like portions. Specifically, each or most of these island-like portions includes at least one peak, and more specifically, each or most of these island-like portions includes multiple peaks. For example, each island-like portion may have a planar extension (along the xy direction or in the xy plane) ranging from 0.2 μm to 15 μm. Advantageously, at least one valley-like portion may be configured as a passageway adjacent to multiple island-like portions. For example, the bottom wall and sidewalls are connected to each other by a transition wall, which is preferably an arcuate wall (or has a different shape and / or inclination). In one embodiment, the thickness extension of the peaks on the transition wall differs from the thickness direction of the peaks on the bottom wall and / or sidewalls. For example, the thickness extension of the peaks on the transition wall is variable; specifically, the thickness extension of the peaks on the transition wall gradually changes from the thickness direction of the peaks on the bottom wall toward the thickness direction of the peaks on the sidewalls. With this structure, the glass surface can have a uniform or substantially uniform roughness throughout the bottom wall or sidewalls. The texture of this glass can improve adhesion to the encapsulation material. Specifically, adhesion can be uniform or similar throughout the region, thus preventing gaps or delamination between the two layers. Furthermore, the stress in the altered areas can also be uniform or similar, which can prevent glass breakage. The laser irradiation onto the glass surface can also be uniform. This compressive stress at the main surface of the glass substrate can be balanced by tensile stress within the glass substrate (also known as "central tension"). Due to the advantages provided by embodiments of the invention, the cavity can be formed with a substantially straight angle. For example, the sidewalls of the cavity can be perpendicular to the main surface of the stack, specifically, the sidewalls of the cavity can be perpendicular to the main surface of the stack within a deviation of ±10°. In one embodiment, the first main surface and the second main surface are planar. Specifically, the surfaces of the bottom wall and the sidewalls in the cavity can have different roughnesses. For example, the roughness of the bottom wall is greater than the roughness of the sidewalls.For example, the surface roughness of the bottom wall and the surface roughness of the sidewalls provide an anchoring boundary region that anchors the attachment membrane or encapsulation material to the bottom and / or sidewalls of the cavity. In one embodiment, a plurality of cavities are provided, wherein at least two cavities may have different dimensions. Advantageously, at least one component may be embedded in the cavity. For example, the component may include the attachment membrane. In one embodiment, the inorganic layer structure comprises glass.

[0095] Regarding the method of manufacturing the component carrier, a combination of laser processing and etching is advantageous. Preferably, the cavity is formed by laser alteration of the glass properties followed by chemical etching. Regarding the type of laser source used, a green-emitting laser source is preferred. According to an exemplary embodiment, a method for forming a blind cavity in an electrically insulating layer structure, preferably in a glass core, can be provided. Components can be embedded in such (preferably, glass) cavities to form packaged component carriers, preferably electronic components, such as active semiconductor wafers and / or passive semiconductor wafers. Advantageously, the cavity can be formed by green laser processing followed by wet chemical etching. This allows the fabrication of cavities with a precisely defined roughness, which can be different from the roughness of the main surface of the electrically insulating layer structure (preferably, glass core) in which the cavity is formed, and preferably, can be greater than the roughness of the main surface of the electrically insulating layer structure (preferably, glass core) in which the cavity is formed.

[0096] Exemplary embodiments can allow for the fabrication of highly accurate cavities within a glass panel. The spatial laser irradiation range or position can be precisely controlled by a laser machine. The cavity depth can also be precisely controlled by laser processing and / or by subsequent wet etching parameters. Descriptively, the surface volume in the electrically insulating layer structure where the cavity is subsequently formed can be defined by a correspondingly defined laser processing. This can include defining the surface area and depth to which the cavity will be formed. Only this volume will be selectively altered (particularly mechanically and / or chemically weakened) by the laser processing. The subsequent etching process can then selectively remove only the altered areas of the electrically insulating layer structure to form the precisely defined cavity; preferably, this etching process is a wet etching process. By adjusting the characteristics of the laser processing and / or the wet etching, in particular, the roughness Ra of at least a portion of the walls defining the cavity can be precisely defined, and in particular, the roughness Ra of at least a portion of the walls defining the cavity can be defined to be different from (preferably greater than) the roughness Ra of the outer main surface of the electrically insulating layer structure. This allows for fine-tuning of the cavity's characteristics for desired applications, particularly for components to be embedded with appropriate adhesion.

[0097] More specifically, a wet chemical anisotropic etching process can be performed after green laser treatment to form one or more cavities within the electrically insulating layer structure. This wet chemical anisotropic etching process is selective for the laser-modified glass material of the electrically insulating layer structure. This allows for precise definition of the location and size of the blind glass cavities to be formed accurately within the glass panel.

[0098] Figure 1 and Figure 2 A cross-sectional view of the structure obtained during the execution of a method for manufacturing a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0099] Reference Figure 1 ,exist Figure 1 The diagram shows a stack 102 comprising an electrically insulating layer structure 106 and an electrically conductive layer structure 104. The electrically insulating layer structure 106 can be implemented as a glass plate or a glass core. The electrically conductive layer structure 104 is configured as copper-filled laser vias extending vertically between a first main surface 108 and an opposite second main surface 110 of the electrically insulating layer structure 106. Therefore, a plurality of oblong vias can be formed in the electrically insulating layer structure 106. The vias can then be filled with an electrically conductive material, for example, by plating or sputtering (e.g., non-plating after electroplating), such as titanium and copper, or copper alone. Figure 1 In this process, the copper-filled laser vias have an hourglass shape (or alternatively, a tapered or straight shape, depending on the laser processing method used). This means that the laser vias are formed by laser drilling from one main surface 108, 110, and then from the opposite main surface 110, 108. Each laser drilling process can form a blind via in the electrical insulating layer structure 106, wherein two blind vias can be connected to form an hourglass-shaped through-hole.

[0100] Furthermore, a blind-hole type cavity 116 is formed in the first main surface 108 of the glass material of the electrically insulating layer structure 106. For example... Figure 2 As shown, each cavity 116 is bounded by a bottom wall 112 and a side wall 114.

[0101] Each cavity 116 is formed through a two-stage process, which will be described below. (Refer to...) Figure 1 The first process is described, and references will be made. Figure 2 The subsequent second process is described.

[0102] exist Figure 1In the first process shown, the laser source 150 can scan a predetermined surface region of the electrically insulating layer structure 106. Therefore, the surface portion of the electrically insulating layer structure 106 adjacent to the first main surface 108 can be subjected to laser shock. Thus, the boundaries of each cavity 116 can be defined by laser processing. Advantageously, the laser source 150 can be configured to emit a green laser beam for the laser processing, the green laser beam being, in particular, a Bessel beam having, for example, a wavelength of 550 nm. The laser source 150 can be a pulsed laser for the laser processing, preferably a picosecond pulsed laser. For the laser processing, the laser beam of the laser source 150 can scan a surface region of the first main surface 108 of the electrically insulating layer structure 106 where the cavities 116 are to be formed. This defines the lateral boundaries of the cavities 116 to be formed and thus defines the positions of the sidewalls 114 of the cavities 116 to be formed. Advantageously, the laser emitted by the laser source 150 can be focused during the laser processing to a desired depth L of the corresponding cavity 116 within the electrically insulating layer structure 106. For example, the depth L of the corresponding cavity 116 can be in the range of 30 μm to 100 μm, such as 60 μm.

[0103] Through this process, a green laser emitted from laser source 150 can impact the entire volume of the electrically insulating layer structure 106, in which a corresponding cavity 116 will be formed. More precisely, the laser impacting the glass volume of the electrically insulating layer structure 106 can locally alter the glass properties of the electrically insulating layer structure 106 in which the at least one cavity 116 is to be formed. This alteration can be achieved through selective weakening of the glass material by the laser, which makes the laser-irradiated glass volume of the electrically insulating layer structure 106 easier to remove subsequently in the second processing stage described below. Surprisingly, the desired depth L of focusing the laser onto the cavity 116 to be formed can reliably and precisely limit the vertical region of the electrically insulating layer structure 106 that will subsequently be removed by etching. In summary, the focused picosecond pulsed laser scans the desired cavity region with an adjusted laser beam size. The laser is vertically focused to a desired depth L of the cavity 116 to be formed, wherein the corresponding vertical working distance of the laser beam can be adjusted by one or more lenses. Therefore, rapid laser aperture of the cavity region can be achieved in a focused depth-processing manner to alter the chemical and physical properties of the glass volume defined by the electrically insulating layer structure 106. In particular, the described process is highly suitable for glass because it selectively attacks the silicon oxide bonds in the glass. Specifically, the laser power, wavelength, irradiation time, scanning speed, and / or pulse parameters can be adjusted to selectively alter the characteristics of the irradiated portion of the electrically insulating layer structure 106 according to its material properties (e.g., glass, ceramic, or semiconductor).

[0104] Now refer to Figure 2 The second processing stage for forming cavity 116 will be described below. Figure 1 After selectively exposing the desired cavity volume portion to laser irradiation, the altered or weakened cavity volume portion material of the laser-irradiated glass volume portion of the electrical insulating layer structure 106 is removed. This can be achieved by performing a chemical wet etching of the electrical insulating layer structure 106 after the laser treatment. This chemical wet etching may involve subjecting the first main surface 108 of the electrical insulating layer structure 108 to an etchant based on hydrofluoric acid (HF). This chemical wet etching process allows for the selective removal of material that has been altered or weakened according to the laser irradiation. Figure 1 The modified glass material is subjected to laser treatment. More specifically, a wet chemical solution (including HF) can be used to etch the modified glass at a higher etching rate than the original glass. This etching can result in sloping sidewalls with a very high tilt angle close to the vertical direction. Thus, a cavity 116 with a generally rectangular cross-section can be formed.

[0105] Advantageously, the described manufacturing method allows the cavities 116 to be formed such that the surfaces of the bottom wall 112 and the side wall 114 of each respective cavity 116 have a roughness Ra that differs from the roughness of the first main surface 108 and the second main surface 110 of the electrical insulating layer structure 106. For example... Figure 2 As shown in detail 152, the roughness Ra at the bottom wall 112 and sidewall 114 of cavity 116 may be significantly greater than that at the first main surface 108 and the second main surface 110. Advantageously, when electronic components (e.g., semiconductor chips) are embedded in cavity 116 (as shown in detail 152), the roughness Ra may be significantly greater. Figure 3 When referring to reference numeral 136 in the accompanying drawings, the surface with increased roughness Ra that defines the cavity 116 can promote adhesion between the electrically insulating layer structure 106 and electronic components (e.g., semiconductor chips). Further advantageously, and still referring to... Figure 2 In detail 152, the minimum horizontal distance d between the first main surface 108 and the bottom wall 112 can be no greater than 15 μm; for example, the minimum horizontal distance d between the first main surface 108 and the bottom wall 112 can be 10 μm. Therefore, an almost vertical sidewall 114 can be obtained because the inclination angle of the sidewall 114 can be steeper compared to conventional methods of forming cavities in an electrically insulating layer structure. This almost vertical sidewall 114 is advantageous in terms of the compactness of the component carrier 100 and the controlled insertion of electronic components into such a cavity 116.

[0106] Figure 3 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown. For example, according to... Figure 3 The component carrier 100 can be implemented as an integrated circuit (IC) substrate or as a printed circuit board (PCB).

[0107] The illustrated component carrier 100 includes a stack 102 having multiple electrically insulating layer structures 106 and multiple electrically conductive layer structures 104. For example, the stack 102 may be a laminated stack consisting of a lower sub-stack in the form of a lower multilayer stack 154 and an upper sub-stack in the form of an upper multilayer stack 156, wherein the layers of the stack may include dielectric materials such as resin, glass fiber, or glass filler. A glass core 158 or glass plate forming the central electrically insulating layer structure 106 may be arranged between the lower multilayer stack 154 and the upper multilayer stack 156. Therefore, the stack 102 includes a central inorganic layer structure, which is implemented here as a glass core 158, but this central inorganic layer structure could also be another inorganic layer structure (such as ceramic or semiconductor, e.g., silicon). A lower multilayer stack 154 is formed beneath the inorganic layer structure, and an upper multilayer stack 156 is formed above the inorganic layer structure. The conductive layer structure 104 may include patterned copper layers that can form horizontal pads and / or horizontal wiring structures. Alternatively or concurrently, the conductive layer structure 104 may include vertical through-connections, such as copper pillars and / or copper-filled laser vias. Such vertical through-connections are also shown in the glass core 158, wherein the density of the through-connections may differ on the stack layers on the two sides of the glass core. Furthermore, the electrical insulating layer structures 106 above and below the glass core 158 may be, for example, prepreg or resin sheets. More generally, the electrical insulating layer structures 106 above and below the glass core 158 may include resins such as epoxy resin and optionally include reinforcing particles, such as glass fibers or glass spheres. The bottom electrical insulation layer structure 106 can be implemented as a patterned solder resist 160. Additionally, the top electrical insulation layer structure 106 can be implemented as a patterned solder resist 162.

[0108] On the bottom main surface of the component carrier 100, a plurality of electrically conductive connection elements 164, such as solder protrusions, may be exposed relative to patterned solder mask portions 160. The bottom-side electrically conductive connection elements 164 may be configured to mount the component carrier 100 (e.g., an integrated circuit (IC) substrate type) onto a mounting base, such as a printed circuit board (PCB, not shown). On the top main surface of the component carrier 100, a plurality of electrically conductive connection elements 166, such as solder protrusions, may be exposed relative to patterned solder mask portions 162. The top-side electrically conductive connection elements 166 may be configured to mount one or more electronic components 168 onto the top side of the component carrier 100. For example, the surface-mount electronic component 168 may be a semiconductor chip.

[0109] If still Figure 3 As shown, electronic components 136 can be embedded in the stack 102. More precisely, each electronic component of electronic components 136 can be inserted into the stack as described above. Figure 1 and Figure 2 In the designated cavity of the cavity 116 formed therein. Due to the intentionally high and locally increased roughness Ra of the sidewalls 114 and bottom wall 112 of the respective cavity 116 (especially high compared to the roughness at the main surfaces 108, 110), the attachment film 132 at the bottom side of the respective electronic component 136 can be suitably adhered to the bottom wall 112 of the cavity 116. Descriptively speaking, the wall with increased roughness Ra that defines the respective cavity 116 can act as an adhesion promoter for embedding the embedded electronic component 136 in the cavity 116. The remaining gap in the cavity 116, i.e., the gap between the glass core 158 and the respective electronic component 136, can be filled with encapsulation material 134. The encapsulation material 134 may be derived from an electrically insulating layer structure 106 (e.g., a sheet of prepreg, resin, photosensitive dielectric, solder resist, or adhesive) that may be directly attached to the upper main surface 108 of an inorganic electrically insulating layer structure 106, which is implemented here as a glass core. A lamination process may then be performed by increasing the temperature and / or applying mechanical pressure. Thus, the still-uncured resin of the electrically insulating layer structure 106 directly above the glass core can become flowable and can flow into the gaps or hollow areas between the glass core 158 and the electronic components 136 in the cavity 116. During the curing process, the resin may polymerize and / or crosslink and may be permanently recured, thereby forming a solid encapsulation material 134 in direct physical contact with the glass core 158 and the embedded electronic components 136. Therefore, the encapsulation material 134 is in direct physical contact with the sidewall 114 of the cavity 116, and optionally with the bottom wall 112 of the cavity 116, and with the surface of the electronic component 136. Furthermore, the locally increased roughness Ra during the formation of the encapsulation material 134 can have a positive effect. As an alternative to the lamination process, the encapsulation material 134 can also be inserted, for example, as an adhesive into the gap between the glass core 158 and the electronic component 136.

[0110] In one embodiment, electronic component 136 may be a bridging member for components surface-mounted on a component carrier. Therefore, the electrical path between the component carrier, the bridging member, and the components mounted on the surface of the component carrier can be shortened.

[0111] Figure 4 A three-dimensional image of a component carrier 100 manufactured according to an exemplary embodiment of the present invention is shown. Figure 5Different cross-sectional views of various portions of a component carrier 100 manufactured according to an exemplary embodiment of the present invention are shown. In particular, in Figure 5 The upper side shows an overview view of the region surrounding cavity 116 of the electrical insulating layer structure 106. Figure 5 On the lower side, different scaled portions of cavity 116 and different scaled portions surrounding cavity 116 are shown, namely, on the left side, the joint between the left side wall 114 and the first main surface 108 is shown, on the right side, the joint between the right side wall 114 and the first main surface 108 is shown, and in the middle, a detailed view of bottom wall 112 is shown. Figures 6 to 9 Plan views of various parts of a component carrier 100 manufactured according to an exemplary embodiment of the present invention are shown at different zoom levels. Figures 6 to 9 An enlarged view of the bottom wall 112 of cavity 116 is shown. More specifically, Figure 7 It shows Figure 6 Enlarged image, Figure 8 It shows Figure 7 An enlarged image, and Figure 9 It shows Figure 8 Enlarged image.

[0112] As shown in the figure, the component carrier 100 includes a stack 102, which may include one or more electrically insulating layer structures 106. Figure 4 and Figure 5 The focus is on the electrically insulating layer structure 106, which is made of glass and forms the core of the stack 102. Additionally, one or more electrically conductive layer structures 104 may be present, such as horizontal and / or vertical copper structures; however, these one or more electrically conductive layer structures 104... Figures 4 to 9 It is not visible in the middle. Figure 4 and Figure 5 The glass-core type electrical insulation layer structure 106 shown has a first main surface 108 and an opposite second main surface 110. Mainly, Figures 4 to 9 Features of the first main surface 108 and the cavity 116 formed in the first main surface 108 are shown.

[0113] The cavity 116 formed in the first main surface 108 is made of glass and is defined by a bottom wall 112 and side walls 114. Advantageously, the surfaces of the bottom wall 112 and the side walls 114 of the cavity 116 have a roughness Ra that is higher than the roughness of the surrounding portion of the first main surface 108 of the electrical insulating layer structure 106, such as in... Figure 5 The best view is seen in the images on the left and right sides. This is because it can be seen as described above. Figure 1 and Figure 2This is caused by the cavity manufacturing process performed on the site. The bottom wall 112 may have a different roughness Ra than the side wall 114, or it may have the same roughness Ra as the side wall 114. In particular, the surface of the bottom wall 112 may have a roughness Ra that is higher than the surface of the side wall 114. During the process of embedding the electronic component 136 into the cavity 116 (see contrast) Figure 3 During the reference numeral 136 in the figures, the roughness Ra of the surface of the bottom wall 112 and the roughness Ra of the surface of the side wall 114 can provide anchoring boundary regions for anchoring the attachment film 132 and / or encapsulation material 134 to the bottom wall 112 and the side wall 114 of the cavity 116. Therefore, the locally increased roughness Ra of the surfaces defining the cavity 116 can have the greatest advantage in improving the integrity of the component carrier 100 in which the electronic component 136 is embedded, and can prevent the glass core from breaking.

[0114] like Figure 5 Central detailed view and Figure 8 and Figure 9 As best seen in the cavity 116, the roughness Ra of the bottom wall 112 is defined by peaks 118 and valleys 120. Corresponding peaks 118 and valleys 120 may also exist at the sidewall 114, see [link to relevant documentation]. Figure 5 and Figure 8 The valley section 120 can be arranged along a straight valley section 122 in the plan view of the cavity 116, see [reference]. Figure 8 and Figure 9 Most of the valleys in valley 120 (e.g., more than 50% of the number of valleys 120) can be arranged in a plan view of cavity 116 along straight valley segments 122 extending generally parallel to each other, see also Figure 9 Furthermore, most of the valleys in valley 120 may extend along an inclined direction 124, which may be a diagonal direction relative to the sidewall 114. This can be seen from... Figure 8 As seen in the image. Furthermore, the peak 118 and the valley 120 can form undercut portions along the thickness direction 126 of the stack 102 within the thickness extension of the peak 118. This can be achieved... Figure 5 As seen in the bottom center image, the thickness extension of the peak 118 on the bottom wall 112 can follow a different direction relative to the thickness extension of the peak 118 on the side wall 114. (See again...) Figure 5The roughness Ra of the bottom wall 112 and the roughness Ra of the side wall 114 in the cavity 116 can be defined by the peak 118 and the valley 120, wherein the undercut of the peak 118 and the valley 120 is provided in the cavity 116 by different extensions of the peak 118 along the thickness direction 126 of the stack 102.

[0115] Reference Figure 9 The valley 120 can divide the peak 118 into islands 128, each island 128 including one or more peaks of the peak 118. Each island 128 can be defined by a groove surrounding it, the groove being defined by one or more valleys of the valley 120. In a plan view of the at least one cavity 116, some of the islands 128 can have a length B in the horizontal direction ranging from 0.2 μm to 15 μm, compared to... Figure 9 The valley portion 120 can be configured as a corridor adjacent to the island portion 128.

[0116] Now refer to Figure 5 The bottom images on the left and right sides show that the bottom wall 112 and the side wall 114 can be connected to each other by a transition wall 130, which can be an arc-shaped wall. The side wall 114 of the cavity 116 can be substantially perpendicular to the first main surface 108 and the second main surface 110; for example, the side wall 114 of the cavity 116 can be perpendicular to the first main surface 108 and the second main surface 110 within a deviation range of ±10°. (Referring to...) Figure 1 and Figure 2 The manufacturing process described has a much smaller deviation compared to conventionally manufactured cavities. The thickness extension of the peak 118 on the transition wall 130 may differ from the thickness extensions of the peak 118 on the bottom wall 112 and the side wall 114. In particular, the thickness extension of the peak 118 on the transition wall 130 may gradually change from the thickness extension of the peak 118 on the bottom wall 112 toward the thickness extension of the peak 118 on the side wall 114.

[0117] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Furthermore, elements described in conjunction with different embodiments can be combined.

[0118] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0119] Implementations of the present invention are not limited to the preferred embodiments shown in the figures and described above. Rather, even in fundamentally different embodiments, various modifications using the illustrated solutions and principles according to the invention are possible.

Claims

1. A component carrier (100), the component carrier (100) comprising: A stack (102) comprising at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), wherein the at least one electrically insulating layer structure (106) has a first main surface (108) and an opposite second main surface (110); and At least one cavity (116) is formed in the first main surface (108) of the at least one electrically insulating layer structure (106) and is bounded by a bottom wall (112) and a side wall (114); The surface of the bottom wall (112) and the surface of the side wall (114) of the at least one cavity (116) have a roughness Ra that is different from the roughness of the first main surface (108) and / or the roughness of the second main surface (110) of the at least one electrical insulating layer structure (106).

2. The component carrier (100) according to claim 1, wherein, The roughness Ra of the bottom wall (112) and / or the side wall (114) in the at least one cavity (116) is defined by peaks (118) and valleys (120), wherein at least a portion of the valleys (120) are arranged along a straight valley segment (122) in a plan view of the at least one cavity (116).

3. The component carrier (100) according to claim 1 or 2, wherein, The roughness Ra of the bottom wall (112) in the at least one cavity (116) is defined by peaks (118) and valleys (120), wherein most of the valleys (120) are arranged in a plan view of the at least one cavity (116) along straight valley segments (122) that extend substantially parallel to each other.

4. The component carrier (100) according to claim 3, wherein, Most of the valleys (120) extend in an inclined direction (124) relative to the sidewall (114), for example, most of the valleys (120) extend in a diagonal direction relative to the sidewall (114).

5. The component carrier (100) according to any one of claims 1 to 4, wherein, The roughness Ra of the bottom wall (112) and / or the side wall (114) in the at least one cavity (116) is defined by peaks (118) and valleys (120), wherein the thickness extensions of at least a plurality of peaks (118) form undercuts along the thickness direction (126) of the stack (102).

6. The component carrier (100) according to any one of claims 1 to 5, wherein, The roughness Ra of the bottom wall (112) and / or the side wall (114) in the at least one cavity (116) is defined by peaks (118) and valleys (120), wherein the thickness extensions of at least a plurality of peaks (118) on the bottom wall (112) follow different directions relative to the thickness extensions of at least a plurality of peaks (118) on the side wall (114).

7. The component carrier (100) according to any one of claims 1 to 6, wherein, The roughness Ra of the bottom wall (112) and / or the side wall (114) in the at least one cavity (116) is defined by peaks (118) and valleys (120), wherein undercuts are provided in the at least one cavity (116) along the thickness direction (126) of the stack (102) by different extensions of the peaks (118).

8. The component carrier (100) according to any one of claims 1 to 7, wherein, The roughness Ra of the bottom wall (112) and / or the side wall (114) in the at least one cavity (116) is defined by peaks (118) and valleys (120), wherein the valleys (120) divide the peaks (118) into islands (128), each of the islands (128) including at least one peak of the peaks (118), for example, each of the islands (128) including multiple peaks of the peaks (118).

9. The component carrier (100) according to claim 8, wherein, In a plan view of the at least one cavity (116), at least a portion of the island portion (128) has a length (B) in at least one horizontal direction ranging from 0.2 μm to 15 μm.

10. The component carrier (100) according to claim 8 or 9, wherein, At least one of the valleys (120) is configured as a passageway adjacent to a plurality of islands in the islands (128).

11. The component carrier (100) according to any one of claims 1 to 10, wherein, The bottom wall (112) and the side wall (114) are connected to each other by a transition wall (130), for example, the transition wall is an arc-shaped wall.

12. The component carrier (100) according to claim 11, wherein, The roughness Ra of the bottom wall (112) and / or the side wall (114) and / or the transition wall (130) in the at least one cavity (116) is defined by peaks (118) and valleys (120), and wherein the thickness extension of the peaks (118) on the transition wall (130) is different from the thickness extension of the peaks (118) on the bottom wall (112) and / or the side wall (114).

13. The component carrier (100) according to claim 12, wherein, The thickness extension of the peak (118) on the transition wall (130) changes from the thickness extension of the peak (118) on the bottom wall (112) toward the thickness extension of the peak (118) on the side wall (114). For example, the thickness extension of the peak (118) on the transition wall (130) gradually changes from the thickness extension of the peak (118) on the bottom wall (112) toward the thickness extension of the peak (118) on the side wall (114).

14. The component carrier (100) according to any one of claims 1 to 13, wherein, The sidewall (114) of the at least one cavity (116) is substantially perpendicular to the first main surface (108) and / or the second main surface (110), for example, the sidewall (114) of the at least one cavity (116) is perpendicular to the first main surface (108) and / or the second main surface (110) within a deviation of ±10°.

15. The component carrier (100) according to any one of claims 1 to 14, wherein, The first main surface (108) and / or the second main surface (110) are planar.

16. The component carrier (100) according to any one of claims 1 to 15, wherein, The surface of the bottom wall (112) has a different roughness Ra than the surface of the side wall (114).

17. The component carrier (100) according to any one of claims 1 to 16, wherein, The surface of the bottom wall (112) has a roughness Ra that is higher than that of the surface of the side wall (114).

18. The component carrier (100) according to any one of claims 1 to 17, wherein, The roughness Ra of the surface of the bottom wall (112) and / or the roughness Ra of the surface of the side wall (114) provides an anchoring boundary region for anchoring the attachment membrane (132) and / or the encapsulation material (134) at the bottom wall (112) and / or the side wall (114) of the at least one cavity (116).

19. The component carrier (100) according to any one of claims 1 to 18, wherein, A plurality of cavities (116) are formed in the first main surface (108) of the at least one electrical insulating layer structure (106), each of the cavities (116) being bounded by a corresponding bottom wall (112) and a corresponding side wall (114).

20. The component carrier (100) according to claim 19, wherein, The different cavities in the cavity (116) have different dimensions, and in particular, the different cavities in the cavity (116) have different dimensions in the horizontal plane and / or in the vertical direction.

21. The component carrier (100) according to any one of claims 1 to 20, the component carrier (100) comprising at least one component (136) embedded in the at least one cavity (116).

22. The component carrier (100) according to claim 21, wherein the component carrier (100) includes an attachment membrane (132) located in the at least one cavity (116), wherein, The at least one component (136) is attached via the attachment film (132).

23. The component carrier (100) according to any one of claims 1 to 22, wherein, The at least one electrically insulating layer structure (106) comprises glass, or the at least one electrically insulating layer structure (106) is composed of glass.

24. The component carrier (100) according to any one of claims 1 to 23, wherein, The surfaces of the bottom wall (112) and the side wall (114) have a roughness Ra that is higher than that of the first main surface (108) and / or the second main surface (110).

25. The component carrier (100) according to any one of claims 1 to 24, wherein, The minimum horizontal distance (d) between the first main surface (108) and the bottom wall (112) is not greater than 50 μm. For example, the minimum horizontal distance (d) between the first main surface (108) and the bottom wall (112) is not greater than 15 μm.

26. The component carrier (100) according to any one of claims 1 to 25, wherein, The depth (L) of the at least one cavity (116) is in the range of 10 μm to 200 μm, for example, the depth (L) of the at least one cavity (116) is in the range of 30 μm to 100 μm.

27. A method for manufacturing a component carrier (100), wherein, The method includes: A stack (102) is provided, the stack (102) including at least one electrically conductive layer structure (104) and at least one electrically insulating layer structure (106), wherein the at least one electrically insulating layer structure (106) has a first main surface (108) and an opposite second main surface (110); At least one cavity (116) is formed in the first main surface (108) of the at least one electrical insulating layer structure (106), and the at least one cavity (116) is defined by a bottom wall (112) and a side wall (114); and The at least one cavity (116) is formed such that the surface of the bottom wall (112) and the surface of the side wall (114) of the at least one cavity (116) have a roughness Ra that is different from the roughness of the first main surface (108) and / or the roughness of the second main surface (110) of the at least one electrical insulating layer structure (106).

28. The method of claim 27, wherein, The method includes: using laser processing to form the at least one cavity (116).

29. The method of claim 28, wherein, The method includes: after the laser processing, using etching to form the at least one cavity (116), for example, the etching is wet etching.

30. The method according to claim 28 or 29, wherein, The method includes performing the laser processing using a laser beam having a wavelength in the range of 520 nm to 580 nm, and in particular, the method includes performing the laser processing using a green laser.

31. The method according to any one of claims 28 to 30, wherein, The method includes performing the laser processing using a pulsed laser, for example, a picosecond pulsed laser.

32. The method according to any one of claims 28 to 31, wherein, The method includes, for the purpose of the laser processing, scanning the surface region of the at least one electrically insulating layer structure (106) where the at least one cavity (116) is to be formed with a laser beam.

33. The method according to any one of claims 28 to 32, wherein, The method includes, for the purpose of the laser processing, focusing a laser to a desired depth (L) of the at least one cavity (116) to be formed in the at least one electrically insulating layer structure (106).

34. The method according to any one of claims 28 to 33, wherein, The method includes, for the purpose of laser processing, configuring the laser to alter the properties of the glass on which the at least one electrically insulating layer structure (106) to be formed with the at least one cavity (116) is to be formed.

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