Semiconductor element with air gap protection structure with non-uniform thickness and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor device includes a substrate, a bit line, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of pads disposed on a side surface of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed on the substrate and close to the isolation spacer. The landing pad is disposed on the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes a higher portion above a top surface of the landing pad and a lower portion below the higher portion.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 918,359 (i.e., priority date "October 17, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device having an air gap protection structure with non-uniform thickness and a method for fabricating the same. Background Technology

[0003] Integrated circuits (ICs) are becoming increasingly powerful and smaller in size, with advancements in materials and design leading to successive generations of smaller and more complex circuits.

[0004] Reducing overlay errors in lithography is becoming increasingly important. For example, when defining the pattern of conductors to connect to a landing pad, sufficiently large overlay errors can cause misalignment between the conductors and the landing pad, resulting in the conductor material filling the air gaps in the insulating spacer and negatively impacting one or more electrical properties of the semiconductor element. Therefore, new semiconductor elements and methods are needed to mitigate such problems.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate; a plurality of isolation structures disposed in the substrate; a bit line disposed on the substrate; an isolation spacer disposed on one sidewall of the bit line and including an air gap; a landing pad disposed on the bit line; and an air gap protection structure covering the landing pad and the air gap. The isolation structure includes an isolation layer disposed in a trench in the substrate, and a plurality of pads disposed on the side surface of the trench.

[0007] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate; a bit line disposed on the substrate; an isolation spacer disposed on one sidewall of the bit line and including an air gap; a conductive layer disposed on the substrate and adjacent to the isolation spacer; a landing pad disposed on the bit line; and an air gap protection structure covering the landing pad and the air gap. The conductive layer includes a second portion and a first portion covering the second portion. The second portion includes a semi-circular cross-sectional profile or a semi-elliptical cross-sectional profile. The air gap protection structure includes a higher portion located above a top surface of the landing pad and a lower portion located below the higher portion, wherein the ratio of a thickness of the lower portion to a thickness of the higher portion is greater than 0.6 and less than 0.8.

[0008] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a trench in the first surface of the substrate; forming a plurality of pads disposed on the side surfaces of the trench; forming an isolation layer filling the trench; and removing a portion of the substrate from the second surface to expose the isolation layer and the pads.

[0009] This disclosure provides a semiconductor device with a non-uniform thickness air gap protection structure and a method for fabricating the same. The air gap protection structure includes a lower portion and a higher portion. The ratio of the thickness of the lower portion to the thickness of the higher portion is greater than 0.6 and less than 0.8, thereby protecting the air gap from being affected during subsequent processes. For example, the air gap of this disclosure can be free of metal atoms or other contaminants due to the protection of the air gap protection structure. As a result, the performance of the semiconductor device can be improved.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein similar reference numerals represent similar elements in the overall drawings, and:

[0012] Figure 1A Cross-sectional views of semiconductor devices are shown according to some embodiments of this disclosure.

[0013] Figure 1B A partial enlarged view of region R of the semiconductor element shown in FIG1 is shown according to some embodiments of the present disclosure.

[0014] Figure 2A According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0015] Figure 2B According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0016] Figure 2C According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0017] Figure 2D According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0018] Figure 2E According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0019] Figure 2F According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0020] Figure 2G According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0021] Figure 2H According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0022] Figure 2I According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0023] Figure 2J According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0024] Figure 2K According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0025] Figure 2L According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0026] Figure 3A and Figure 3B A flowchart of a method for fabricating a semiconductor device is shown according to some embodiments of this disclosure.

[0027] Figure 4A Cross-sectional views of semiconductor devices are shown according to various embodiments of this disclosure.

[0028] Figure 5A According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0029] Figure 5B According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0030] Figure 5C According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0031] Figure 5D According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0032] Figure 5E According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0033] Figure 5F According to some embodiments of this disclosure, one or more stages of a method for preparing a semiconductor device are shown.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 100: Semiconductor components

[0036] 103: First Surface

[0037] 105: Second Surface

[0038] 110: Substrate

[0039] 112: Isolation Structure

[0040] 113: Isolation Structure

[0041] 113': Lining

[0042] 113-1: Isolation layer

[0043] 113-3: Padding

[0044] 113T: Thickness

[0045] 114: Dielectric layer

[0046] 116: Bit line contact

[0047] 116': Conductive layer

[0048] 118: Bit line stacking

[0049] 118': Barrier layer

[0050] 118s1: Sidewall

[0051] 118s2: Sidewall

[0052] 120: Bit line

[0053] 120': Metallization layer

[0054] 120s1: Sidewall

[0055] 120s2: Sidewall

[0056] 122: Dielectric layer

[0057] 122s1: Sidewall

[0058] 122s2: Sidewall

[0059] 130-1: Isolation spacers

[0060] 130-2: Isolation spacers

[0061] 130s1: Sidewall

[0062] 130s2: Sidewall

[0063] 132-1: Dielectric layer

[0064] 132s1: Sidewall

[0065] 132-2: Dielectric layer

[0066] 132s2: Sidewall

[0067] 134-1: Air gap

[0068] 134-2: Air gap

[0069] 136-1: Dielectric layer

[0070] 136s1: Sidewall

[0071] 136-2: Dielectric layer

[0072] 136s2: Sidewall

[0073] 138-1: Dielectric layer

[0074] 138s1: Sidewall

[0075] 138-2: Dielectric layer

[0076] 138s2: Sidewall

[0077] 140: Capacitor Contact

[0078] 140TS: Top surface

[0079] 142: Stacked conductive structure

[0080] 144: Padding

[0081] 146: Landing pad

[0082] 146s1: Surface

[0083] 146s2: Surface

[0084] 148: Air gap protection structure

[0085] 148s1: Surface

[0086] 148s2: Surface

[0087] 148p1: Lower part

[0088] 148p2: Higher section

[0089] 160: Trench

[0090] 162: Trench

[0091] 164: Trench

[0092] 200: Method

[0093] 201: Doped region

[0094] 202: Operation

[0095] 204: Operation

[0096] 206: Operation

[0097] 208: Operation

[0098] 210: Operation

[0099] 212: Operation

[0100] 214: Operation

[0101] 216: Operation

[0102] 218: Operation

[0103] 220: Operation

[0104] 222: Operation

[0105] 224: Operation

[0106] 300: Semiconductor components

[0107] 301: Conductive layer

[0108] 301-1: Part One

[0109] 301-1BS: Bottom surface

[0110] 301-1E: End

[0111] 301-1TS: Top surface

[0112] 301-3: Part Two

[0113] 301-3BS: Bottom surface

[0114] 301-3TS: Top surface

[0115] H1: Hole

[0116] L1: Width

[0117] L2: Width

[0118] P1: Deposition process

[0119] R: Region

[0120] T1: Thickness

[0121] T2: Thickness

[0122] TR1: Trench

[0123] TR-bs: Bottom surface

[0124] TR-s1: Side surface

[0125] TR-s2: Side surface Detailed Implementation

[0126] The following discloses various embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to define relationships between the different embodiments and / or structures discussed.

[0127] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0128] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the concepts of this disclosure. As used herein, unless the context explicitly indicates otherwise, the singular forms “a / an” and “the” also include the plural forms. It should be understood that the terms “comprises” and “comprising” as used in this specification indicate the presence of said components, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more components, integers, steps, operations, elements, components, or combinations thereof.

[0129] Figure 1A A cross-sectional view of a semiconductor element 100 is shown according to some embodiments of this disclosure. In some embodiments, the semiconductor element 100 may include cell regions in which memory elements are formed. The memory elements may include, for example, dynamic random-access memory (DRAM) elements, one-time programming (OTP) elements, static random-access memory (SRAM) elements, or other suitable elements. In some embodiments, DRAM may include, for example, transistors, capacitors, and / or other components. During a read operation, a word line (WL) is asserted, thereby turning on a transistor. The turned-on transistor allows a sense amplifier to read the voltage across a capacitor via a bit line (BL). During a write operation, data to be written is provided on the bit line when the word line is asserted.

[0130] In some embodiments, the semiconductor element 100 may include a surrounding area for forming logic elements (e.g., system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) elements, sensor elements, micro-electro-mechanical system (MEMS) elements, signal processing elements (e.g., digital signal processing (DSP) elements), front-end elements (e.g., analog front-end (AFE) elements), or other elements.

[0131] Semiconductor element 100 may include substrate 110. Substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Substrate 110 may include elemental semiconductors, including single-crystal, polycrystalline, or amorphous forms of silicon or germanium; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature. In some embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, another material in contact with the SiGe alloy may cause the SiGe alloy to be mechanically strained. In some embodiments, substrate 110 may have a multilayer structure, or substrate 110 may include a multilayer compound semiconductor structure.

[0132] In some embodiments, the substrate 110 may include a plurality of active regions. The active regions may be used as channels, for example, for electrical connections.

[0133] In some embodiments, the semiconductor device 100 may include a plurality of isolation structures 112. In some embodiments, active regions may be separated by isolation structures 112. In some embodiments, isolation structures 112 may be embedded in a substrate 110. In some embodiments, isolation structures 112 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), or other suitable materials.

[0134] In some embodiments, the semiconductor device 100 may include a dielectric layer 114. The dielectric layer 114 may be disposed on a substrate 110. In some embodiments, the dielectric layer 114 may cover a portion of the isolation structure 112. In some embodiments, the dielectric layer 114 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), a high-k dielectric material, or a combination thereof. Examples of high-k dielectric materials include dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO2), or dielectric materials with a dielectric constant greater than about 3.9. In some embodiments, the dielectric layer 114 may include at least one metal element, such as hafnium oxide (HfO2), silicon-doped hafnium oxide (HSO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), or a combination thereof.

[0135] In some embodiments, the semiconductor element 100 may include a bit line contact 116. In some embodiments, the bit line contact 116 may be disposed on an active region of the substrate 110. The bit line contact 116 may include a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or a metallic material having suitable resistivity and gap-filling capability.

[0136] In some embodiments, the semiconductor device 100 may include a plurality of bit line stacks 118. In some embodiments, the bit line stacks 118 may include a multilayer structure. In some embodiments, a portion of the bit line stacks 118 may be disposed on a bit line contact 116. In some embodiments, a portion of the bit line stacks 118 may be in contact with the bit line contact 116. In some embodiments, a portion of the bit line stacks 118 may be electrically connected to the bit line contact 116. In some embodiments, a portion of the bit line stacks 118 may be disposed on a dielectric layer 114. In some embodiments, a portion of the bit line stacks 118 may be in contact with the dielectric layer 114. The bit line stacks 118 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), manganese nitride (MnN), or combinations thereof.

[0137] In some embodiments, the semiconductor element 100 may include a plurality of bit lines 120. In some embodiments, each bit line 120 may be disposed on a bit line stack 118. In some embodiments, a portion of the bit line 120 may be disposed on a bit line contact 116. In some embodiments, a portion of the bit line 120 may be electrically connected to the bit line contact 116. In some embodiments, a portion of the bit line 120 may be disposed on a dielectric layer 114. The bit lines 120 may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof.

[0138] In some embodiments, the semiconductor device 100 may include a plurality of dielectric layers 122. In some embodiments, each dielectric layer 122 may be disposed on a bit line 120. In some embodiments, the dielectric layer 122 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, a high dielectric constant material, or a combination thereof.

[0139] In some embodiments, the semiconductor element 100 may include a plurality of isolation spacers 130-1 and 130-2. Isolation spacer 130-1 may be disposed on the sidewall 120s1 of the bit line 120. Isolation spacer 130-2 may be disposed on the sidewall 120s2 of the bit line 120. Although Figure 1A The isolation spacers 130-1 and 130-2 are shown separated in the cross-sectional view. It should be noted that, from the top view, the isolation spacers 130-1 and 130-2 may be part of an integral (or monolithic) structure, wherein the integral structure has a circular outline, an elliptical outline, or a similar outline.

[0140] In some embodiments, the spacer 130-1 may have a dielectric layer 132-1, an air gap 134-1, and a dielectric layer 136-1. In some embodiments, the spacer 130-2 may have a dielectric layer 132-2, an air gap 134-2, and a dielectric layer 136-2. In some embodiments, dielectric layers 132-1 and 132-2 may be formed on the sidewalls of the bit line contact 116, the bit line stack 118, the bit line 120, and the dielectric layer 122. For example, dielectric layer 132-1 may be formed on the sidewall 120s1 of the bit line 120, and dielectric layer 132-2 may be formed on the sidewall 120s2 of the bit line 120. In some embodiments, dielectric layer 132-1 may contact the sidewall 120s1 of the bit line 120. In some embodiments, dielectric layer 132-2 may contact the sidewall 120s2 of the bit line 120. In some embodiments, a portion of dielectric layer 132-1 may be embedded in substrate 110. In some embodiments, a portion of dielectric layer 132-2 may be embedded in substrate 110.

[0141] In some embodiments, air gap 134-1 may be spaced apart from bit line 120 by dielectric layer 132-1. In some embodiments, air gap 134-2 may be spaced apart from bit line 120 by dielectric layer 132-2. In some embodiments, air gap 134-1 may be disposed between dielectric layers 132-1 and 136-1. In some embodiments, air gap 134-2 may be disposed between dielectric layers 132-2 and 136-2. In some embodiments, the length of air gap 134-2 may be less than the length of air gap 134-1. Although FIG1 shows that air gap 134-1 and air gap 134-2 are spaced apart or different, it should be noted that in some embodiments, air gap 134-1 may be connected to air gap 134-2.

[0142] In some embodiments, dielectric layer 136-1 may be disposed on dielectric layer 132-1. In some embodiments, dielectric layer 136-2 may be disposed on dielectric layer 132-2. In some embodiments, each of dielectric layers 132-1, 132-2, 136-1, and 136-2 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, a high dielectric constant material, or a combination thereof. Although Figure 1A The dielectric layer 132-1 is shown to be spaced apart from the dielectric layer 136-1, but in some embodiments, the dielectric layer 132-1 may be connected to the dielectric layer 136-1.

[0143] In some embodiments, the semiconductor element 100 may include capacitor contacts 140. In some embodiments, capacitor contacts 140 may be formed between two bit lines 120. In some embodiments, capacitor contacts 140 may be formed between spacers 130-1 and 130-2. In some embodiments, capacitor contacts 140 may be formed between dielectric layers 136-1 and 136-2. In some embodiments, capacitor contacts 140 may be formed between sidewall 130s1 of spacer 130-1 and sidewall 130s2 of spacer 130-2. Capacitor contacts 140 may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or other metallic materials.

[0144] In some embodiments, the semiconductor element 100 may include a stacked conductive structure 142. The stacked conductive structure 142 may include a multilayer structure. In some embodiments, the stacked conductive structure 142 may be formed on the top surface of the capacitor contact 140. In some embodiments, the stacked conductive structure 142 may include a metal silicide, such as cobalt silicide (CoSi), or other suitable materials.

[0145] In some embodiments, the semiconductor element 100 may include a pad 144. In some embodiments, the pad 144 may be formed on the top surface of the stacked conductive structure 142. In some embodiments, the pad 144 may be formed on the sidewall 130s1 of the spacer 130-1. In some embodiments, the pad 144 may be formed on the sidewall of the dielectric layer 136-1. In some embodiments, the pad 144 may be formed on the sidewall 130s2 of the spacer 130-2. In some embodiments, the pad 144 may be formed on the sidewall of the dielectric layer 136-2. In some embodiments, the pad 144 may include a metal nitride, such as titanium nitride (TiN), or other suitable materials.

[0146] In some embodiments, the semiconductor element 100 may include a plurality of landing pads 146. Landing pads 146 may be configured to be electrically connected to a capacitor structure (not shown). In some embodiments, landing pads 146 may be formed on a liner 144. In some embodiments, landing pads 146 may be formed between two bit lines 120. In some embodiments, landing pads 146 may be formed between spacers 130-1 and 130-2. In some embodiments, landing pads 146 may cover the top surface of spacer 130-1. In some embodiments, landing pads 146 may cover the top surface of dielectric layer 132-1. In some embodiments, landing pads 146 may cover the top surface of dielectric layer 136-1. In some embodiments, air gap 134-1 may be covered by landing pads 146. In some embodiments, air gap 134-2 may not perpendicularly overlap with landing pads 146. In some embodiments, a portion of landing pads 146 may be surrounded by liner 144. In some embodiments, landing pads 146 may cover the top surface of dielectric layer 122. In some embodiments, landing pad 146 may include a higher portion located above dielectric layer 122 and a lower portion located between adjacent dielectric layers 122. In some embodiments, landing pad 146 may include a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof. Landing pad 146 may have a surface 146s1 and a surface 146s2. Surface 146s1 (or top surface) may face away from substrate 110. Surface 146s2 (or side surface) may be continuous with the side surface of dielectric layer 122.

[0147] In some embodiments, the landing pad 146, dielectric layer 122, and spacer 130-2 may define an aperture H1 (or opening). The aperture H1 may have an aspect ratio equal to or greater than 2, such as 2, 2.3, 2.5, 2.8, 3, or greater. The aspect ratio may be defined as the ratio of the width (or aperture) of the aperture H1 (e.g., the distance between adjacent landing pads) to the depth of the aperture H1 (e.g., the distance between surface 146s1 and the top of spacer 130-2).

[0148] In some embodiments, the semiconductor element 100 may include an air gap protection structure 148. In some embodiments, a portion of the air gap protection structure 148 may be disposed within an aperture H1. In some embodiments, the air gap protection structure 148 may cover a landing pad 146. In some embodiments, the air gap protection structure 148 may cover an isolation spacer 130-2. In some embodiments, an air gap 134-2 may be covered by the air gap protection structure 148. In some embodiments, the air gap protection structure 148 may be spaced apart from the isolation spacer 130-1 by the landing pad 146. The air gap protection structure 148 may have a surface 148s1 and a surface 148s2. Surface 148s1 (or top surface) may face away from the substrate 110. Surface 148s2 (or side surface) may cover surface 146s2. The air gap protection structure 148 may be configured to protect the air gap 134-2 to ensure the desired parasitic capacitance. In some embodiments, the air gap protection structure 148 may have a non-uniform thickness. In some embodiments, the air gap protection structure 148 may include silicon nitride and other impurities. In some embodiments, the air gap protection structure 148 may include atoms, molecules, or ions of silicon, carbon, nitrogen, and hydrogen. In some embodiments, the air gap protection structure 148 may be composed of carbon with an atomic ratio equal to or greater than 4.8%, such as 4.8%, 4.9%, 5%, or more. In some embodiments, the air gap protection structure 148 may be composed of silicon with an atomic ratio between about 48% and about 50%. In some embodiments, the air gap protection structure 148 may be composed of nitrogen with an atomic ratio between about 46% and about 49%. In some embodiments, the silicon content in the air gap protection structure 148 may be greater than the nitrogen content in the air gap protection structure 148.

[0149] Reference Figure 1BThe air gap protection structure 148 may have a lower portion 148p1 with thickness T1 located between surfaces 146s2 and 148s2, and a higher portion 148p2 with thickness T2 located between surfaces 146s1 and 148s1. The lower portion 148p1 may be disposed in the hole H1. The higher portion 148p2 may be located above the lower portion 148p1 and above surface 146s1. In some embodiments, the thickness T1 may be less than the thickness T2. In some embodiments, the ratio of thickness T1 to thickness T2 may be between about 0.6 and about 0.8. In some embodiments, the ratio of thickness T1 to thickness T2 may be greater than 0.6, such as 0.61, 0.62, 0.63, 0.64, 0.65, 0.66, 0.67, 0.68, 0.69, 0.7, 0.72, 0.74, 0.76, 0.78, or 0.8.

[0150] The hole H1 defined by the air gap protection structure 148 may have a width L1 (or aperture) at the top of the air gap protection structure 148 (e.g., at surface 148s1) and a width L2 (or aperture) at the middle or bottom of the air gap protection structure 148. In some embodiments, the width L1 may be smaller than the width L2.

[0151] As described above, the aperture defined by the landing pad and the isolation structure has a relatively large aspect ratio (e.g., aspect ratio greater than 2) and a narrower aperture at the top, thus preventing the dielectric material from easily filling the aperture. Therefore, the lower portion of the air gap protection structure does not have sufficient thickness to effectively protect the air gap, resulting in high parasitic capacitance. When the ratio of the thickness T1 of the lower portion 148p1 of the air gap protection structure 148 to the thickness T2 of the higher portion 148p2 of the air gap protection structure 148 is greater than 0.6, preferably equal to or greater than 0.66, the air gap 134-2 can be protected unaffected during subsequent processes. For example, in the comparative example, since the air gap 134-2 is not effectively protected, metal atoms or other contaminants can diffuse into the air gap 134-2 during subsequent processes. Conversely, in the current embodiment, due to the protection of the air gap protection structure 148, the air gap 134-2 may be free of metal atoms or other contaminants, and the lower portion 148p1 of the air gap protection structure 148 has a relatively large thickness.

[0152] Figures 2A to 2L The various stages of a method for preparing a semiconductor element 100 are shown according to some embodiments of this disclosure.

[0153] Reference Figure 2AA substrate 110 is provided. In some embodiments, the substrate 110 may include a plurality of active regions separated by a plurality of isolation structures 112. A dielectric layer 114 may be formed on the substrate 110. In some embodiments, the substrate 110 may include active regions and isolation structures 112. In some embodiments, the fabrication techniques of the dielectric layer 114 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0154] Reference Figure 2B A trench 160 may be formed. In some embodiments, the trench 160 may be recessed into the top surface of the substrate 110. In some embodiments, the trench 160 may be recessed into the top surface of the dielectric layer 114. In some embodiments, the trench 160 may be defined by the dielectric layer 114, the substrate 110, and the isolation structure 112. In some embodiments, an etching process may be performed to form the trench 160. The etching process may include dry etching, wet etching, or a combination thereof.

[0155] Reference Figure 2C A conductive layer 116' may be formed. In some embodiments, the conductive layer 116' may fill the trench 160. In some embodiments, the conductive layer 116' may be surrounded by a dielectric layer 114. In some embodiments, the conductive layer 116' may be surrounded by a substrate 110. In some embodiments, the fabrication technology of the conductive layer 116' may include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes. Furthermore, a chemical polishing process may be performed to planarize the top surfaces of the conductive layer 116' and the dielectric layer 114.

[0156] Reference Figure 2DA barrier layer 118', a metallization layer 120', and a dielectric layer 122 can be formed sequentially. The barrier layer 118' can be fabricated using CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes. The metallization layer 120' can be formed on the barrier layer 118'. The metallization layer 120' can be fabricated using CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes. The dielectric layer 122 can be formed on the metallization layer 120'. The dielectric layer 122 can be fabricated using CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes.

[0157] In some embodiments, barrier layer 118' may cover substrate 110. In some embodiments, barrier layer 118' may cover dielectric layer 114.

[0158] In some embodiments, the metallization layer 120' may be configured to form bit lines 120. In some embodiments, the metallization layer 120' may cover the barrier layer 118'.

[0159] In some embodiments, dielectric layer 122 may cover metallization layer 120'.

[0160] Reference Figure 2E A portion of the metallization layer 120' can be removed to form a plurality of bit lines 120. In some embodiments, a portion of the barrier layer 118' can be removed to form a plurality of bit line stacks 118. In some embodiments, a portion of the dielectric layer 122 can be removed. An etching process can be performed to remove portions of the metallization layer 120', the barrier layer 118', and the dielectric layer 122. The etching process may include dry etching, wet etching, or other suitable processes.

[0161] In some embodiments, the sidewalls 120s1 and 120s2 of the bit line 120 may be exposed. It should be noted that, from a top view perspective, each of the dielectric layer 122, the bit line 120, and the bit line stack 118 may have a circular profile, an elliptical profile, or a similar profile, and the sidewalls of the dielectric layer 122, the bit line 120, and the bit line stack 118 may be shown as lateral edges in a cross-sectional view.

[0162] In some embodiments, bit line stack 118 may expose a portion of conductive layer 116'. In some embodiments, bit line 120 may expose a portion of conductive layer 116'. In some embodiments, dielectric layer 122 may expose a portion of conductive layer 116'.

[0163] In some embodiments, a portion of bit line 120 may be disposed on conductive layer 116'. In some embodiments, a portion of bit line stack 118 may be disposed on conductive layer 116'. In some embodiments, a portion of bit line 120 may be disposed on isolation structure 112. In some embodiments, a portion of bit line stack 118 may be disposed on isolation structure 112.

[0164] Reference Figure 2F A portion of the conductive layer 116' is removed to form a bit line contact 116 in the trench 162. In some embodiments, the portion of the conductive layer 116' exposed by the bit line 120 may be removed. In some embodiments, the portion of the conductive layer 116' exposed by the bit line stack 118 may be removed. In some embodiments, the portion of the conductive layer 116' exposed by the dielectric layer 122 may be removed. In some embodiments, the bit line contact 116 may taper gradually in the direction from the bit line 120 toward the substrate 110.

[0165] Reference Figure 2G Multiple dielectric layers 132-1, 132-2, 138-1, 138-2, 136-1, and 136-2 can be formed. In some embodiments, dielectric layers 132-1 and 132-2 can be formed on the sidewalls of bit line contact 116, bit line stack 118, bit line 120, and dielectric layer 122. For example, dielectric layer 132-1 can be formed on the sidewall 120s1 of bit line 120, and dielectric layer 132-2 can be formed on the sidewall 120s2 of bit line 120. In some embodiments, dielectric layer 132-1 can be in contact with the sidewall 120s1 of bit line 120. In some embodiments, dielectric layer 132-2 can be in contact with the sidewall 120s2 of bit line 120. It should be noted that dielectric layer 132-1 and dielectric layer 132-2 may be part of an integral (or monolithic) structure, and from a top view, the integral structure may have a circular outline, an elliptical outline, or a similar outline.

[0166] In some embodiments, dielectric layer 138-1 may be disposed on the sidewall 132s1 of dielectric layer 132-1. In some embodiments, dielectric layer 138-2 may be disposed on the sidewall 132s2 of dielectric layer 132-2. It should be noted that dielectric layers 138-1 and 138-2 may be part of an integral (or monolithic) structure, and from a top view, the integral structure may have a circular outline, an elliptical outline, or a similar outline.

[0167] In some embodiments, dielectric layer 136-1 may be disposed on the sidewall 138s1 of dielectric layer 138-1. In some embodiments, dielectric layer 136-2 may be disposed on the sidewall 138s2 of dielectric layer 138-2. In some embodiments, dielectric layer 136-1 may be spaced apart from dielectric layer 132-1 by dielectric layer 138-1. In some embodiments, dielectric layer 136-2 may be spaced apart from dielectric layer 132-2 by dielectric layer 138-2. It should be noted that dielectric layers 136-1 and 136-2 may be part of an integral (or monolithic) structure, and from a top view, the integral structure may have a circular outline, an elliptical outline, or a similar outline.

[0168] In some embodiments, dielectric layer 138-1 may comprise a material different from that of dielectric layers 132-1 and 136-1. In some embodiments, dielectric layer 132-1 may comprise the same material as dielectric layer 136-1. In some embodiments, dielectric layer 138-2 may comprise a material different from that of dielectric layers 132-2 and 136-2. In some embodiments, dielectric layer 132-2 may comprise the same material as dielectric layer 136-2. A trench 164 may be defined between dielectric layers 136-1 and 136-2. The contours of dielectric layers 132-1, 132-2, 138-1, 138-2, 136-1, and 136-2 may be modified by appropriate etching processes, and this disclosure is not intended to be limiting.

[0169] Reference Figure 2H A capacitor contact 140 can be formed. The capacitor contact 140 can be formed in a trench 164. The fabrication techniques for the capacitor contact 140 may include, for example, CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes. In some embodiments, the capacitor contact 140 can be formed between two bit lines 120. In some embodiments, the capacitor contact 140 can be formed between dielectric layers 136-1 and 136-2.

[0170] Reference Figure 2I Dielectric layer 138-1 can be removed to form an air gap 134-1. Dielectric layer 138-2 can be removed to form an air gap 134-2. As a result, multiple spacers 130-1 and 130-2 are created. In some embodiments, air gap 134-1 can be separated from bit line 120 by dielectric layer 132-1. In some embodiments, air gap 134-2 can be separated from bit line 120 by dielectric layer 132-2. The removal techniques for dielectric layers 138-1 and 138-2 may include etching processes, such as dry etching, wet etching, or a combination thereof.

[0171] Reference Figure 2JA stacked conductive structure 142, a pad 144, and a landing pad 146 can be formed. The stacked conductive structure 142 can be formed in a trench 164. In some embodiments, the stacked conductive structure 142 can be formed on the top surface of the capacitor contact 140. In some embodiments, the stacked conductive structure 142 can be formed between dielectric layers 136-1 and 136-2. The fabrication techniques for the stacked conductive structure 142, the pad 144, and the landing pad 146 may include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes.

[0172] In some embodiments, pad 144 may be formed on the top surface of the stacked conductive structure 142. In some embodiments, pad 144 may be formed on the sidewall 130s1 of the spacer 130-1. In some embodiments, pad 144 may be formed on the sidewall 136s1 of the dielectric layer 136-1. In some embodiments, pad 144 may be formed on the sidewall 130s2 of the spacer 130-2. In some embodiments, pad 144 may be formed on the sidewall 136s2 of the dielectric layer 136-2.

[0173] In some embodiments, a landing pad 146 may be formed on a liner 144. In some embodiments, a landing pad 146 may be formed between two bit lines 120. In some embodiments, a landing pad 146 may be formed between spacers 130-1 and 130-2. In some embodiments, a landing pad 146 may cover the top surface of spacer 130-1. In some embodiments, a landing pad 146 may cover the top surface of dielectric layer 132-1. In some embodiments, a landing pad 146 may cover the top surface of dielectric layer 136-1. In some embodiments, an air gap 134-1 may be covered by a landing pad 146. In some embodiments, a landing pad 146 may cover the top surface of dielectric layer 132-2. In some embodiments, a landing pad 146 may cover the top surface of dielectric layer 136-2. In some embodiments, an air gap 134-2 may be covered by a landing pad 146. In some embodiments, a landing pad 146 may cover the top surface of dielectric layer 122. In some embodiments, the landing pad 146 may be formed in a trench 164 defined by the isolation spacers 130-1 and 130-2.

[0174] Reference Figure 2K A portion of the landing pad 146 can be removed or patterned. The aperture H1 may be defined by the landing pad 146, the dielectric layer 122, and the spacers 130-2. A portion of the landing pad 146 can be removed via an etching process. In some embodiments, the aperture H1 may have an aspect ratio greater than 2.

[0175] Reference Figure 2LA deposition process P1 can be performed to form a gas gap protection structure 148 in the hole H1, thereby producing a semiconductor device 100. The fabrication techniques for the gas gap protection structure 148 may include ALD, CVD, PVD, or other suitable processes. The gas gap protection structure 148 may have a lower portion 148p1 and a higher portion 148p2. In some embodiments, the ratio of the thickness of the lower portion 148p1 to the thickness of the higher portion 148p2 may be greater than 0.6, preferably equal to or greater than 0.66.

[0176] In some embodiments, the hole H1 may have a smaller width or aperture (e.g., L1) at the top of the air gap protection structure 148 (e.g., at the surface 148s1) and a larger width or aperture (e.g., L2) at the middle or bottom of the air gap protection structure 148.

[0177] In some embodiments, the air gap protection structure 148 may include silicon nitride and other impurities, such as carbon and / or hydrogen. In some embodiments, the temperature range of the deposition process P1 may be from about 530°C to about 570°C, such as 530°C, 540°C, 550°C, 560°C, or 570°C.

[0178] In some embodiments, the pressure of the deposition process P1 may be equal to or less than 3 Torr, such as 3 Torr, 2.5 Torr, 2 Torr, 1.5 Torr, or 1 Torr, or less.

[0179] In some embodiments, the deposition process P1 may include the use of gases such as silane (SiH4), ammonia (NH3), tetramethylsilane (TMS), nitrogen (N2), or combinations thereof, including reactive and non-reactive gases. In some embodiments, the deposition process P1 does not include helium (He). More specifically, He is not used during the step of depositing the gas gap protection structure 148. However, He may be used during stages before or after the deposition of the gas gap protection structure 148, such as heating, cooling, purging, or other steps.

[0180] In some embodiments, during the deposition process P1, the flow rate of SiH4 may be equal to or greater than 200 sccm, such as 200 sccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm, 300 sccm, 320 sccm, or more.

[0181] In some embodiments, during the deposition process P1, the flow rate of NH3 may be equal to or greater than 600 sccm, such as 600 sccm, 1,500 sccm, 2,200 sccm, 2,700 sccm, 3,200 sccm, 4,000 sccm, or more.

[0182] In some embodiments, during the deposition process P1, the flow rate of the TMS may be equal to or greater than 45 sccm, such as 45 sccm, 48 sccm, 50 sccm, 55 sccm, or more.

[0183] In some embodiments, during the deposition process P1, the flow rate of N2 may be equal to or less than 10,000 sccm, such as 10,000 sccm, 7,000 sccm, 4,000 sccm, 1,000 sccm, or less.

[0184] In some embodiments, the deposition rate of the air gap protection structure 148 may be equal to or less than that of the air gap protection structure 148. Like Or smaller.

[0185] Due to the aforementioned process conditions, the ratio of the thickness T1 to the thickness T2 of the air gap protection structure 148 can be greater than 0.6, thereby protecting the air gap 134-2 during subsequent processes.

[0186] Figure 3A and 3B A flowchart of a method 200 for preparing a semiconductor device is shown according to some embodiments of this disclosure.

[0187] Reference Figure 3A Method 200 begins with operation 202, which involves providing a substrate. For example, as... Figure 2A As shown, a substrate 110 may be provided. The substrate 110 may include a plurality of active regions separated by an isolation structure 112. In some embodiments, a first dielectric layer 114 may be formed on the substrate 110. In some embodiments, the substrate 110 may include active regions and an isolation structure 112. In some embodiments, a plurality of word lines may be formed in the substrate 110.

[0188] Method 200 continues to operation 204, which can form a trench. For example, as Figure 2A As shown, trench 160 may be formed in substrate 110. Trench 160 is defined by substrate 110. The fabrication technique of trench 160 may include an etching process. In some embodiments, trench 160 may be recessed into substrate 110. In some embodiments, trench 160 may be recessed into first dielectric layer 114. In some embodiments, trench 160 may be defined by first dielectric layer 114, substrate 110, and isolation structure 112.

[0189] Method 200 continues to operation 206, forming a conductive layer in trench 160. For example, as Figure 2C As shown, a conductive layer 116' may be formed in the trench 160. The conductive layer 116' may fill the trench 160. In some embodiments, the conductive layer 116' may be surrounded by a first dielectric layer 114.

[0190] Method 200 continues to operation 208, where a barrier layer, a metallization layer, and a second dielectric layer can be formed. The barrier layer may cover the substrate 110. The metallization layer may be formed on the barrier layer. The second dielectric layer may be formed on the metallization layer. For example, as... Figure 2D As shown, a barrier layer 118', a metallization layer 120', and a dielectric layer 122 can be formed. The barrier layer 118' can cover the substrate 110. The metallization layer 120' can be formed on the barrier layer 118'. The dielectric layer 122 can be formed on the metallization layer 120'.

[0191] Method 200 continues to operation 210, removing a portion of the barrier layer and a portion of the metallization layer to form a stack of multiple bit lines and multiple bit lines. For example, as Figure 2E As shown, a portion of the barrier layer 118' can be removed to form the bit line stack 118, and a portion of the metallization layer 120' can be removed to form the bit lines 120. In some embodiments, a portion of the dielectric layer 122 can be removed. An etching process can be performed to remove portions of the metallization layer 120', the barrier layer 118', and the dielectric layer 122.

[0192] In some embodiments, the sidewalls 120s1 and 120s2 of the bit line 120 may be exposed. In some embodiments, the sidewalls 118s1 and 118s2 of the bit line stack 118 may be exposed. In some embodiments, the sidewalls 122s1 and 122s2 of the dielectric layer may be exposed.

[0193] In some embodiments, bit line stack 118 may expose a portion of conductive layer 116'. In some embodiments, bit line 120 may expose a portion of conductive layer 116'. In some embodiments, dielectric layer 122 may expose a portion of conductive layer 116'.

[0194] In some embodiments, a portion of bit line 120 may be disposed on conductive layer 116'. In some embodiments, a portion of bit line stack 118 may be disposed on conductive layer 116'. In some embodiments, a portion of bit line 120 may be disposed on isolation structure 112. In some embodiments, a portion of bit line stack 118 may be disposed on isolation structure 112.

[0195] Method 200 continues to operation 212, removing a portion of the conductive layer 116' to form bitline contacts in the trench. For example, as Figure 2FAs shown, the portion of the conductive layer 116' exposed by the bit line 120 can be removed to form a bit line contact 116 in the trench 162. In some embodiments, the portion of the conductive layer 116' exposed by the dielectric layer 122 can be removed to form a bit line contact 116 in the trench 162. The bit line contact 116 may taper gradually from the bit line 120 toward the substrate 110.

[0196] Reference Figure 3B Method 200 continues to operation 214, which can form a first isolation spacer and a second isolation spacer on the sidewall of the bit line. For example, as Figure 2G As shown, an isolation spacer including dielectric layers 132-1, 136-1, and 138-1 can be formed on the first sidewall 120s1 of the bit line 120, and another isolation spacer including dielectric layers 132-2, 136-2, and 138-2 can be formed on the second sidewall 120s2 of the bit line 120. Each of the first isolation spacer (i.e., dielectric layers 132-1, 138-1, and 136-1) and the second isolation spacer (i.e., dielectric layers 132-2, 138-2, and 136-2) can have a multilayer structure. In some embodiments, the first isolation spacer and the second isolation spacer may comprise silicon nitride / silicon oxide / silicon nitride.

[0197] Method 200 continues to operation 216, which can form a capacitor contact. For example, as Figure 2H As shown, capacitor contacts 140 can be formed. In some embodiments, an etching process can be performed to remove a portion of the substrate 110 and dielectric layer 114 to form a trench 164, and capacitor contacts 140 can be formed in the trench 164. In some embodiments, capacitor contacts 140 can be formed between two bit lines 120. In some embodiments, capacitor contacts 140 can be formed between a first insulating spacer (i.e., dielectric layers 132-1, 138-1, and 136-1) and a second insulating spacer (i.e., dielectric layers 132-2, 138-2, and 136-2).

[0198] Method 200 continues to operation 218, whereby multiple air gaps can be formed in the first and second isolation spacers, respectively. For example, as Figure 2IAs shown, air gaps 134-1 and 134-2 can be formed in the first and second spacers, respectively. As a result, a first spacer 130-1 including air gap 134-1 and a second spacer 130-2 including air gap 134-2 can be formed. In some embodiments, the silicon oxide layers (i.e., dielectric layers 132-1 / 136-1 and 132-2 / 136-2) of the first and second spacers can be removed to form air gaps 134-1 and 134-2. In some embodiments, air gaps 134-1 and 134-2 can be separated from bit line 120 by a silicon nitride layer.

[0199] Method 200 continues to operation 220, which can form a stacked conductive structure, a liner, and a landing pad. For example, as Figure 2J As shown, a stacked conductive structure 142, a pad 144, and a landing pad 146 can be formed. In some embodiments, the stacked conductive structure 142 may be formed on the top surface of the capacitor contact 140.

[0200] In some embodiments, a pad 144 may be formed on the top surface of the stacked conductive structure 142. In some embodiments, a pad 144 may be formed on the sidewall of the first insulating spacer 130-1. In some embodiments, a pad 144 may be formed on the sidewall of the second insulating spacer 130-2.

[0201] In some embodiments, a landing pad 146 may be formed on a liner 144. In some embodiments, a landing pad 146 may be formed between two bit lines 120. In some embodiments, a landing pad 146 may be formed between a first isolation spacer 130-1 and a second isolation spacer 130-2. In some embodiments, the landing pad 146 may cover the top surface of the first isolation spacer 130-1. In some embodiments, the air gap 134-1 of the first isolation spacer 130-1 may be covered by the landing pad 146. In some embodiments, the landing pad 146 may cover the top surface of the second isolation spacer 130-2. In some embodiments, the air gap 134-2 of the second isolation spacer 130-2 may be covered by the landing pad 146.

[0202] Method 200 continues to operation 222, removing a portion of the landing pad 146 to define an opening exposing the air gap 134-2. For example, as Figure 2K As shown, a portion of the landing pad 146 is removed. The landing pad 146, dielectric layer 122, and second isolation spacer 130-2 may define a hole H1 (or opening). A portion of the air gap 134-2 may be exposed. The aspect ratio of the hole H1 may be greater than 2.

[0203] Method 200 continues to operation 224, which can form an air gap protection structure. For example, such as Figure 2LAs shown, an air gap protection structure 148 is formed. In some embodiments, a deposition process may be performed to form the air gap protection structure 148.

[0204] In some embodiments, the air gap protection structure 148 may include silicon nitride and other impurities, such as carbon and / or hydrogen. In some embodiments, the deposition process temperature may be between about 530°C and about 570°C, such as 530°C, 540°C, 550°C, 560°C, or 570°C.

[0205] In some embodiments, the pressure of the deposition process may be equal to or less than 3 Torr, such as 3 Torr, 2.5 Torr, 2 Torr, 1.5 Torr, or 1 Torr, or less.

[0206] In some embodiments, the deposition process may use SiH4, NH3, TMS, N2, or a combination thereof. In some embodiments, the deposition process does not contain helium (He).

[0207] In some embodiments, the flow rate of SiH4 during the deposition process may be equal to or greater than 200 sccm, such as 200 sccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm, 300 sccm, 320 sccm, or more.

[0208] In some embodiments, the flow rate of NH3 during the deposition process may be equal to or greater than 600 sccm, such as 600 sccm, 1,500 sccm, 2,200 sccm, 2,700 sccm, 3,200 sccm, 4,000 sccm, or more.

[0209] In some embodiments, the flow rate of the TMS during the deposition process may be equal to or greater than 45 sccm, such as 45 sccm, 48 sccm, 50 sccm, 55 sccm, or more.

[0210] In some embodiments, during the deposition process, the flow rate of N2 may be equal to or less than 10,000 sccm, such as 10,000 sccm, 7,000 sccm, 4,000 sccm, 1,000 sccm, or less.

[0211] In some embodiments, the deposition rate of the air gap protection structure 148 may be equal to or less than that of the air gap protection structure 148. Like Or smaller.

[0212] As a result of the above process, during subsequent processes, the lower portion 148p1 of the air gap protection structure 148 can have sufficient thickness to protect the air gap 134-2.

[0213] Method 200 is merely an example and is not intended to limit the scope of this disclosure beyond that expressly stated in the claims. Additional operations may be provided before, during, or after each operation of method 200, and some operations may be replaced, deleted, or reordered for additional embodiments of the method. In some embodiments, method 200 may include... Figure 3A or Figure 3B Further operations not described herein. In some embodiments, method 200 may include... Figure 3A or Figure 3B One or more operations described in the document.

[0214] Figure 4A Cross-sectional views of a semiconductor device 300 are shown according to various embodiments of this disclosure. The structure of the semiconductor device 300 may be similar to... Figure 1A The structure shown. Figure 4A Zhongyu Figure 1A Similar or identical components are marked with similar reference numerals, and repeated descriptions are omitted.

[0215] Reference Figure 4A The semiconductor element 300 may include a plurality of isolation structures 113 disposed in the substrate 110 and a conductive layer 301 disposed on the capacitor contact 140.

[0216] The isolation structure 113 may include an isolation layer 113-1 disposed in a trench TR1 in the substrate 110, and a plurality of pads 113-3 disposed on the side surfaces TR-s1 and TR-s2 of the trench TR1.

[0217] In some embodiments, the isolation layer 113-1 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), or other suitable materials.

[0218] In some embodiments, the thickness 113T of the pad 113-3 may be between about 1.0 μm and about 10 μm. Alternatively, in some embodiments, the thickness of the pad 113-3 may be between about 10 nm and about 100 nm. The pad 113-3 may comprise, for example, titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the resistivity of the pad 113-3 may be less than the resistivity of the substrate 110. The pad 113-3 can reduce the equivalent series resistance of the semiconductor element 300 and improve the performance of the semiconductor element 300. Furthermore, the presence of these pads 113-3 allows for a thinner space between the active regions (or the width of the isolation layer 113-1). As a result, the capacitance of the semiconductor element 300 can be increased. Therefore, the performance of the semiconductor element 300 is improved.

[0219] The conductive layer 301 may include a first portion 301-1 and a second portion 301-3. The second portion 301-3 may be disposed on the capacitor contact 140 and may have a semi-circular or semi-elliptical cross-sectional profile. The first portion 301-1 may be configured to cover the top surface 301-3TS of the second portion 301-3 and may have an arcuate cross-sectional profile. The top surface 301-1TS and the bottom surface 301-1BS of the first portion 301-1 may be convex. In some embodiments, the two ends 301-1E of the first portion 301-1, the bottom surface 301-3BS of the second portion 301-3, and the top surface 140TS of the capacitor contact 140 may be substantially coplanar. The first portion 301-1 may have a substantially uniform thickness.

[0220] The first portion 301-1 of the conductive layer 301 may include, for example, a metal silicide. In some embodiments, the first portion 301-1 of the conductive layer 301 may include impurities such as phosphorus, arsenic, antimony, or boron. The second portion 301-3 of the conductive layer 301 may include, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, or the like. In some embodiments, the second portion 301-3 of the conductive layer 301 may include impurities such as phosphorus, arsenic, antimony, or boron.

[0221] Figures 5A to 5C Operation 202 of method 200 shows multiple stages of fabricating semiconductor device 300.

[0222] Reference Figure 5A A substrate 110 may be provided, having a first surface 103 and a second surface 105 opposite to the first surface 103. The substrate 110 may include a plurality of trenches TR1 disposed therein. Doped regions 201 may be formed in the substrate 110. An implantation process may be performed above the first surface 103 of the substrate 110 to form the doped regions 201 in the substrate 110. The doped regions 201 may be disposed in the first surface 103 of the substrate 110, and on the side surfaces TR-s1, TR-s2 and the bottom surface TR-bs of the trenches TR1. The resistivity of the doped regions 201 may be less than or equal to the resistivity of the substrate 110. In some embodiments, the doped regions 201 may be doped with a dopant, such as phosphorus, arsenic, or antimony.

[0223] Next, a substrate 113' may be deposited on the first surface 103 of the substrate 110, the side surfaces TR-s1 and TR-s2 of the trench TR1, and the bottom surface TR-bs of the trench TR1. The substrate 113' may include, for example, titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or a combination thereof.

[0224] Reference Figure 5BAn etching process, such as anisotropic dry etching, can be performed to form multiple pads 113-3 attached to the side surfaces TR-s1 and TR-s2 of the trench TR1. These pads 113-3 can be electrically connected to the doped region 201.

[0225] Next, an isolation layer 113-1 may be deposited to fill the trench TR1. In some embodiments, the isolation layer 113-1 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), or other suitable combinations thereof. In some embodiments, a planarization process may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0226] Reference Figure 5C A portion of the substrate 110 can be removed from the second surface 105 until the pads 113-3 and the isolation layer 113-1 are exposed. A removal process such as chemical mechanical polishing can be performed on the second surface 105 of the substrate 110 to expose the pads 113-3 and the isolation layer 113-1.

[0227] Figures 5D to 5F Operation 220 of method 200 shows multiple stages of fabricating semiconductor device 300.

[0228] Reference Figure 5D An intermediate structure can be provided. The structure of the intermediate structure can be similar to... Figure 2I The intermediate structure shown is different in that Figure 5D The intermediate structures in the process may include, for example, Figure 5C The substrate 110 described herein.

[0229] Reference Figure 5E Multiple second portions 301-3 can be formed on the capacitor contact 140. The second portions 301-3 may have a semi-circular or semi-elliptical cross-sectional profile. Next, multiple first portions 301-1 can be provided, covering the top surface 301-3TS of the second portions 301-3 and potentially having an arcuate cross-sectional profile. In some embodiments, the top surface 301-1TS and bottom surface 301-1BS of the first portions 301-1 may be convex. In some embodiments, the two ends 301-1E of the first portions 301-1, the bottom surface 301-3BS of the second portions 301-3, and the top surface 140TS of the capacitor contact 140 may be substantially coplanar. The first portions 301-1 may have a substantially uniform thickness.

[0230] The first portion 301-1 of the conductive layer 301 may include, for example, a metal silicide. In some embodiments, the first portion 301-1 of the conductive layer 301 may include impurities such as phosphorus, arsenic, antimony, or boron. The second portion 301-3 of the conductive layer 301 may include, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, or the like. In some embodiments, the second portion 301-3 of the conductive layer 301 may include impurities such as phosphorus, arsenic, antimony, or boron. The first portion 301-1 and the second portion 301-3 together form the conductive layer 301.

[0231] Reference Figure 5F This can form a liner 144 and a landing pad 146. The formation of the liner 144 and the landing pad 146 is related to... Figure 2J The formation shown is the same, so its description will not be repeated.

[0232] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate; a plurality of isolation structures disposed in the substrate; a bit line disposed on the substrate; an isolation spacer disposed on one sidewall of the bit line and including an air gap; a landing pad disposed on the bit line; and an air gap protection structure covering the landing pad and the air gap. The isolation structure includes an isolation layer disposed in a trench in the substrate, and a plurality of pads disposed on the side surface of the trench.

[0233] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate; a bit line disposed on the substrate; an isolation spacer disposed on one sidewall of the bit line and including an air gap; a conductive layer disposed on the substrate and adjacent to the isolation spacer; a landing pad disposed on the bit line; and an air gap protection structure covering the landing pad and the air gap. The conductive layer includes a second portion and a first portion covering the second portion. The second portion includes a semi-circular cross-sectional profile or a semi-elliptical cross-sectional profile. The air gap protection structure includes a higher portion located above a top surface of the landing pad and a lower portion located below the higher portion, wherein the ratio of a thickness of the lower portion to a thickness of the higher portion is greater than 0.6 and less than 0.8.

[0234] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a trench in the first surface of the substrate; forming a plurality of pads disposed on the side surfaces of the trench; forming an isolation layer filling the trench; and removing a portion of the substrate from the second surface to expose the isolation layer and the pads.

[0235] This disclosure provides a semiconductor device with a non-uniform thickness air gap protection structure and a method for fabricating the same. The air gap protection structure includes a lower portion and a higher portion. The ratio of the thickness of the lower portion to the thickness of the higher portion is greater than 0.6 and less than 0.8, thereby protecting the air gap from being affected during subsequent processes. For example, the air gap of this disclosure can be free of metal atoms or other contaminants due to the protection of the air gap protection structure. As a result, the performance of the semiconductor device is improved.

[0236] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0237] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; Multiple isolation structures are disposed in the substrate, wherein each of the multiple isolation structures includes an isolation layer disposed in a trench in the substrate, and multiple gaskets disposed on the side surface of the trench. A single-element line is disposed on the substrate; An isolation spacer is disposed on one side wall of the bit line, wherein the isolation spacer includes an air gap; A landing pad is placed on this bit line; as well as An air gap protection structure covers the landing pad and the air gap.

2. The semiconductor device of claim 1, wherein the isolation layers of the isolation structures comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or a combination thereof, and the pads of the isolation structures comprise titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or a combination thereof.

3. The semiconductor device of claim 2, wherein the thickness of the pad is between about 10 nm and about 100 nm.

4. The semiconductor device of claim 3, wherein the resistivity of the pad is less than the resistivity of the substrate.

5. The semiconductor element of claim 1, wherein the air gap protection structure includes a higher portion above a top surface of the landing pad and a lower portion below the higher portion, and the ratio of a thickness of the lower portion to a thickness of the higher portion is greater than 0.6 and less than 0.

8.

6. The semiconductor device of claim 1, wherein the air gap protection structure comprises silicon nitride.

7. The semiconductor device of claim 1, wherein the air gap protection structure comprises carbon.

8. The semiconductor device of claim 7, wherein the air gap protection structure is composed of carbon with an atomic ratio equal to or greater than 4.8%.

9. The semiconductor device of claim 1, wherein the air gap protection structure comprises hydrogen.

10. The semiconductor element of claim 5, wherein the landing pad defines an aperture located above the air gap, wherein the lower portion of the air gap protection structure is disposed within the aperture.

11. The semiconductor element of claim 10, wherein the aperture defined by the landing pad includes a smaller aperture near the higher portion of the air gap protection structure and a larger aperture near the lower portion of the air gap protection structure.

12. The semiconductor element of claim 11, wherein the aspect ratio of the hole is greater than 2.

13. The semiconductor device of claim 1, further comprising: A capacitor contact is disposed in the substrate and spaced apart from the bit line by the insulating spacer; as well as A conductive layer is disposed on the capacitor contact and close to the insulating spacer, wherein the conductive layer includes a second portion and a first portion covering the second portion, and wherein the second portion includes a semi-circular cross-sectional profile or a semi-elliptical cross-sectional profile.

14. A semiconductor element, comprising: One substrate; A single-element line is disposed on the substrate; An isolation spacer is disposed on one side wall of the bit line, wherein the isolation spacer includes an air gap; A conductive layer is disposed on the substrate and close to the insulating spacer, wherein the conductive layer includes a second portion and a first portion covering the second portion, and wherein the second portion includes a semi-circular cross-sectional profile or a semi-elliptical cross-sectional profile. A landing pad is placed on this bit line; and An air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes a higher portion located above a top surface of the landing pad and a lower portion located below the higher portion, wherein the ratio of the thickness of the lower portion to the thickness of the higher portion is greater than 0.6 and less than 0.

8.

15. The semiconductor device of claim 14, further comprising: An isolation structure is disposed in the substrate, wherein the isolation structure includes an isolation layer disposed in a trench in the substrate and a pad disposed on a side surface of the trench.

16. The semiconductor device of claim 15, wherein the isolation layer of the isolation structure comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or a combination thereof, and the pad of the isolation structure comprises titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or a combination thereof.

17. The semiconductor device of claim 16, wherein the thickness of the pad is between about 10 nm and about 100 nm.

18. The semiconductor device of claim 17, wherein the resistivity of the pad is less than the resistivity of the substrate.

19. The semiconductor element of claim 14, wherein the first portion of the conductive layer covers a top surface of the second portion and includes an arcuate cross-sectional profile.

20. The semiconductor element of claim 19, wherein a top surface and a bottom surface of the first portion are convex.

21. The semiconductor device of claim 20, wherein the first portion of the conductive layer comprises a metal silicide.

Images