Field effect transistor of sliding channel and preparation method thereof

Abstract

The invention relates to the field of integrated circuit manufacturing, in particular to a field effect transistor of a sliding channel and a preparation method thereof, and the field effect transistor comprises a back gate substrate layer, a gate dielectric layer, a two-dimensional semiconductor channel layer, a source electrode plate and a drain electrode plate which are arranged from bottom to top; the top of the source electrode plate and the top of the drain electrode plate are each provided with a metal cap layer. The source electrode plate and the drain electrode plate are electrically connected with an external circuit through the corresponding metal cap layers. The two-dimensional conductive material microchip is arranged on the surface of the two-dimensional semiconductor channel layer, and forms a structural ultra-smooth slip interface with the surface of the two-dimensional semiconductor channel layer; the effective channel length between the source electrode plate and the drain electrode plate can be continuously changed by driving the two-dimensional conductive material microchip to controllably slide in the plane on the two-dimensional semiconductor channel layer. According to the invention, stable and repeatable electrical contact and device working state reconstruction capability can be obtained under a slidable condition, and the test efficiency and the result reliability and accuracy of the field effect transistor in research are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a slip-channel field-effect transistor and its fabrication method. Background Technology

[0002] Two-dimensional semiconductor field-effect transistors (such as MoS2 FETs) are widely used in the research of novel micro-nano electronics and reconfigurable devices due to their atomic-level thickness, excellent gate control capability, and potential low power consumption. However, existing two-dimensional devices typically use photolithography / electron beam exposure combined with metal deposition to form source / drain electrodes. The electrode positions and effective channel lengths are fixed after fabrication. If performance comparison between devices with different channel lengths is required, multiple sets of devices with different channel lengths need to be fabricated for testing, which is time-consuming, costly, and difficult to avoid differences between devices, resulting in low accuracy of test results. At the same time, the interface of two-dimensional materials is highly sensitive, and the traditional metal electrode fabrication and contact process is prone to introducing contamination and defects, leading to high contact resistance, contact nonlinearity, and decreased consistency. If movable electrodes are introduced to achieve adjustable channel length, friction wear, interface scratches, and debris residue are likely to occur, which in turn cause contact resistance drift and unstable repositioning, still reducing the accuracy of test results.

[0003] Therefore, how to shorten the testing cycle and reduce testing costs while avoiding the decrease in testing stability and reliability caused by differences between different testing devices and surface wear and scratches is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a slip-channel field-effect transistor and its fabrication method, so as to solve the problem that the prior art cannot simultaneously achieve low testing cost, high testing efficiency and high testing reliability and stability.

[0005] To solve the above-mentioned technical problems, the present invention provides a sliding channel field-effect transistor, comprising a back gate substrate layer, a gate dielectric layer, a two-dimensional semiconductor channel layer, a source electrode sheet, and a drain electrode sheet arranged from bottom to top;

[0006] The top of both the source electrode and the drain electrode includes a metal cap layer, and the source electrode and the drain electrode are electrically connected to an external circuit through the corresponding metal cap layer.

[0007] At least one of the source electrode and the drain electrode is a two-dimensional conductive material microsheet; the two-dimensional conductive material microsheet is disposed on the surface of the two-dimensional semiconductor channel layer and forms a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer;

[0008] By driving the two-dimensional conductive material micro-sheet to slide controllably within the plane of the two-dimensional semiconductor channel layer, the effective channel length between the source electrode sheet and the drain electrode sheet can be continuously changed.

[0009] Optionally, in the slip-channel field-effect transistor, both the source electrode and the drain electrode are two-dimensional conductive material micro-sheets.

[0010] Optionally, in the slip-channel field-effect transistor, the two-dimensional conductive material microsheet includes at least one of single-crystal graphite sheet, highly oriented pyrolytic graphite sheet, and graphene sheet.

[0011] Optionally, in the slip-channel field-effect transistor, the two-dimensional semiconductor channel layer includes at least one of a molybdenum disulfide layer, a molybdenum diselenide layer, a tungsten disulfide layer, a tungsten diselenide layer, an indium selenide layer, and a black phosphorus layer.

[0012] Optionally, in the slip-channel field-effect transistor, the metal cap layer includes a metal adhesion layer and a metal conductive layer disposed from bottom to top;

[0013] The metal adhesion layer includes at least one of a titanium metal layer and a chromium metal layer;

[0014] The thickness of the metal adhesion layer ranges from 1 nanometer to 30 nanometers, including the endpoint values;

[0015] The conductive metal layer is a gold layer;

[0016] The thickness of the metallic conductive layer ranges from 20 nanometers to 500 nanometers, including the endpoint values.

[0017] Optionally, in the aforementioned slip-channel field-effect transistor, the super-slippery slip interface is an incommensurable interface.

[0018] Optionally, in the slip-channel field-effect transistor, the planar size of the two-dimensional conductive material microsheet ranges from 1 micrometer to 50 micrometers, including the endpoint values;

[0019] The thickness of the two-dimensional conductive material microsheet ranges from 50 nanometers to 20,000 nanometers, including the endpoint values.

[0020] A method for fabricating a slip-channel field-effect transistor, the method being used to fabricate any of the slip-channel field-effect transistors described above, comprising:

[0021] Preparation of two-dimensional conductive material layers;

[0022] A patterned metal cap layer is disposed on the two-dimensional conductive material layer;

[0023] The two-dimensional conductive material layer with the metal cap layer is patterned and etched to form a two-dimensional conductive platform under the metal cap layer;

[0024] The two-dimensional conductive platform is cut off from the two-dimensional conductive material layer to obtain the two-dimensional conductive material micro-sheet;

[0025] The two-dimensional conductive material micro-wafer is transferred onto a transistor substrate to form a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer of the transistor substrate, thereby obtaining the sliding channel field-effect transistor; the transistor substrate includes the back gate substrate layer, the gate dielectric layer and the two-dimensional semiconductor channel layer arranged from bottom to top.

[0026] Optionally, in the method for fabricating the slip-channel field-effect transistor, after transferring the two-dimensional conductive material micro-wafer onto the transistor substrate and forming a structurally super-slippery slip interface with the surface of the two-dimensional semiconductor channel layer of the transistor substrate, the method further includes:

[0027] Adjust the effective channel length between the source electrode and the drain electrode to a preset target value;

[0028] A dielectric encapsulation layer is disposed on the surface of the transistor substrate where the two-dimensional conductive material microsheet is located, and the encapsulation dielectric layer covers the source electrode sheet, the drain electrode sheet and the two-dimensional semiconductor channel layer;

[0029] The dielectric encapsulation layer located on top of the source electrode sheet and the dielectric encapsulation layer located on top of the drain electrode sheet are patterned and etched to obtain contact vias; the bottom surface of the contact vias exposes the corresponding metal cap layer.

[0030] Metal is deposited within the contact via and a metal interconnect electrode is formed on the surface of the dielectric encapsulation layer. The metal interconnect electrode is connected to the metal cap layer through the contact via.

[0031] Optionally, in the method for fabricating the slip-channel field-effect transistor, the dielectric encapsulation layer includes a first dielectric layer and a second dielectric layer disposed from bottom to top;

[0032] Accordingly, a dielectric encapsulation layer is disposed on the surface of the transistor substrate where the two-dimensional conductive material microsheet is located, including:

[0033] The first dielectric layer is obtained by first deposition on the surface of the transistor substrate where the two-dimensional conductive material microsheet is located; the thickness of the first dielectric layer ranges from 5 nanometers to 100 nanometers, including the endpoint values.

[0034] A second encapsulation layer is obtained by redeposition on the surface of the first encapsulation layer; the thickness of the second dielectric layer ranges from 0.2 micrometers to 5 micrometers, including the endpoint values.

[0035] The slip-channel field-effect transistor provided by this invention includes, from bottom to top, a back gate substrate layer, a gate dielectric layer, a two-dimensional semiconductor channel layer, a source electrode plate, and a drain electrode plate; the top of each of the source electrode plate and the drain electrode plate includes a metal cap layer, and the source electrode plate and the drain electrode plate are electrically connected to an external circuit through the corresponding metal cap layer; at least one of the source electrode plate and the drain electrode plate is a two-dimensional conductive material microplate; the two-dimensional conductive material microplate is disposed on the surface of the two-dimensional semiconductor channel layer and forms a structurally super-slippery slip interface with the surface of the two-dimensional semiconductor channel layer; by driving the two-dimensional conductive material microplate to controllably slide in a plane on the two-dimensional semiconductor channel layer, the effective channel length between the source electrode plate and the drain electrode plate can be continuously changed.

[0036] This invention utilizes the stable relative sliding characteristics of a super-slippery interface under external driving to achieve in-situ continuous adjustment of the source / drain electrode positions and effective channel length. This avoids fabricating multiple devices with different effective channel lengths during testing, thus avoiding interference caused by device differences and improving the accuracy and reliability of test results. Simultaneously, the super-slippery contact between the two-dimensional semiconductor channel layer and the two-dimensional conductive material microsheet maintains a non-destructive and low-contamination contact interface during repeated sliding of the two-dimensional conductive material microsheet. This avoids a decrease in the consistency and stability of contact resistance, achieving stable and repeatable electrical contact and device operating state reconfiguration capability under sliding conditions. This improves the testing efficiency, reliability, and accuracy of field-effect transistors in research. This invention also provides a method for fabricating a sliding-channel field-effect transistor with the above-mentioned beneficial effects. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of a specific embodiment of the slip-channel field-effect transistor provided by the present invention;

[0039] Figure 2 A schematic flowchart illustrating a specific embodiment of the method for fabricating a slip-channel field-effect transistor provided by the present invention;

[0040] Figures 3 to 12 A schematic diagram of the process structure of a specific embodiment of the slip-channel field-effect transistor provided by the present invention.

[0041] Figure label:

[0042] 10-Back gate substrate layer; 20-Gate dielectric layer; 30-Two-dimensional semiconductor channel layer; 40-Two-dimensional conductive material microchip; 41-Metal cap layer; 30A-Two-dimensional conductive material layer; 50-Photoresist layer; 60-Encapsulation dielectric layer; 61-Contact via; 70-Deposited layer; 71-Metal interconnect electrode. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] The core of this invention is to provide a slip-channel field-effect transistor, and a schematic diagram of one specific embodiment is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method 1, which includes a back gate substrate layer 10, a gate dielectric layer 20, a two-dimensional semiconductor channel layer 30, a source electrode sheet, and a drain electrode sheet arranged from bottom to top.

[0045] The top of both the source electrode and the drain electrode includes a metal cap layer 41, and the source electrode and the drain electrode are electrically connected to an external circuit through the corresponding metal cap layer 41.

[0046] At least one of the source electrode and the drain electrode is a two-dimensional conductive material microplate 40; the two-dimensional conductive material microplate 40 is disposed on the surface of the two-dimensional semiconductor channel layer 30 and forms a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer 30.

[0047] By driving the two-dimensional conductive material micro-chip 40 to slide controllably in the plane on the two-dimensional semiconductor channel layer 30, the effective channel length between the source electrode and the drain electrode can be continuously changed.

[0048] The super-lubricating interface of the structure satisfies low friction (typically the differential coefficient of friction of the interface does not exceed 0.001) and low wear conditions during the sliding process, so as to achieve non-destructive contact with the two-dimensional semiconductor channel layer 30 and maintain stable electrical contact. It also outputs the device conductivity state corresponding to different effective channel lengths under gate bias, thereby achieving repeatable reconfiguration of the device operating state. Furthermore, the adjustable range of the effective channel length is preferably from 0.1 micrometers to 100.0 micrometers, including endpoint values ​​such as 0.10 micrometers, 58.14 micrometers, or 100.00 micrometers. This range essentially satisfies the range that the effective channel length needs to cover in various tests, thus expanding the versatility of the invention.

[0049] In one specific embodiment, the back gate substrate 10 is a heavily doped silicon back gate substrate, the gate dielectric layer 20 is a silicon dioxide layer, and the thickness of the silicon dioxide layer ranges from 50 nanometers to 500 nanometers, including endpoint values ​​such as any one of 50.0 nanometers, 420.3 nanometers, or 500.0 nanometers.

[0050] In this invention, a carrier injection path including an edge-to-face contact region is formed between the source electrode and / or the drain electrode and the two-dimensional semiconductor channel layer 30. This reduces the effective potential barrier and achieves approximately ohmic contact characteristics. At room temperature, the current-voltage relationship between the source / drain electrodes and the two-dimensional semiconductor channel layer 30 in this invention satisfies a linear fit goodness R within a range of ±1V. 2 ≥0.99; and / or contact resistance per unit width R c Less than or equal to 100 kΩ·μm.

[0051] Preferably, both the source electrode and the drain electrode are two-dimensional conductive material micro-plates 40. In other words, in this preferred embodiment, both the source electrode and the drain electrode are slidable on the two-dimensional semiconductor channel layer 30, and the effective channel length between the source and drain can be adjusted by changing the position of either one. Of course, both can also be adjusted simultaneously to change the effective channel length. This specific embodiment provides more flexibility in adjusting the effective channel length of the field-effect transistor, expanding the applicability of the field-effect transistor.

[0052] Of course, one of the source electrode and the drain electrode can be a conventional fixed electrode, and only one electrode can be the two-dimensional conductive material microplate 40 of the present invention. The choice can be made according to the specific situation, and the present invention will not elaborate further here.

[0053] In one specific embodiment, the two-dimensional conductive material microsheet 40 includes at least one of single-crystal graphite sheets, highly oriented pyrolytic graphite sheets, and graphene sheets. Selecting these materials as the two-dimensional conductive material microsheet 40 achieves good conductivity while also obtaining a good two-dimensional molecular structure plane, enabling better contact with the two-dimensional semiconductor channel layer 30 to form a structurally super-slippery interface. The two-dimensional conductive material microsheet 40 can be any of the above-mentioned materials, or a heterogeneous stacked structure of the above materials, and can be selected according to actual conditions. Further details are omitted here.

[0054] In one specific embodiment, the two-dimensional semiconductor channel layer 30 includes at least one of a molybdenum disulfide layer, a molybdenum diselenide layer, a tungsten disulfide layer, a tungsten diselenide layer, an indium selenide layer, and a black phosphorus layer. Selecting these material layers as the two-dimensional semiconductor channel layer 30 can minimize contact resistance while obtaining a good two-dimensional molecular structure plane, enabling better contact with the two-dimensional conductive material microsheet 40 to form a structurally super-slippery sliding interface. The two-dimensional conductive material microsheet 40 can be any of the above-mentioned material sheets, or a combination of the above-mentioned material layers, and can be selected according to actual conditions; further details are omitted here.

[0055] In one specific embodiment, the metal cap layer 41 includes a metal adhesion layer and a metal conductive layer disposed from bottom to top;

[0056] The metal adhesion layer includes at least one of a titanium metal layer and a chromium metal layer;

[0057] The thickness of the metal adhesion layer ranges from 1 nanometer to 30 nanometers, including endpoint values ​​such as any one of 1.0 nanometer, 15.4 nanometer or 30.0 nanometer;

[0058] The conductive metal layer is a gold layer;

[0059] The thickness of the metallic conductive layer ranges from 20 nanometers to 500 nanometers, including endpoint values ​​such as any one of 20.0 nanometers, 325.4 nanometers, or 500.0 nanometers.

[0060] In this specific embodiment, the metal cap layer 41 is divided into a metal adhesion layer and a metal conductive layer. Preferred material layers and corresponding thickness ranges for each layer are given. By utilizing the metal adhesion layer, which has better adhesion to semiconductor materials, the metal conductive layer with superior conductivity can adhere better to the two-dimensional conductive material micro-sheet 40, is less prone to detachment, and exhibits better operational stability. The aforementioned thickness ranges are preferred ranges after extensive theoretical calculations and practical testing. Within these ranges, the metal adhesion layer is neither too thin, leading to decreased adhesion, nor too thick, affecting conductivity and increasing cost. Similarly, the metal conductive layer is neither too thin, increasing the difficulty of subsequent electrical connection processes, nor too thick, leading to excessively high costs. Of course, the parameters can be adjusted according to actual conditions, and this invention does not limit this adjustment.

[0061] Specifically, the super-slippery interface is a non-commensurable interface. That is, the two-dimensional conductive material micro-plate 40 and the two-dimensional semiconductor channel layer 30 satisfy the conditions of lattice orientation difference or lattice mismatch, so that the interface is in a super-slippery state. The super-slippery state produced by this structure has better working stability and higher product yield.

[0062] Furthermore, the planar dimensions of the two-dimensional conductive material microsheet 40 range from 1 micrometer to 50 micrometers, including endpoint values ​​such as any one of 1.0 micrometer, 44.1 micrometer, or 50.0 micrometer;

[0063] The thickness of the two-dimensional conductive material microsheet 40 ranges from 50 nanometers to 20,000 nanometers, including endpoint values ​​such as 50.0 nanometers, 11,451.4 nanometers, or 20,000.0 nanometers.

[0064] In this application, the source and / or drain of the transistor are modified into a sliding two-dimensional conductive material microplate 40. Therefore, the two-dimensional conductive material microplate 40 needs to be of a certain size to facilitate position adjustment. The above-mentioned size parameter range is the optimal result after a large number of theoretical calculations and actual tests. Within the above-mentioned size range, the two-dimensional conductive material microplate 40 is neither too small to make position adjustment difficult, nor too large to increase the device volume and cost. Of course, it can also be adjusted according to the actual situation, and this invention does not limit it.

[0065] The sliding channel field-effect transistor provided by the present invention includes, from bottom to top, a back gate substrate layer 10, a gate dielectric layer 20, a two-dimensional semiconductor channel layer 30, a source electrode plate, and a drain electrode plate; the top of the source electrode plate and the drain electrode plate are both included with a metal cap layer 41, and the source electrode plate and the drain electrode plate are electrically connected to an external circuit through the corresponding metal cap layer 41; at least one of the source electrode plate and the drain electrode plate is a two-dimensional conductive material microplate 40; the two-dimensional conductive material microplate 40 is disposed on the surface of the two-dimensional semiconductor channel layer 30 and forms a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer 30; by driving the two-dimensional conductive material microplate 40 to perform controllable sliding in the plane on the two-dimensional semiconductor channel layer 30, the effective channel length between the source electrode plate and the drain electrode plate can be continuously changed. This invention utilizes the stable relative sliding characteristics of a super-slippery interface under external driving to achieve in-situ continuous adjustment of the source / drain electrode positions and effective channel length. This avoids the fabrication of multiple devices with different effective channel lengths during testing, thus avoiding interference caused by device differences and improving the accuracy and reliability of test results. Simultaneously, the super-slippery contact between the two-dimensional semiconductor channel layer 30 and the two-dimensional conductive material microplate 40 maintains a non-destructive and low-contamination contact interface during repeated sliding of the two-dimensional conductive material microplate 40. This avoids a decrease in the consistency and stability of contact resistance, achieving stable and repeatable electrical contact and device operating state reconfiguration capabilities under sliding conditions. This improves the testing efficiency, reliability, and accuracy of field-effect transistors in research.

[0066] This invention also provides a method for fabricating a slip-channel field-effect transistor, a flowchart of one specific embodiment of which is shown below. Figure 2 As shown, referred to as Specific Embodiment Two, the method for fabricating the slip-channel field-effect transistor is used to fabricate any of the slip-channel field-effect transistors described above, comprising:

[0067] S101: Prepare two-dimensional conductive material layer 30A.

[0068] The specific material composition of the two-dimensional conductive material layer 30A can be referred to the previous description of the slip channel field-effect transistor, and will not be repeated here.

[0069] S102: A patterned metal cap layer 41 is provided on the two-dimensional conductive material layer 30A.

[0070] The specific method for setting the graphical metal cap layer 41 in this step may include:

[0071] S1021: Spin-coat the entire surface of the two-dimensional conductive material layer 30A with a photoresist layer 50.

[0072] The corresponding process structure diagram for this step can be referenced. Figure 3 .

[0073] S1022: Pattern the photoresist layer 50.

[0074] The photoresist layer 50 can be patterned using electron beam lithography. The corresponding process structure diagram for this step can be found by referring to... Figure 4 .

[0075] S1023: Deposit the metal cap layer 41 using the patterned photoresist layer 50 as a barrier layer.

[0076] The corresponding process structure diagram for this step can be referenced. Figure 5 .

[0077] S1024: Remove the photoresist layer 50 and leave a patterned metal cap layer 41 on the two-dimensional conductive material layer 30A.

[0078] That is, a patterned metal cap layer 41 can be obtained using a lift-off process. The corresponding process structure diagram for this step can be found in the reference diagram. Figure 6 .

[0079] S103: The two-dimensional conductive material layer 30A on which the metal cap layer 41 is disposed is patterned and etched to form a two-dimensional conductive platform under the metal cap layer 41.

[0080] Specifically, reactive ion etching can be used to pattern the two-dimensional conductive material layer 30A, and the resulting patterned structure is shown in the figure below. Figure 7 As shown.

[0081] S104: The two-dimensional conductive platform is cut off from the two-dimensional conductive material layer 30A to obtain the two-dimensional conductive material micro-sheet 40.

[0082] S105: The two-dimensional conductive material micro-film 40 is transferred to the transistor substrate to form a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer 30 of the transistor substrate, thereby obtaining the field-effect transistor with the sliding channel; the transistor substrate includes the back gate substrate layer 10, the gate dielectric layer 20 and the two-dimensional semiconductor channel layer 30 arranged from bottom to top.

[0083] A schematic diagram of the transistor substrate is shown below. Figure 8 As shown, a schematic diagram of the structure after the two-dimensional conductive material micro-sheet 40 is transferred onto the transistor substrate is shown below. Figure 1 As shown, of course, in Figure 1In the corresponding specific embodiments, both the source electrode sheet and the drain electrode sheet are the two-dimensional conductive material micro-chips 40. In actual production, only one of the source / drain electrodes may be the two-dimensional conductive material micro-chips 40.

[0084] In a preferred embodiment, after transferring the two-dimensional conductive material microsheet 40 onto the transistor substrate and forming a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer 30 of the transistor substrate, the method further includes:

[0085] A1: Adjust the effective channel length between the source electrode and the drain electrode to a preset target value.

[0086] The target value can be the optimal value after repeated trials, and can be determined according to the specific use case.

[0087] A2: A dielectric encapsulation layer is provided on the surface of the transistor substrate where the two-dimensional conductive material microplate 40 is located, and the encapsulation dielectric layer 60 covers the source electrode sheet, the drain electrode sheet and the two-dimensional semiconductor channel layer 30.

[0088] Figure 9 This is a process structure diagram corresponding to a specific embodiment of this step. Figure 9 In this embodiment, the dielectric encapsulation layer completely covers the transistor substrate and is planarized on top. Of course, the dielectric encapsulation layer can also be a layer with the same thickness at all locations, and this invention does not limit it.

[0089] The encapsulation medium layer 60 is at least one of silicon dioxide, aluminum oxide, hafnium dioxide, or silicon nitride. It can be a single material layer or a composite layer of multiple materials. Its total thickness ranges from 0.1 micrometers to 5.0 micrometers, including endpoint values ​​such as any one of 0.10 micrometers, 2.50 micrometers, or 5.00 micrometers. Within the above range, the encapsulation medium layer 60 can ensure good encapsulation effect while reducing production costs.

[0090] A3: The dielectric encapsulation layer located on top of the source electrode sheet and the dielectric encapsulation layer located on top of the drain electrode sheet are patterned and etched to obtain contact via 61; the bottom surface of the contact via 61 exposes the corresponding metal cap layer 41.

[0091] The aperture of the contact via 61 ranges from 1 micrometer to 20 micrometers, including endpoint values ​​such as 1.0 micrometer, 11.4 micrometer, or 20.0 micrometer. The corresponding process structure diagram for this step is shown below. Figure 10 As shown. It should be noted that the dielectric encapsulation layer on the top of a single two-dimensional conductive material microchip 40 may have only one contact via 61 or may include multiple contact vias 61, which is not limited in this invention.

[0092] A4: Deposit metal in the contact via 61 and form a metal interconnect electrode 71 on the surface of the dielectric encapsulation layer. The metal interconnect electrode 71 is connected to the metal cap layer 41 through the contact via 61.

[0093] In one specific embodiment, a metal interconnect electrode can be disposed on the surface of the dielectric encapsulation layer. The metal interconnect electrode is electrically connected to the metal cap layer 41 through the contact via 61, and the external circuit is directly connected to the metal interconnect electrode 71.

[0094] The metal interconnect electrode 71 can also be set in two steps. First, metal can be deposited over the entire surface of the dielectric encapsulation layer to obtain the deposition layer 70, such as... Figure 11 As shown, patterned etching is then performed to retain only the metal layers at the corresponding positions of the source electrode and the drain electrode, resulting in the metal interconnect electrode 71. The process structure diagram of the metal interconnect electrode 71 after the electrical connection process is shown in the figure. Figure 12 As shown.

[0095] In this preferred embodiment, after determining the target value of the effective channel length, the dielectric encapsulation layer is directly covered on the surface of the transistor structure to fix the relative position between the two-dimensional conductive material micro-chip 40 and the two-dimensional semiconductor channel layer 30, thereby obtaining a relatively ideal transistor structure after testing. While retaining the adjustability during the testing stage, it also enables the transistor to be used in more complex operating environments, thus broadening the versatility of the present invention.

[0096] Furthermore, the dielectric encapsulation layer includes a first dielectric layer and a second dielectric layer disposed from bottom to top;

[0097] Accordingly, a dielectric encapsulation layer is disposed on the surface of the transistor substrate where the two-dimensional conductive material microchip 40 is located, including:

[0098] B1: A first dielectric layer is obtained by depositing a first dielectric layer on the surface of the transistor substrate where the two-dimensional conductive material microsheet 40 is located; the thickness of the first dielectric layer is in the range of 5 nanometers to 100 nanometers, including endpoint values ​​such as any one of 5.0 nanometers, 22.1 nanometers or 100.0 nanometers.

[0099] B2: A second encapsulation layer is obtained by redeposition on the surface of the first encapsulation layer; the thickness of the second dielectric layer ranges from 0.2 micrometers to 5 micrometers, including endpoint values ​​such as any one of 0.20 micrometers, 4.70 micrometers or 5.00 micrometers.

[0100] In this preferred embodiment, the dielectric encapsulation layer is deposited in two separate depositions. The first deposition deposits a thinner first dielectric layer, and the second deposition deposits a thicker second dielectric layer. The two-stage deposition effectively reduces the damage of the dielectric encapsulation layer to the two-dimensional semiconductor channel layer 30, and improves the operating stability of the device and the yield of the product.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0102] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] The foregoing has provided a detailed description of the slip-channel field-effect transistor and its fabrication method provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A slip-channel field-effect transistor, characterized in that, It includes, from bottom to top, a back gate substrate layer, a gate dielectric layer, a two-dimensional semiconductor channel layer, a source electrode sheet, and a drain electrode sheet; The top of both the source electrode and the drain electrode includes a metal cap layer, and the source electrode and the drain electrode are electrically connected to an external circuit through the corresponding metal cap layer. At least one of the source electrode and the drain electrode is a two-dimensional conductive material microsheet; the two-dimensional conductive material microsheet is disposed on the surface of the two-dimensional semiconductor channel layer and forms a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer; By driving the two-dimensional conductive material micro-sheet to slide controllably within the plane of the two-dimensional semiconductor channel layer, the effective channel length between the source electrode sheet and the drain electrode sheet can be continuously changed.

2. The slip-channel field-effect transistor as described in claim 1, characterized in that, Both the source electrode and the drain electrode are micro-sheets of the two-dimensional conductive material.

3. The slip-channel field-effect transistor as described in claim 1, characterized in that, The two-dimensional conductive material microsheets include at least one of single-crystal graphite sheets, highly oriented pyrolytic graphite sheets, and graphene sheets.

4. The slip-channel field-effect transistor as described in claim 1, characterized in that, The two-dimensional semiconductor channel layer includes at least one of molybdenum disulfide, molybdenum diselenide, tungsten disulfide, tungsten diselenide, indium selenide, and black phosphorus.

5. The slip-channel field-effect transistor as described in claim 1, characterized in that, The metal cap layer includes a metal adhesion layer and a metal conductive layer arranged from bottom to top; The metal adhesion layer includes at least one of a titanium metal layer and a chromium metal layer; The thickness of the metal adhesion layer ranges from 1 nanometer to 30 nanometers, including the endpoint values; The conductive metal layer is a gold layer; The thickness of the metallic conductive layer ranges from 20 nanometers to 500 nanometers, including the endpoint values.

6. The slip-channel field-effect transistor as described in claim 1, characterized in that, The super-slippery sliding interface of the structure is a non-commensurable interface.

7. The slip-channel field-effect transistor as described in claim 1, characterized in that, The planar dimensions of the two-dimensional conductive material microsheets range from 1 micrometer to 50 micrometers, including the endpoint values; The thickness of the two-dimensional conductive material microsheet ranges from 50 nanometers to 20,000 nanometers, including the endpoint values.

8. A method for fabricating a slip-channel field-effect transistor, characterized in that, The method for fabricating the slip-channel field-effect transistor is used to fabricate the slip-channel field-effect transistor as described in any one of claims 1 to 7, comprising: Preparation of two-dimensional conductive material layers; A patterned metal cap layer is disposed on the two-dimensional conductive material layer; The two-dimensional conductive material layer with the metal cap layer is patterned and etched to form a two-dimensional conductive platform under the metal cap layer; The two-dimensional conductive platform is cut off from the two-dimensional conductive material layer to obtain the two-dimensional conductive material micro-sheet; The two-dimensional conductive material micro-wafer is transferred onto a transistor substrate to form a structurally super-slippery sliding interface with the surface of the two-dimensional semiconductor channel layer of the transistor substrate, thereby obtaining the sliding channel field-effect transistor; the transistor substrate includes the back gate substrate layer, the gate dielectric layer and the two-dimensional semiconductor channel layer disposed from bottom to top.

9. The method for fabricating a slip-channel field-effect transistor as described in claim 8, characterized in that, After transferring the two-dimensional conductive material microsheet onto a transistor substrate and forming a structurally super-slippery interface with the surface of the two-dimensional semiconductor channel layer of the transistor substrate, the process further includes: Adjust the effective channel length between the source electrode and the drain electrode to a preset target value; A dielectric encapsulation layer is disposed on the surface of the transistor substrate where the two-dimensional conductive material microsheet is located, and the encapsulation dielectric layer covers the source electrode sheet, the drain electrode sheet and the two-dimensional semiconductor channel layer; The dielectric encapsulation layer located on top of the source electrode sheet and the dielectric encapsulation layer located on top of the drain electrode sheet are patterned and etched to obtain contact vias; the bottom surface of the contact vias exposes the corresponding metal cap layer. Metal is deposited within the contact via and a metal interconnect electrode is formed on the surface of the dielectric encapsulation layer. The metal interconnect electrode is connected to the metal cap layer through the contact via.

10. The method for fabricating a slip-channel field-effect transistor as described in claim 9, characterized in that, The dielectric encapsulation layer includes a first dielectric layer and a second dielectric layer disposed from bottom to top; Accordingly, a dielectric encapsulation layer is disposed on the surface of the transistor substrate where the two-dimensional conductive material microsheet is located, including: The first dielectric layer is obtained by first deposition on the surface of the transistor substrate where the two-dimensional conductive material microsheet is located; the thickness of the first dielectric layer ranges from 5 nanometers to 100 nanometers, including the endpoint values. A second encapsulation layer is obtained by redeposition on the surface of the first encapsulation layer; the thickness of the second dielectric layer ranges from 0.2 micrometers to 5 micrometers, including the endpoint values.

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