Heterojunction battery and preparation method thereof

Abstract

The invention discloses a heterojunction battery and a preparation method thereof, and the heterojunction battery comprises the components of a silicon wafer which is an N-type silicon wafer and comprises a first surface and a second surface which are oppositely arranged; the first intrinsic layer and the N-type doped layer are sequentially stacked on the first surface; the second intrinsic layer and the P-type doped layer are sequentially stacked on the second surface; the first transparent conductive layer is laminated on the N-type doped layer; the second transparent conductive layer is laminated on the P-type doped layer; the first electrode is in electric contact with the first transparent conductive layer; the second electrode is in electric contact with the second transparent conductive layer; doping elements in the N-type doping layer comprise an antimony element, and the doping concentration of the antimony element is 1E18 cm <-3 >-2.5 E20 cm <-3 >. According to the invention, the effective doping concentration of the N-type doping layer can be ensured, the ultraviolet induced degradation risk of the heterojunction cell is reduced, and the energy band alignment precision of the heterojunction is ensured.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic cell technology, specifically relating to a heterojunction cell and its preparation method. Background Technology

[0002] Heterojunction (HJT) solar cells are a hybrid type of solar cell made from crystalline silicon wafers and amorphous silicon thin films. They have many advantages, such as simple fabrication process, low processing temperature, high open-circuit voltage, high photoelectric conversion efficiency, and low temperature coefficient. They are one of the most widely used high-efficiency crystalline silicon solar cell technologies.

[0003] However, heterojunction solar cells still face some challenges in practical applications, especially under ultraviolet (UV) light irradiation, where they are prone to UV-induced degradation (UVID), affecting their long-term performance. One of the main reasons for this degradation is that the N-type doped microcrystalline or amorphous silicon layer on the front side of the cell undergoes chemical changes under UV irradiation, leading to a decrease in the effective doping concentration in the N-type doped layer. This not only affects the electrical performance of the heterojunction solar cell but also accelerates its aging process.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a heterojunction solar cell and its preparation method. Summary of the Invention

[0005] The purpose of this invention is to provide a heterojunction solar cell and its preparation method, so as to reduce the risk of ultraviolet-induced degradation of heterojunction solar cells.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A heterojunction solar cell, the heterojunction solar cell comprising:

[0008] A silicon wafer, wherein the silicon wafer is an N-type silicon wafer, comprising a first surface and a second surface disposed opposite to each other;

[0009] The first intrinsic layer and the N-type doped layer are sequentially stacked on the first surface;

[0010] The second intrinsic layer and the P-type doped layer are sequentially stacked on the second surface;

[0011] A first transparent conductive layer stacked on the N-type doped layer;

[0012] A second transparent conductive layer stacked on the p-type doped layer; and,

[0013] A first electrode that is electrically in contact with the first transparent conductive layer and a second electrode that is electrically in contact with the second transparent conductive layer;

[0014] The N-type doped layer contains antimony as a doping element, and the antimony doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 .

[0015] In one or more embodiments of the present invention, the antimony doping concentration in the N-type doped layer is 1E18cm⁻¹. -3 ~1E20cm -3 .

[0016] In one or more embodiments of the present invention, the N-type doped layer is a single layer, the doping element is antimony, and the antimony doping concentration is 1E18cm⁻¹. -3 ~1E20cm -3 ;or,

[0017] The N-type doped layer is a single layer, and the doping elements are antimony and phosphorus, with an antimony doping concentration of 1E18cm⁻¹. -3 ~1E20cm -3 The phosphorus doping concentration is 1E18cm⁻¹ -3 ~1E20cm -3 .

[0018] In one or more embodiments of the present invention, the N-type doped layer includes a first N-type doped layer and a second N-type doped layer stacked along a first surface away from the silicon wafer, wherein the doping concentration of the first N-type doped layer is less than the doping concentration of the second N-type doped layer, and at least one of the first N-type doped layer and the second N-type doped layer contains antimony as a doping element.

[0019] In one or more embodiments of the present invention, the doping element of the first N-type doped layer is antimony, and the doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 The second N-type doped layer is doped with phosphorus at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 ;or,

[0020] The first N-type doped layer is doped with phosphorus at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 The second N-type doped layer is doped with antimony at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 .

[0021] In one or more embodiments of the present invention, the N-type doped layer is one or more layers selected from N-type doped amorphous silicon layers, N-type doped microcrystalline silicon layers, or N-type doped nanocrystalline silicon layers; and / or,

[0022] The P-type doped layer is one or more layers selected from P-type doped amorphous silicon, P-type doped microcrystalline silicon, or P-type doped nanocrystalline silicon; and / or,

[0023] The thickness of the N-type doped layer is 20 nm to 40 nm; and / or,

[0024] The thickness of the P-type doped layer is 20 nm to 40 nm.

[0025] In one or more embodiments of the present invention, the N-type doped layer is an N-type doped microcrystalline silicon layer with a crystallinity of 25% to 50%; and / or,

[0026] The P-type doped layer is a P-type doped microcrystalline silicon layer with a crystallinity of 25% to 50%.

[0027] In one or more embodiments of the present invention, the doping element in the silicon wafer includes phosphorus, with a doping concentration of 1E19cm⁻¹. -3 ~5E19cm -3 .

[0028] In one or more embodiments of the present invention, the doping elements in the silicon wafer include antimony and phosphorus, and the atomic percentage of antimony is greater than or equal to 30%.

[0029] Another specific embodiment of the present invention provides the following technical solution:

[0030] A method for fabricating a heterojunction solar cell, the method comprising the following steps:

[0031] A silicon wafer is provided, the silicon wafer being an N-type silicon wafer, including a first surface and a second surface disposed opposite to each other;

[0032] A first intrinsic layer and an N-type doped layer are sequentially deposited on the first surface of the silicon wafer. The doping element in the N-type doped layer includes antimony, and the antimony doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 ;

[0033] A second intrinsic layer and a P-type doped layer are sequentially deposited on the second surface of the silicon wafer;

[0034] A first transparent conductive layer is deposited on the N-type doped layer, and a second transparent conductive layer is deposited on the P-type doped layer;

[0035] A first electrode that is in electrical contact with the first transparent conductive layer is prepared on the first transparent conductive layer, and a first electrode that is in electrical contact with the second transparent conductive layer is prepared on the second transparent conductive layer.

[0036] Compared with the prior art, the present invention, by doping antimony into the N-type doped layer, can ensure the effective doping concentration of the N-type doped layer, reduce the risk of ultraviolet-induced degradation of heterojunction cells, prevent the degradation of cell performance and accelerated aging, ensure the band alignment accuracy of the heterojunction, and improve the overall performance of the cell. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a heterojunction battery in a specific embodiment of the present invention.

[0039] Explanation of key figure labels:

[0040] 10-Silicon wafer, 21-First intrinsic layer, 22-Second intrinsic layer, 31-N-type doped layer, 32-P-type doped layer, 41-First transparent conductive layer, 42-Second transparent conductive layer, 51-First electrode, 52-Second electrode. Detailed Implementation

[0041] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0042] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0043] This invention discloses a heterojunction solar cell, comprising:

[0044] A silicon wafer, specifically an N-type silicon wafer, comprising a first surface and a second surface disposed opposite to each other;

[0045] A first intrinsic layer and an N-type doped layer stacked on the first surface in sequence;

[0046] A second intrinsic layer and a P-type doped layer stacked on the second surface in sequence;

[0047] A first transparent conductive layer stacked on the N-type doped layer;

[0048] A second transparent conductive layer stacked on the P-type doped layer; and

[0049] A first electrode in electrical contact with the first transparent conductive layer and a second electrode in electrical contact with the second transparent conductive layer;

[0050] wherein, the doping element in the N-type doped layer includes antimony element, and the doping concentration of the antimony element is 1E18 cm -3 ~2.5E20 cm -3 .

[0051] The present invention also discloses a preparation method of a heterojunction battery, comprising the following steps:

[0052] Provide a silicon wafer, which is an N-type silicon wafer and includes a first surface and a second surface arranged opposite to each other;

[0053] Deposit a first intrinsic layer and an N-type doped layer on the first surface of the silicon wafer in sequence. The doping element in the N-type doped layer includes antimony element, and the doping concentration of the antimony element is 1E18 cm -3 ~2.5E20 cm -3 ;

[0054] Deposit a second intrinsic layer and a P-type doped layer on the second surface of the silicon wafer in sequence;

[0055] Deposit a first transparent conductive layer on the N-type doped layer and deposit a second transparent conductive layer on the P-type doped layer;

[0056] Prepare a first electrode in electrical contact with the first transparent conductive layer on the first transparent conductive layer, and prepare a first electrode in electrical contact with the second transparent conductive layer on the second transparent conductive layer.

[0057] By doping antimony element in the N-type doped layer, the present invention can ensure the effective doping concentration of the N-type doped layer, reduce the risk of ultraviolet-induced attenuation of the heterojunction battery, prevent the reduction of battery performance and the acceleration of aging, ensure the energy band alignment accuracy of the heterojunction, and improve the overall performance of the battery.

[0058] The following further describes the present invention in conjunction with specific embodiments.

[0059] Refer Figure 1 Shown is a schematic structural diagram of a heterojunction battery in a specific embodiment of the present invention. The heterojunction battery includes:

[0060] The silicon wafer 10 includes a first surface (i.e., a front or light-receiving surface) and a second surface (i.e., a back or backlighting surface) disposed opposite to each other.

[0061] The first intrinsic layer 21 is stacked on the first surface and the second intrinsic layer 22 is stacked on the second surface;

[0062] An N-type doped layer 31 and a first transparent conductive layer 41 are stacked on the first intrinsic layer 21;

[0063] A P-type doped layer 32 and a second transparent conductive layer 42 are stacked on the second intrinsic layer 22;

[0064] The first electrode 51 is in contact with the first transparent conductive layer 41;

[0065] The second electrode 52 is in contact with the second transparent conductive layer 42.

[0066] For example, the silicon wafer 10 is an N-type silicon substrate; the N-type doped layer 31 is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; the P-type doped layer 32 is a P-type doped amorphous silicon layer or a microcrystalline silicon layer; the first transparent conductive layer 41 and the second transparent conductive layer 42 are both TCO (Transparent Conductive Oxides) layers; the first electrode 51 and the second electrode 52 are both gate electrodes.

[0067] The silicon wafer 10 can be made of at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The silicon wafer 10 is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0068] Specifically, this embodiment uses a phosphorus-doped single-crystal silicon substrate as an example for explanation.

[0069] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 can be intrinsic amorphous silicon layers or intrinsic hydrogenated amorphous silicon layers, or intrinsic microcrystalline silicon layers or intrinsic hydrogenated microcrystalline silicon layers. The intrinsic layers mainly serve the function of surface passivation.

[0070] In some embodiments, the first intrinsic layer 21 and the second intrinsic layer 22 may be deposited using a PECVD (plasma-enhanced chemical vapor deposition) process at a deposition temperature of 180°C to 230°C, for example, 180°C, 190°C, 200°C, 210°C, or 230°C, and with a deposition thickness of 4nm to 10nm, for example, 4nm, 6nm, 8nm, or 10nm, but not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0071] For example, when the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic hydrogenated amorphous silicon layers, a PECVD process is used for deposition, during which hydrogen and silane are introduced. When the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon, a PECVD process is used for deposition, during which only silane is introduced.

[0072] In addition, in this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are described as a single layer. In other embodiments, the first intrinsic layer 21 and / or the second intrinsic layer 22 may also be an intrinsic stack formed by multiple intrinsic layers, such as an intrinsic stack composed of an intrinsic amorphous silicon layer and an intrinsic hydrogenated amorphous silicon layer, to further improve the passivation performance.

[0073] In this embodiment, the N-type doped layer 31 is located on the first surface (i.e., the front or light-receiving surface) of the silicon wafer 10. The N-type doped layer 31 is doped with an N-type doping element, which includes at least antimony (Sb). In some embodiments, it may also include at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0074] In this embodiment, the P-type doped layer 32 is located on the second surface (i.e., the back surface or the backlight surface) of the silicon wafer 10. The P-type doped layer 32 is doped with a P-type doping element, which can be at least one of group III elements such as boron (B), indium (In) or gallium (Ga).

[0075] In some embodiments, the N-type doped layer 31 can be an N-type doped amorphous silicon layer, an N-type doped microcrystalline silicon layer, or an N-type doped nanocrystalline silicon layer, and the P-type doped layer 32 can be a P-type doped amorphous silicon layer, a P-type doped microcrystalline silicon layer, or a P-type doped nanocrystalline silicon layer. Preferably, the crystallinity of the N-type doped microcrystalline silicon layer and the P-type doped microcrystalline silicon layer is 25% to 50%, for example, 25%, 30%, 40%, or 50%, and the thickness is 20 nm to 40 nm, for example, 20 nm, 30 nm, or 40 nm, but is not limited to the listed values; other unlisted values ​​within the range are also applicable.

[0076] For example, in this embodiment, the N-type doped layer 31 and the P-type doped layer 32 are described using the P-type doped microcrystalline silicon layer and the N-type doped microcrystalline silicon layer as examples, respectively. The doping element in the N-type doped layer 31 is antimony (Sb), and the doping element in the P-type doped layer 32 is boron (B).

[0077] In the prior art, phosphorus (P) is the commonly used doping element in N-type doped layers 31, but phosphorus doping has certain limitations. Because phosphorus atoms exhibit strong covalent properties in the crystal lattice, they easily combine with hydrogen atoms released by ultraviolet light, thereby reducing the effective doping concentration of the N-type doped layer. This not only affects the electrical performance of the battery but also leads to accelerated battery aging.

[0078] In this invention, an N-type doped layer 31 is disposed on the light-receiving surface of a silicon wafer 10, and antimony (Sb) is used for doping. Since antimony atoms have a weaker ability to combine with hydrogen atoms released by ultraviolet light, the effective doping concentration in the N-type doped layer is less affected by ultraviolet light irradiation, thereby obtaining lower ultraviolet-induced degradation, significantly improving the ultraviolet stability and lifespan of the battery, and preventing the degradation of battery performance and accelerated aging.

[0079] On the other hand, due to the low-temperature processing characteristics of heterojunction solar cells, traditional N-type dopants (such as phosphorus) are at risk of slight diffusion at low temperatures, which may lead to blurring of the heterojunction interface and a reduction in the built-in electric field strength. By doping the N-type doped layer with antimony, the boundary of the N-type doped layer can be made clear, avoiding atomic interdiffusion between the N-type doped layer and the intrinsic layer (ia-Si:H) or the silicon substrate, thus ensuring the bandgap alignment accuracy of the heterojunction. At the same time, doping the N-type doped layer with antimony also ensures good thermal stability of the N-type doped layer during lamination.

[0080] In some implementations, to reduce the risk of UV-induced degradation of the battery and prevent performance degradation and accelerated aging, the antimony doping concentration in the N-type doped layer 31 needs to be controlled to be between 1E18cm⁻¹. -3 and 2.5E20cm -3 Between, for example, could be 1E18cm -3 5E18cm -3 1E19cm -3 5E19cm -3 1E20cm -3 2E20cm -3 Or 2.5E20cm -3 However, this does not limit the listed values; other unlisted values ​​within the range are also applicable.

[0081] More preferably, the antimony doping concentration of the N-type doped layer is between 1E18cm⁻¹. -3 and 1E20cm -3 Between, for example, could be 1E18cm -3 5E10cm -3 1E19cm -3 5E19cm -3 1E20cm -3However, this does not limit the listed values; other unlisted values ​​within the range are also applicable.

[0082] In some embodiments, the N-type doped layer 31 can contain two or more doping elements, such as antimony (Sb) and phosphorus (P) co-doping. To reduce the risk of UV-induced degradation, the atomic percentage of antimony is greater than or equal to 10%, for example, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 100%, but not limited to the listed values; other unlisted values ​​within the range are also applicable. More preferably, the atomic percentage of antimony is greater than or equal to 50%, for example, 50%, 60%, 70%, 80%, 90%, or 100%, but not limited to the listed values; other unlisted values ​​within the range are also applicable. Here, the atomic percentage of antimony refers to the percentage of antimony atoms in the N-type doped layer 31 relative to the total content of all doped atoms (antimony and phosphorus atoms). When only antimony is used for doping, the atomic percentage of antimony in the N-type doped layer 31 is 100%.

[0083] The N-type doped layer 31 and the P-type doped layer 32 can be deposited using PECVD processes. For example, during the deposition of the N-type doped layer, hydrogen, silane, antimonyane, and an oxygen source are introduced, while during the deposition of the P-type doped layer, hydrogen, borane, and an oxygen source are introduced. The deposition of the P-type doped layer is an existing process and will not be described in detail here.

[0084] When the N-type doped layer is an antimony-doped microcrystalline silicon layer, hydrogen, silane, antimony, and an oxygen source are introduced into the PECVD process. For example, the hydrogen flow rate is 20,000 sccm, the silane flow rate is 100 sccm, the antimony flow rate is 10 sccm to 60 sccm, the oxygen source flow rate is 30 sccm, the RF power is 1,000 W to 2,000 W, the chamber pressure is 4 Torr to 6 Torr, and the deposition thickness is 20 nm to 40 nm.

[0085] In the PECVD process, the antimony content is controlled by the flow ratio of silane to antimonyane, which is typically (2~8):1, for example, 2:1, 4:1, or 8:1. A smaller silane to antimonyane flow ratio results in a higher proportion of antimony flow, a higher antimony doping concentration in the N-type doped layer, and better UV-induced degradation performance of the battery.

[0086] In some implementations, the flow rate ratio of hydrogen to silane is (200~300):1, for example, it can be 200:1, 250:1 or 300:1.

[0087] In some embodiments, the oxygen source can be nitrous oxide (N2O), carbon dioxide (CO2), etc. When the oxygen source is nitrous oxide (N2O), the flow rate ratio of the oxygen source to silane is 1:(3~10), for example, it can be 1:3, 1:5, 1:10, etc.

[0088] In some embodiments, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be deposited using a PVD (physical vapor deposition) process.

[0089] In some embodiments, the first transparent conductive layer 41 and the second transparent conductive layer 42 each independently comprise an In-containing oxide conductive film and / or an In-free oxide conductive film. The In-containing oxide conductive film can be any one or a combination of at least two of ITO, VTTO, HITO, or IWO.

[0090] In some embodiments, the thicknesses of the first transparent conductive layer 41 and the second transparent conductive layer 42 are independently 50nm to 150nm, for example, 50nm, 70nm, 90nm, 110nm, 130nm or 150nm, but are not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0091] In some embodiments, the first electrode 51 and the second electrode 52 are grid line electrodes, which are prepared by screen printing using conductive paste and then dried and cured.

[0092] In some embodiments, the conductive paste is a low-temperature silver paste or a silver-copper paste; the curing temperature is 200°C to 220°C, for example, 200°C, 210°C or 220°C, but not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0093] In this embodiment, the N-type doped layer 31 is a single layer of antimony-doped microcrystalline silicon. By controlling the flow rate ratio of the N-type doped layer 31 to the reaction gas in the PECVD process, different heterojunction cells can be prepared. The ultraviolet degradation of different heterojunction cells was verified, and the data are shown in Table 1.

[0094] Table 1: Comparison of UV attenuation data for monolayer doped layers

[0095]

[0096] The UV degradation conditions are as follows: the battery is in open circuit mode, using 150W / m 2 The UV light irradiation was 30 kWh / m², and the ambient temperature was 60°C.

[0097] In Table 1, the N-type doped layer 31 in Comparative Example 1 is a phosphorus-doped microcrystalline silicon layer, and the flow ratio of silane to phosphine during deposition is 8:1. In Examples 1 to 5, the N-type doped layer 31 is an antimony-doped microcrystalline silicon layer, and the flow ratios of silane to antimony during deposition are 100:1, 40:1, 8:1, 4:1, and 2:1, respectively. By controlling the flow rates of silane and antimony, the doping concentration of antimony in the N-type doped layer can be adjusted. The antimony doping concentrations in Examples 1 to 5, as measured by ECV, are 1E18 cm⁻¹. -3 1E19cm -3 1E20cm -3 1.9E20cm -3 2.5E20cm -3 .

[0098] In the heterojunction solar cell, the silicon wafer 10, the P-type doped layer 32, the first intrinsic layer 21, and the second intrinsic layer 22 are all the same. Among them, the silicon wafer 10 is a phosphorus-doped monocrystalline silicon substrate, the P-type doped layer 32 is a boron-doped microcrystalline silicon layer, and the first intrinsic layer 21 and the second intrinsic layer 22 are both intrinsic hydrogenated amorphous silicon layers.

[0099] Comparing Example 1 and Comparative Example 1, it can be seen that, under the same flow range, antimony doping significantly improves the degradation of the battery's short-circuit current Isc, open-circuit voltage Voc, fill factor FF, and battery efficiency Eff compared to phosphorus doping. Compared with Example 1, increasing the amount of antimony doping in Examples 2 to 5 can further improve the degradation of electrical performance.

[0100] Furthermore, compared to Comparative Example 1, Examples 1 to 5 show that because the radius of antimony atoms is larger than that of phosphorus atoms, antimony atoms are more difficult to penetrate into the intrinsic layer during PECVD deposition, thereby improving the passivation effect of the intrinsic layer and also helping to enhance the battery's UV tolerance. Simultaneously, the minority carrier lifetime in the antimony-doped N-type layer is significantly better than that in the phosphorus-doped N-type layer, thus ensuring battery efficiency.

[0101] As can be seen from Examples 6 to 8, using phosphine and antimonyane as mixed doping gases, with the increase of antimonyane in the gas ratio, that is, with the increase of the atomic proportion of antimony in the N-type doped layer, has a certain improvement effect on UV attenuation. Considering both cost and UV attenuation, the preferred approach is to use a combination of phosphorus and antimony doping to improve UV attenuation and reduce cost.

[0102] In some implementations, to balance cost and UV attenuation, when using co-doping with phosphorus and antimony, the antimony doping concentration in the N-type doped layer 31 needs to be controlled to be between 1E18cm⁻¹. -3 ~1E20cm -3 Between, for example, could be 1E18cm -35E18cm -3 1E19cm -3 5E19cm -3 or 1E20cm -3 However, this does not limit the listed values; other unlisted values ​​within the range also apply. Simultaneously, the phosphorus doping concentration should be controlled within 1E18 cm⁻¹. -3 ~1E20cm -3 Between, for example, could be 1E18cm -3 5E18cm -3 1E19cm -3 5E19cm -3 or 1E20cm -3 However, this does not apply to all values ​​within the range that are not listed, but rather to the values ​​listed above.

[0103] In some embodiments, the N-type doped layer 31 may be a multilayer doped microcrystalline silicon layer. For example, the N-type doped layer may include a first N-type doped layer (i.e., an inner doped layer) and a second N-type doped layer (i.e., an outer doped layer) stacked along a first surface away from the silicon wafer, and the doping concentration of the first N-type doped layer is less than that of the second N-type doped layer. At least one of the first N-type doped layer and the second N-type doped layer contains antimony as a doping element.

[0104] In some embodiments, the dopant element of the first N-type doped layer is antimony, and the doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 For example, it could be 1E18cm -3 5E18cm -3 1E19cm -3 5E19cm -3 1E20cm -3 2E20cm -3 Or 2.5E20cm -3 However, this does not limit the listed values; other unlisted values ​​within the range also apply. The second N-type doped layer is doped with phosphorus at a concentration of 1E18 cm⁻¹. -3 ~2.5E20cm -3 For example, it could be 1E18cm -3 5E18cm -3 1E19cm -3 5E19cm -3 1E20cm -3 2E20cm -3 Or 2.5E20cm -3 However, this does not limit the listed values; other unlisted values ​​within the range are also applicable.

[0105] In some embodiments, the dopant element of the first N-type doped layer is phosphorus, and the doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 For example, it could be 1E18cm -3 5E18cm -3 1E19cm -3 5E19cm -3 1E20cm -3 2E20cm -3 Or 2.5E20cm -3 However, this does not limit the listed values; other unlisted values ​​within the range also apply. The second N-type doped layer is doped with antimony at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 The doping concentration is 1E18cm. -3 ~2.5E20cm -3 For example, it could be 1E18cm -3 5E18cm -3 1E19cm -3 5E19cm -3 1E20cm -3 2E20cm -3 Or 2.5E20cm -3 However, this does not limit the listed values; other unlisted values ​​within the range are also applicable.

[0106] When the N-type doped layer 31 is a multilayer doped layer, different heterojunction cells can be prepared by controlling the flow rate ratio of the reactant gas in each doped layer during the PECVD process. The ultraviolet degradation of different heterojunction cells was verified, and the data are shown in Table 2.

[0107] Table 2: Comparison of UV attenuation data for multilayer doped layers

[0108]

[0109] The UV degradation conditions are as follows: the battery is in open circuit mode, using 150W / m 2 The UV light irradiation was 30 kWh / m², and the ambient temperature was 60°C.

[0110] In Table 2, the first N-type doped layer (i.e., the inner doped layer) and the second N-type doped layer (i.e., the outer doped layer) of Comparative Example 2 are both phosphorus-doped microcrystalline silicon layers. In Examples 9 to 11, the first N-type doped layer and the second N-type doped layer are both antimony-doped microcrystalline silicon layers. In Examples 12 to 14, the first N-type doped layer is a phosphorus-doped microcrystalline silicon layer, and the second N-type doped layer is an antimony-doped microcrystalline silicon layer. In Examples 15 to 17, the first N-type doped layer is an antimony-doped microcrystalline silicon layer, and the second N-type doped layer is a phosphorus-doped microcrystalline silicon layer. The thickness of the first N-type doped layer and the second N-type doped layer in all the above comparative examples and examples is 10 nm.

[0111] As can be seen from Examples 9 to 17, replacing any one or both of the inner or outer doped layers with antimony doping can reduce the risk of UV-induced degradation. For mass production equipment, using a single doping element for both doped layers can simplify the piping design in the deposition process and save costs.

[0112] In some embodiments, the N-type dopant element in the silicon wafer 10 is phosphorus, and the doping concentration is 1E19cm⁻¹. -3 ~5E19cm -3 For example, it could be 1E19cm -3 2E19cm -3 3E19cm -3 4E19cm -3 Or 5E19cm -3 However, this does not limit the listed values; other unlisted values ​​within the range are also applicable.

[0113] In another embodiment of the heterojunction solar cell of the present invention, the N-type doping element doped in the silicon wafer 10 can be antimony (Sb) or multiple elements can be doped together. In the case of multiple elements being doped together, one of them is antimony (Sb), and the remaining elements are at least one of group V elements such as phosphorus (P), bismuth (Bi), or arsenic (As).

[0114] Preferably, the silicon wafer 10 is doped with phosphorus and antimony. Phosphorus doping has a gettering effect, while antimony doping enhances and improves this effect, resulting in a significant increase in the short-circuit current Isc and open-circuit voltage Voc of the crystalline silicon cell. Simultaneously, antimony has a low segregation coefficient, and by controlling the concentration of antimony doping, the resistivity uniformity of the silicon wafer can be improved. Therefore, the mixed doping of antimony and phosphorus achieves a balance between resistivity and gettering effect, and further improves cell efficiency.

[0115] Batteries with heterojunction structures utilize low-temperature processing, typically at temperatures not exceeding 250°C. This is significantly lower than the processing temperatures of TOPCon and TBC batteries, which employ high-temperature processing, usually exceeding 500°C. The low-temperature processing of heterojunction structures mitigates the highly volatile nature of antimony during doping, offering a significant advantage over non-heterojunction batteries like TOPCon and TBC. Furthermore, due to the inherent properties of antimony, its doping solubility is low; however, excessively high concentrations of antimony doping can easily lead to interface instability in the silicon wafer, affecting lattice quality. Therefore, controlling the doping concentration is crucial, ensuring both doping efficiency and interface stability of the crystalline silicon substrate.

[0116] By doping antimony into silicon wafer 10, the radius of antimony atoms is larger than that of phosphorus atoms. During ultraviolet irradiation, structural relaxation is less likely to occur in local areas to form defect states, reducing the probability of recombination center formation. Therefore, silicon wafers doped with antimony can further reduce the risk of ultraviolet-induced degradation.

[0117] In some embodiments, the doping element in silicon wafer 10 includes antimony, and the atomic percentage of antimony is greater than or equal to 30%, for example, it can be 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 100%, but is not limited to the listed values; other unlisted values ​​within the range are also applicable. Here, the atomic percentage of antimony refers to the percentage of antimony atoms in silicon wafer 10 relative to the total content of all doped atoms. When only antimony is used for doping, the atomic percentage of antimony in silicon wafer 10 is 100%.

[0118] More preferably, the atomic percentage of antimony is greater than or equal to 60%, for example, it can be 60%, 70%, 80%, 90% or 100%, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0119] The atomic percentage of antimony refers to the percentage of antimony atoms in the crystalline silicon substrate 10 relative to the total content of all doped atoms (antimony and phosphorus atoms). When only antimony is used for doping, the atomic percentage of antimony in the crystalline silicon substrate 10 is 100%. By controlling the content of antimony atoms in the crystalline silicon substrate, the crystallinity and grain size of the crystalline silicon substrate can be improved, and the defect structure in the crystalline silicon matrix can be optimized.

[0120] In some embodiments, the silicon wafer 10 is an N-type monocrystalline silicon substrate. Doping the N-type monocrystalline silicon substrate with antimony can maintain a uniform resistivity distribution during crystal growth, reducing the difference in resistivity between the beginning and end of the substrate. The resulting crystalline silicon solar cell exhibits more uniform surface and internal resistivity. Simultaneously, the interaction between antimony and the silicon lattice stabilizes the lattice structure, reduces vacancy defects, and enhances the mechanical strength of the crystalline silicon substrate. This is particularly important for heterojunction solar cells. Heterojunction solar cells feature thinner silicon wafers; compared to conventional cells, the thickness of the crystalline silicon substrate is reduced from 150 μm to approximately 100 μm, leading to a decrease in the mechanical strength of the substrate. Doping with antimony can improve the mechanical properties of the crystalline silicon substrate, reduce the breakage rate, and increase product yield.

[0121] In some embodiments, the thickness of silicon wafer 10 is less than or equal to 150 μm. More preferably, the thickness of silicon wafer 10 is between 100 μm and 120 μm, for example, it can be 120 μm, 115 μm, 110 μm, 105 μm, or 100 μm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0122] In some embodiments, the thickness of the silicon wafer 10 may be less than 100 μm. More preferably, the thickness of the silicon wafer 10 is between 80 μm and 100 μm, for example, it may be 95 μm, 90 μm, 85 μm, 80 μm, etc.

[0123] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0124] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A heterojunction battery, characterized in that, The heterojunction solar cell includes: A silicon wafer, wherein the silicon wafer is an N-type silicon wafer, comprising a first surface and a second surface disposed opposite to each other; The first intrinsic layer and the N-type doped layer are sequentially stacked on the first surface; The second intrinsic layer and the P-type doped layer are sequentially stacked on the second surface; A first transparent conductive layer stacked on the N-type doped layer; A second transparent conductive layer stacked on the p-type doped layer; and, A first electrode that is electrically in contact with the first transparent conductive layer and a second electrode that is electrically in contact with the second transparent conductive layer; The N-type doped layer contains antimony as a doping element, and the antimony doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 .

2. The heterojunction solar cell according to claim 1, characterized in that, The antimony doping concentration in the N-type doped layer is 1E18cm⁻¹. -3 ~1E20cm -3 .

3. The heterojunction solar cell according to claim 1, characterized in that, The N-type doped layer is a single layer, and the doping element is antimony, with an antimony doping concentration of 1E18cm⁻¹. -3 ~1E20cm -3 ;or, The N-type doped layer is a single layer, and the doping elements are antimony and phosphorus, with an antimony doping concentration of 1E18cm⁻¹. -3 ~1E20cm -3 The phosphorus doping concentration is 1E18cm⁻¹ -3 ~1E20cm -3 .

4. The heterojunction solar cell according to claim 1, characterized in that, The N-type doped layer includes a first N-type doped layer and a second N-type doped layer stacked along a first surface away from the silicon wafer, wherein the doping concentration of the first N-type doped layer is less than that of the second N-type doped layer, and at least one of the first N-type doped layer and the second N-type doped layer contains antimony as a doping element.

5. The heterojunction battery according to claim 4, characterized in that, The first N-type doped layer is doped with antimony at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 The second N-type doped layer is doped with phosphorus at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 ;or, The first N-type doped layer is doped with phosphorus at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 The second N-type doped layer is doped with antimony at a concentration of 1E18cm⁻¹. -3 ~2.5E20cm -3 .

6. The heterojunction solar cell according to claim 1, characterized in that, The N-type doped layer is one or more layers selected from N-type doped amorphous silicon, N-type doped microcrystalline silicon, or N-type doped nanocrystalline silicon; and / or, The P-type doped layer is one or more layers selected from P-type doped amorphous silicon, P-type doped microcrystalline silicon, or P-type doped nanocrystalline silicon; and / or, The thickness of the N-type doped layer is 20 nm to 40 nm; and / or, The thickness of the P-type doped layer is 20 nm to 40 nm.

7. The heterojunction solar cell according to claim 1, characterized in that, The N-type doped layer is an N-type doped microcrystalline silicon layer with a crystallinity of 25%~50%; and / or, The P-type doped layer is a P-type doped microcrystalline silicon layer with a crystallinity of 25% to 50%.

8. The heterojunction battery according to claim 1, characterized in that, The silicon wafer contains phosphorus as a doping element, with a doping concentration of 1E19cm⁻¹. -3 ~5E19cm -3 .

9. The heterojunction battery according to claim 1, characterized in that, The doping elements in the silicon wafer include antimony and phosphorus, and the atomic percentage of antimony is greater than or equal to 30%.

10. A method for preparing a heterojunction solar cell as described in any one of claims 1 to 9, characterized in that, The preparation method includes the following steps: A silicon wafer is provided, the silicon wafer being an N-type silicon wafer, including a first surface and a second surface disposed opposite to each other; A first intrinsic layer and an N-type doped layer are sequentially deposited on the first surface of the silicon wafer. The doping element in the N-type doped layer includes antimony, and the antimony doping concentration is 1E18cm⁻¹. -3 ~2.5E20cm -3 ; A second intrinsic layer and a P-type doped layer are sequentially deposited on the second surface of the silicon wafer; A first transparent conductive layer is deposited on the N-type doped layer, and a second transparent conductive layer is deposited on the P-type doped layer; A first electrode that is in electrical contact with the first transparent conductive layer is prepared on the first transparent conductive layer, and a first electrode that is in electrical contact with the second transparent conductive layer is prepared on the second transparent conductive layer.

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