Preparation process of high-temperature superconducting diode device structure

Abstract

The invention discloses a preparation technology of a high-temperature superconducting diode device structure, and particularly relates to the technical field of superconducting electronic devices and micro-nano machining, and the preparation technology comprises the steps: preparing an on-chip magnetic field generation unit on a substrate, and forming an insulation isolation layer above the on-chip magnetic field generation unit; transferring and fixing a high-temperature superconducting material sheet on the surface of the insulating isolation layer, forming a metal electrode layer on the surface of the sheet, and constructing a micro-bridge asymmetric structure; and forming a side wall passivation packaging layer on the surface of the device, and windowing an electrode lead-out area to realize interconnection. After the device is prepared, factory closed-loop calibration is executed by taking coil driving current as control quantity under a low-temperature condition, forward and reverse critical current is obtained through bidirectional sampling, feedback quantity is constructed, and an optimal working window is determined by adopting coarse scanning and fine scanning adaptive iteration; when it is detected that peak position deviation or feedback quantity deviation exceeds a threshold value, re-calibration is triggered, and finally the parameter set is solidified to serve as a factory acceptance basis.

Description

Technical Field

[0001] This invention relates to the field of superconducting electronic devices and micro / nano fabrication technology, and more specifically, to a fabrication process for a high-temperature superconducting diode device structure. Background Technology

[0002] High-temperature superconducting materials exhibit zero resistance and significant nonlinear transport characteristics under operating conditions below their critical temperature. Microbridge devices constructed based on high-temperature superconducting thin films or sheets typically exhibit critical current, flux dynamics, and non-reciprocal transport behaviors, attracting attention in low-temperature electronic devices and related applications. To address the superconducting diode effect or rectification-related non-reciprocal transport phenomena, existing research typically achieves forward and reverse transport differences by introducing structural asymmetry, interface modulation, or external magnetic fields into the superconducting channel, and combines this with electrical measurements to obtain the device's operating window and performance indicators.

[0003] However, existing technologies still have significant shortcomings in the engineering fabrication and consistent delivery of devices. First, the non-reciprocal transport strength and operating window of devices are highly sensitive to external magnetic field conditions. Existing solutions often rely on external magnets or field sweeping devices for parameter optimization, resulting in large system volumes and the debugging process being easily affected by the clamping environment, magnetic field uniformity, and measurement noise, making it difficult to stably reproduce the operating window. Second, high-temperature superconducting thin-film devices are prone to edge damage, step sidewall defects, or contact differences during transfer, patterning, and interconnection, causing significant dispersion in critical current and non-reciprocal characteristics among different samples. Even with the same process parameters, it is difficult to obtain stable and consistent device performance. Third, devices may exhibit performance drift and hysteresis behavior during low-temperature cycling or environmental exposure, leading to shifts in the operating window position or a decrease in effective non-reciprocal strength, making it difficult to establish a long-term sustainable delivery operating point.

[0004] Furthermore, existing methods rely heavily on manual experience scanning and discrete point trial-and-error to determine the working window, lacking a convergent calibration process and consistency judgment mechanism. This not only affects the consistency of device fabrication in different batches, but also makes it difficult to establish verifiable parameters for factory acceptance and to unify device delivery standards.

[0005] Therefore, there is an urgent need for a fabrication process that can improve the consistency of high-temperature superconducting diode device structure fabrication and form a basis for acceptable delivery parameters, so as to overcome the problems of difficult stable determination of the working window, large device dispersion and insufficient long-term stability in the existing technology. Summary of the Invention

[0006] To overcome the aforementioned deficiencies in the prior art, this invention provides a fabrication process for a high-temperature superconducting diode device structure. This process involves fabricating an on-chip magnetic field generating unit on a substrate and forming a sidewall passivated package and a windowed interconnect structure. Combined with a factory closed-loop calibration process using the coil drive current as the control quantity, the optimal set of drive parameters corresponding to the optimal operating window is determined and solidified, thereby solving the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: A fabrication process for a high-temperature superconducting diode device structure includes the following steps: Step 1: Fabricate an on-chip magnetic field generating unit on the substrate, and form an insulating isolation layer above the on-chip magnetic field generating unit; Step 2: Transfer and fix the high-temperature superconducting material sheet onto the surface of the insulating layer, and form a metal electrode layer on the surface of the sheet. The metal electrode layer is used for electrical connection and also serves as an electrode protection layer. The metal electrode layer can be deposited as a whole and then patterned to form the termination electrode and pad area, or it can be defined simultaneously in the subsequent patterning step. Step 3: The thin film obtained in Step 2 is patterned to form a high-temperature superconducting microbridge structure with geometrically asymmetrical edges; Step 4: After the microbridge structure is formed, a sidewall passivation encapsulation layer is formed to cover the top surface, edges and stepped sidewalls of the microbridge structure, and windows are opened in the electrode lead-out area to expose the metal electrode layer of the pad area to achieve interconnection. Step 5: After completing the windowed interconnect, perform factory closed-loop calibration under low-temperature conditions: use the coil drive current of the on-chip magnetic field generating unit as the control quantity for bidirectional sampling, extract the forward critical current and reverse critical current, and construct a feedback quantity to characterize the difference between the two; establish a drive parameter-feedback quantity response model based on the sampled data, and use an optimization strategy that combines coarse scanning to locate candidate intervals and fine scanning adaptive step iteration to update the sampling points and determine the optimal working window; perform consistency judgment on the round-trip scan results, and trigger recalibration to update the working window if the deviation threshold is exceeded; solidify the drive parameter set corresponding to the optimal working window into device calibration parameters and use it as the basis for factory acceptance.

[0008] The preparation process of the present invention includes a manufacturing process and a factory calibration and curing process, which together constitute a process method for consistent delivery. As a further embodiment of the present invention, the on-chip magnetic field generating unit is a planar spiral microcoil. The linewidth of the planar spiral microcoil is 5-20 μm, the line spacing is 5-20 μm, the number of turns is 3-12, the outer diameter is 200-1200 μm, the conductive layer thickness is 200-1200 nm, and the planar spiral microcoil includes an adhesion layer with a thickness of 5-10 nm.

[0009] As a further embodiment of the present invention, the insulating layer is an aluminum oxide layer or a composite layer of aluminum oxide and silicon dioxide, and the total thickness of the insulating layer is 30-150 nm.

[0010] As a further embodiment of the present invention, the thickness of the high-temperature superconducting material sheet is 50-300 nm, and the metal electrode layer is a gold layer or a multilayer metal film containing a gold layer, with a thickness of 30-150 nm.

[0011] As a further embodiment of the present invention, the patterning process in step three is a two-stage patterning process, including pre-definition of the mesa and fine engraving of the microbridge; the pre-definition of the mesa removes the high-temperature superconducting material sheet and metal electrode layer in the non-working area and forms a mesa structure; the fine engraving of the microbridge forms the main channel and geometrically asymmetrical edge of the high-temperature superconducting microbridge structure on the mesa structure.

[0012] As a further embodiment of the present invention, the main channel width of the high-temperature superconducting microbridge structure is 1-20 μm and the length is 5-100 μm; the geometrically asymmetric edge is a periodic microtooth edge or a gradient notch edge, the period of the periodic microtooth edge or the gradient notch edge is 0.5-5 μm, and the tooth depth or notch depth is 0.2-2 μm.

[0013] As a further embodiment of the present invention, the sidewall passivation encapsulation layer is an aluminum oxide layer or a composite layer of aluminum oxide and silicon nitride, the thickness of the sidewall passivation encapsulation layer is 20-120 nm, and it covers the top surface, edge and stepped sidewall of the high-temperature superconducting microbridge structure; the window size of the electrode lead-out area is 100 μm × 100 μm to 800 μm × 800 μm.

[0014] As a further aspect of the present invention, the bidirectional sampling in step five includes forward current scanning and reverse current scanning; the forward critical current and the reverse critical current are extracted by sliding window fitting and consistency criteria. The consistency criteria include determining that the current enters the dissipation state and the corresponding current is determined as the critical current when K consecutive sampling points simultaneously satisfy the condition that the voltage exceeds the threshold and the local slope exceeds the threshold; the coil driving current step of the coarse scan is 2 to 10 mA, and the initial coil driving current step of the fine scan is 0.2 to 2 mA.

[0015] As a further aspect of the present invention, the driving parameter-feedback response model in step five includes a single-peak fitting or prediction model, and the single-peak fitting or prediction model includes a quadratic fitting model; the adaptive step iteration is determined to converge when the feedback increase is less than the threshold ε or the peak position change is less than the threshold δ after N consecutive iterations.

[0016] As a further aspect of the present invention, the consistency determination in step five includes: the peak position is the coil drive current corresponding to the maximum value of the feedback quantity, the peak position difference is no more than 1 to 3 mA and the feedback quantity deviation is no more than 0.02 to 0.05; the device calibration parameters include at least the optimal working window range, window reference feedback quantity, window lower limit threshold, scan configuration parameters, consistency determination threshold and recalibration trigger threshold.

[0017] The technical effects and advantages of the fabrication process of the high-temperature superconducting diode device structure of the present invention are as follows: This invention integrates controllable modulation conditions into the device structure, transforming the determination of the working window from dependence on external field sweeps to optimization of on-chip controllable parameters. This significantly reduces the system's sensitivity to peripheral magnetic fields and clamping environment, improves debugging efficiency and repeatability, and provides fundamental support for device miniaturization and batch consistency.

[0018] This invention employs passivated encapsulation covering the top surface and stepped sidewalls, combined with windowed interconnects, to effectively isolate and protect the edges and sidewall regions of high-temperature superconducting channels. This reduces the impact of adsorption, defect propagation, and environmental degradation on critical current and non-reciprocal characteristics, improves interconnect reliability and long-term stability, and reduces the risk of performance drift.

[0019] This invention establishes a closed-loop calibration process centered on measurable feedback quantities. It achieves rapid convergence and determination of the working window through response models and adaptive step iterations, and introduces consistency judgment and recalibration triggering mechanisms to make the window determination process verifiable and convergent, thereby improving the delivery consistency between different devices and different batches.

[0020] This invention solidifies the parameter set corresponding to the optimal working window and uses it as the basis for acceptance, forming a verifiable and traceable delivery state parameter standard. It can absorb the dispersion caused by thin film thickness, edge damage and contact differences, reduce reliance on human experience, improve the proportion of effective devices and application stability, and facilitate subsequent large-scale manufacturing and testing. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a high-temperature superconducting diode device according to the present invention; Figure 2 This is a schematic diagram of the fabrication process of a high-temperature superconducting diode device structure according to the present invention; Figure 3 This is a schematic diagram of the factory closed-loop calibration and working window curing process of the present invention; In the figure: 1. Substrate; 2. On-chip magnetic field generating unit; 3. Insulating isolation layer; 4. High-temperature superconducting material sheet; 5. High-temperature superconducting microbridge structure; 6. Metal electrode layer; 7. Sidewall passivation packaging layer; 8. Windowed interconnect structure. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1 like Figure 1 As shown, the high-temperature superconducting diode device structure of this embodiment uses a substrate 1 as the supporting substrate. An on-chip magnetic field generating unit 2 is formed on the substrate 1, and an insulating isolation layer 3 and a high-temperature superconducting material sheet 4 are formed sequentially on top of it. A metal electrode layer (also serving as an electrode protection layer) 6 is formed on the surface of the high-temperature superconducting material sheet 4, and the high-temperature superconducting material sheet 4 is patterned to form a high-temperature superconducting microbridge structure 5 with geometrically asymmetrical edges. Subsequently, a sidewall passivation encapsulation layer 7 is formed on the device surface, and a windowed interconnect structure 8 is formed in the electrode lead-out area. The on-chip magnetic field generating unit 2 is used to provide locally controllable magnetic field modulation input. The geometrically asymmetrical edges of the microbridge structure 5 are used to form the structural barrier difference required for non-reciprocal transport. The sidewall passivation encapsulation layer 7 covers the top surface, edges, and stepped sidewalls of the microbridge structure to improve structural stability. The windowed interconnect structure 8 in the electrode lead-out area is used to expose the metal electrode layer in the pad area to realize electrical connection and measurement interconnection.

[0024] according to Figure 2 The process flow shown begins with substrate cleaning and pretreatment, followed by the fabrication of the on-chip magnetic field generating unit. This is followed by the sequential formation of the insulating isolation layer, wafer transfer and metal electrode layer (which also serves as an electrode protection layer), microbridge patterning, sidewall passivation encapsulation, and windowed interconnects. At the start of fabrication, substrate 1 undergoes cleaning and pretreatment. The substrate is ultrasonically cleaned sequentially in acetone and isopropanol for 5–10 minutes each time, then rinsed with deionized water and dried with nitrogen gas. Finally, it is baked at 120–180°C for 10–20 minutes to remove surface-adsorbed water. To improve subsequent alignment and interconnect consistency, alignment marks and a base pad metal layer can be pre-fabricated at the substrate edge. The base pads can use a Ti / Au system, with Ti thickness of 5–10 nm as an adhesion layer and Au thickness of 80–200 nm as a conductive layer. These are then set aside for later use.

[0025] Subsequently, an on-chip magnetic field generating unit 2 is fabricated on the surface of substrate 1. The on-chip magnetic field generating unit adopts a planar spiral microcoil structure, with a linewidth w preferably of 5–20 μm, a line spacing s preferably of 5–20 μm, a number of turns n preferably of 3–12 turns, and an outer diameter D preferably of 200–1200 μm. The microcoil metal layer adopts a Ti / Au structure, wherein the Ti thickness is 5–10 nm and the Au thickness is 200–1200 nm. The above-mentioned linewidth, line spacing, number of turns, and metal thickness range can achieve low coil resistance and controllable power consumption under low temperature conditions, while ensuring that the coil generates effective local magnetic field modulation in the target working area. The microcoil can be obtained by defining the coil pattern by photolithography and then depositing and peeling off the metal, or it can be obtained by etching. In this embodiment, the peeling process is preferred to improve the consistency of the linewidth boundary and facilitate batch reproducibility. After the microcoil is formed, continuity and resistance are checked. The room temperature resistance is usually in the range of 1–30 Ω. If a short circuit or open circuit is found, it is directly rejected to avoid the accumulation of errors in subsequent processes.

[0026] An insulating layer 3 is formed above the on-chip magnetic field generating unit 2. This insulating layer serves to achieve electrical isolation between the coil and the subsequent high-temperature superconducting thin film and provides a bearing interface. Preferably, an alumina (Al2O3) thin film is formed by atomic layer deposition, with a total thickness preferably of 30–150 nm, more preferably 50–100 nm. When higher dielectric reliability is required, a composite stacked structure of alumina and silicon dioxide can be used, with the total thickness still controlled within the range of 30–150 nm to balance insulation and coupling distance. After the insulating layer is formed, insulation can be verified, for example, by measuring the insulation resistance between the coil port and the substrate surface to confirm effective isolation, thus avoiding unexpected electrical leakage paths or parasitic current paths during subsequent sampling.

[0027] After completing the insulating layer 3, a high-temperature superconducting material sheet 4 is transferred to the surface of the insulating layer 3. In this embodiment, a Bi2Sr2CaCu2O8+x (BSCCO) high-temperature superconducting material sheet is preferably used. The sheet can be obtained through mechanical cleaving and transferred to the surface of the insulating layer 3 using a dry transfer method, ensuring that the sheet covers the predetermined working area and is aligned with the center region of the microcoil. The sheet's planar dimensions are preferably 200μm×200μm to 2mm×2mm, and its thickness is preferably 50–300nm. Excessive thickness will reduce the coil's magnetic field modulation efficiency and increase the difficulty of patterning, while insufficient thickness may lead to local breaks or insufficient continuity. After the sheet transfer is completed, the integrity of the sheet's edges, its coverage area, and its alignment are inspected using a microscope to ensure that the subsequent microbridge working area is within the effective modulation area of ​​the coil. The alignment error can be controlled within 50μm or within 5% of the microcoil's outer diameter. Within this alignment tolerance range, subsequent closed-loop calibration can still stably determine the working window within the reachable modulation range.

[0028] After the wafer transfer is completed, a metal electrode layer 6 is formed on the wafer. The metal electrode layer 6 is used to form electrode lead-out pads and also serves as an electrode protective layer, providing subsequent interconnect interfaces and protecting the top surface of the wafer during patterning and packaging. It is preferably a gold layer or a multilayer metal film containing a gold layer, with a thickness preferably of 30-150 nm, more preferably 50-100 nm. To reduce surface adsorption and performance fluctuations caused by wafer exposure, the metal electrode layer 6 is preferably formed by in-situ deposition or rapid transfer to a vacuum chamber for deposition. If necessary, an ultrathin adhesion layer can be introduced to improve adhesion, but the thickness of the adhesion layer should be kept small to reduce the impact of stress.

[0029] After forming the metal electrode layer 6, the thin sheet is patterned to form a high-temperature superconducting microbridge structure 5 with geometrically asymmetric edges. This embodiment employs a two-stage patterning process: first, a mesa is predefined to remove the high-temperature superconducting material and metal electrode layer from the non-working area and form a mesa structure; then, fine microbridge engraving is performed on the mesa structure to form the main channel and geometrically asymmetric edges of the microbridge. The width W of the main channel is preferably 1–20 μm, and the length L is preferably 5–100 μm. The geometrically asymmetric edges preferably use a combination of periodic microtooth edges or gradient notch edges and straight edges to form a structural barrier difference, wherein the period p of the microtooth or notch is preferably 0.5–5 μm, and the tooth depth or notch depth h is preferably 0.2–2 μm. Fine microbridge engraving can be achieved using ion beam etching or reactive ion etching. Intermittent etching and low power parameters are preferred to reduce localized heating and irreversible edge damage, thereby ensuring the consistency of the microbridge edge morphology with the critical current.

[0030] After the microbridge structure is formed, a sidewall passivation encapsulation layer 7 is formed, and a windowed interconnect structure 8 is formed in the electrode lead-out area. The windowed interconnect structure 8 is an opening window formed on the sidewall passivation encapsulation layer 7, which exposes the metal electrode layer 6 in the pad area to achieve interconnection. The sidewall passivation encapsulation layer 7 covers the top surface, edges, and stepped sidewalls of the microbridge structure to improve structural stability and ensure interconnect reliability. In this embodiment, an alumina passivation layer is preferably formed by atomic layer deposition, with a thickness preferably of 20-120 nm, more preferably 40-80 nm; a composite passivation structure of alumina and silicon nitride can also be used, with the thickness still controlled in the range of 20-120 nm. After the passivation layer is deposited, a window is opened in the electrode lead-out area, with a window area preferably of 100 μm × 100 μm to 800 μm × 800 μm. After the sidewall passivation encapsulation and windowed interconnect are completed, the device has bidirectional sampling electrical connection conditions and coil drive interface conditions.

[0031] After the device is fabricated, such as Figure 3The process shown includes: coarse scanning to locate candidate intervals using coil drive current as control quantity, fine scanning with adaptive step iteration to determine the optimal working window, consistency judgment of reciprocating scans, recalibration triggered by deviation threshold, and solidification of calibration parameter set as acceptance basis.

[0032] Closed-loop calibration is performed under low-temperature conditions that allow the high-temperature superconducting material to enter the superconducting operating state, with the coil drive current I... coil As a control variable for closed-loop optimization, the bidirectional sampling current is used to extract the positive critical current I. c+ With reverse critical current And calculate the feedback quantity F. The closed-loop process first starts at the preset I. coil Coarse scanning is performed within the range to locate the candidate interval of the feedback peak. Then, within the candidate interval, fine scanning adaptive step iteration is performed in combination with the driving parameter-feedback response model to update the sampling points until the convergence criterion is met, and the optimal working window is obtained. After that, the consistency judgment of round-trip scanning is performed. If the deviation from the threshold is triggered, recalibration is triggered to update the working window. Finally, the driving parameter set corresponding to the optimal working window is solidified as the device calibration parameter and used as the acceptance basis.

[0033] In specific execution, in fixed I coil Bidirectional sampling is performed. The forward sampling current gradually increases from 0 to the preset maximum current I. max The reverse sampling current gradually decreases from 0 to -I max I max To cover the critical current and avoid excessive self-heating, in practice, a pre-sampling can be performed to estimate the critical current range before setting I. max Set the current step size to 1.2 to 1.8 times the critical current. The preferred current step size ΔI is 0.1 μA to 20 μA, and the preferred sampling interval is 0.5 ms to 10 ms, ensuring that a single bidirectional sampling is completed within a few seconds. The sampled voltage-current data is used to extract I. c+ and A sliding window fitting and consistency criterion extraction method is used: the sampling points are locally fitted according to the window length m to obtain the voltage level and equivalent slope within the window. When K consecutive sampling points simultaneously satisfy the condition that the voltage exceeds the threshold V, the slope is determined. th And the local slope exceeds the threshold k th The system determines when a state has entered a dissipative state and sets the corresponding current as the critical current. V th The preferred voltage is 0.2μV to 5μV, the preferred window length m is 5 to 30 points, the preferred continuity criterion K is 3 to 10 points, and the preferred local slope threshold k is... th The optimal value is 2 to 10 times the mean of the equivalent slope under noise background, in order to reduce noise misjudgment and ensure the stability of critical current extraction. This extraction method can stably obtain the critical current under noise background and improve the closed-loop iterative convergence stability.

[0034] Based on the extracted I c+ and Construct a feedback quantity F for closed-loop optimization. The feedback quantity adopts the normalized difference form and is defined as (1):

[0035] in, Forward critical current, unit The reverse critical current, unit This is the absolute value of the reverse critical current; The larger of the two values ​​is used for normalization; F is a dimensionless quantity, taking values ​​from 0 to 1, and F is used as a closed-loop feedback variable to guide optimization and window fixing.

[0036] Closed-loop optimization using coil drive current I coil To control the quantity, find the optimal working window within a set range that maximizes the feedback quantity F while maintaining stability at the threshold. coil The preferred range is 1mA to 80mA, with the specific upper limit determined by the low-temperature resistance and thermal stability constraints of the micro-coil. The coil drive current generates Joule heat, and the coil power consumption P is estimated as (2):

[0037] in, The coil drive current, in units For coil resistance, unit Power consumption, in watts (W). During closed-loop calibration, the power consumption P is preferably controlled within the range of 1mW to 50mW, with the upper limit adjusted based on the temperature drift level of the low-temperature platform. In actual operation, the low-temperature resistance of the coil is measured first. Based on this calculation, the allowed I coil To maintain stable closed-loop execution, measures such as increasing the upper limit, shortening the sampling time, increasing heat dissipation contact, or using pulse drive to reduce average power consumption can be implemented.

[0038] Coarse scanning positioning is performed while meeting power consumption constraints. During the coarse scanning phase, I... coil Within the range, with a larger step ΔI coil11 Multiple control points are sampled, and bidirectional sampling, critical current extraction, and feedback quantity F calculation are performed at each control point to obtain F as a function of I. coil The approximate distribution of changes is determined, and candidate peak intervals are located. ΔI coil1 The preferred range is 2mA to 10mA. After the candidate interval is determined, the process enters the fine-scan adaptive iteration stage, using a small initial step ΔI within the candidate interval. coil2 Perform sampling and update the sampling points, ΔI coil2 The preferred range is 0.2mA to 2mA.

[0039] To support adaptive updates during the fine scanning stage, this embodiment establishes a driving parameter-feedback response model as the minimum feasible version, selecting at least 5 different sampling points I within the candidate interval. coil Sampling points are used to obtain the corresponding feedback quantity F, and a single-peak prediction model is constructed using quadratic polynomial fitting. Specifically, the sampling points are arranged according to I... coil Sort by size from smallest to largest, and fit I using a quadratic polynomial. coil The relationship with F is fitted to obtain a fitted curve, and the peak position I of the fitted curve is calculated. peak Then with I peak Perform validation sampling within its neighborhood centered at the validation interval. Δ is taken as 0.5~2mA.

[0040] If the feedback value at the verification point is higher than the current optimal value, then I will be... peak The nearby area is updated as a new candidate interval, and the step size is further reduced. If the validation point is not improved, the candidate interval is shifted to the side with higher feedback value and resampled and fitted, based on the magnitude or peak position change trend of the feedback quantity or peak position of the fitted curve at the boundary of the candidate interval. The second fitting version can be directly implemented in common data processing environments, and the fit is consistent with the change in F. coil It converges rapidly in cases of unimodal variation. To improve noise resistance or enhance the confidence assessment of peak position when there are few sampling points, an interpolation model or regression model can be used to output the uncertainty of peak position to guide the selection of the next sampling point. However, the overall closed-loop framework remains unchanged, combining coarse scanning positioning with fine scanning adaptive updates.

[0041] The fine-scan iteration continues until the convergence criterion is met, at which point the optimal working window is determined. The convergence criterion is either "the increase in feedback quantity after N consecutive iterations is less than a threshold ε" or "the change in peak position is less than a threshold δ", where N is preferably 3–8, ε is preferably 0.005–0.02, and δ is preferably 0.2 mA–1 mA. After the convergence criterion is met, the optimal peak position I is recorded. peak And the window range, and record the corresponding feedback reference value F, and then perform a round-trip scan consistency determination: perform positive I-waves near the optimal window respectively. coil Scan and Reverse I coil The scan is performed, and bidirectional sampling, critical current extraction, and feedback calculation are completed to obtain the peak positions and feedback reference values ​​in two directions; when the peak position difference ΔI peak Consistency is deemed satisfied when the feedback deviation ΔF does not exceed the threshold. Peak position difference ΔI peak The threshold is preferably 1mA to 3mA, and the feedback deviation ΔF threshold is preferably 0.02 to 0.05. When the consistency requirement is higher, three round-trip scans can be used and the intersection window can be taken as the final window to reduce the impact of random deviations.

[0042] When the consistency judgment is not met or the feedback quantity decreases by more than a preset proportion during acceptance retesting, recalibration is triggered. Recalibration expands ±(5~20)mA based on the current window center to perform a rapid coarse scan to locate new candidate intervals, and then enters a fine scan for adaptive iterative update I. peak This is based on the window range, allowing for quick updates to the optimal window while maintaining acceptance requirements. Recalibration is triggered when the feedback amount falls below a minimum threshold F. min Or the relative decrease ratio exceeds η trigger, F min The preferred value is 0.05–0.20, and η is preferably 0.15–0.40. After closed-loop calibration, the set of coil drive current parameters corresponding to the optimal operating window is fixed as the device calibration parameters and used as the acceptance criterion. The fixed parameter set should at least include: the optimal operating window range (I coil Lower limit and upper limit, or central peak I peak and left and right tolerance range), window reference feedback amount F ref Window lower limit threshold F min Recommended sampling and scanning configuration (including ΔI, ΔI) coil1 ΔI coil2 The parameters include sampling interval, consistency judgment threshold (peak position difference threshold and feedback deviation threshold), and recalibration trigger ratio threshold η. The solidified parameter set can be written into a parameter table, lookup table, or configuration file, so that the device can quickly enter the window and maintain consistency during subsequent retesting or use.

[0043] Example 2

[0044] This embodiment is consistent with Embodiment 1 in terms of overall device structure and process flow, including: fabricating an on-chip magnetic field generating unit on a substrate and forming an insulating isolation layer; transferring and fixing a high-temperature superconducting material sheet to the surface of the insulating isolation layer, and forming a metal electrode layer (for electrical connection and also serving as an electrode protection layer) on the sheet surface; using two-stage patterning to form a high-temperature superconducting microbridge structure with geometrically asymmetrical edges; forming a sidewall passivation encapsulation layer and opening windows in the electrode lead-out area to expose the metal electrode layer in the pad area for interconnection; finally, performing factory closed-loop calibration under low-temperature conditions and solidifying the driving parameter set corresponding to the optimal working window as the acceptance criterion. Compared with Embodiment 1, this embodiment provides a more engineering-oriented parameter combination and supplements strategies for sheet fixing, pad interconnection, etching endpoint control, and closed-loop calibration anomaly handling.

[0045] In this embodiment, a high-resistivity silicon substrate (or sapphire substrate) is selected as substrate 1. A planar spiral microcoil is fabricated as the on-chip magnetic field generating unit 2 using a photolithography-metal deposition-lift process. The microcoil linewidth w is 10 μm, the line spacing s is 10 μm, the number of turns n is 8 turns, and the outer diameter D is 800 μm. The coil metal layer adopts a Ti / Au structure, where the Ti thickness is 8 nm for enhanced adhesion and the Au thickness is 700 nm for conductivity. After the coil is formed, continuity testing is performed and the room temperature resistance (typically 5–20 Ω) is recorded. This resistance value is used for subsequent power consumption constraint estimation and drive range setting, thereby reducing the impact of coil heating on low-temperature calibration stability.

[0046] An insulating layer 3 is deposited above the microcoil. The insulating layer is an 80nm thick Al2O3 thin film deposited by ALD. When higher dielectric reliability is required, a 20nm SiO2 layer can be deposited on top of the Al2O3 to form a composite insulating layer. After the insulating layer is completed, the insulation resistance between the coil port and the surface can be tested to confirm the effectiveness of the isolation, thus avoiding leakage current affecting the critical current measurement and feedback calculation.

[0047] The high-temperature superconducting material wafer 4 is a BSCCO wafer with a thickness of 120 nm and a size of approximately 500 μm × 500 μm. Before wafer mounting, the surface of the insulating layer is cleaned with isopropanol and deionized water and dried with nitrogen to reduce particulate contamination and interface residue. The wafer is transferred to the surface of the insulating layer using a dry transfer method, and positioning and alignment are completed under a microscope to ensure that the wafer covers the effective modulation area of ​​the coil. Subsequently, constant pressure is applied for 30–90 seconds to eliminate interface air bubbles, and then baked at 60–90°C for 5–10 minutes to achieve fixation. If necessary, a small amount of insulating adhesive can be introduced at the edge of the wafer to assist in fixation, but the adhesive application area should avoid the microbridge working area and the pad window area, and maintain a distance of at least 50 μm from the working area to reduce the impact of volatile residues on device directionality and contact stability.

[0048] After the thin film is fixed, a metal electrode layer 6 is deposited on the surface of the thin film. The metal electrode layer is used for electrical connection and also serves as an electrode protection layer. In this embodiment, a gold layer with a thickness of 80 nm is used. To improve adhesion, a 2-5 nm ultrathin Ti or Cr adhesion layer can be introduced. After the metal electrode layer is deposited, it is patterned by photolithography and metal etching or lift-off processes to form the termination electrodes at both ends of the microbridge and the electrode lead-out pad areas. The typical size of the pads is 300 μm × 300 μm to match the subsequent windowed interconnect structure, thereby ensuring that "the exposed object is clearly defined and electrical connection can be achieved".

[0049] After the metal electrode layer and pad patterning are completed, a high-temperature superconducting microbridge structure 5 is formed by two-stage patterning. First, the mesa is predefined: the non-working area thin film and its metal layer are removed to form the mesa structure, so as to limit the microbridge processing area and reduce the impact of invalid edge damage on device consistency. Then, the microbridge is finely engraved. The width W of the main channel of the microbridge is 6μm and the length L is 30μm.

[0050] The asymmetric edges of the microbridges are achieved using a combination of "gradient notch edges + straight edges" to create direction-dependent structural barrier differences. Specifically, the notch period p is 2 μm, and the notch depth h gradually increases from 0.3 μm to 1.2 μm, resulting in an asymmetric distribution of the boundary morphology along the current direction. Reactive ion etching or ion beam etching can be used, preferably with low power parameters combined with a segmented etching and intermittent cooling strategy: a 5-10 s pause after every 10-20 s of etching to reduce the risk of localized heating and edge degradation. After etching, the continuity of the microbridge edges is confirmed by microscopic observation, and the reliable connection between the microbridge channel and the terminating electrode is confirmed by electrical continuity testing to avoid over-etching leading to bridge breakage or poor contact, thus ensuring the repeated extraction of the critical current.

[0051] After the microbridge structure is formed, a sidewall passivation encapsulation layer 7 is deposited on the device surface. In this embodiment, a composite passivation structure is adopted: first, Al2O3 with a thickness of 40 nm is deposited, and then SiN is deposited. x The thickness is 40 nm, and the total thickness is 80 nm. The passivation layer covers the top surface, edges, and step sidewalls of the microbridge structure to reduce the influence of environmental adsorption, defect propagation, and mechanical disturbances on the critical current and improve the stability of the device under low-temperature cycling conditions.

[0052] After passivation, a windowed interconnect structure 8 is formed in the electrode lead-out area. The window size is 300μm × 300μm, exposing the metal electrode layer in the pad area to achieve probe contact or bonding interconnection. The window etching can be performed in steps to sequentially remove SiN. x Al2O3 was used, with a metal electrode layer as the stop interface to avoid over-etching and damaging the pads. After windowing, cleaning was performed, and the interconnect reliability was confirmed by probe contact resistance testing, providing stable electrical connection conditions for subsequent low-temperature closed-loop calibration.

[0053] After passivation, a windowed interconnect structure 8 is formed in the electrode lead-out area. The window size is 300μm × 300μm, exposing the metal electrode layer in the pad area to achieve probe contact or bonding interconnection. The window etching can be performed in steps to sequentially remove SiN. x Al2O3 was used, with a metal electrode layer as the stop interface to avoid over-etching and damaging the pads. After windowing, cleaning was performed, and the interconnect reliability was confirmed by probe contact resistance testing, providing stable electrical connection conditions for subsequent low-temperature closed-loop calibration.

[0054] After the device completes the windowed interconnect, it undergoes factory closed-loop calibration in a low-temperature environment below the critical temperature of the high-temperature superconducting material, using the coil drive current I. coil Bidirectional sampling is performed to obtain the forward critical current for the control quantity. With reverse critical current A feedback quantity F for closed-loop optimization is constructed based on the critical current, and the feedback quantity F is calculated according to the aforementioned equation (1). The critical current is extracted using a voltage threshold criterion: at a fixed I... coil The VI curve is obtained under the condition that the voltage across the device reaches the threshold V. th The current corresponding to (0.5~2μV) is determined as the critical current; to reduce noise misjudgment, the voltage signal can be averaged or the average value can be obtained by repeated measurement.

[0055] To limit the impact of coil heating on calibration stability, the coil power consumption P is calculated according to the aforementioned equation (2), and I is determined based on the preset power consumption upper limit. coil Within the allowable range; when a temperature rise is detected that causes a decrease in the critical current or an increase in the feedback fluctuation, reduce I. coil The upper limit may employ pulse driving to reduce average power consumption. Closed-loop optimization uses a combined coarse and fine scan strategy: the coarse scan stage in I... coil Within the range of 0 to 60 mA, sampling is performed in 5 mA increments to locate the candidate peak interval; in the fine scanning stage, sampling is performed in 0.5 mA increments within the candidate interval, and a driving parameter-feedback response model is established at at least 5 sampling points. The peak position I is obtained through quadratic fitting. peak (The peak position is the coil drive current corresponding to the maximum value of the feedback quantity F), and then in The optimal working window is updated iteratively by sampling and validating samples from the neighborhood. The convergence criterion is that the increase in feedback value is less than ε=0.01 or the change in peak position is less than δ=0.5mA after N=5 consecutive iterations, which determines convergence and thus the optimal working window.

[0056] When the feedback curve exhibits noise multi-peak characteristics, the largest peak is preferentially selected as the candidate peak position, and the average value is repeatedly sampled in its neighborhood to confirm the true peak. If the fitting residual is too large, the candidate interval is expanded or the step size is reduced for resampling to ensure stable convergence of the closed-loop calibration. The final solidified parameter set includes at least the optimal working window range, window reference feedback quantity, window lower limit threshold, scan configuration parameters, consistency judgment threshold, and recalibration trigger threshold, and serves as the basis for device factory acceptance and retesting, making the device operating point traceable and reverifiable, thereby improving the device's directional stability and batch consistency.

[0057] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0058] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A fabrication process for a high-temperature superconducting diode device structure, characterized in that, Includes the following steps: Step 1: Fabricate an on-chip magnetic field generating unit on the substrate, and form an insulating isolation layer above the on-chip magnetic field generating unit; Step 2: Transfer and fix the high-temperature superconducting material sheet onto the surface of the insulating layer, and form a metal electrode layer on the surface of the sheet. The metal electrode layer is used for electrical connection and also serves as an electrode protection layer. Step 3: The thin film obtained in Step 2 is patterned to form a high-temperature superconducting microbridge structure with geometrically asymmetrical edges; Step 4: After the microbridge structure is formed, a sidewall passivation encapsulation layer is formed to cover the top surface, edges and stepped sidewalls of the microbridge structure, and windows are opened in the electrode lead-out area to expose the metal electrode layer of the pad area to achieve interconnection. Step 5: After completing the windowed interconnect, perform factory closed-loop calibration under low-temperature conditions: use the coil drive current of the on-chip magnetic field generating unit as the control quantity for bidirectional sampling, extract the forward critical current and reverse critical current, and construct a feedback quantity to characterize the difference between the two; establish a drive parameter-feedback quantity response model based on the sampled data, and use an optimization strategy that combines coarse scanning to locate candidate intervals and fine scanning adaptive step iteration to update the sampling points and determine the optimal working window; perform consistency judgment on the round-trip scan results, and trigger recalibration to update the working window if the deviation threshold is exceeded; solidify the drive parameter set corresponding to the optimal working window into device calibration parameters and use it as the basis for factory acceptance.

2. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The on-chip magnetic field generating unit is a planar spiral microcoil. The linewidth of the planar spiral microcoil is 5-20 μm, the line spacing is 5-20 μm, the number of turns is 3-12, the outer diameter is 200-1200 μm, the conductive layer thickness is 200-1200 nm, and the planar spiral microcoil includes an adhesion layer with a thickness of 5-10 nm.

3. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The insulating layer is an aluminum oxide layer or a composite layer of aluminum oxide and silicon dioxide, and the total thickness of the insulating layer is 30-150 nm.

4. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The thickness of the high-temperature superconducting material sheet is 50–300 nm, and the metal electrode layer is a gold layer or a multilayer metal film containing a gold layer, with a thickness of 30–150 nm.

5. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The patterning process described in step three is a two-stage patterning process, including pre-defining the mesa and fine carving the microbridges. The pre-defining of the mesa removes the high-temperature superconducting material sheet and metal electrode layer from the non-working area and forms the mesa structure. The fine carving of the microbridges forms the main channel and geometrically asymmetrical edges of the high-temperature superconducting microbridge structure on the mesa structure.

6. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The main channel width of the high-temperature superconducting microbridge structure is 1–20 μm, and the length is 5–100 μm; the geometrically asymmetric edge is a periodic microtooth edge or a gradient notch edge, the period of the periodic microtooth edge or the gradient notch edge is 0.5–5 μm, and the tooth depth or notch depth is 0.2–2 μm.

7. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The sidewall passivation encapsulation layer is an aluminum oxide layer or a composite layer of aluminum oxide and silicon nitride. The thickness of the sidewall passivation encapsulation layer is 20-120 nm, and it covers the top surface, edge and stepped sidewall of the high-temperature superconducting microbridge structure. The window size of the electrode lead-out area is 100 μm × 100 μm to 800 μm × 800 μm.

8. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, Step 5, the bidirectional sampling, includes forward current scanning and reverse current scanning. The forward critical current and reverse critical current are extracted through sliding window fitting and consistency criteria. The consistency criteria include determining that the current enters the dissipation state and the corresponding current is determined as the critical current when K consecutive sampling points simultaneously satisfy the condition that the voltage exceeds the threshold and the local slope exceeds the threshold. The coil drive current step of the coarse scan is 2 to 10 mA, and the initial coil drive current step of the fine scan is 0.2 to 2 mA.

9. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The driving parameter-feedback response model in step five includes a single-peak fitting or prediction model, which includes a quadratic fitting model; the adaptive step iteration is determined to converge when the feedback increase is less than the threshold ε or the peak position change is less than the threshold δ after N consecutive iterations.

10. The fabrication process of a high-temperature superconducting diode device structure according to claim 1, characterized in that, The consistency determination in step five includes: the peak position is the coil drive current corresponding to the maximum value of the feedback quantity, the peak position difference is no more than 1 to 3 mA and the feedback quantity deviation is no more than 0.02 to 0.05; the device calibration parameters include at least the optimal working window range, window reference feedback quantity, window lower limit threshold, scan configuration parameters, consistency determination threshold and recalibration trigger threshold.

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