Electronic device with metal shielding to reduce spate charge

Abstract

The invention relates to an electronic device with reduced space charge effect metal shielding and a method of manufacturing the same. A semiconductor die includes a semiconductor substrate and a dielectric layer extending over the semiconductor substrate. The high voltage module extends over the semiconductor substrate. The metal guard ring extends into the dielectric layer and completely surrounds the high voltage module. The die further includes at least one electronic device extending to an exterior of the guard ring. The metal cover layer includes a first portion extending over the high voltage module and a second portion extending over and in electrical contact with the metal guard ring. A bond wire is electrically coupled to the first portion and extends over the dielectric layer at the electronic device. A metal shield extends over the guard ring, is interposed between the bond wire and the electronic device, and is physically and electrically connected to a second portion of the metal cap layer.

Description

[0001] Priority statement:

[0002] This application claims priority to Italian patent application No. 102024000023214, filed on October 18, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This invention relates to an electronic device and a method for manufacturing the same, and more specifically, to an electronic device including a screen for reducing space charge effects. Background Technology

[0004] In the semiconductor industry, high-voltage (HV) and current-isolated integrated circuits are provided as system-in-package (SiP), in which multiple integrated circuit dies are electrically connected to each other by bonding wires and fixed to electrically insulated corresponding frames.

[0005] In use, the circuit elements of a die can be biased to a high voltage (e.g., between 100V and 1700V) via bonding wires. Typically, the bonding wires extend from the biasing element toward the external environment, passing over and partially facing the corresponding die. These bias voltages differ from the voltage values ​​on the surface of the corresponding die facing the biased bonding wires (e.g., ground or between 0V and 100V).

[0006] The voltage difference between the bond wire and the surface of the underlying die generates a high electric field within the surface layer of the die. This electric field causes a problem known as the "space charge effect." The space charge effect exists as the accumulation of charge in a finite region of the material. This accumulated charge, in turn, generates an electric field that affects the operation of electronic devices integrated into the corresponding die and located near the charge accumulation region. Specifically, MOS transistors located in the die region below or near the bond wire experience a change in their turn-on threshold voltage due to the space charge effect.

[0007] In addition, high-resistance polycrystalline resistors ("HIPO resistors") located in the die region below or near the bond lines experience changes in resistance due to the space charge effect.

[0008] Similarly, bipolar transistors may experience gain drift.

[0009] In addition, space charge effects may also lead to the formation of parasitic MOS transistors.

[0010] These issues particularly affect the operation of analog circuit modules such as differential amplifiers and current mirrors.

[0011] Figure 1A The transverse cross-sectional view in the xz plane schematically illustrates the bare die 1 in a mutually orthogonal x, y, z triaxial system.

[0012] The bare die 1 includes a solid body 2, which in turn includes a substrate 4 made of a semiconductor material, such as, for example, silicon (Si), or silicon carbide (SiC), or gallium nitride (GaN), or SOI (silicon on insulator) type; a dielectric layer 6 extending on a surface 4a of the substrate 4; and a passivation layer 8 extending on the dielectric layer 6, in particular in direct physical contact with the surface 6a of the dielectric layer 6.

[0013] The dielectric layer 6 is, for example, silicon dioxide (SiO2). A first metal plate 10 extends within the dielectric layer 6, spaced a distance from the surface 4a of the substrate 4; a second metal plate 12 extends into the dielectric layer 6 above the first metal plate 10 and is also spaced a distance from the first metal plate 10. The first metal plate 10 and the second metal plate 12 are, for example, made of copper (Cu) and together form a capacitor 14 suitable for operation as an electrical insulator.

[0014] Furthermore, the guard ring 16 extends within the dielectric layer 6 and completely surrounds the capacitor 14 in a top view on the xy plane. The guard ring 16 includes a plurality of metal layers 18(1)-18(N) extending parallel to the xy plane at corresponding metal levels M(1)-M(N), electrically connected to each other and electrically connected to the substrate 4 through metal vias 20. Metal level M(1) corresponds to the metal level closer to or closest to the surface 4a of the substrate 4, and metal level M(N) corresponds to the metal level furthest from the surface 4a of the substrate 4; intermediate metal levels M(2)-M(N-1) extend between metal levels M(1) and metal levels M(N) in an increasing order away from the surface 4a of the substrate 4 along the z-axis. The number N of metal levels depends on the architecture of the integrated circuit provided as a SiP and is, for example, between 2 and 10, such as equal to 5.

[0015] Therefore, metal layer 18(1) is the bottom metal layer with the smallest distance from the surface 4a of substrate 4 relative to the other metal layers 18(2)-18(N), and metal layer 18(N) is the top metal layer with the largest distance from the surface 4a of substrate 4 relative to the other metal layers 18(1)-18(N-1).

[0016] The guard ring 16 is coupled to the GND reference potential through the substrate 4.

[0017] Additional metal layers 19(1)-19(N), (especially made of copper), are adapted to form electrical interconnects between different portions of the die 1 and also extend at the metal layer level M(1)-M(N) that houses the metal layers 18(1)-18(N).

[0018] The first metal plate 10 and the second metal plate 12 of the capacitor 14 extend in corresponding metal layers M(1)-M(N). For example, the first metal plate 10 extends in the metal layers between M(1) and M(N-1) (e.g. Figure 1A The metal layer M(4) extends in the middle, and the second metal plate 12 extends in the last metal layer M(N).

[0019] Furthermore, the metal capping layer 24 extends onto the metal layer 18(N) and into the dielectric layer 6 on the second plate 12, making direct electrical contact with both the metal layer 18(N) and the second plate 12. Specifically, a portion 26 of the capping layer 24 extending into the second plate 12 has a surface 26a at least partially exposed through an opening in the surface 6a of the dielectric layer 6 and a via in the passivation layer 8. Furthermore, a portion 28 of the capping layer 24 extending into the metal layer 18(N) and making electrical contact with the guard ring 16 has a surface 28a at least partially exposed through a corresponding opening in the surface 6a of the dielectric layer 6 and a via in the passivation layer 8.

[0020] The capping layer 24 provides surfaces 26a, 28a suitable for coupling with external bonding lines, and also protects the metal layer 18(N) and the second plate 12 from external factors such as moisture or contaminants. The capping layer 24 is made of aluminum (Al), for example.

[0021] The die 1 also includes a plurality of semiconductor devices 22 (illustrated only in FIG. 1), such as, for example, MOS transistors, bipolar transistors, and / or polycrystalline resistors, which extend at surface 4a into the substrate 4 and to the outside of the guard ring 16. The guard ring 16 is adapted to protect the plurality of semiconductor devices 22 from the high bias voltage applied to the capacitor 14.

[0022] Bonding wire 30 extends over a portion of die 1, spaced a distance from passivation layer 8, and terminates at one end in electrical contact with surface 26a of portion 26 of capping layer 24. In use, the bonding wire 30 allows a bias voltage to be applied to the second plate 12 of capacitor 14, or allows additional die 200 to be connected to die 100 (see [link to documentation]). Figure 4 For example, for applications that require isolation between inputs and outputs, especially in isolated gate drivers or isolated UARTs.

[0023] The voltage difference between the bonding wire 30 and the substrate 4 of the bare die 1 (where the bonding wire 30 faces the bare die 1) causes charge to accumulate in the charge accumulation region 32, which extends partly inside the dielectric layer 6 and partly inside the passivation layer 8. Therefore, the performance of the semiconductor device 22 extending at the charge accumulation region 32 is reduced due to the accumulated space charge.

[0024] Solutions to the space charge problem, such as Figure 1B As shown in the diagram.

[0025] Figure 1B A schematic cross-sectional view in the xz plane illustrates the bare die 1' in a triaxial system of mutually orthogonal x, y, and z axes. Figure 1B In the middle, nude film 1' and Figure 1A The common elements of the bare die 1 are indicated by the same reference numerals and will not be described further.

[0026] The bare die 1' includes a metal shield 34 that extends into the dielectric layer 6, laterally into the guard ring 16, and is in direct physical and electrical contact with the guard ring 16. The metal shield 34 is therefore coupled to the reference potential GND. Specifically, the metal shield 34 is an extension of metal layers 18(1)-18(N). Figure 1B In the illustrated example, metal shield 34 is a lateral extension of metal layer 18 (N).

[0027] A metal shield 34 extends to be inserted between the semiconductor device 22 and the bonding wire 30. Furthermore, the metal shield 34 confines the charge accumulated by the space charge effect within a region 32', which extends partially above the metal shield 34 in the dielectric layer 6 and partially in the passivation layer 8. In this way, the electric field at the semiconductor device 22 is reduced, and the metal shield 34 protects the semiconductor device 22a from the effects of the space charge effect.

[0028] However, the metal shield 34 occupies a portion of the corresponding metal layers M(1)-M(N) that cannot be used to provide further electrical connections. Therefore, due to the presence of the metal shield 34, a larger area needs to be occupied or additional metal layers M(N+1) need to be added to provide such electrical interconnects. Both of these approaches complicate the manufacturing process and increase the production cost of the final device.

[0029] Therefore, there is a need to provide an electronic device and a method for manufacturing the same to overcome the shortcomings of the prior art. Summary of the Invention

[0030] In an embodiment, the semiconductor die includes: a semiconductor substrate having a first surface; a dielectric layer extending on the first surface and having a second surface opposite to the first surface along an axis; a high-voltage module extending at least partially into the dielectric layer on the semiconductor substrate; a metal guard ring extending into the dielectric layer to completely surround the high-voltage module, wherein the metal guard ring is configured to be electrically coupled to a reference potential in use; at least one electronic device extending at the first surface to the outside of the metal guard ring; and a metal overlay layer, including: extending on the high-voltage module and adjacent to the high-voltage module. The first portion of the block electrical contact; and a second portion extending on and electrically insulated from the first portion and in electrical contact with the metal guard ring; a bonding wire electrically coupled to the first portion of the metal overlay and extending on the dielectric layer at the electronic device; a plurality of metal levels in the dielectric layer, each metal level including at least one corresponding first metal path for routing electrical signals and at least one corresponding second metal path forming the portion of the guard ring; and a metal shield above the guard ring, the metal shield being inserted between the bonding wire and the electronic device and physically and electrically connected to the second portion of the metal overlay.

[0031] In one embodiment, the system includes: the semiconductor die described above; and another semiconductor die; wherein the bonding wire connects the other semiconductor die to a first portion of the semiconductor die.

[0032] In an embodiment, a method of manufacturing a semiconductor die includes the following steps: forming a dielectric layer on a first surface of a semiconductor substrate, the semiconductor substrate housing at least one electronic device at the first surface, the dielectric layer having a second surface opposite to the first surface along an axis; forming a high-voltage module at least partially in the dielectric layer; forming a metal guard ring in the dielectric layer, the metal guard ring completely surrounding the high-voltage module and configured to be electrically coupled to a reference potential in use, the electronic device being outside the metal guard ring; forming a metal capping layer including: forming a first portion on the high-voltage module and electrically contacting the high-voltage module; and forming a second portion on the metal guard ring that is electrically insulated from the first portion and electrically contacting the metal guard ring; forming a bonding wire electrically coupled to the first portion of the metal capping layer and extending on the dielectric layer at the electronic device; and forming a shield of metallic material on the guard ring, inserted between the bonding wire and the electronic device, physically and electrically connected to the second portion of the metal capping layer. Attached Figure Description

[0033] To better understand the invention, some embodiments of the invention will now be described by way of non-limiting example with reference to the accompanying drawings, in which:

[0034] Figure 1AThe cross-sectional view illustrates the bare die of the integrated circuit;

[0035] Figure 1B The cross-sectional view illustrates the bare die of the integrated circuit;

[0036] Figure 2 The cross-sectional view illustrates the bare die of the integrated circuit;

[0037] Figures 3A-3E The manufacturing steps of an integrated circuit die are illustrated in a cross-sectional view.

[0038] Figure 4 A system including a die of an integrated circuit is schematically illustrated in perspective view. Detailed Implementation

[0039] Figure 2 A schematic cross-sectional view in the xz plane, according to an embodiment, illustrates the blank 100 in a triaxial system of mutually orthogonal x, y, and z axes.

[0040] Elements common to both bare film 100 and bare film 1 are identified by the same reference numerals and will not be described further.

[0041] Therefore, the bare die 100 includes: a solid body 2, which in turn includes a substrate; a dielectric layer 6 on a surface 4a of the substrate 4; and a passivation layer 8 extending to contact the surface 6a of the dielectric layer 6.

[0042] The passivation layer 8 is made of, for example, silicon dioxide (SiO2) or silicon nitride (Si3N4) or silicon oxynitride (SiON) and / or polymeric materials such as polyimide or polyamide, and has a thickness between 10 µm and 20 µm, particularly equal to 15 µm.

[0043] The dielectric layer 6 is made of, for example, silicon dioxide (SiO2), silicon oxynitride (SiON), or silicon nitride (Si3N4). In one embodiment, the dielectric layer 6 is a stack of a single dielectric material such as silicon oxide, silicon oxynitride (SiON), or silicon nitride (Si3N4). In another embodiment, the dielectric layer 6 comprises a stack of different dielectric materials, such as, for example, silicon dioxide (SiO2), silicon oxynitride (SiON), or silicon nitride (Si3N4).

[0044] The dielectric layer 6 has a thickness between 5 µm and 20 µm, and in particular equal to 14 µm.

[0045] In one embodiment, with Figure 1AAs described above, the first metal plate 10 and the second metal plate 12 form a capacitor 14 adapted to function as an electrical insulator. In another embodiment (not shown), the capacitor 14 may be replaced by or arranged side-by-side with different high-voltage modules 14 (e.g., one or more electronic devices adapted to be biased to a high voltage, such as a high-voltage inductor or transistor). In corresponding embodiments, the high-voltage module 14 includes one or more of the following: a capacitor, an inductor, a transistor, or a resistor.

[0046] The dielectric layer 6 is also housed in a protective ring 16 that completely surrounds the capacitor 14 in a top view on the xy plane. In embodiments where the capacitor 14 is replaced by or arranged side-by-side with one or more electronic devices adapted to be biased to a high voltage, the protective ring 16 completely surrounds such one or more devices.

[0047] In one embodiment, in a top view on the xy plane, the protective ring 16 has a substantially circular shape. Alternatively, the protective ring 16 may be elliptical, or typically polygonal or a polygon with rounded edges.

[0048] The dielectric layer 6 contains a cover layer 24 of metallic material that extends over the top metal layer 18(N) and the second plate 12, and is in electrical contact with the top metal layer 18(N) and the second plate 12.

[0049] The capping layer 24 does not have wiring or electrical interconnect functions, but is adapted to protect the top metal layer 18(N) from contaminants such as, for example, moisture or corrosive agents and to provide surfaces 26a, 28a suitable for coupling to one or more bonding wires via solder / wire bonding. The capping layer 24 is made of a metallic material, such as aluminum (Al) or a metallic material comprising an aluminum content (or tenor) of 90% or more.

[0050] In one embodiment, the metallic material of the cover layer 24 is substantially aluminum. “Substantially” means aluminum except for potential impurity elements, such as those inherent to the raw materials and / or introduced during the processing of the raw materials.

[0051] In one embodiment, the metal material of the cover layer 24 includes an aluminum-copper alloy (AlCu), comprising an aluminum content (or grade) of 95% or more, preferably 97% or more, and more preferably 99% or more, and a copper content (or grade) of 5% or more, preferably 3% or more, and more preferably 1% or more.

[0052] The cover layer 24 has a thickness between 0.5 µm and 3 µm, for example, equal to 1.2 µm.

[0053] The bare die 100 also includes multiple semiconductor devices 22, and Figure 1AThe semiconductor device extends into the substrate 4 at surface 4a and extends to the outside of the protective ring 16, as described above.

[0054] In one embodiment, there is a bonding line 30, also referenced Figure 1A The description is as follows. Specifically, a portion 30a of the bonding wire 30 extends a distance from the passivation layer 8, at least partially above the semiconductor device 22. The bonding wire 30 is made of, for example, aluminum (Al), gold (Au), silver (Ag), or copper (Cu). For example, the bonding wire 30 has a portion with a diameter between 20 µm and 50 µm.

[0055] The bare die 100 also includes a shield 134, particularly a metal shield 134. In one embodiment, the metal shield 134 comprises aluminum with a content (or grade) greater than or equal to 90%. In one embodiment, the shield 134 is formed by a patterned capping layer 24, extending laterally parallel to the xy plane in the dielectric layer 6 and extending to the outside of the guard ring 16. Specifically, the metal shield 134 is inserted between the semiconductor device 22 and the bonding wire 30 and makes electrical contact with portion 28. Even more specifically, the metal shield 134 is inserted vertically (i.e., along the z-axis) between the semiconductor device 22 and the bonding wire 30 and is physically and electrically connected to portion 28. Specifically, the metal shield 134 extends as a continuation of portion 28 of the capping layer 24. More specifically, the metal shield 134 and portion 28 of the capping layer 24 are monolithic.

[0056] Metal shield 134 extends inside dielectric layer 6. In one embodiment, in a top view on the xy plane, metal layer 134 extends completely around protective ring 16.

[0057] In another embodiment, in a top view on the xy plane, the metal shield 134 extends around the protective ring 16 but still extends above the semiconductor device 22, between the bonding line 30 and the semiconductor device 22.

[0058] The metal shield 134 is electrically coupled to the guard ring 16 through part 28, and is therefore biased to the reference potential GND during use.

[0059] Specifically, the metal shield 134 and the cover layer 24 (part 28) are made of the same material.

[0060] In a preferred embodiment, the metal shield 134 is made of aluminum (Al) or an aluminum-copper alloy (AlCu) or an alloy including aluminum, while the metal layers 18(1)-18(N) are made of copper or substantially copper.

[0061] A high voltage difference (e.g., in the range of 100V-1700V) between the bonding wire 30 and the substrate 4 of the bare die 100 can cause charge to accumulate in a charge accumulation region 132, which extends above the metal shield 134 at the bonding wire 30, partially within the dielectric layer 6 and partially within the passivation layer 8. In other words, the metal shield 134 confines the charge accumulated by the space charge effect within the charge accumulation region 132. In this way, at the semiconductor device 22, the electric field generated by the charge accumulated by the space charge effect in the charge accumulation region 132 is reduced or shielded; therefore, the metal shield 134 protects the semiconductor device 22 from the effects of the space charge effect.

[0062] Metal shielding 134 allows protection of semiconductor devices from space charge effects without the need for portions of metal layers 18(1)-18(N) (such as...). Figure 1B (as seen in the embodiments), thereby saving area and avoiding the need for additional metal layers, reducing the complexity and cost of the manufacturing process of the bare die 100.

[0063] refer to Figures 3A-3E A method for manufacturing a die 100 according to an embodiment will now be described, the method being limited to manufacturing steps and portions of the die 100 associated with the embodiment. Figures 3A-3E The cross-section of the bare die 100 in the xz plane is schematically shown.

[0064] refer to Figure 3A A substrate 4 including a semiconductor device 22 is provided. On the substrate 4, a protective ring 16, a first metal plate 10 and a second metal plate 12 of a capacitor 14, additional metal layers 19(1)-19(N), and a first dielectric portion 105 of a dielectric layer 6 are formed in a manner known to the art. The first dielectric portion 105 completely covers the protective ring 16 and the capacitor 14, and has a first surface 105a and a second surface 105b that are opposite each other along the z-axis. The second surface 105b directly faces (specifically, directly physically contacts) the surface 4a of the substrate 4.

[0065] refer to Figure 3B Mask etching (e.g., by photolithography and reactive ion etching (RIE) steps) is performed on the first surface 105a of the first dielectric portion 105 to open trenches 107 at the guard ring 116 and the second metal plate 12. The trenches 107 expose the surface 116a of the top metal layer 18(N) of the guard ring 16 and the surface 112a of the second metal plate 12, respectively.

[0066] refer to Figure 3CThe capping layer 24 is deposited on the first surface 105a and surfaces 116a and 112a (e.g., by physical vapor deposition (PVD) or by sputtering). The capping layer 24 is then patterned (e.g., by successive photolithography and etching steps) to form portions 26 and 28 and a metal shield 134.

[0067] refer to Figure 3D Above the capping layer 24 and the first dielectric portion 105, a deposition step of the second dielectric portion 109 is performed (e.g., by plasma-assisted chemical vapor deposition (CVD)). The first dielectric portion 105 and the second dielectric portion 109 together form the dielectric layer 6.

[0068] refer to Figure 3E The process involves depositing the passivation layer 8 (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or other processes), followed by one or more mask etching steps (e.g., by sequential photolithography or chemical etching) of the passivation layer 8 and the dielectric layer 6 to expose corresponding portions of the surface 26a of the corresponding portion 26 and the surface 28a of the corresponding portion 28. Then, a coupling step of the bonding wire 30 is performed (e.g., by soldering or bonding) to physically or electrically couple one end of the bonding wire 30 to the surface 26a of the covered portion 26, thereby obtaining... Figure 2 100 nude photos.

[0069] Optionally, the die 100 may be fully or partially encapsulated in a passivation layer of molding compound 140, which is adapted to protect the die 100 and the bonding wires 30 from external contaminants and reduce mechanical stresses that could cause the bonding wires 30 to separate. Electrical contact areas are formed through the passivation layer of the molding compound in a manner known per se for biasing the die 100.

[0070] Finally, it is obvious that modifications and variations may be made to the content described and illustrated herein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor die, comprising: A semiconductor substrate having a first surface; A dielectric layer extending on a first surface and having a second surface opposite to the first surface along an axis; A high-voltage circuit module that extends at least partially into a dielectric layer on a semiconductor substrate; A metal guard ring extends into the dielectric layer, completely surrounds the high-voltage circuit module, and is configured to be electrically coupled to a reference potential during use. At least one electronic device, said at least one electronic device extending at a first surface to the outside of a metal protective ring; The metal overlay includes: a first portion extending on and in electrical contact with the high-voltage module; and a second portion extending on and in electrical contact with the metal protective ring, which is electrically insulated from the first portion; A bonding wire electrically coupled to a first portion of a metal overlay and extending on a dielectric layer at the electronic device; A plurality of metal levels in a dielectric layer, each metal level including at least one corresponding first metal path for routing electrical signals, and at least one corresponding second metal path forming a metal guard ring; and The metal shield above the protective ring is inserted between the bonding wire and the electronic device, and is physically and electrically connected to the second part of the metal cover layer.

2. The semiconductor die of claim 1, wherein the second portion of the metal shield and the metal overlay is made of the same metallic material.

3. The semiconductor die according to claim 1: The top metal layer of the plurality of metal layers is located at a greater distance from the first surface of the substrate along the axis; and The second portion of the metal overlay is in electrical contact with the second metal path of the top metal layer.

4. The semiconductor die according to claim 3: The top metal layer further accommodates the first metal portion of the high-voltage module; and The first part of the metal cover layer is in electrical contact with the first metal part of the high-voltage module.

5. The semiconductor die of claim 3, wherein the metal shielding portion extends along the axis at a distance from the first surface of the substrate, the distance being greater than the corresponding distance of the top metal layer from the first surface of the substrate.

6. The semiconductor die of claim 1, wherein the first and second portions of the metal overlay and the metal shield are made of one of the following: aluminum, or an alloy comprising aluminum, or an aluminum-copper alloy.

7. The semiconductor die of claim 1, wherein each of the first metal path and the second metal path is made of or includes copper.

8. The semiconductor die of claim 1, wherein the metal shield completely surrounds the metal protective ring.

9. The semiconductor die of claim 1, wherein the first and second portions of the metal overlay and the metal shield have corresponding thicknesses along the axis, between 0.5 µm and 3 µm.

10. A system comprising: The semiconductor die according to claim 1; as well as Other semiconductor dies; The bonding wires connect the additional semiconductor die to a first portion of the semiconductor die.

11. An electronic device, comprising: A semiconductor substrate having a first surface including active components; as well as A solid body extending on a first surface of the semiconductor substrate, the solid body comprising: dielectric layer, A capacitor in a dielectric layer, wherein the capacitor includes a first metal plate at a first height relative to a semiconductor substrate and a second metal plate at a second height relative to the semiconductor substrate that is less than the first height; A metal guard ring enters the dielectric layer, the metal guard ring completely surrounding the capacitor; and A metal capping layer comprising a first portion extending over and in electrical contact with a capacitor; and a second portion electrically insulated from the first portion, extending over and in electrical contact with a metal guard ring; At least one of the active components extends on the first surface of the semiconductor substrate on the opposite side of the metal guard ring relative to the capacitor. The second portion of the metal overlay extends beyond the area occupied by the metal protective ring to cover the active component.

12. The electronic device of claim 11, wherein the solid body further comprises a plurality of metal levels in a dielectric layer, each metal level comprising at least one corresponding first metal path for routing electrical signals and at least one corresponding second metal path for forming a metal guard ring.

13. The electronic device of claim 12, wherein the top metal layer of the plurality of metal layers includes a top first metal path and a top second metal path, wherein the top metal layer is the metal layer furthest from the semiconductor substrate among the plurality of metal layers, and wherein a second portion of the metal overlay is in electrical contact with the top second metal path.

14. The electronic device of claim 13, wherein the top metal layer further accommodates a first metal plate of a capacitor, wherein a first portion of the metal overlay is in electrical contact with a first metal portion of the capacitor.

15. The electronic device of claim 13, wherein the distance between the active component and the second portion of the metal overlay along the vertical direction is greater than the corresponding distance between the active component and the top metal layer along the vertical direction.

16. The electronic device of claim 11, wherein the first and second portions of the metal overlay are aluminum, or an alloy comprising aluminum, or an aluminum-copper alloy.

17. The electronic device of claim 13, wherein each first metal path and each second metal path is made of or comprises copper.

18. The electronic device of claim 11, wherein a second portion of the metal overlay completely surrounds the metal protective ring.

19. The electronic device of claim 11, wherein the first and second portions of the metal overlay have corresponding thicknesses between 0.5 µm and 3 µm.

20. A system comprising: The electronic device according to claim 11; Other electronic components; as well as Bonding wires connect the additional electronic device to the electronic device at a first portion of the metal overlay.

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