Package device and method of forming same

Abstract

The invention relates to a packaging device and a forming method thereof. The forming method of the packaging device comprises the following steps that a packaging body is formed, the packaging body comprises a first main face and a second main face which are oppositely distributed, the packaging body comprises a chip and a main plastic packaging layer for plastic packaging of the chip, and the chip is exposed out of the first main face of the packaging body; forming a supporting assembly on the second main surface of the packaging body; forming a conductive lead-out structure electrically connected with the chip on the first main surface of the packaging body; and the supporting assembly is removed. According to the invention, the warping of the packaging body is improved, and the method is suitable for thin chip and ultra-thin packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a packaged device and a method for forming the same. Background Technology

[0002] As semiconductor devices increasingly move towards thinner, more integrated, and more reliable designs, fan-out packaging has become one of the mainstream packaging technologies due to its advantages such as not requiring traditional ceramic or organic substrates, small package size, excellent electrical performance, and controllable cost.

[0003] One type of fan-out packaging structure further reduces the size of the packaged device by removing the substrate and directly using the molding compound as the packaging substrate, while effectively improving the heat dissipation performance of the packaged device, thus having a wide range of applications in the field of mid-to-high-end semiconductor devices.

[0004] However, due to the lack of substrate support, this structure exhibits warpage after the carrier board is removed via a peeling process. This warpage is influenced by factors such as the silicon content of the chip, chip thickness, and molding compound thickness. During the bumping process following molding compound formation, processes like adhesive application, plasma sputtering, and electroplating all affect stress distribution within the structure. As subsequent processes proceed, stacking multiple semiconductor layers gradually increases the warpage. Large warpage places extremely high demands on production equipment. Conventional wafer handling equipment is only suitable for semiconductor products with small warpage; large warpage structures are prone to wafer handling failures and chip breakage during handling. Furthermore, the wafer cassettes for loading wafers require a slotted design to allow for additional deformation space, increasing cassette manufacturing costs and reducing the single-load capacity. To address these issues, existing technologies typically require dedicated production lines for products without substrate support, making it impossible to share equipment with conventional fan-out packaging products. This leads to reduced semiconductor production efficiency and increased production costs.

[0005] Therefore, how to reduce the warpage of the fan-out packaging structure so that the fan-out packaging technology can be applied to the field of thin chips, and at the same time improve the performance of the fan-out packaging structure, expand the application field of the fan-out packaging technology, is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] This invention provides a packaging device and a method for forming the same, which reduces the warpage of a fan-out packaging structure, thereby enabling the fan-out packaging process to be applied to the field of thin chips. While improving the performance of the fan-out packaging structure, it also expands the application areas of the fan-out packaging process.

[0007] According to some embodiments, the present invention provides a method for forming a packaged device, comprising the following steps: A package is formed, the package including a first main surface and a second main surface that are distributed opposite to each other, and the package including a chip and a main molding layer for molding the chip, and the chip being exposed on the first main surface of the package; A support component is formed on the second main surface of the package; A conductive lead-out structure electrically connected to the chip is formed on the first main surface of the package; Remove the support components.

[0008] In some embodiments, the specific steps for forming the package include: Provide carrier board; The chip is mounted on the carrier board; A main molding layer for encapsulating the chip is formed on the carrier substrate, with the surface of the main molding layer facing the carrier substrate as the first main surface and the surface of the main molding layer facing away from the carrier substrate as the second main surface.

[0009] In some embodiments, the carrier plate is a metal carrier plate.

[0010] In some embodiments, the specific steps of mounting the chip on the carrier board include: The chip is provided, the chip including a functional surface and a back surface that are relatively distributed, and the functional surface of the chip having pads; The chip is mounted on the carrier board with its functional surface facing the carrier board.

[0011] In some embodiments, the thickness of the chip is less than or equal to 500 μm.

[0012] In some embodiments, the specific steps of forming the main molding layer for molding the chip on the carrier substrate include: A main molding compound is formed on the carrier substrate to cover the chip, and the surface of the main molding compound facing away from the carrier substrate is higher than the back surface of the chip.

[0013] In some embodiments, the specific steps of forming a support component on the second main surface of the package include: The support component is formed on the second main surface of the package, and the support component includes an auxiliary molding layer and a support structure embedded in the auxiliary molding layer.

[0014] In some embodiments, the support structure is a support wafer.

[0015] In some embodiments, the supporting wafer is a single-crystal silicon wafer.

[0016] In some embodiments, the specific steps for forming the support component on the second main surface of the package include: The support wafer is mounted on the second main surface of the package; An auxiliary molding layer for molding the supporting wafer is formed on the second main surface of the package.

[0017] In some embodiments, before mounting the support wafer onto the second main surface of the package, the following steps are further included: Provide the supporting wafer; The supporting wafer is thinned to a preset thickness, which is 200 μm to 500 μm.

[0018] In some embodiments, the specific steps of providing the supporting wafer further include: The area of ​​the supporting wafer is adjusted so that the area of ​​the supporting wafer is smaller than the area of ​​the second main surface of the package.

[0019] In some embodiments, the specific steps of mounting the support wafer onto the second main surface of the package include: The support wafer is attached to the second main surface of the package by an adhesive layer, and the projection of the support wafer on the second main surface of the package covers the projection of the chip on the second main surface of the package.

[0020] In some embodiments, the package includes a plurality of chips spaced apart along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer to the second main surface of the package by an adhesive layer, wherein the projection of the support wafer on the second main surface of the package covers the projection of the chips on the second main surface of the package, include: One of the support wafers is attached to the second main surface of the package by an adhesive layer, and the projection of the support wafer on the second main surface of the package continuously covers the projections of multiple chips on the second main surface of the package.

[0021] In some embodiments, the package includes a plurality of chips spaced apart along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer to the second main surface of the package by an adhesive layer, wherein the projection of the support wafer on the second main surface of the package covers the projection of the chips on the second main surface of the package, include: Multiple support wafers are bonded to the second main surface of the package by an adhesive layer, and the projection of each support wafer on the second main surface of the package at least covers the projection of one chip on the second main surface of the package.

[0022] In some embodiments, the specific steps of forming the auxiliary molding layer for molding the supporting wafer on the second main surface of the package include: The supporting wafer is encapsulated using the same material as the main encapsulation layer to form the auxiliary encapsulation layer, which continuously covers the side surface of the supporting wafer, the surface of the supporting wafer facing away from the package, and the second main surface of the package.

[0023] In some embodiments, the thickness of the auxiliary molding layer is less than or equal to the thickness of the main molding layer.

[0024] In some embodiments, the thickness of the auxiliary molding layer covering the surface of the supporting wafer opposite to the package is 100 μm to 150 μm.

[0025] In some embodiments, the specific steps of forming a conductive lead-out structure electrically connected to the chip on the first main surface of the package include: Peel off the carrier plate to expose the first main surface of the package; A conductive lead-out structure electrically connected to the chip is formed on the first main surface of the package.

[0026] In some embodiments, the specific steps of forming a conductive lead-out structure electrically connected to the chip on the first main surface of the package include: A wiring layer is formed on the first main surface of the package, and the wiring layer is electrically connected to the pads on the chip. A plurality of solder balls electrically connected to the wiring layer are formed on the wiring layer, forming the conductive lead structure including the solder balls and the wiring layer.

[0027] In some embodiments, the specific steps for removing the support component include: The supporting wafer and the auxiliary molding layer are removed by a grinding process to expose the second main surface of the package.

[0028] In some embodiments, the specific steps of removing the support wafer and at least a portion of the auxiliary molding layer using a grinding process include: The auxiliary molding layer covering the surface of the support wafer opposite to the package is removed using a first grinding process; The second grinding process is used to remove the support wafer and the remaining auxiliary molding layer.

[0029] In some embodiments, after removing the support wafer and the auxiliary molding layer using a grinding process to expose the second main surface of the package, the following steps are further included: The second main surface of the package is processed using a planarization process.

[0030] In some embodiments, the specific steps for removing the support component include: The auxiliary molding layer covering the surface of the support wafer opposite to the package is removed using a first grinding process; The supporting wafer is removed using a thermal stripping process.

[0031] In some embodiments, the package includes a plurality of chips arranged at intervals along a direction parallel to the first main surface of the package; after removing the support assembly, the package further includes the following steps: The package body and the conductive lead-out structure are cut to form multiple independent packaged devices.

[0032] According to other embodiments, the present invention also provides a packaging device formed using the packaging device forming method described above; the packaging device includes: A package monomer, the package monomer including a chip and a molding layer for molding the chip, the package monomer including a first surface and a second surface that are distributed opposite to each other, the chip being exposed on the first surface of the package monomer; The lead-out unit is located on the first surface of the package unit and is electrically connected to the chip.

[0033] In some embodiments, the thickness of the chip is less than or equal to 500 μm.

[0034] In some embodiments, the molding compound covers the side of the chip and the surface of the chip facing away from the lead-out unit, and the thickness of the molding compound on the surface of the chip facing away from the lead-out unit is 100 μm to 150 μm.

[0035] The packaging device and its forming method provided by this invention form a support component on the second main surface of the package body before forming the conductive lead structure on the first main surface of the package body. On the one hand, the support component enhances the strength of the package body, thereby alleviating or reducing the warpage of the package body after removing the carrier board. On the other hand, by forming the support component to support the package body, the influence of the process of forming the conductive lead structure on the first main surface of the package body on the stress distribution within the package body is reduced, thereby further improving the warpage of the package body. It also helps to enhance the connection strength and stability between the conductive lead structure and the chip. Because this invention reduces the warpage of the final packaged device through the support component, the use of dedicated lines is eliminated during the transfer or transport of the packaged device, thereby reducing the cost of semiconductor manufacturing processes. Furthermore, this invention has no limitation on chip thickness and is applicable to thin chips and ultra-thin packages, thus expanding the application field of fan-out packaging technology.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart of the method for forming a packaged device in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the structure after the chip is mounted on the carrier board in a specific embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after the main plastic sealant layer is formed on the carrier plate in a specific embodiment of the present invention; Figure 4 This is a schematic diagram of a structure after the supporting wafer is mounted on the package body in a specific embodiment of the present invention; Figure 5 This is another structural diagram after the mounting support structure is attached to the package body in a specific embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the auxiliary sealing layer is formed in a specific embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after removing the carrier plate in a specific embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after the conductive lead-out structure is formed in a specific embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after removing the support components in a specific embodiment of the present invention; Figure 10 This is a schematic diagram of the structure after cutting the package and conductive lead-out structure according to a specific embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures 20 carrier boards 21 Adhesive Layer 22 chips 23 pads 30 main sealing layer 40 adhesive layers 41 Support Wafers 60 auxiliary molding layer 80 layers of insulating material 81 conductive interconnect structure 82 dielectric layer 83 lead-out solder balls 110 sealing layer 111 isolation layer Detailed Implementation The specific embodiments of the packaging device and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0040] This specific embodiment provides a method for forming a packaged device. Figure 1 This is a flowchart illustrating the method for forming a packaged device according to a specific embodiment of the present invention. For example... Figure 1 As shown, the method for forming the packaged device includes the following steps: Step S11, forming a package, the package including a first main surface and a second main surface that are relatively distributed, and the package including a chip and a main molding layer for molding the chip, and the chip being exposed on the first main surface of the package; Step S12: A support component is formed on the second main surface of the package; Step S13: A conductive lead-out structure electrically connected to the chip is formed on the first main surface of the package; Step S14: Remove the support component.

[0041] Figure 2 This is a schematic diagram of the structure after the chip is mounted on the carrier board in a specific embodiment of the present invention. Figure 3This is a schematic diagram of the structure after the main molding layer is formed on the carrier plate in a specific embodiment of the present invention. In some embodiments, the specific steps for forming the package include: Provide carrier board 20; The chip 22 is mounted on the carrier board 20, such as... Figure 2 As shown; The main molding layer 30 for molding the chip 22 is formed on the carrier 20, such as... Figure 3 As shown, the surface of the main plastic sealant 30 facing the carrier plate 20 is taken as the first main surface, and the surface of the main plastic sealant 30 facing away from the carrier plate 20 is taken as the second main surface.

[0042] In some embodiments, the carrier plate 20 is a metal carrier plate.

[0043] In some embodiments, the specific steps of mounting the chip 22 onto the carrier board 20 include: The chip 22 is provided, the chip 22 includes a functional surface and a back surface that are distributed opposite to each other, and the functional surface of the chip 22 has pads 23; The chip 22 is mounted on the carrier 20 with its functional surface facing the carrier 20.

[0044] For example, a metal carrier plate is used as a temporary support carrier plate during the formation of the packaged device. The metal carrier plate has advantages such as high flatness, high rigidity, and easy peeling, thereby stably supporting the subsequently formed package and reducing or even avoiding warping and other deformations of the package during the formation process, thereby further improving the performance of the final packaged device. In one example, the material of the metal carrier plate can be copper, copper-zinc alloy, aluminum, or aluminum-magnesium alloy to enhance the support performance of the metal carrier plate while improving its heat dissipation performance, so as to dissipate the heat generated during the subsequent formation of the package. The carrier plate 20 includes a top surface and a bottom surface that are relatively distributed along the first direction D1, and the top surface of the carrier plate 20 is flat. An adhesive material such as epoxy resin, acrylic resin, or silicone resin is uniformly coated on the top surface of the carrier plate 20 to form an adhesive layer 21 covering the top surface of the carrier plate 20.

[0045] One or more chips 22 are provided, each chip 22 including a functional surface and a back surface distributed opposite to each other along the first direction D1, and each chip 22 has at least one pad 23 on its functional surface. The pad 23 is used to transmit external signals to the chip 22 or to output signals from the chip 22 to the outside. In one example, the pad 23 is a metal pad, and the material of the metal pad includes aluminum or copper. Before mounting the chip 22 onto the carrier board 20, the chip 22 is cleaned with any one or a combination of chemical cleaning agent and deionized water to remove particulate contaminants or organic contaminants from the surface of the chip 22, ensuring the cleanliness of the chip 22 surface. Then, the chip 22 is mounted on the adhesive layer 21 with its functional surface facing the carrier board 20, so that the chip 22 is connected to the carrier board 20 through the adhesive layer 21. In one example, there are multiple chips 22, and the multiple chips 22 are arranged at least at intervals along a second direction D2, which is parallel to the functional surfaces of the chips 22, that is, the second direction D2 intersects the first direction D1 perpendicularly. Figure 2 As shown. In another example, a plurality of the chips 22 are arranged in a two-dimensional array along a direction parallel to the top surface of the carrier 20.

[0046] The chip 22 can be a power chip or a radio frequency chip. In one example, multiple chips 22 mounted on the carrier 20 have the same structure and function. In another example, at least two chips 22 mounted on the carrier 20 have different structures to improve the flexibility of the manufacturing process. In this specific embodiment, "multiple" refers to two or more.

[0047] In some embodiments, the thickness of the chip 22 is less than or equal to 500 μm.

[0048] In one example, the thickness of the chip 22 along the first direction D1 is less than or equal to 400 μm, thereby meeting the packaging requirements of thin chips and expanding the application areas of the packaging device formation method and the packaging device itself. The width of the chip 22 is 1 mm to 10 mm.

[0049] In other embodiments, the thickness of the chip 22 along the first direction D1 can also be greater than 500 μm, further expanding the application field of the method for forming the packaged device and the application field of the packaged device to meet different usage requirements.

[0050] In some embodiments, the specific steps of forming the main molding layer 30 for molding the chip 22 on the carrier 20 include: A main molding compound 30 is formed on the carrier 20 to cover the chip 22, and the surface of the main molding compound 30 facing away from the carrier 20 is higher than the back surface of the chip 22.

[0051] For example, after mounting the chip 22 onto the carrier board 20, the chip 22 is molded using a molding compound, forming a main molding layer 30 on the adhesive layer 21 that continuously molds multiple chips. In one example, the material of the main molding layer 30 is epoxy resin molding compound to meet the requirements of low stress, low warpage, and high flowability in the molding process. By adjusting the parameters of the molding process, the formed main molding layer 30 can continuously cover the side and back of each chip 22, and the main molding layer 30 can fill the gaps between adjacent chips 22, thereby achieving five-sided coverage of the chip 22. That is, the main molding layer 30 achieves over-molding of the chip 22, which fully protects each chip 22, prevents the chip 22 from being affected by moisture, dust, etc. in the external environment, and improves the mechanical strength and reliability of the chip 22.

[0052] In some embodiments, the thickness of the main molding compound 30 covering the back side of the chip 22 (e.g., the thickness of the main molding compound 30 along the first direction D1) is 100μm to 150μm. This ensures sufficient coverage of the chip 22 while avoiding an increase in the overall thickness of the package. It also prevents increased packaging costs and packaging time due to excessive thickness of the main molding compound 30. In one example, the diameter of the main molding compound 30 matches the size of the subsequent support wafer. For example, when the subsequent support wafer is 12 inches, the diameter of the main molding compound 30 is 300mm; when the subsequent support wafer is 8 inches, the diameter of the main molding compound 30 is 200mm.

[0053] Figure 4 This is a schematic diagram of a structure after the supporting wafer is mounted on the package body in a specific embodiment of the present invention. Figure 6 This is a schematic diagram of the structure after the auxiliary molding layer is formed in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a support component on the second main surface of the package include: The support component is formed on the second main surface of the package, and the support component includes an auxiliary molding layer and a support structure embedded in the auxiliary molding layer.

[0054] Specifically, after forming the package comprising the chip 22 and the main molding layer 30 encapsulating the chip 22, a support assembly comprising the support structure and the auxiliary molding layer encapsulating the support structure is formed on the second main surface of the package (i.e., the surface of the main molding layer 30 facing away from the carrier 20). On the one hand, the support assembly enhances the strength of the package, thereby alleviating or reducing the warpage of the package after removing the carrier 20. On the other hand, by forming the support assembly to support the package, the influence of the process of forming the conductive lead structure on the first main surface of the package on the stress distribution within the package is reduced, thereby further improving the warpage of the package and also helping to enhance the connection strength and connection stability between the conductive lead structure and the chip. Since this specific embodiment reduces the warpage of the final packaged device through the support assembly, no dedicated line is needed during the transfer or transport of the packaged device, thereby reducing the cost of the semiconductor manufacturing process. By incorporating the support structure and the auxiliary molding layer encapsulating the support structure within the support assembly, on the one hand, the auxiliary molding layer protects and positions the support structure, preventing it from shifting or detaching during subsequent processes (e.g., detachment due to the use of organic etchants in subsequent operations) or being affected by the external environment, thus hindering the suppression of package warpage. On the other hand, both the auxiliary molding layer and the main molding layer 30 are made of molding materials, and both can be formed using molding processes. This reduces the differences in materials and processes between the support assembly and the package, avoiding defects caused by excessive differences in materials and processes, and further improving the yield and long-term reliability of the final packaged product.

[0055] In some embodiments, the support structure is a support wafer 41.

[0056] In some embodiments, the supporting wafer is a single-crystal silicon wafer.

[0057] In some embodiments, the specific steps for forming the support component on the second main surface of the package include: The support wafer 41 is mounted on the second main surface of the package, as follows: Figure 4 As shown; An auxiliary molding layer 60 for molding the supporting wafer 41 is formed on the second main surface of the package, such as... Figure 6 As shown.

[0058] For example, the supporting wafer 41 is used as the supporting structure and is mounted on the second main surface of the package. In one example, the supporting wafer 41 is a monocrystalline silicon wafer. Since the material of the monocrystalline silicon wafer is similar to that of the chip 22 (for example, the main material of both the monocrystalline silicon wafer and the chip is monocrystalline silicon), the coefficients of thermal expansion of the monocrystalline silicon wafer and the chip 22 are the same or similar. This ensures that the thermal expansion and contraction of the monocrystalline silicon wafer and the chip 22 are the same or similar in subsequent processes, avoiding additional stress caused by differences in the coefficients of thermal expansion. At the same time, the rigidity of the monocrystalline silicon wafer is significantly higher than that of the molding compound, thereby offsetting multiple stresses generated in subsequent processes, such as the stress generated during the formation of the auxiliary molding layer 60 and the stress generated during the formation of the conductive lead-out structure. In addition, the monocrystalline silicon wafer can form a high-strength bond with the molding compound without chemical reaction, thereby avoiding delamination or detachment of the supporting component in subsequent processes.

[0059] This specific embodiment incorporates a monocrystalline silicon wafer and an auxiliary molding layer 60 for encapsulating the monocrystalline silicon wafer within the support assembly. Since the rigidity of the monocrystalline silicon wafer is significantly higher than that of the molding compound, it not only offsets multiple stresses generated during subsequent processes, such as stresses generated during the formation of the auxiliary molding layer 60 and the formation of the conductive lead-out structure, but also further enhances the support performance of the support assembly for the package, thereby improving the warpage of the package. Furthermore, both the auxiliary molding layer and the main molding layer 30 are constructed from molding materials and can be formed using molding processes. The material of the monocrystalline silicon wafer is similar to that of the chip 22 (e.g., both the monocrystalline silicon wafer and the chip are primarily made of monocrystalline silicon), thereby reducing the differences in materials and processes between the support assembly and the package. This avoids defects caused by excessive differences in materials and processes between the support assembly and the package, further improving the yield and long-term reliability of the final packaged product.

[0060] In some embodiments, before mounting the support wafer 41 onto the second main surface of the package, the following steps are further included: Provide the support wafer 41; The supporting wafer 41 is thinned to a preset thickness, which is 200 μm to 500 μm.

[0061] For example, the support wafer 41 can be a P-type or N-type monocrystalline silicon wafer. The monocrystalline silicon wafer is thinned using physical grinding (e.g., grinding with a grinding wheel) or chemical mechanical polishing processes to reduce its thickness (e.g., the thickness of the monocrystalline silicon wafer along the first direction D1) to 200μm~500μm. This avoids the increased difficulty and time required for subsequent removal of the support component due to excessive thickness of the monocrystalline silicon wafer, and also prevents uneven distribution of thermal stress within the package and the support component caused by excessive thickness. Furthermore, it is compatible with ultra-thin packaging processes. Simultaneously, the thinning process of the monocrystalline silicon wafer (e.g., grinding with a grinding wheel) or chemical mechanical polishing also reduces the surface roughness of the support wafer 41, ensuring a tight, bubble-free, and void-free fit between the support wafer 41 and the package.

[0062] In some embodiments, the specific steps of providing the support wafer 41 further include: The area of ​​the supporting wafer 41 is adjusted so that the area of ​​the supporting wafer 41 is smaller than the area of ​​the second main surface of the package.

[0063] Specifically, by reasonably selecting or designing the support wafer 41, the area of ​​the support wafer 41 is made smaller than the area of ​​the second main surface of the package. This allows a gap (e.g., a gap of 10mm to 20mm) to be maintained between the edge of the support wafer 41 and the edge of the main molding compound 30, reserving space for the subsequent formation of the auxiliary molding compound 60. This ensures a high-strength bond between the auxiliary molding compound 60 and the main molding compound 30, avoiding delamination between the support component and the package in subsequent processes. In one example, the support wafer is a 12-inch wafer (diameter 250mm to 280mm), and the main molding compound 30 has a diameter of 300mm. In another example, the support wafer is an 8-inch wafer (diameter 150mm to 180mm), and the main molding compound 30 has a diameter of 200mm.

[0064] In some embodiments, the specific steps of mounting the support wafer 41 onto the second main surface of the package include: The support wafer 41 is attached to the second main surface of the package by the adhesive layer 40, and the projection of the support wafer 41 on the second main surface of the package covers the projection of the chip 22 on the second main surface of the package.

[0065] Specifically, by making the projection of the supporting wafer 41 on the second main surface of the package cover the projection of the chip 22 on the second main surface of the package, the stress in the package can be evenly distributed, avoiding cracking caused by excessive local stress on the chip 22, thereby better suppressing the warping of the package.

[0066] In some embodiments, the package includes a plurality of chips 22 spaced apart along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer 41 to the second main surface of the package by an adhesive layer 40, and having the projection of the support wafer 41 on the second main surface of the package cover the projection of the chips 22 on the second main surface of the package, include: A support wafer 41 is attached to the second main surface of the package via an adhesive layer 40, and the projection of the support wafer 41 on the second main surface of the package continuously covers the projections of multiple chips 22 on the second main surface of the package.

[0067] For example, a die-attach film (DAF) is bonded to the second main surface of the package using a thermoforming process to form the adhesive layer 40. Next, a relatively large support wafer 41 is aligned and bonded to the surface of the adhesive layer 40 facing away from the package, such as... Figure 4 As shown. By having the projection of one of the support wafers 41 onto the second main surface of the package continuously cover the projections of multiple chips 22 onto the second main surface of the package, the strength of multiple chips 22 within the package can be simultaneously enhanced by the same support wafer 41. This reduces the warpage of the package and further simplifies the manufacturing process of the packaged device (e.g., eliminating the need to separately fabricate multiple relatively small support wafers 41 and to perform multiple mounting processes of multiple support wafers 41).

[0068] In other embodiments, the package includes a plurality of chips 22 spaced apart along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer 41 to the second main surface of the package by an adhesive layer 40, and having the projection of the support wafer 41 on the second main surface of the package cover the projection of the chips 22 on the second main surface of the package, include: Multiple support wafers 41 are attached to the second main surface of the package via an adhesive layer 40, and the projection of each support wafer 41 on the second main surface of the package at least covers the projection of one chip 22 on the second main surface of the package.

[0069] For example, a die-attach film (DAF) is bonded to the second main surface of the package using a thermoforming process, forming multiple adhesive layers 40 corresponding one-to-one with the multiple chips 22 on the second main surface of the package. Next, multiple support wafers 41 are bonded one-to-one with the multiple adhesive layers 40, and the projection of each support wafer 41 on the second main surface of the package covers the projection of its corresponding chip 22 on the second main surface of the package, such as... Figure 5 As shown. By mounting multiple support wafers 41, each corresponding to one of the multiple chips 22 within the package, on the second main surface of the package, not only is the overall strength of the package enhanced, but the warpage of the package can also be adjusted in different regions, improving the flexibility of warpage adjustment and helping to further reduce the warpage of the packaged device. For example, when the multiple chips 22 have different structures or sizes, a matching support wafer 41 can be selected according to the structure and size of each chip 22 (a larger support wafer 41 is selected for a relatively larger chip 22, and a smaller support wafer 41 is selected for a relatively smaller chip 22).

[0070] In some other embodiments, the package includes a plurality of chips 22 spaced apart along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer 41 to the second main surface of the package by an adhesive layer 40, and having the projection of the support wafer 41 on the second main surface of the package cover the projection of the chips 22 on the second main surface of the package, include: Multiple support wafers 41 are attached to the second main surface of the package via an adhesive layer 40, and the projections of a portion of the support wafers 41 on the second main surface of the package continuously cover the projections of multiple chips 22 on the second main surface of the package, while the projections of another portion of the support wafers 41 on the second main surface of the package correspond one-to-one with the projections of multiple chips 22 on the second main surface of the package.

[0071] For example, a DAF (Die Attach Film) is bonded to the second main surface of the package using a thermoforming process to form multiple adhesive layers 40 on the second main surface of the package. Next, multiple support wafers 41 are bonded one-to-one to the multiple adhesive layers 40, with a portion of the projections of the support wafers 41 on the second main surface of the package continuously covering the projections of multiple chips 22 on the second main surface of the package, and another portion of the projections of the support wafers 41 on the second main surface of the package correspondingly covering the projections of multiple chips 22 on the second main surface of the package. By bonding multiple support wafers 41 to the second main surface of the package, and ensuring that at least two support wafers 41 cover different numbers of chips 22, not only is the overall strength of the package enhanced, but the warpage of the package can also be adjusted in different areas, improving the flexibility of package warpage adjustment and helping to further reduce the warpage of the packaged device.

[0072] In some embodiments, the specific steps of forming the auxiliary molding layer 60 for molding the supporting wafer 41 on the second main surface of the package include: The supporting wafer 41 is encapsulated using the same material as the main encapsulation layer 30, forming the auxiliary encapsulation layer 60 that continuously covers the side surface of the supporting wafer 41, the surface of the supporting wafer 41 facing away from the package, and the second main surface of the package.

[0073] For example, after mounting the support wafer 41 onto the second main surface of the package, the support wafer 41 is encapsulated using the same encapsulation material and the same encapsulation process as the main encapsulation layer 30, forming an auxiliary encapsulation layer 60 that continuously covers the side surface of the support wafer 41, the surface of the support wafer 41 facing away from the package, and the second main surface of the package. This makes the coefficient of thermal expansion and mechanical properties of the auxiliary encapsulation layer 60 consistent with those of the main encapsulation layer 30, thereby reducing the stress at the interface between the auxiliary encapsulation layer 60 and the main encapsulation layer 30. In one example, the sidewall of the auxiliary encapsulation layer 60 (e.g., the sidewall of the auxiliary encapsulation layer 60 along the second direction D2) is flush with the sidewall of the main encapsulation layer 30 (e.g., the sidewall of the main encapsulation layer 30 along the second direction D2). By using the same molding material and molding process as the main molding layer 30 to form the auxiliary molding layer 60, no new process equipment or new raw materials are required, which helps to further reduce the manufacturing cost of the packaged device.

[0074] In some embodiments, the molding process parameters (e.g., molding temperature, molding time, molding pressure, etc.) for forming the auxiliary molding layer 60 are the same as those for forming the main molding layer 30, thereby avoiding differences in the shrinkage degree of the auxiliary molding layer 60 and the main molding layer 30 in subsequent processes due to differences in molding process parameters, and ensuring that the auxiliary molding layer 60 and the main molding layer 30 always maintain a stable connection.

[0075] This specific embodiment protects the support wafer 41 by sandwiching it between the main molding compound 30 and the auxiliary molding compound 60, isolating it from the external environment. This prevents the adhesive layer 40, used to connect the support wafer 41 to the package, from being corroded by chemical reagents during subsequent processes, thus avoiding the problem of the support wafer 41 detaching from the package during later operations. Furthermore, sandwiching the support wafer 41 between the main molding compound 30 and the auxiliary molding compound 60 also prevents it from being damaged by subsequent processes. After the support wafer 41 is removed non-destructively, it can be recycled, further reducing semiconductor manufacturing costs. Furthermore, by sandwiching the support wafer 41 between the main molding compound 30 and the auxiliary molding compound 60, the relative positional relationship between the support wafer 41 and the chip 22 can be stably defined, avoiding the impact on the stress distribution within the package due to the displacement of the position of the support wafer 41 during subsequent operations.

[0076] In one example, the supporting wafer is a 12-inch wafer (250mm~280mm in diameter), and the auxiliary molding layer 60 has a diameter of 300mm. In another example, the supporting wafer is an 8-inch wafer (150mm~180mm in diameter), and the auxiliary molding layer 60 has a diameter of 200mm.

[0077] In some embodiments, the thickness of the auxiliary molding layer 60 is less than or equal to the thickness of the main molding layer 30.

[0078] Specifically, by making the thickness of the auxiliary molding layer 60 less than or equal to the thickness of the main molding layer 30, the overall thickness of the support assembly is reduced while ensuring that the auxiliary molding layer 60 covers the support wafer 41. This further simplifies the subsequent process of removing the support assembly and also makes it compatible with ultra-thin packaging processes.

[0079] In some embodiments, the thickness of the auxiliary molding layer 60 covering the surface of the supporting wafer opposite to the package is 100 μm to 150 μm.

[0080] In one example, the sum of the thickness of the chip 22, the thickness of the main molding compound 30 covering the back of the chip 22, the thickness of the support wafer 41, and the thickness of the surface of the support wafer 41 facing away from the package is less than 1000 μm, thereby enabling the overall manufacturing process of the package structure to meet the requirements of ultra-thin packaging.

[0081] Figure 7 This is a schematic diagram of the structure after removing the carrier plate in a specific embodiment of the present invention. Figure 8 This is a schematic diagram of the structure after the conductive lead-out structure is formed in a specific embodiment of the present invention. In some embodiments, the specific steps of forming a conductive lead-out structure electrically connected to the chip 22 on the first main surface of the package include: Peel off the carrier plate 20 to expose the first main surface of the package, as shown below. Figure 7 As shown; A conductive lead-out structure electrically connected to the chip 22 is formed on the first main surface of the package, such as... Figure 8 As shown.

[0082] Specifically, after forming the support assembly that provides rigid support to the package on the second main surface of the package, the carrier plate 20 can be peeled off using a thermal peeling process to expose the first main surface of the package. Then, the package is flipped over to obtain the desired result. Figure 7 The structure is shown. Because the support component is formed on the second main surface of the package before the carrier plate 20 is peeled off, the impact of the process of peeling off the carrier plate 20 on the warpage of the package can be reduced. For example, after peeling off the carrier plate 20, the overall warpage of the package is less than or equal to 150 μm, thereby ensuring that the conductive lead structure that is stably connected to the package can be formed on the first main surface of the package.

[0083] In some embodiments, the specific steps of forming a conductive lead-out structure electrically connected to the chip 22 on the first main surface of the package include: A wiring layer is formed on the first main surface of the package, and the wiring layer is electrically connected to the pad 23 on the chip 22; A plurality of lead-out solder balls 83 electrically connected to the wiring layer are formed on the wiring layer, forming the conductive lead-out structure including the lead-out solder balls 83 and the wiring layer.

[0084] For example, after peeling off the carrier 20, the package is flipped so that the first main surface of the package faces upward. Next, an isolation material layer 80 is formed covering the first main surface of the package. The material of the isolation material layer 80 is an insulating material. The isolation material layer 80 is used to protect the functional surfaces of the main molding compound 30 and the chip 22, preventing damage to the functional surfaces of the main molding compound 30 and the chip 22 by subsequent processes. Then, the isolation material layer 80 is etched using an etching process to form openings in the isolation material layer that expose the pads 23 on the chip 22. Next, a wiring layer is formed on the surface of the isolation material layer 80 facing away from the package. The wiring layer includes a dielectric layer 82 and a conductive interconnect structure 81, and the conductive interconnect structure 81 penetrates the dielectric layer 82 along the first direction D1. The conductive interconnect structure 81 includes a top end and a bottom end that are distributed opposite to each other along the first direction D1. The bottom end of the conductive interconnect structure 81 passes through the opening in the insulating material layer and is electrically connected to the pad 23 on the chip 22. The top end of the conductive interconnect structure 81 protrudes from the surface of the dielectric layer 82 away from the package. In one example, the material of the conductive interconnect structure 81 is metallic copper. Subsequently, the lead-out solder balls 83 are formed on the top end of the conductive interconnect structure 81 by an electroplating process.

[0085] Because the support component stably supports the package during the formation of the conductive interconnect structure, the impact of the process of forming the wiring layer and the lead-out solder balls 83 on the warpage of the package can be reduced. For example, the warpage of the package can be less than or equal to 150 μm after the formation of the conductive lead-out structure.

[0086] Figure 9 This is a schematic diagram of the structure after removing the support component in a specific embodiment of the present invention. In some embodiments, the specific steps for removing the support component include: The supporting wafer 41 and the auxiliary molding layer 60 are removed using a grinding process, exposing the second main surface of the package, such as... Figure 9 As shown.

[0087] In some embodiments, the specific steps of removing the support wafer 41 and at least a portion of the auxiliary molding layer 60 using a grinding process include: The auxiliary molding layer 60 covering the surface of the support wafer 41 opposite to the package is removed by a first grinding process; The second grinding process is used to remove the support wafer 41 and the remaining auxiliary molding layer 60.

[0088] For example, firstly, using the supporting wafer 41 as a polishing stop layer, the auxiliary molding compound layer 60 covering the surface of the supporting wafer 41 facing away from the package is removed by a chemical mechanical polishing (CMP) or physical polishing (PMP) process, exposing the surface of the supporting wafer 41 facing away from the package. Next, a second polishing process is used to remove the supporting wafer 41 and the remaining auxiliary molding compound layer 60, exposing the second main surface of the package, such as... Figure 9 As shown. The support wafer 41 and all of the auxiliary molding layer 60 are removed through two polishing processes, which makes it easier to control the polishing endpoint and avoid over-polishing, thereby avoiding damage to the main molding layer 30 and the chip 22.

[0089] In some embodiments, after removing the support wafer 41 and the auxiliary molding layer 60 using a grinding process to expose the second main surface of the package, the following steps are further included: The second main surface of the package is processed using a planarization process.

[0090] For example, after removing the support component, the second main surface of the package can be planarized using chemical mechanical polishing or chemical micro-etching processes to reduce the roughness of the second main surface of the package, so as to meet the flatness requirements of the second main surface of the package in subsequent processes.

[0091] In other embodiments, the specific steps of removing the support wafer 41 and at least a portion of the auxiliary molding layer 60 using a grinding process include: The supporting wafer 41 and the auxiliary molding layer 60 are removed simultaneously using a single grinding process.

[0092] For example, to improve the removal efficiency of the support component, a single polishing process can be used to remove both the support wafer 41 and the auxiliary molding compound 60. The polishing process for simultaneously removing the support wafer 41 and the auxiliary molding compound 60 can be a physical polishing process (e.g., diamond wheel polishing) or a chemical mechanical polishing process. During the polishing process, to avoid damage to the chip 22 and the main molding compound 30, the thickness (e.g., the total thickness of the package and the support component) needs to be monitored in real time to ensure that the support component is completely removed without removing the main molding compound 30.

[0093] In some other embodiments, the specific steps for removing the support component include: The auxiliary molding layer 60 covering the surface of the support wafer 41 opposite to the package is removed by a first grinding process; The supporting wafer 41 is removed using a thermal stripping process.

[0094] For example, to achieve thermal peeling of the support wafer 41, the adhesive layer 40 can be made to cover the entire second main surface of the package during the mounting process of the support wafer 41. After the auxiliary molding compound 60 covering the surface of the support wafer 41 facing away from the package is removed by the first polishing process (e.g., physical polishing or chemical mechanical polishing), the support wafer 41 or the support wafer 41 and the remaining auxiliary molding compound 60 can be peeled off using a thermal peeling process. Since the support wafer 41 is separated from the package through a thermal peeling process, it will not be damaged, thus enabling the support wafer 41 to be reused, which helps to further reduce the cost of semiconductor manufacturing processes.

[0095] Since the support component described in this embodiment is removed through a grinding process or a combination of grinding and thermal stripping after the conductive lead structure is formed, the support component is not present in the final packaged device, thus not affecting the performance (e.g., electrical and heat dissipation performance) of the packaged device. Furthermore, the equipment for mounting the support wafer 41, the equipment for encapsulating the support wafer 41, and the equipment for grinding to remove the support component in this embodiment are all based on existing semiconductor packaging equipment, requiring no additional process equipment. This makes the method for forming the packaged device provided in this embodiment easy to promote and mass-produce.

[0096] Figure 10 This is a schematic diagram of the structure after cutting the package and conductive lead-out structure according to a specific embodiment of the present invention. In some embodiments, the package includes a plurality of chips arranged at intervals along a direction parallel to the first main surface of the package; after removing the support component, the following steps are also included: Cut the package body and the conductive lead structure to form multiple independent packaged devices, see [link to documentation]. Figure 10 .

[0097] For example, after removing the support components, the package and the conductive lead-out structure can be cut with a dicing tool to form multiple independent packaged devices. In one example, the dicing tool can be a diamond blade. The package is divided into multiple independent package units and the conductive lead-out structure is divided into multiple independent lead-out units by the cutting process, so that each packaged device includes one package unit and a lead-out unit electrically connected to the package unit. Each package unit includes the chip 22 and a molding compound 110 encapsulating the chip 22 (the dicing tool divides the main molding compound 30 into multiple independent molding compound layers 110). The package unit includes a first surface and a second surface that are relatively distributed, and the chip 22 is exposed on the first surface of the package unit. The lead-out unit is located on the first surface of the package unit, and the lead-out unit includes wiring units and multiple lead-out solder balls 83 located on the wiring structure (the dicing tool divides the wiring layer into multiple independent wiring structures) and located on and electrically connected to the wiring structure.

[0098] This specific embodiment also provides a packaging device, the structural schematic diagram of which is shown below. Figure 10 The packaged device provided in this specific embodiment is formed using the packaged device forming method described above. See [link to documentation]. Figures 1-10 .like Figures 1-10 As shown, the packaging device includes: The packaged unit includes a chip 22 and a molding layer 110 for molding the chip 22. The packaged unit includes a first surface and a second surface that are distributed opposite to each other. The chip 22 is exposed on the first surface of the packaged unit. The lead-out unit is located on the first surface of the package unit and is electrically connected to the chip 22.

[0099] Specifically, the packaging device includes the packaging unit and the lead-out unit located on the first surface of the packaging unit and electrically connected to the packaging unit. The lead-out unit is used to transmit external control signals to the chip 22 within the packaging unit or to lead the chip 22 out to the outside. The packaging unit includes the chip 22 and a molding compound 110 covering the chip 22 on all five sides. In one example, the molding compound 110 is made of epoxy resin. The chip 22 includes a functional surface and a back surface distributed opposite to each other along a first direction D1, and the functional surface of the chip 22 has at least one pad 23. In one example, the pad 23 is a metal pad, and the material of the metal pad includes aluminum or copper. The functional surface of the chip 22 faces the lead-out unit. The lead-out unit includes an isolation layer 111 covering the first surface of the packaging unit, a wiring structure located on the isolation layer 111, and lead-out solder balls 83 located on the wiring structure. The isolation layer 111 is made of an insulating material. The wiring structure includes a dielectric layer 82 and a conductive interconnect structure 81 penetrating the dielectric layer 82. The conductive interconnect structure 81 includes a top end and a bottom end that are relatively distributed along the first direction D1. The bottom end of the conductive interconnect structure 81 penetrates the isolation layer 111 and is electrically connected to the pad 23 on the chip 22. The top end of the conductive interconnect structure 81 protrudes from the surface of the dielectric layer 82 and is electrically connected to the lead-out solder ball 83. The chip 22 can be a power chip or an radio frequency chip.

[0100] In some embodiments, the thickness of the chip 22 is less than or equal to 500 μm.

[0101] In one example, the thickness of the chip 22 along the first direction D1 is less than or equal to 400 μm, thereby meeting the packaging requirements of thin chips and expanding the application areas of the packaging device formation method and the packaging device itself. The width of the chip 22 is 1 mm to 10 mm.

[0102] In other embodiments, the thickness of the chip 22 along the first direction D1 can also be greater than 500 μm, further expanding the application field of the method for forming the packaged device and the application field of the packaged device to meet different usage requirements.

[0103] In some embodiments, the molding compound 110 covers the side surface of the chip 22 and the surface of the chip 22 facing away from the lead-out unit, and the thickness of the molding compound 110 on the surface of the chip 22 facing away from the lead-out unit is 100μm to 150μm.

[0104] In one example, the molding compound 110 is made of epoxy resin molding compound. The molding compound 110 continuously covers the side and back of the chip 22, thereby achieving five-sided coverage of the chip 22. That is, the molding compound 110 provides overmolding over the chip 22, which fully protects each chip 22 from the intrusion of moisture, dust, etc. in the external environment, while improving the mechanical strength and reliability of the chip 22.

[0105] The packaging device and its formation method provided in this specific embodiment form a support component on the second main surface of the package body before forming the conductive lead structure on the first main surface of the package body. On the one hand, the support component enhances the strength of the package body, thereby alleviating or reducing the warpage of the package body after removing the carrier board. On the other hand, by forming the support component to support the package body, the influence of the process of forming the conductive lead structure on the first main surface of the package body on the stress distribution within the package body is reduced, thereby further improving the warpage of the package body. It also helps to enhance the connection strength and stability between the conductive lead structure and the chip. Since this specific embodiment reduces the warpage of the final packaged device through the support component, no dedicated line is needed during the transfer or transport of the packaged device, thereby reducing the cost of semiconductor manufacturing processes. Furthermore, this specific embodiment has no limitation on chip thickness, and is applicable to thin chips and ultra-thin packages, thus expanding the application field of the technology.

[0106] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0107] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0108] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a packaged device, characterized in that, Includes the following steps: A package is formed, the package including a first main surface and a second main surface that are distributed opposite to each other, and the package including a chip and a main molding layer for molding the chip, and the chip being exposed on the first main surface of the package; A support component is formed on the second main surface of the package; A conductive lead-out structure electrically connected to the chip is formed on the first main surface of the package; Remove the support components.

2. The method for forming a packaged device according to claim 1, characterized in that, The specific steps for forming the package include: Provide carrier board; The chip is mounted on the carrier board; A main molding layer for encapsulating the chip is formed on the carrier substrate, with the surface of the main molding layer facing the carrier substrate as the first main surface and the surface of the main molding layer facing away from the carrier substrate as the second main surface.

3. The method for forming a packaged device according to claim 2, characterized in that, The carrier plate is a metal carrier plate.

4. The method for forming a packaged device according to claim 2, characterized in that, The specific steps for mounting the chip on the carrier board include: The chip is provided, the chip including a functional surface and a back surface that are relatively distributed, and the functional surface of the chip having pads; The chip is mounted on the carrier board with its functional surface facing the carrier board.

5. The method for forming a packaged device according to claim 1, characterized in that, The thickness of the chip is less than or equal to 500 μm.

6. The method for forming a packaged device according to claim 4, characterized in that, The specific steps for forming the main molding layer for molding the chip on the carrier substrate include: A main molding compound is formed on the carrier substrate to cover the chip, and the surface of the main molding compound facing away from the carrier substrate is higher than the back surface of the chip.

7. The method for forming a packaged device according to claim 1, characterized in that, The specific steps for forming the support component on the second main surface of the package include: The support component is formed on the second main surface of the package, and the support component includes an auxiliary molding layer and a support structure embedded in the auxiliary molding layer.

8. The method for forming a packaged device according to claim 7, characterized in that, The support structure is a support wafer.

9. The method for forming a packaged device according to claim 8, characterized in that, The supporting wafer is a monocrystalline silicon wafer.

10. The method for forming a packaged device according to claim 8, characterized in that, The specific steps for forming the support component on the second main surface of the package include: The support wafer is mounted on the second main surface of the package; An auxiliary molding layer for molding the supporting wafer is formed on the second main surface of the package.

11. The method for forming a packaged device according to claim 10, characterized in that, Before mounting the support wafer onto the second main surface of the package, the following steps are also included: Provide the supporting wafer; The supporting wafer is thinned to a preset thickness, which is 200 μm to 500 μm.

12. The method for forming a packaged device according to claim 11, characterized in that, The specific steps for providing the support wafer also include: The area of ​​the supporting wafer is adjusted so that the area of ​​the supporting wafer is smaller than the area of ​​the second main surface of the package.

13. The method for forming a packaged device according to claim 10, characterized in that, The specific steps for mounting the support wafer onto the second main surface of the package include: The support wafer is attached to the second main surface of the package by an adhesive layer, and the projection of the support wafer on the second main surface of the package covers the projection of the chip on the second main surface of the package.

14. The method for forming a packaged device according to claim 13, characterized in that, The package includes a plurality of chips arranged at intervals along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer to the second main surface of the package through an adhesive layer, wherein the projection of the support wafer on the second main surface of the package covers the projection of the chips on the second main surface of the package, include: A support wafer is attached to the second main surface of the package by an adhesive layer, and the projection of the support wafer on the second main surface of the package continuously covers the projections of multiple chips on the second main surface of the package.

15. The method for forming a packaged device according to claim 13, characterized in that, The package includes a plurality of chips arranged at intervals along a direction parallel to the first main surface of the package; the specific steps of attaching the support wafer to the second main surface of the package through an adhesive layer, wherein the projection of the support wafer on the second main surface of the package covers the projection of the chips on the second main surface of the package, include: Multiple support wafers are bonded to the second main surface of the package by an adhesive layer, and the projection of each support wafer on the second main surface of the package at least covers the projection of one chip on the second main surface of the package.

16. The method for forming a packaged device according to claim 10, characterized in that, The specific steps for forming the auxiliary molding layer for molding the supporting wafer on the second main surface of the package include: The supporting wafer is encapsulated using the same material as the main encapsulation layer to form the auxiliary encapsulation layer, which continuously covers the side surface of the supporting wafer, the surface of the supporting wafer facing away from the package, and the second main surface of the package.

17. The method for forming a packaged device according to claim 16, characterized in that, The thickness of the auxiliary molding layer is less than or equal to the thickness of the main molding layer.

18. The method for forming a packaged device according to claim 17, characterized in that, The thickness of the auxiliary molding layer covering the surface of the supporting wafer opposite to the package is 100 μm to 150 μm.

19. The method for forming a packaged device according to claim 4, characterized in that, The specific steps for forming a conductive lead-out structure electrically connected to the chip on the first main surface of the package include: Peel off the carrier plate to expose the first main surface of the package; A conductive lead-out structure electrically connected to the chip is formed on the first main surface of the package.

20. The method for forming a packaged device according to claim 19, characterized in that, The specific steps for forming a conductive lead-out structure electrically connected to the chip on the first main surface of the package include: A wiring layer is formed on the first main surface of the package, and the wiring layer is electrically connected to the pads on the chip. A plurality of solder balls electrically connected to the wiring layer are formed on the wiring layer, forming the conductive lead structure including the solder balls and the wiring layer.

21. The method for forming a packaged device according to claim 8, characterized in that, The specific steps for removing the support components include: The supporting wafer and the auxiliary molding layer are removed by a grinding process to expose the second main surface of the package.

22. The method for forming a packaged device according to claim 21, characterized in that, The specific steps for removing the support wafer and at least a portion of the auxiliary molding layer using a grinding process include: The auxiliary molding layer covering the surface of the support wafer opposite to the package is removed using a first grinding process; The second grinding process is used to remove the support wafer and the remaining auxiliary molding layer.

23. The method for forming a packaged device according to claim 21, characterized in that, After removing the supporting wafer and the auxiliary molding layer using a grinding process to expose the second main surface of the package, the process further includes the following steps: The second main surface of the package is processed using a planarization process.

24. The method for forming a packaged device according to claim 8, characterized in that, The specific steps for removing the support components include: The auxiliary molding layer covering the surface of the support wafer opposite to the package is removed using a first grinding process; The supporting wafer is removed using a thermal stripping process.

25. The method for forming a packaged device according to claim 1, characterized in that, The package includes a plurality of chips arranged at intervals along a direction parallel to the first main surface of the package; after removing the support assembly, the package further includes the following steps: The package body and the conductive lead-out structure are cut to form multiple independent packaged devices.

26. A packaged device, characterized in that, The packaged device is formed using the method for forming a packaged device as described in claim 1; the packaged device comprises: A package monomer, the package monomer including a chip and a molding layer for molding the chip, the package monomer including a first surface and a second surface that are distributed opposite to each other, the chip being exposed on the first surface of the package monomer; The lead-out unit is located on the first surface of the package unit and is electrically connected to the chip.

27. The packaged device according to claim 26, characterized in that, The thickness of the chip is less than or equal to 500 μm.

28. The packaged device according to claim 26, characterized in that, The molding compound covers the side of the chip and the surface of the chip facing away from the lead-out unit, and the thickness of the molding compound on the surface of the chip facing away from the lead-out unit is 100μm to 150μm.

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