Package including bridge between metallization portions

Abstract

A package includes: a first metallization portion; a first integrated device, the first integrated device being coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer such that the first integrated device, the bridge, and the encapsulation layer are between the first metallization portion and the second metallization portion; and a second integrated device coupled to the second metallization portion, where the second integrated device at least partially vertically overlaps the bridge.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Non-Provisional Application Serial No. 18 / 470,344, filed September 19, 2023, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] Various features involve packages with metallized portions and integrated devices. Background Technology

[0004] A package may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. There has always been a need to provide packages with better performance and to reduce the overall size of the packages. Summary of the Invention

[0005] Various features involve packages with metallized portions and integrated devices.

[0006] One example provides a package including a first metallization portion including at least one first dielectric layer; and a first plurality of metallized interconnects; a first integrated device coupled to the first metallization portion; a bridging member coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; and a second metallization portion coupled to the bridging member and the encapsulation layer such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: at least one second dielectric layer; a second plurality of metallized interconnects; and a second integrated device coupled to the second metallization portion, wherein the second integrated device at least partially vertically overlaps the bridging member.

[0007] Another example provides a package including a first metallization portion comprising: at least one first dielectric layer; and a first plurality of metallized interconnects; a first integrated device coupled to the first metallization portion via at least a first plurality of solder interconnects; a bridging member coupled to the first metallization portion via at least a second plurality of solder interconnects; an encapsulation layer coupled to the first metallization portion; and a second metallization portion coupled to the bridging member and the encapsulation layer such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: at least one second dielectric layer; a second plurality of metallized interconnects; and a second integrated device coupled to the second metallization portion via at least a third plurality of solder interconnects, wherein the second integrated device and the bridging member at least partially overlap vertically. Attached Figure Description

[0008] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0009] Figure 1 An exemplary cross-sectional profile of a package including a metallized portion and at least one bridging member is illustrated.

[0010] Figure 2 An exemplary cross-sectional profile of a package including a metallized portion and at least one bridging member is illustrated.

[0011] Figure 3 An exemplary cross-sectional profile of a package including a metallized portion and at least one bridging member is illustrated.

[0012] Figure 4 An exemplary cross-sectional profile of a package including a metallized portion and at least one bridging member is illustrated.

[0013] Figure 5 An exemplary cross-sectional profile of a package including a metallized portion and at least one bridging member is illustrated.

[0014] Figure 6 An exemplary cross-sectional profile of a package including a metallized portion and at least one bridging member is illustrated.

[0015] Figure 7 An exemplary plan view of a package including a bridging element is shown.

[0016] Figure 8 An exemplary plan view of a package including a bridging element is shown.

[0017] Figure 9 An exemplary plan view of a package including a bridging element is shown.

[0018] Figure 10 An exemplary plan view of a package including a bridging element is shown.

[0019] Figures 11A to 11D Exemplary steps for manufacturing a package including metallized portions and bridging elements are illustrated.

[0020] Figures 12A to 12E Exemplary steps for manufacturing a package including metallized portions and bridging elements are illustrated.

[0021] Figures 13A to 13C Exemplary steps for manufacturing a package including metallized portions and bridging elements are illustrated.

[0022] Figure 14 An exemplary flowchart illustrating a method for manufacturing a package including metallized portions and bridging elements is shown.

[0023] Figures 15A to 15D Exemplary steps for manufacturing a package including metallized portions and bridging elements are illustrated.

[0024] Figures 16A to 16F Exemplary steps for manufacturing a package including metallized portions and bridging elements are illustrated.

[0025] Figures 17A to 17D Exemplary steps for manufacturing a package including metallized portions and bridging elements are illustrated.

[0026] Figure 18 An exemplary flowchart illustrating a method for manufacturing a package including metallized portions and bridging elements is shown.

[0027] Figures 19A to 19B An exemplary process for manufacturing metallized parts is illustrated.

[0028] Figure 20 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0029] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0030] This disclosure describes a package including a first metallization portion including at least one first dielectric layer; and a first plurality of metallized interconnects; a first integrated device coupled to the first metallization portion; a bridging member coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; and a second metallization portion coupled to the bridging member and the encapsulation layer, such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: at least one second dielectric layer; a second plurality of metallized interconnects; and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridging member at least partially overlap vertically. As will be further described below, the package provides interconnects with a high aspect ratio and high-density interconnects, which helps to provide improved package performance while keeping the package small and thin.

[0031] Exemplary package including bridging element

[0032] Figure 1 A cross-sectional profile view of a package 100 including metallized portions and bridging elements is illustrated. The package 100 is coupled to a board 110 via a plurality of solder interconnects 182. The board 110 includes at least one board dielectric layer 112 and a plurality of board interconnects 114. The board 110 may include a printed circuit board (PCB). The package 100 is coupled to the plurality of board interconnects 114 of the board 110 via the plurality of solder interconnects 182.

[0033] Package 100 includes an integrated device 101, a metallized portion 102, a metallized portion 104, an integrated device 103, an integrated device 105, a bridging component 107, a passive component 109, an encapsulation layer 106, and an encapsulation layer 108. Metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. Metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. Metallized portion 102 and / or metallized portion 104 may be redistributed portions. The plurality of metallized interconnects 122 and / or the plurality of metallized interconnects 142 may be redistributed interconnects.

[0034] Integrated device 101 includes a front side and a back side. The back side may be opposite to the front side. The back side may include a bare die substrate. The front side may include bare die pad interconnects. Integrated device 101 may be coupled to a metallization portion 102 such that the front side of integrated device 101 faces the metallization portion 102. Integrated device 101 may be coupled to and contact the metallization portion 102. For example, the pad interconnects of integrated device 101 may be coupled to and contact the metallization interconnects of a plurality of metallization interconnects 122 from the metallization portion 102.

[0035] Bridge 107 may be coupled to and contact metallization portion 102. Bridge 107 may include bridge substrate 170 (e.g., silicon substrate, silicon interposer, silicon layer) and a plurality of bridge interconnects 172. The plurality of bridge interconnects 172 may extend through the thickness of bridge substrate 170. In some embodiments, the plurality of bridge interconnects 172 may include bridge interconnects on the surface of bridge substrate 170. The plurality of bridge interconnects 172 may be coupled to and contact metallization interconnects from a plurality of metallization interconnects 122 of metallization portion 102. Bridge 107 may be coupled to and contact metallization portion 104. The plurality of bridge interconnects 172 may be coupled to and contact metallization interconnects from a plurality of metallization interconnects 142 of metallization portion 104. Bridge 107 may include an interposer layer including interposer interconnects.

[0036] The passive component 109 may be directly or indirectly coupled to the metallized portions 102 and 104. In some embodiments, one or more pillar interconnects may be used to couple the passive component 109 to the metallized portions 102 and / or 104.

[0037] Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging member 107, and passive component 109. Encapsulation layer 106 may be coupled to metallized portions 102 and 104. For example, encapsulation layer 106 may be coupled to a first surface (e.g., top surface) of metallized portion 102 and a second surface (e.g., bottom surface) of metallized portion 104. Encapsulation layer 106, integrated device 101, bridging member 107, and passive component 109 may be located between metallized portion 102 and metallized portion 104. The rear side of integrated device 101 may or may not contact the second surface (e.g., bottom surface) of metallized portion 104. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0038] Multiple pillar interconnects 162 are located within encapsulation layer 106. The multiple pillar interconnects 162 may extend through encapsulation layer 106. The multiple pillar interconnects 162 may be coupled to and contact (i) metallized interconnects of multiple metallized interconnects 122 from metallization portion 102 and (ii) metallized interconnects of multiple metallized interconnects 142 from metallization portion 104. Two or more pillar interconnects from the multiple pillar interconnects may have a pitch (e.g., pillar interconnect pitch). Two or more bridging interconnects from the multiple bridging interconnects 172 may have a pitch (e.g., bridging interconnect pitch). The pitch of the multiple pillar interconnects 162 may differ from the pitch of the multiple bridging interconnects 172 from bridging element 107. In some embodiments, the pitch of the multiple bridging interconnects 172 (e.g., minimum pitch) may be smaller than the pitch of the multiple pillar interconnects 162 (e.g., minimum pitch). In some embodiments, the pitch (e.g., minimum pitch) of the plurality of bridging interconnects 172 may be approximately 1 / 2 to 1 / 10 of the pitch (e.g., minimum pitch) of the plurality of post interconnects 162. For example, if two or more post interconnects have a pitch of approximately 100 micrometers, then two or more bridging interconnects may have a pitch of approximately 50 micrometers. It should be noted that the dimensions and / or relative dimensions described above are merely exemplary. In some embodiments, the pitch of the plurality of post interconnects 162 and / or the pitch of the bridging interconnects 172 may differ from those mentioned above. In some embodiments, the plurality of post interconnects 162 may have different pitches between different post interconnects. In some embodiments, the plurality of bridging interconnects 172 may have different pitches between different bridging interconnects.

[0039] The integrated device 103 can be coupled to a first surface (e.g., top surface) of the metallization portion 104 via a plurality of solder interconnects 130. The plurality of solder interconnects 130 can be coupled to pad interconnects of the integrated device 103 and to metallization interconnects of a plurality of metallization interconnects 142 from the metallization portion 104.

[0040] The integrated device 105 is coupled to a first surface (e.g., top surface) of the metallization portion 104 via a plurality of solder interconnects 150. The plurality of solder interconnects 150 may be coupled to pad interconnects of the integrated device 105 and to metallization interconnects of a plurality of metallization interconnects 142 from the metallization portion 104.

[0041] Encapsulation layer 108 may at least partially encapsulate integrated device 103 and / or integrated device 105. Encapsulation layer 108 may be coupled to a first surface of metallized portion 104. Encapsulation layer 108 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 108 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0042] The bridging element 107 is located within the package 100 such that it vertically overlaps (e.g., partially overlaps, fully overlaps) with the integrated device 103. The bridging element 107 is configured to provide one or more electrical paths between the integrated device 101 and the integrated device 103. The bridging element 107 achieves a short, high-density electrical path between the integrated device 101 and the integrated device 103.

[0043] The electrical path 190 between integrated device 103 and integrated device 101 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) bridging interconnects from a plurality of bridging interconnects 172 of bridging member 107, and (iv) metallized interconnects from a plurality of metallized interconnects 122 of metallized portion 102. A portion of the electrical path 190 between metallized portion 104 and integrated device 101 may be without any solder interconnects. A portion of the electrical path 190 between metallized portion 102 and integrated device 101 may be without any solder interconnects. For example, integrated device 101 may be coupled to metallized interconnects from metallized portion 102 without any intermediate solder interconnects. Similarly, a portion of the electrical path 190 between metallized portion 102 and bridging member 107 may be without any solder interconnects. For example, the bridging interconnect of bridging 107 can be coupled to the metallized interconnect from metallized portion 102 without any intermediate solder interconnect.

[0044] In some implementations, integrated device 101 may be a first chiplet, and integrated device 103 may be a second chiplet, or vice versa. Both integrated device 101 and integrated device 103 may be configured to perform high-speed data and signal processing and transmission between integrated device 101 and integrated device 103. Bridge 107 may be configured to facilitate such high-speed data and signal transmission between integrated device 101 and integrated device 103.

[0045] Figure 2 A package 200 including metallized portions and bridging elements is illustrated. Package 200 is similar to package 100 and includes components similar to and / or the same as those in package 100. Package 200 may be a stacked package (PoP). Package 200 is coupled to multiple board interconnects 114 of board 110 via multiple solder interconnects 182. Package 200 includes three metallized portions.

[0046] Package 200 includes an integrated device 101, a metallized portion 102, a metallized portion 104, an integrated device 203, an integrated device 205, a bridging component 107, a passive component 109, an encapsulation layer 106, an encapsulation layer 108, and a metallized portion 204. Metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. Metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. Metallized portion 204 includes at least one dielectric layer 240 and a plurality of metallized interconnects 242. Metallized portions 102, 104, and / or 204 may be redistributed portions. The plurality of metallized interconnects 122, 142, and / or 242 may be redistributed interconnects.

[0047] Integrated device 101, bridging element 107, passive component 109, and encapsulation layer 106 are located between metallized portion 102 and metallized portion 104. The front side of integrated device 101 is coupled to and contacts a first surface (e.g., top surface) of metallized portion 102. For example, pad interconnects of integrated device 101 are coupled to and contact the metallized interconnects of a plurality of metallized interconnects 122 of metallized portion 102. Bridging element 107 is coupled to and contacts metallized portion 102 and metallized portion 104. For example, bridging interconnects from a plurality of bridging interconnects 172 are coupled to and contact (i) the metallized interconnects of a plurality of metallized interconnects 122 of metallized portion 102 and (ii) the metallized interconnects of a plurality of metallized interconnects 142 of metallized portion 104.

[0048] An integrated device 203, an encapsulation layer 208, and a plurality of pillar interconnects 280 are located between metallized portions 104 and 204. The integrated device 203 can be coupled to a first surface (e.g., the top surface) of the metallized portion 104 via a plurality of solder interconnects 230. The plurality of pillar interconnects 280 can extend through the encapsulation layer 208. The plurality of pillar interconnects 280 can be coupled to and contact the metallized portions 104 and 204. The plurality of pillar interconnects 280 can be coupled to and contact a plurality of metallized interconnects 142 and a plurality of metallized interconnects 242. The encapsulation layer 208 can at least partially encapsulate the integrated device 203 and the plurality of pillar interconnects 280. The integrated device 203 can be perpendicularly overlapped with the bridging member 107 and the integrated device 101. The integrated device 205 can be coupled to the metallized portion 204 via a plurality of solder interconnects 250.

[0049] The electrical path 290 between integrated device 203 and integrated device 101 may include (i) solder interconnects from a plurality of solder interconnects 230, (ii) metallized interconnects from a plurality of metallized interconnects 142 of metallized portion 104, (iii) bridging interconnects from a plurality of bridging interconnects 172 of bridging member 107, and (iv) metallized interconnects from a plurality of metallized interconnects 122 of metallized portion 102. A portion of the electrical path 290 between metallized portion 104 and integrated device 101 may be without any solder interconnects. A portion of the electrical path 290 between metallized portion 102 and integrated device 101 may be without any solder interconnects. For example, integrated device 101 may be coupled to metallized interconnects from metallized portion 102 without any intermediate solder interconnects. Similarly, a portion of the electrical path 290 between metallized portion 102 and bridging member 107 may be without any solder interconnects. For example, the bridging interconnect of bridging 107 can be coupled to the metallized interconnect from metallized portion 102 without any intermediate solder interconnect.

[0050] In some implementations, integrated device 101 may be a first chiplet, and integrated device 203 may be a second chiplet, or vice versa. Both integrated device 101 and integrated device 203 may be configured to perform high-speed data and signal processing and transmission between integrated device 101 and integrated device 203. Bridge 107 may be configured to facilitate such high-speed data and signal transmission between integrated device 101 and integrated device 203.

[0051] Figure 3 A package 300 including metallized portions and bridging elements is illustrated. Package 300 is similar to packages 200 and 100 and includes components similar to and / or identical to those in packages 200 and 100. Package 300 may be a stacked package (PoP). Package 300 is coupled to multiple board interconnects 114 of board 110 via multiple solder interconnects 182. Package 300 includes two metallized portions and a substrate.

[0052] Package 300 includes an integrated device 101, a metallized portion 102, a metallized portion 104, an integrated device 203, an integrated device 205, a bridging component 107, a passive component 109, an encapsulation layer 106, an encapsulation layer 108, and a substrate 304. The metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. The metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. The substrate 302 includes at least one dielectric layer 340 and a plurality of interconnects 342. The metallized portion 102 and / or the metallized portion 104 may be a redistributed portion. The plurality of metallized interconnects 122 and / or the plurality of metallized interconnects 142 may be redistributed interconnects. The substrate 304 may be a laminated substrate.

[0053] Package 300 includes a substrate 304 and a non-metallized portion 204. An integrated device 203, a plurality of pillar interconnects 280, and an encapsulation layer 208 are located between the metallized portion 104 and the substrate 304. The encapsulation layer 208 is coupled to and contacts the metallized portion 104 and the substrate 304. The plurality of pillar interconnects 280 are coupled to the substrate 304 via a plurality of solder interconnects 350. The plurality of solder interconnects 350 are coupled to and contact the plurality of pillar interconnects 280 and a plurality of interconnects 342 of the substrate 304. Integrated device 205 can be coupled to the substrate 304 via a plurality of solder interconnects 250.

[0054] The electrical path between integrated device 203 and integrated device 101 can be similar to Figure 2 The described electrical path is 290.

[0055] Figure 4 A package 400 including metallized portions and bridging elements is illustrated. Package 400 is similar to package 100 and includes components similar to and / or the same as those in package 100. Package 400 may be a stacked package (PoP). Package 400 is coupled to multiple board interconnects 114 of board 110 via multiple solder interconnects 182. Package 400 includes two metallized portions.

[0056] Package 400 includes an integrated device 101, a metallized portion 102, a metallized portion 104, an integrated device 103, an integrated device 105, a bridging element 107, a passive component 109, an encapsulation layer 106, and an encapsulation layer 108. The metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. The front side of the integrated device 101 is coupled to the metallized portion 102 via a plurality of solder interconnects 410. The bridging element 107 is coupled to the metallized portion 102 via a plurality of solder interconnects 470. The passive component 109 is coupled to the metallized portion 102 via a plurality of solder interconnects 480.

[0057] A bridging element 107 is located within the package 400 such that it vertically overlaps (e.g., partially overlaps, fully overlaps) with the integrated device 103. The bridging element 107 is configured to provide one or more electrical paths between the integrated device 101 and the integrated device 103. The bridging element 107 achieves a short, high-density electrical path between the integrated device 101 and the integrated device 103.

[0058] The electrical path 490 between integrated device 103 and integrated device 101 may include (i) solder interconnects from a plurality of solder interconnects 130, (ii) metallized interconnects from a plurality of metallized interconnects 142 from metallized portion 104, (iii) bridging interconnects from a plurality of bridging interconnects 172 from bridging portion 107, (iv) solder interconnects from a plurality of solder interconnects 470, (v) metallized interconnects from a plurality of metallized interconnects 122 from metallized portion 102, and / or (vi) solder interconnects from a plurality of solder interconnects 410.

[0059] Figure 5 A package 500 including metallized portions and bridging elements is illustrated. Package 500 is similar to package 200 and includes components similar to and / or the same as those in package 200. Package 500 may be a stacked package (PoP). Package 500 is coupled to multiple board interconnects 114 of board 110 via multiple solder interconnects 182. Package 500 includes three metallized portions.

[0060] Package 500 includes an integrated device 101, a metallized portion 102, a metallized portion 104, a metallized portion 204, an integrated device 203, an integrated device 205, a bridging element 107, a passive component 109, an encapsulation layer 106, and an encapsulation layer 208. The front side of the integrated device 101 is coupled to the metallized portion 102 via multiple solder interconnects 410. The bridging element 107 is coupled to the metallized portion 102 via multiple solder interconnects 470. The passive component 109 is coupled to the metallized portion 102 via multiple solder interconnects 480.

[0061] The bridging element 107 is located within the package 500 such that it vertically overlaps (e.g., partially overlaps, fully overlaps) with the integrated device 203. The bridging element 107 is configured to provide one or more electrical paths between the integrated device 101 and the integrated device 203. The bridging element 107 achieves short, high-density electrical paths between the integrated device 101 and the integrated device 203.

[0062] The electrical path 590 between integrated device 203 and integrated device 101 may include (i) solder interconnects from a plurality of solder interconnects 230, (ii) metallized interconnects from a plurality of metallized interconnects 142 from metallized portion 104, (iii) bridging interconnects from a plurality of bridging interconnects 172 from bridging portion 107, (iv) solder interconnects from a plurality of solder interconnects 470, (v) metallized interconnects from a plurality of metallized interconnects 122 from metallized portion 102, and / or (vi) solder interconnects from a plurality of solder interconnects 410.

[0063] Figure 6 A package 600 including metallized portions and bridging elements is illustrated. Package 600 is similar to package 300 and includes components similar to and / or the same as those in package 300. Package 600 may be a stacked package (PoP). Package 600 is coupled to multiple board interconnects 114 of board 110 via multiple solder interconnects 182. Package 600 includes two metallized portions and a substrate.

[0064] Package 600 includes an integrated device 101, a metallized portion 102, a metallized portion 104, a substrate 304, an integrated device 203, an integrated device 205, a bridging element 107, a passive component 109, an encapsulation layer 106, and an encapsulation layer 208. The front side of the integrated device 101 is coupled to the metallized portion 102 via multiple solder interconnects 410. The bridging element 107 is coupled to the metallized portion 102 via multiple solder interconnects 470. The passive component 109 is coupled to the metallized portion 102 via multiple solder interconnects 480.

[0065] The bridging element 107 is located within the package 600 such that it vertically overlaps (e.g., partially overlaps, fully overlaps) with the integrated device 203. The bridging element 107 is configured to provide one or more electrical paths between the integrated device 101 and the integrated device 203. The bridging element 107 achieves a short, high-density electrical path between the integrated device 101 and the integrated device 203.

[0066] The electrical path between integrated device 203 and integrated device 101 can be... Figure 5 The described electrical path 590 is similar to and / or identical to that described.

[0067] Figure 7 A plan view of package 700 is illustrated. Package 700 may represent any of the packages described in this disclosure. Package 700 includes integrated device 101, bridging element 107, and integrated device 103. Although Figure 7As not shown, package 700 may further include integrated device 105. Bridging element 107 is laterally located near integrated device 101. Bridging element 107 at least partially overlaps vertically with integrated device 103. In some embodiments, bridging element 107 and / or integrated device 101 may at least partially overlap vertically with integrated device 105.

[0068] Figure 8 A plan view of package 800 is illustrated. Package 800 may represent any of the packages described in this disclosure. Package 800 includes integrated device 101, bridge 107a, bridge 107b, and integrated device 103. Although Figure 7 Not shown, package 700 may further include integrated device 105. Bridging elements 107a and 107b are laterally located near integrated device 101. Integrated device 101 and integrated device 103 at least partially overlap vertically. In some embodiments, integrated device 101, bridging elements 107a and / or bridging elements 107b may at least partially overlap vertically with integrated device 103.

[0069] Figure 9 A plan view of package 900 is illustrated. Package 900 may represent any of the packages described in this disclosure. Package 900 includes integrated device 101, bridging element 107a, bridging element 107b, and integrated device 203. Bridging elements 107a and 107b are laterally located near integrated device 101. Integrated device 101 and integrated device 203 at least partially overlap vertically. Bridging elements 107a and 107b at least partially overlap vertically with integrated device 203.

[0070] Figure 10 A plan view of package 1000 is illustrated. Package 1000 may represent any of the packages described in this disclosure. Package 1000 includes integrated device 101, bridging element 107a, bridging element 107b, and integrated device 203. Bridging elements 107a and 107b are laterally located near integrated device 101. Integrated device 101 and integrated device 203 at least partially overlap vertically.

[0071] Different specific implementations may have different arrangements and / or configurations of integrated devices and / or bridging components.

[0072] As mentioned above, the metallized portions (e.g., 102, 104) may include redistribution portions comprising redistribution interconnects (e.g., redistribution layer (RDL) interconnects). The redistribution interconnects may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be used interchangeably. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or the redistribution interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0073] Integrated devices (e.g., 300, 400) may include dies (e.g., semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include input / output (I / O) hubs. Integrated devices may include transistors. Integrated devices may be examples of electronic components and / or electronic devices.

[0074] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 100) described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and chiplets may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the same technology node or different technology nodes may be used to manufacture the first integrated device and the second integrated device of the package. In some embodiments, the same technology node or different technology nodes may be used to manufacture the chiplet and another chiplet of the package.

[0075] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require that specific technology node to be used. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0076] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0077] Packages (e.g., 100, 200, 300, 400, 500, 600) may be implemented in a radio frequency (RF) package. This RF package may be a radio frequency front-end (RFFE) package. Packages (e.g., 100) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G, 6G). Packages (e.g., 100) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). Packages (e.g., 100, 200) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0078] Exemplary process for manufacturing a package including bridging elements between metallized portions.

[0079] In some specific implementations, manufacturing the package involves several processes. Figures 11A to 11D Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, Figures 11A to 11D The process can be used to provide or manufacture package 100. However, Figures 11A to 11D The process can be used to manufacture any of the packages described in this disclosure.

[0080] It should be noted that the figure Figures 11A to 11D The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0081] like Figure 11A As shown, stage 1 illustrates the state after a plurality of pillar interconnects 162 have been formed on a carrier 1100. The carrier 1100 may be a first carrier. The plurality of pillar interconnects 162 may include different heights. The plurality of pillar interconnects 162 may be formed using an electroplating process.

[0082] Phase 2 illustrates the state after the integrated device 101, bridge 107, and passive component 109 are coupled to the carrier 1100. A pick-and-place process can be used to couple the integrated device 101, bridge 107, and passive component 109 to the carrier 1100. In some embodiments, adhesives can be used to couple the back side of the integrated device 101 and / or the bridge 107 to the carrier 1100. The passive component 109 can be coupled to some of the pillar interconnects from the plurality of pillar interconnects 162.

[0083] Phase 3 illustrates the state after encapsulation layer 106 has been formed and coupled to carrier 1100, integrated device 101, bridging element 107, and passive component 109. Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0084] like Figure 11B As shown, stage 4 illustrates the state after the metallization portion 102 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 102 includes at least one dielectric layer 120 and multiple metallized interconnects 122. The multiple metallized interconnects 122 may include multiple redistributed interconnects. The multiple metallized interconnects 122 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162.

[0085] Phase 5 illustrates the state after the carrier 1100 is decoupled from the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple post interconnects 162. The carrier 1100 can be detached and / or stripped from the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple post interconnects 162.

[0086] Phase 6 illustrates the state after the carrier 1110 is coupled to the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may include an adhesive.

[0087] Phase 7 illustrates the state after the metallization portion 104 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 104 includes at least one dielectric layer 140 and multiple metallized interconnects 142. The multiple metallized interconnects 142 may include multiple redistributed interconnects. The multiple metallized interconnects 142 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162. The encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162 may be located between the metallization portion 102 and the metallization portion 104.

[0088] like Figure 11C As shown, stage 8 illustrates the state after integrated device 103 is coupled to metallized portion 104 via multiple solder interconnects 130. Stage 8 also illustrates the state after integrated device 105 is coupled to metallized portion 104 via multiple solder interconnects 150. One or more solder reflow processes can be used to couple integrated device 103 and / or integrated device 105 to metallized portion 104 via multiple solder interconnects.

[0089] Phase 9 illustrates the state after encapsulation layer 108 has been formed and coupled to metallized portion 104, integrated device 103, and integrated device 105. Encapsulation layer 108 may at least partially encapsulate integrated device 103 and integrated device 105. Encapsulation layer 108 may include molding material, resin, and / or epoxy resin. Encapsulation layer 108 may be a component for encapsulation. Encapsulation layer 108 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0090] like Figure 11D As shown, stage 10 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0091] Phase 11 illustrates the state after multiple solder interconnects 182 are coupled to metallized portions 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122. Phase 11 can also illustrate a package 100 including two metallized portions and a bridging element located between the two metallized portions.

[0092] Exemplary process for manufacturing a package including bridging elements between metallized portions.

[0093] In some specific implementations, manufacturing the package involves several processes. Figures 12A to 12E Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, Figures 12A to 12EThe process can be used to provide or manufacture package 300. However, Figures 12A to 12E The process can be used to manufacture any of the packages described in this disclosure.

[0094] It should be noted that Figures 12A to 12E The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0095] like Figure 12A As shown, stage 1 illustrates the state after a plurality of pillar interconnects 162 have been formed on a carrier 1100. The carrier 1100 may be a first carrier. The plurality of pillar interconnects 162 may include different heights. The plurality of pillar interconnects 162 may be formed using an electroplating process.

[0096] Phase 2 illustrates the state after the integrated device 101, bridge 107, and passive component 109 are coupled to the carrier 1100. A pick-and-place process can be used to couple the integrated device 101, bridge 107, and passive component 109 to the carrier 1100. In some embodiments, adhesives can be used to couple the back side of the integrated device 101 and / or the bridge 107 to the carrier 1100. The passive component 109 can be coupled to some of the pillar interconnects from the plurality of pillar interconnects 162.

[0097] Phase 3 illustrates the state after encapsulation layer 106 has been formed and coupled to carrier 1100, integrated device 101, bridging element 107, and passive component 109. Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0098] Phase 4 illustrates the state after the metallization portion 102 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 102 includes at least one dielectric layer 120 and multiple metallized interconnects 122. The multiple metallized interconnects 122 may include multiple redistributed interconnects. The multiple metallized interconnects 122 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162.

[0099] Phase 5 illustrates the state after the carrier 1100 is decoupled from the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple post interconnects 162. The carrier 1100 can be detached and / or stripped from the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple post interconnects 162.

[0100] like Figure 12B As shown, stage 6 illustrates the state after the carrier 1110 is coupled to the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may include an adhesive.

[0101] Phase 7 illustrates the state after the metallization portion 104 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 104 includes at least one dielectric layer 140 and multiple metallized interconnects 142. The multiple metallized interconnects 142 may include multiple redistributed interconnects. The multiple metallized interconnects 142 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162. The encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162 may be located between the metallization portion 102 and the metallization portion 104.

[0102] Stage 8 illustrates the state after multiple pillar interconnects 280 have been formed and coupled to the metallized portion 104. The multiple pillar interconnects 280 can be coupled to multiple metallized interconnects 142. The multiple pillar interconnects 280 can be formed using an electroplating process.

[0103] like Figure 12C As shown, stage 9 illustrates the state after the integrated device 203 is coupled to the metallization portion 104 via multiple solder interconnects 230. A solder reflow process can be used to couple the integrated device 203 to the metallization portion 104 via multiple solder interconnects.

[0104] Phase 10 illustrates the state after the substrate 304 is coupled to a plurality of pillar interconnects 280 via a plurality of solder interconnects 350. The substrate 304 can be coupled to the plurality of pillar interconnects 280 using a solder reflow process. The substrate 304 may be a laminated substrate. The substrate 304 includes at least one dielectric layer 340 and a plurality of interconnects 342. The plurality of solder interconnects 350 can be coupled to the plurality of interconnects 342 and the plurality of pillar interconnects 280.

[0105] like Figure 12DAs shown, stage 11 illustrates the state after the encapsulation layer 208 has been formed and coupled to the metallization portion 104, the integrated device 203, and the substrate 304. The encapsulation layer 208 may at least partially encapsulate the integrated device 203. The encapsulation layer 208 may be located between the metallization portion 104 and the substrate 304. The encapsulation layer 208 may include a molding compound, resin, and / or epoxy resin. The encapsulation layer 208 may be a component for encapsulation. The encapsulation layer 208 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0106] Phase 12 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0107] like Figure 12E As shown, stage 13 illustrates the state after multiple solder interconnects 182 are coupled to the metallized portion 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122.

[0108] Phase 14 illustrates the state after the integrated device 205 is coupled to the substrate 304 via multiple solder interconnects 250. A solder reflow process can be used to couple the integrated device 205 to the substrate 304. Phase 14 may illustrate a package 300 including a substrate, two metallized portions, and a bridging element located between the two metallized portions.

[0109] Exemplary process for manufacturing a package including bridging elements between metallized portions.

[0110] In some specific implementations, manufacturing the package involves several processes. Figures 13A to 13C Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, the following can be used: Figures 13A to 13C The process is used to provide or manufacture package 200. However, Figures 13A to 13C The process can be used to manufacture any of the packages described in this disclosure.

[0111] It should be noted that Figures 13A to 13C The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0112] like Figure 13AAs shown, stage 1 illustrates the state after providing and / or manufacturing the carrier 1110, metallized portion 102, integrated device 101, bridging component 107, passive component 109, multiple pillar interconnects 162, encapsulation layer 106, and metallized portion 104. Figure 12A Phase 1 to Figure 12B Phase 7 may exemplify and describe examples of providing and / or manufacturing carrier 1110, metallized portion 102, integrated device 101, bridging component 107, passive component 109, multiple pillar interconnect 162, encapsulation layer 106, and metallized portion 104.

[0113] Phase 2 illustrates the state after multiple pillar interconnects 280 have been formed and coupled to the metallized portion 104. The multiple pillar interconnects 280 can be coupled to multiple metallized interconnects 142. The multiple pillar interconnects 280 can be formed using an electroplating process.

[0114] Phase 3 illustrates the state after the integrated device 203 is coupled to the metallized portion 104 via multiple solder interconnects 230. A solder reflow process can be used to couple the integrated device 203 to the metallized portion 104 via the multiple solder interconnects.

[0115] like Figure 13B As shown, stage 4 illustrates the state after the encapsulation layer 208 has been formed and coupled to the metallization portion 104, the integrated device 203, and the plurality of pillar interconnects 280. The encapsulation layer 208 may at least partially encapsulate the integrated device 203 and the plurality of pillar interconnects 280. The encapsulation layer 208 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 208 may be a component for encapsulation. The encapsulation layer 208 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0116] Phase 5 illustrates the state after the metallization portion 204 has been formed and coupled to the encapsulation layer 208, the integrated device 203, and the plurality of pillar interconnects 280. The metallization portion 204 includes at least one dielectric layer 240 and a plurality of metallized interconnects 242. The plurality of metallized interconnects 242 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 242 may be coupled to the plurality of pillar interconnects 280. The encapsulation layer 208, the integrated device 203, and the plurality of pillar interconnects 280 may be located between the metallization portion 104 and the metallization portion 204.

[0117] like Figure 13C As shown, stage 6 illustrates the state after the integrated device 205 is coupled to the metallization portion 204 via multiple solder interconnects 250. The integrated device 205 can be coupled to the metallization portion 204 using a solder reflow process.

[0118] Phase 7 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0119] Phase 7 also illustrates the state after multiple solder interconnects 182 are coupled to metallized portions 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122. Phase 7 may illustrate a package 200 including three metallized portions and a bridging element located between two of the three metallized portions.

[0120] Exemplary flowchart of a method for manufacturing a package including bridging elements between metallized portions

[0121] In some specific implementations, manufacturing the package involves several processes. Figure 14 An exemplary flowchart illustrating a method 1400 for providing or manufacturing a package is shown. In some specific implementations, Figure 14 Method 1400 can be used to provide or manufacture the package 100 described in this disclosure. However, method 1400 can be used to provide or manufacture any package described in this disclosure.

[0122] It should be noted that Figure 14 Method 1400 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some implementations, the order of the processes may be changed or modified.

[0123] The method (at 1405) provides a carrier and forms multiple pillar interconnects. Figure 11A Stage 1 illustrates the state after a plurality of pillar interconnects 162 have been formed on a carrier 1100. The carrier 1100 may be a first carrier. The plurality of pillar interconnects 162 may include different heights. The plurality of pillar interconnects 162 may be formed using an electroplating process.

[0124] This method (at 1410) couples integrated devices, bridging elements, and / or other components to a carrier. Figure 11A Phase 2 illustrates the state after the integrated device 101, bridge 107, and passive component 109 are coupled to the carrier 1100. A pick-and-place process can be used to couple the integrated device 101, bridge 107, and passive component 109 to the carrier 1100. In some embodiments, adhesives can be used to couple the back side of the integrated device 101 and / or the bridge 107 to the carrier 1100. The passive component 109 can be coupled to some of the pillar interconnects from the plurality of pillar interconnects 162.

[0125] This method (at 1415) forms an encapsulation layer. Figure 11AStage 3 illustrates the state after encapsulation layer 106 has been formed and coupled to carrier 1100, integrated device 101, bridging element 107, and passive component 109. Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0126] This method (at 1420) forms the first metallization portion. Figure 11B Phase 4 illustrates the state after the metallized portion 102 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallized portion 102 includes at least one dielectric layer 120 and multiple metallized interconnects 122. The multiple metallized interconnects 122 may include multiple redistributed interconnects. The multiple metallized interconnects 122 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162.

[0127] After the first metallization portion is formed, the carrier can be decoupled and another carrier can be coupled to the first metallization portion. Figure 11B Phase 5 illustrates the state after the carrier 1100 is decoupled from the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple post interconnects 162. The carrier 1100 can be detached and / or stripped from the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple post interconnects 162.

[0128] Figure 11B Phase 6 illustrates the state after the carrier 1110 is coupled to the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may include an adhesive.

[0129] This method (at 1425) forms a second metallization portion. Figure 11BPhase 7 illustrates the state after the metallization portion 104 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 104 includes at least one dielectric layer 140 and multiple metallized interconnects 142. The multiple metallized interconnects 142 may include multiple redistributed interconnects. The multiple metallized interconnects 142 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162. The encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162 may be located between the metallization portion 102 and the metallization portion 104.

[0130] This method (at 1430) couples the integrated device to the second metallization portion. Figure 11C Phase 8 illustrates the state after integrated device 103 is coupled to metallized portion 104 via multiple solder interconnects 130. Phase 8 also illustrates the state after integrated device 105 is coupled to metallized portion 104 via multiple solder interconnects 150. One or more solder reflow processes can be used to couple integrated device 103 and / or integrated device 105 to metallized portion 104 via multiple solder interconnects.

[0131] This method (at 1435) forms another encapsulation layer. Figure 11C Stage 9 illustrates the state after encapsulation layer 108 has been formed and coupled to metallized portion 104, integrated device 103, and integrated device 105. Encapsulation layer 108 may at least partially encapsulate integrated device 103 and integrated device 105. Encapsulation layer 108 may include molding material, resin, and / or epoxy resin. Encapsulation layer 108 may be a component for encapsulation. Encapsulation layer 108 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0132] The method (at 1440) decouples the second carrier and (at 1440) couples multiple solder interconnects to the first metallization portion. Figure 11D Stage 10 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0133] Figure 11D Phase 11 illustrates the state after multiple solder interconnects 182 are coupled to metallized portions 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122. Phase 11 can also illustrate a package 100 including two metallized portions and a bridging element located between the two metallized portions.

[0134] In some implementations, several packages are manufactured simultaneously. In such cases, the method allows for the individual cutting of the packages.

[0135] Exemplary process for manufacturing a package including bridging elements between metallized portions.

[0136] In some specific implementations, manufacturing the package involves several processes. Figures 15A to 15D Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, the following can be used: Figures 15A to 15D The process is used to provide or manufacture package 400. However, Figures 15A to 15D The process can be used to manufacture any of the packages described in this disclosure.

[0137] It should be noted that Figures 15A to 15D The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0138] like Figure 15A As shown, stage 1 illustrates the state after the provision and / or formation of the carrier 1100 and the metallized portion 102. The metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. The metallized portion 102 may be coupled to the carrier 1100.

[0139] Phase 2 illustrates the state after a plurality of pillar interconnects 162 have been formed on the metallized portion 102. The plurality of pillar interconnects 162 can be coupled to a plurality of metallized interconnects 122. The plurality of pillar interconnects 162 can be formed using an electroplating process.

[0140] Phase 3 illustrates the state after the integrated device 101, bridge 107, and passive component 109 are coupled to the metallized portion 102 via multiple solder interconnects. The integrated device 101, bridge 107, and passive component 109 can be coupled to the metallized portion 102 using a solder reflow process. The integrated device 101 is coupled to the metallized portion 102 via multiple solder interconnects 410. The bridge 107 can be coupled to the metallized portion 102 via multiple solder interconnects 470. The passive component 109 can be coupled to the metallized portion 102 via multiple solder interconnects 480.

[0141] like Figure 15BAs shown, stage 4 illustrates the state after encapsulation layer 106 has been formed and coupled to metallized portion 102, integrated device 101, bridging member 107, and passive component 109. Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging member 107, passive component 109, and multiple pillar interconnects 162. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0142] Phase 5 illustrates the state after the metallization portion 104 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 104 includes at least one dielectric layer 140 and multiple metallized interconnects 142. The multiple metallized interconnects 142 may include multiple redistributed interconnects. The multiple metallized interconnects 142 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162. The encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162 may be located between the metallization portion 102 and the metallization portion 104.

[0143] like Figure 15C As shown, stage 6 illustrates the state after integrated device 103 is coupled to metallized portion 104 via multiple solder interconnects 130. Stage 6 also illustrates the state after integrated device 105 is coupled to metallized portion 104 via multiple solder interconnects 150. One or more solder reflow processes can be used to couple integrated device 103 and / or integrated device 105 to metallized portion 104 via multiple solder interconnects.

[0144] Phase 7 illustrates the state after encapsulation layer 108 has been formed and coupled to metallized portion 104, integrated device 103, and integrated device 105. Encapsulation layer 108 may at least partially encapsulate integrated device 103 and integrated device 105. Encapsulation layer 108 may include molding material, resin, and / or epoxy resin. Encapsulation layer 108 may be a component for encapsulation. Encapsulation layer 108 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0145] like Figure 15D As shown, stage 8 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0146] Phase 9 illustrates the state after multiple solder interconnects 182 are coupled to metallized portions 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122. Phase 9 may also illustrate a package 400 including two metallized portions and a bridging element located between the two metallized portions.

[0147] Exemplary process for manufacturing a package including bridging elements between metallized portions.

[0148] In some specific implementations, manufacturing the package involves several processes. Figures 16A to 16F Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, the following can be used: Figures 16A to 16F The process is used to provide or manufacture package 400. However, Figures 16A to 16F The process can be used to manufacture any of the packages described in this disclosure.

[0149] It should be noted that Figures 16A to 16F The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0150] like Figure 16A As shown, stage 1 illustrates the state after the provision and / or formation of the carrier 1100 and the metallized portion 102. The metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. The metallized portion 102 may be coupled to the carrier 1100.

[0151] Phase 2 illustrates the state after a plurality of pillar interconnects 162 have been formed on the metallized portion 102. The plurality of pillar interconnects 162 can be coupled to a plurality of metallized interconnects 122. The plurality of pillar interconnects 162 can be formed using an electroplating process.

[0152] Phase 3 illustrates the state after the integrated device 101, bridge 107, and passive component 109 are coupled to the metallized portion 102 via multiple solder interconnects. The integrated device 101, bridge 107, and passive component 109 can be coupled to the metallized portion 102 using a solder reflow process. The integrated device 101 is coupled to the metallized portion 102 via multiple solder interconnects 410. The bridge 107 can be coupled to the metallized portion 102 via multiple solder interconnects 470. The passive component 109 can be coupled to the metallized portion 102 via multiple solder interconnects 480.

[0153] like Figure 16BAs shown, stage 4 illustrates the state after encapsulation layer 106 has been formed and coupled to metallized portion 102, integrated device 101, bridging member 107, and passive component 109. Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging member 107, passive component 109, and multiple pillar interconnects 162. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0154] Phase 5 illustrates the state after the metallization portion 104 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallization portion 104 includes at least one dielectric layer 140 and multiple metallized interconnects 142. The multiple metallized interconnects 142 may include multiple redistributed interconnects. The multiple metallized interconnects 142 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162. The encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162 may be located between the metallization portion 102 and the metallization portion 104.

[0155] like Figure 16C As shown, stage 6 illustrates the state after the plurality of pillar interconnects 280 have been formed and coupled to the metallized portion 104. The plurality of pillar interconnects 280 can be coupled to the plurality of metallized interconnects 142. The plurality of pillar interconnects 280 can be formed using an electroplating process.

[0156] Phase 7 illustrates the state after the integrated device 203 is coupled to the metallized portion 104 via multiple solder interconnects 230. A solder reflow process can be used to couple the integrated device 203 to the metallized portion 104 via multiple solder interconnects.

[0157] like Figure 16D As shown, stage 8 illustrates the state after substrate 304 is coupled to multiple pillar interconnects 280 via multiple solder interconnects 350. The substrate 304 can be coupled to the multiple pillar interconnects 280 using a solder reflow process. Substrate 304 may be a laminated substrate. Substrate 304 includes at least one dielectric layer 340 and multiple interconnects 342. The multiple solder interconnects 350 can be coupled to the multiple interconnects 342 and the multiple pillar interconnects 280.

[0158] Stage 9 illustrates the state after encapsulation layer 208 has been formed and coupled to metallization portion 104, integrated device 203, and substrate 304. Encapsulation layer 208 may at least partially encapsulate integrated device 203. Encapsulation layer 208 may be located between metallization portion 104 and substrate 304. Encapsulation layer 208 may include molding material, resin, and / or epoxy resin. Encapsulation layer 208 may be a component for encapsulation. Encapsulation layer 208 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0159] like Figure 16E As shown, stage 10 illustrates the state after the integrated device 205 is coupled to the substrate 304 via multiple solder interconnects 250. A solder reflow process can be used to couple the integrated device 205 to the substrate 304. Stage 14 may illustrate a package 300 including a substrate, two metallized portions, and a bridging element located between the two metallized portions.

[0160] Phase 11 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0161] Phase 11 also illustrates the state after the multiple solder interconnects 182 are coupled to the metallized portion 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122.

[0162] Exemplary process for manufacturing a package including bridging elements between metallized portions.

[0163] In some specific implementations, manufacturing the package involves several processes. Figures 17A to 17D Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, the following can be used: Figures 17A to 17D The process is to provide or manufacture package 500. However, Figures 17A to 17D The process can be used to manufacture any of the packages described in this disclosure.

[0164] It should be noted that Figures 17A to 17D The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0165] like Figure 17AAs shown, stage 1 illustrates the state after providing and / or manufacturing the carrier 1110, metallized portion 102, integrated device 101, bridging component 107, passive component 109, multiple pillar interconnects 162, encapsulation layer 106, and metallized portion 104. Figure 16A Phase 1 to Figure 16B Phase 5 may exemplify and describe examples of providing and / or manufacturing carrier 1100, metallized portion 102, integrated device 101, bridging component 107, passive component 109, multiple pillar interconnect 162, encapsulation layer 106, and metallized portion 104.

[0166] Phase 2 illustrates the state after multiple pillar interconnects 280 have been formed and coupled to the metallized portion 104. The multiple pillar interconnects 280 can be coupled to multiple metallized interconnects 142. The multiple pillar interconnects 280 can be formed using an electroplating process.

[0167] like Figure 17B As shown, stage 3 illustrates the state after the integrated device 203 is coupled to the metallization portion 104 via multiple solder interconnects 230. A solder reflow process can be used to couple the integrated device 203 to the metallization portion 104 via multiple solder interconnects.

[0168] Phase 4 illustrates the state after the encapsulation layer 208 has been formed and coupled to the metallization portion 104, the integrated device 203, and the plurality of pillar interconnects 280. The encapsulation layer 208 may at least partially encapsulate the integrated device 203 and the plurality of pillar interconnects 280. The encapsulation layer 208 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 208 may be a component for encapsulation. The encapsulation layer 208 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0169] like Figure 17C As shown, stage 5 illustrates the state after the metallization portion 204 has been formed and coupled to the encapsulation layer 208, the integrated device 203, and the plurality of pillar interconnects 280. The metallization portion 204 includes at least one dielectric layer 240 and a plurality of metallized interconnects 242. The plurality of metallized interconnects 242 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 242 may be coupled to the plurality of pillar interconnects 280. The encapsulation layer 208, the integrated device 203, and the plurality of pillar interconnects 280 may be located between the metallization portion 104 and the metallization portion 204.

[0170] Phase 6 illustrates the state after the integrated device 205 is coupled to the metallized portion 204 via multiple solder interconnects 250. The integrated device 205 can be coupled to the metallized portion 204 using a solder reflow process.

[0171] like Figure 17DAs shown, stage 7 illustrates the state after the carrier 1100 is decoupled from the metallized portion 102. The carrier 1100 may be a second carrier. The carrier 1100 may be detached and / or peeled off from the metallized portion 102.

[0172] Phase 7 also illustrates the state after multiple solder interconnects 182 are coupled to metallized portions 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122. Phase 7 may illustrate a package 500 including three metallized portions and a bridging element located between two of the three metallized portions.

[0173] Exemplary flowchart of a method for manufacturing a package including bridging elements between metallized portions

[0174] In some specific implementations, manufacturing the package involves several processes. Figure 18 An exemplary flowchart illustrating a method 1800 for providing or manufacturing a package is shown. In some specific implementations, Figure 18 Method 1800 can be used to provide or manufacture the package 400 described in this disclosure. However, method 1800 can be used to provide or manufacture any package described in this disclosure.

[0175] It should be noted that Figure 18 Method 1800 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some implementations, the order of the processes may be changed or modified.

[0176] The method (at 1805) provides a carrier, a metallized portion, and forms multiple pillar interconnects. Figure 15A Phase 1 illustrates the state after the provision and / or formation of the carrier 1100 and the metallized portion 102. The metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. The metallized portion 102 may be coupled to the carrier 1100.

[0177] Figure 15A Stage 2 illustrates the state after a plurality of pillar interconnects 162 have been formed on the metallized portion 102. The plurality of pillar interconnects 162 can be coupled to a plurality of metallized interconnects 122. The plurality of pillar interconnects 162 can be formed using an electroplating process.

[0178] This method (at 1810) couples the integrated device, bridge, and / or other components to the first metallization portion. Figure 15APhase 3 illustrates the state after the integrated device 101, bridge 107, and passive component 109 are coupled to the metallized portion 102 via multiple solder interconnects. The integrated device 101, bridge 107, and passive component 109 can be coupled to the metallized portion 102 using a solder reflow process. The integrated device 101 is coupled to the metallized portion 102 via multiple solder interconnects 410. The bridge 107 can be coupled to the metallized portion 102 via multiple solder interconnects 470. The passive component 109 can be coupled to the metallized portion 102 via multiple solder interconnects 480.

[0179] This method (at 1815) forms an encapsulation layer. Figure 15B Stage 4 illustrates the state after encapsulation layer 106 has been formed and coupled to metallized portion 102, integrated device 101, bridging member 107, and passive component 109. Encapsulation layer 106 may at least partially encapsulate integrated device 101, bridging member 107, passive component 109, and multiple pillar interconnects 162. Encapsulation layer 106 may include molding material, resin, and / or epoxy resin. Encapsulation layer 106 may be a component for encapsulation. Encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0180] This method (at 1820) forms a second metallization portion. Figure 15B Phase 5 illustrates the state after the metallized portion 104 has been formed and coupled to the encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162. The metallized portion 104 includes at least one dielectric layer 140 and multiple metallized interconnects 142. The multiple metallized interconnects 142 may include multiple redistributed interconnects. The multiple metallized interconnects 142 may be coupled to the integrated device 101, bridging element 107, passive component 109, and / or multiple pillar interconnects 162. The encapsulation layer 106, integrated device 101, bridging element 107, passive component 109, and multiple pillar interconnects 162 may be located between the metallized portion 102 and the metallized portion 104.

[0181] This method (at 1825) couples the integrated device to the second metallization portion. Figure 15C Phase 6 illustrates the state after integrated device 103 is coupled to metallized portion 104 via multiple solder interconnects 130. Phase 6 also illustrates the state after integrated device 105 is coupled to metallized portion 104 via multiple solder interconnects 150. One or more solder reflow processes can be used to couple integrated device 103 and / or integrated device 105 to metallized portion 104 via multiple solder interconnects.

[0182] This method (at 1830) forms an encapsulation layer. Figure 15CStage 7 illustrates the state after the encapsulation layer 108 has been formed and coupled to the metallized portion 104, integrated device 103, and integrated device 105. The encapsulation layer 108 may at least partially encapsulate integrated device 103 and integrated device 105. The encapsulation layer 108 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 108 may be a component for encapsulation. The encapsulation layer 108 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0183] The method (at 1835) decouples the carrier and then (at 1835) couples multiple solder interconnects to the first metallization portion. Figure 15D Stage 8 illustrates the state after the carrier 1110 is decoupled from the metallized portion 102. The carrier 1110 may be a second carrier. The carrier 1110 may be detached and / or peeled off from the metallized portion 102.

[0184] Figure 15D Phase 9 illustrates the state after multiple solder interconnects 182 are coupled to metallized portions 102 via a solder reflow process. The multiple solder interconnects 182 can be coupled to multiple metallized interconnects 122. Phase 9 may also illustrate a package 400 including two metallized portions and a bridging element located between the two metallized portions.

[0185] In some implementations, several packages are manufactured simultaneously. In such cases, the method allows for the individual cutting of the packages.

[0186] Exemplary process for manufacturing metallized parts

[0187] In some specific implementations, manufacturing the metallized parts involves several processes. Figures 19A to 19B Exemplary processes for providing or manufacturing metallized portions are illustrated. In some specific implementations, Figures 19A to 19B The process can be used to provide or manufacture the metallized part 102. However, it can be used... Figures 19A to 19B The process used to manufacture any of the metallized portions (e.g., 104, 204) described in this disclosure.

[0188] It should be noted that Figures 19A to 19B The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the metallized portion. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the scope of this disclosure.

[0189] like Figure 12A As shown, stage 1 illustrates the state after the provision and / or formation of the carrier 1902, the integrated device 101, and the encapsulation layer 106.

[0190] Phase 2 illustrates the state after the dielectric layer 1910 is formed over the integrated device 101 and the encapsulation layer 106. The dielectric layer 1910 may include a plurality of openings 1911. The dielectric layer 1910 may be formed using deposition processes and / or lamination processes. The dielectric layer 1910 may include a prepreg. The plurality of openings 1911 may be formed using etching processes (e.g., photolithography) or laser processes. For example, the plurality of openings 1911 may be formed using exposure and development processes.

[0191] Phase 3 illustrates the state after a plurality of interconnects 1912 have been formed in and above the dielectric layer 1910 (including in and above the plurality of openings 1911). For example, via interconnects, pad interconnects, and / or trace interconnects may be formed. Plating processes may be used to form the interconnects. Phase 3 illustrates that some portions of the interconnects 1912 may have a U-shape or a V-shape. The terms “U-shape” and “V-shape” should be used interchangeably. The terms “U-shape” and “V-shape” may refer to the side profile shape of the interconnect and / or redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0192] like Figure 19B As shown, stage 4 illustrates the state after dielectric layer 1920 is formed over dielectric layer 1910. Dielectric layer 1920 may include a plurality of openings 1921. Dielectric layer 1920 may be formed using deposition and / or lamination processes. Dielectric layer 1920 may include prepreg. The plurality of openings 1921 may be formed using etching processes (e.g., photolithography) or laser processes. For example, the plurality of openings 1921 may be formed using exposure and development processes.

[0193] Phase 5 illustrates the state after multiple interconnects 1922 have been formed in and above the dielectric layer 1920 (including in and above the multiple openings 1921). For example, via interconnects, pad interconnects, and / or trace interconnects may be formed. Plating processes may be used to form the interconnects. Phase 5 illustrates that some portions of the interconnects 1922 may have a U-shape or a V-shape. The terms “U-shape” and “V-shape” should be used interchangeably. The terms “U-shape” and “V-shape” may refer to the side profile shape of the interconnect and / or redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0194] Note that the process of forming the dielectric layer, multiple openings, and multiple interconnects can be performed iteratively to form additional metal layers in the metallized portion.

[0195] Different implementations may use different processes to form the metal layers and / or interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the metal layers.

[0196] Exemplary electronic devices

[0197] Figure 20 Examples are illustrated of various electronic devices that may integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 2002, laptop computer device 2004, fixed-location terminal device 2006, wearable device 2008, or motor vehicle 2010 may include device 2000 as described herein. For example, device 2000 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 20 The illustrated devices 2002, 2004, 2006, and 2008, as well as vehicle 2010, are merely exemplary. Other electronic devices may also feature device 2000, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0198] Figures 1 to 10 , Figures 11A to 11D , Figures 12A to 12E , Figures 13A to 13C , Figure 14 , Figures 15A to 15D , Figures 16A to 16F , Figures 17A to 17D , Figure 18 , Figures 19A to 19B as well as Figure 20One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 10 , Figures 11A to 11D , Figures 12A to 12E , Figures 13A to 13C , Figure 14 , Figures 15A to 15D , Figures 16A to 16F , Figures 17A to 17D , Figure 18 , Figures 19A to 19B as well as Figure 20 The corresponding descriptions herein are not limited to bare dies and / or ICs. In some specific implementations, Figures 1 to 10 , Figures 11A to 11D , Figures 12A to 12E , Figures 13A to 13C , Figure 14 , Figures 15A to 15D , Figures 16A to 16F , Figures 17A to 17D , Figure 18 , Figures 19A to 19B as well as Figure 20 The descriptions and their corresponding information can be used to fabricate, build, provide, and / or produce equipment and / or integrated devices. In some specific implementations, the equipment may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0199] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0200] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. An object coupled to another object may be coupled to at least a portion of another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "on top of" as used in the context of one component being on top of another component in this application can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component on top of second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or entirely located in the second component.As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "A plurality of" components may include all possible components or only some of all possible components. For example, if the device comprises ten components, the use of the term "a plurality of components" may refer to all ten components or only some of those ten components.

[0201] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0202] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0203] Further examples are described below to facilitate understanding of this disclosure.

[0204] Aspect 1: A package comprising a first metallization portion, the first metallization portion including: at least one first dielectric layer; and a first plurality of metallized interconnects; a first integrated device coupled to the first metallization portion; a bridging member coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; and a second metallization portion coupled to the bridging member and the encapsulation layer such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: at least one second dielectric layer; and a second plurality of metallized interconnects; and a second integrated device coupled to the second metallization portion, wherein the second integrated device at least partially vertically overlaps the bridging member.

[0205] Aspect 2: The package according to aspect 1, wherein the bridging element comprises: a silicon substrate; and a plurality of bridging interconnects.

[0206] Aspect 3: The package according to aspects 1 to 2, wherein the first integrated device includes a first chiplet, and the second integrated device includes a second chiplet.

[0207] Aspect 4: The package according to aspects 1 to 3, wherein the first metallization portion includes a first redistribution portion, wherein the first plurality of metallized interconnects includes a first plurality of redistributed interconnects, wherein the second metallization portion includes a second redistribution portion, and wherein the second plurality of metallized interconnects includes a second plurality of redistributed interconnects.

[0208] Aspect 5: The package according to aspects 1 to 4 further includes a plurality of pillar interconnects located at least partially in the encapsulation layer.

[0209] Aspect 6: The package according to aspects 1 to 5, wherein the electrical path between the first integrated device and the second integrated device includes the first metallization portion, the bridging member and the second metallization portion.

[0210] Aspect 7: The package according to aspects 1 to 6, wherein the bridging interconnect of the bridging member is coupled to the metallized interconnect from the first metallized portion, without any intermediate solder interconnect.

[0211] Aspect 8: The package according to aspects 1 to 7, wherein the first integrated device is coupled to a metallized interconnect from the first metallized portion, without any intermediate solder interconnect.

[0212] Aspect 9: The package according to aspects 1 to 8 further includes a second encapsulation layer coupled to the second metallization portion and the second integrated device.

[0213] Aspect 10: The package according to aspect 9 further includes a plurality of pillar interconnects located at least partially in the second encapsulation layer.

[0214] Aspect 11: The package according to aspects 9 to 10 further includes a third metallization portion coupled to the second encapsulation layer.

[0215] Aspect 12: The package according to aspects 9 to 11 further includes a substrate coupled to the second encapsulation layer.

[0216] Aspect 13: The package according to aspect 12, wherein the substrate is coupled to a plurality of pillar interconnects via a plurality of solder interconnects.

[0217] Aspect 14: The package according to aspects 12 to 13 further includes a third integrated device coupled to the substrate.

[0218] Aspect 15: The package according to aspects 1 to 14 further includes a plurality of pillar interconnects located at least partially in the encapsulation layer, wherein the plurality of pillar interconnects includes a first pitch, and wherein the bridging element includes a plurality of bridging interconnects, wherein the plurality of bridging interconnects includes a second pitch smaller than the first pitch.

[0219] Aspect 16: The package according to aspect 15, wherein the second pitch of the plurality of bridging interconnects is approximately 1 / 2 to 1 / 10 of the first pitch of the plurality of pillar interconnects.

[0220] Aspect 17: The package according to aspects 1 to 16, wherein the package is implemented in a device selected from the group consisting of: music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, and device in motor vehicle.

[0221] Aspect 18: A package comprising a first metallization portion, the first metallization portion including: at least one first dielectric layer; and a first plurality of metallized interconnects; a first integrated device coupled to the first metallization portion via at least a first plurality of solder interconnects; a bridging member coupled to the first metallization portion via at least a second plurality of solder interconnects; an encapsulation layer coupled to the first metallization portion; and a second metallization portion coupled to the bridging member and the encapsulation layer such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: at least one second dielectric layer; a second plurality of metallized interconnects; and a second integrated device coupled to the second metallization portion via at least a third plurality of solder interconnects, wherein the second integrated device at least partially vertically overlaps the bridging member.

[0222] Aspect 19: The package according to aspect 18, wherein the bridging element comprises: a silicon substrate; and a plurality of bridging interconnects.

[0223] Aspect 20: The package according to aspects 18 to 19, wherein the first integrated device includes a first chiplet, and the second integrated device includes a second chiplet.

[0224] Aspect 21: The package according to aspects 18 to 20, wherein the first metallization portion includes a first redistribution portion, wherein the first plurality of metallized interconnects includes a first plurality of redistributed interconnects, wherein the second metallization portion includes a second redistribution portion, and wherein the second plurality of metallized interconnects includes a second plurality of redistributed interconnects.

[0225] Aspect 22: The package according to aspects 18 to 21 further includes a plurality of pillar interconnects located at least partially in the encapsulation layer.

[0226] Aspect 23: The package according to aspects 18 to 22, wherein the electrical path between the first integrated device and the second integrated device includes solder interconnects from the first plurality of solder interconnects, the first metallization portion, solder interconnects from the second plurality of solder interconnects, the bridging element, the second metallization portion, and solder interconnects from the third plurality of solder interconnects.

[0227] Aspect 24: The package according to aspects 18 to 23 further includes a second encapsulation layer coupled to the second metallization portion and the second integrated device.

[0228] Aspect 25: The package according to aspect 24 further includes a plurality of pillar interconnects located at least partially in the second encapsulation layer.

[0229] Aspect 26: The package according to aspects 24 to 25 further includes a third metallization portion coupled to the second encapsulation layer.

[0230] Aspect 27: The package according to aspects 24 to 26 further includes a substrate coupled to the second encapsulation layer.

[0231] Aspect 28: The package according to aspect 27 further includes a plurality of pillar interconnects located in the second encapsulation layer, wherein the substrate is coupled to the plurality of pillar interconnects via a fourth plurality of solder interconnects.

[0232] Aspect 29: The package according to aspect 28 further includes a third integrated device coupled to the substrate.

[0233] Aspect 30: The package according to aspects 18 to 29 further includes a plurality of pillar interconnects located at least partially in the encapsulation layer, wherein the plurality of pillar interconnects includes a first pitch, and wherein the bridging element includes a plurality of bridging interconnects, wherein the plurality of bridging interconnects includes a second pitch smaller than the first pitch.

[0234] Aspect 31: The package according to aspect 30, wherein the second pitch of the plurality of bridging interconnects is approximately 1 / 2 to 1 / 10 of the first pitch of the plurality of pillar interconnects.

[0235] Aspect 32: The package according to aspects 18 to 31, wherein the package is implemented in a device selected from the group consisting of: music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, and device in motor vehicle.

[0236] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, the package comprising: The first metallization portion includes: At least one first dielectric layer; and The first multiple metallized interconnects; A first integrated device, the first integrated device being coupled to the first metallized portion; A bridging element coupled to the first metallized portion; An encapsulation layer coupled to the first metallization portion; A second metallization portion, coupled to the bridging member and the encapsulation layer, such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: At least one second dielectric layer; and The second plurality of metallized interconnects; and A second integrated device coupled to the second metallized portion, wherein the second integrated device at least partially overlaps vertically with the bridging member.

2. The package according to claim 1, wherein the bridging element comprises: silicon substrate; as well as Multiple bridging interconnects.

3. The package according to claim 1, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

4. The packaging component according to claim 1, The first metallized portion includes a first redistribution portion. The first plurality of metallized interconnects include a first plurality of redistributed interconnects. The second metallization portion includes a second redistribution portion, and The second plurality of metallized interconnects includes a second plurality of redistributed interconnects.

5. The package of claim 1, further comprising a plurality of pillar interconnects at least partially located in the encapsulation layer.

6. The package of claim 1, wherein the electrical path between the first integrated device and the second integrated device comprises the first metallized portion, the bridging member, and the second metallized portion.

7. The package of claim 1, wherein the bridging interconnect of the bridging member is coupled to the metallized interconnect from the first metallized portion, without any intermediate solder interconnect.

8. The package of claim 1, wherein the first integrated device is coupled to a metallized interconnect from the first metallized portion, without any intermediate solder interconnects.

9. The package of claim 1, further comprising a second encapsulation layer coupled to the second metallization portion and the second integrated device.

10. The package of claim 9, further comprising a plurality of pillar interconnects at least partially located in the second encapsulation layer.

11. The package of claim 9, further comprising a third metallization portion coupled to the second encapsulation layer.

12. The package of claim 9, further comprising a substrate coupled to the second encapsulation layer.

13. The package of claim 12, wherein the substrate is coupled to a plurality of pillar interconnects via a plurality of solder interconnects.

14. The package of claim 12, further comprising a third integrated device coupled to the substrate.

15. The package of claim 1, further comprising a plurality of pillar interconnects at least partially located within the encapsulation layer. The plurality of column interconnects includes a first pitch, and The bridging element includes a plurality of bridging interconnects, the plurality of bridging interconnects including a second pitch smaller than the first pitch.

16. The package of claim 15, wherein the second pitch of the plurality of bridging interconnects is approximately 1 / 2 to 1 / 10 of the first pitch of the plurality of pillar interconnects.

17. The package of claim 1, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

18. A package comprising: The first metallization portion includes: At least one first dielectric layer; and The first multiple metallized interconnects; A first integrated device, the first integrated device being coupled to the first metallized portion via at least a first plurality of solder interconnects; A bridging element coupled to the first metallized portion via at least a second plurality of solder interconnects; An encapsulation layer coupled to the first metallization portion; A second metallization portion, coupled to the bridging member and the encapsulation layer, such that the first integrated device, the bridging member, and the encapsulation layer are located between the first metallization portion and the second metallization portion, wherein the second metallization portion includes: At least one second dielectric layer; and The second plurality of metallized interconnects; and A second integrated device is coupled to the second metallized portion via at least a third plurality of solder interconnects, wherein the second integrated device at least partially overlaps vertically with the bridging element.

19. The package of claim 18, wherein the bridging element comprises: silicon substrate; as well as Multiple bridging interconnects.

20. The package of claim 18, wherein the first integrated device comprises a first chiplet, and the second integrated device comprises a second chiplet.

21. The package according to claim 18, The first metallized portion includes a first redistribution portion. The first plurality of metallized interconnects include a first plurality of redistributed interconnects. The second metallization portion includes a second redistribution portion, and The second plurality of metallized interconnects includes a second plurality of redistributed interconnects.

22. The package of claim 18, further comprising a plurality of pillar interconnects at least partially located in the encapsulation layer.

23. The package of claim 18, wherein the electrical path between the first integrated device and the second integrated device includes solder interconnects from the first plurality of solder interconnects, the first metallization portion, solder interconnects from the second plurality of solder interconnects, the bridging element, the second metallization portion, and solder interconnects from the third plurality of solder interconnects.

24. The package of claim 18, further comprising a second encapsulation layer coupled to the second metallization portion and the second integrated device.

25. The package of claim 24, further comprising a plurality of pillar interconnects at least partially located in the second encapsulation layer.

26. The package of claim 24, further comprising a third metallization portion coupled to the second encapsulation layer.

27. The package of claim 24, further comprising a substrate coupled to the second encapsulation layer.

28. The package of claim 27, further comprising a plurality of pillar interconnects located in the second encapsulation layer, wherein the substrate is coupled to the plurality of pillar interconnects via a fourth plurality of solder interconnects.

29. The package of claim 28, further comprising a third integrated device coupled to the substrate.

30. The package of claim 18, further comprising a plurality of pillar interconnects at least partially located within the encapsulation layer. The plurality of column interconnects includes a first pitch, and The bridging element includes a plurality of bridging interconnects, the plurality of bridging interconnects including a second pitch smaller than the first pitch.

31. The package of claim 30, wherein the second pitch of the plurality of bridging interconnects is approximately 1 / 2 to 1 / 10 of the first pitch of the plurality of pillar interconnects.

32. The package of claim 18, wherein the package is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

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