Voltage stabilizing circuit

Abstract

The invention relates to a voltage stabilizing circuit. A voltage stabilizing circuit comprises a slow loop circuit and a fast loop circuit. The slow loop circuit comprises a first transistor and an amplifier, and the first transistor is coupled between the output end and the first node and used for adjusting the first voltage of the output end. The first voltage is a regulated supply voltage. The fast loop circuit includes a plurality of power circuits coupled in parallel between the output terminal and the first node, each of the power circuits including a power transistor coupled between the supply voltage and the output terminal, in which the power circuits adjust a conductivity of the power transistor according to a second voltage of the first node to adjust a first voltage of the output terminal.

Description

Technical Field

[0001] This disclosure relates to a voltage regulator circuit, and more particularly to a current regulator circuit with a low dropout voltage regulator. Background Technology

[0002] Voltage regulators provide two functions: converting input voltage into output voltages with different voltage levels, and maintaining output voltage stability. Low-dropout voltage regulators (LDOs) are linear regulators designed for applications with low input-output voltage differences and are suitable for low- to medium-power devices. Power supply rejection ratio (PSRR) is a measure of the performance of a low-dropout regulator. PSRR reflects the ability of a low-dropout regulator to maintain a stable output voltage despite noise and voltage fluctuations. The PSRR of low-dropout regulators is particularly important for audio circuits, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Summary of the Invention

[0003] This disclosure provides a voltage regulator circuit comprising a slow-loop circuit and a fast-loop circuit. The slow-loop circuit includes a first transistor and an amplifier. The first transistor is coupled between an output terminal and a first node to adjust a first voltage at the output terminal. The first voltage serves as a regulated power supply voltage. The fast-loop circuit includes multiple power circuits coupled in parallel between the output terminal and the first node. Each of these power circuits includes a power transistor coupled between the supply voltage and the output terminal. The power circuits adjust the conduction of the power transistor according to a second voltage at the first node to adjust the first voltage at the output terminal.

[0004] This disclosure provides a voltage regulator circuit including a first transistor, an operational amplifier, and a fast-loop circuit. The first transistor is coupled between the output terminal of the voltage regulator circuit and a first node. The output voltage of the output terminal is used as a regulated power supply voltage. The operational amplifier is used to adjust the voltage at the control terminal of the first transistor according to fluctuations in a reference voltage, thereby adjusting the output voltage. The fast-loop circuit includes multiple power circuits coupled in parallel between the output terminal of the voltage regulator circuit and the first node, wherein these power circuits are used to receive the supply voltage and adjust the conduction level of the power transistor between the supply voltage and the output terminal of the voltage regulator circuit according to the voltage of the first node, thereby adjusting the output voltage. Attached Figure Description

[0005] The appearance of one embodiment of this invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0006] Figure 1 This is a schematic diagram of a circuit according to some embodiments of the present disclosure;

[0007] Figure 2 Based on some embodiments disclosed herein Figure 1 A schematic diagram of the circuit configuration;

[0008] Figure 3 Based on some embodiments disclosed herein Figures 1 to 2 A schematic diagram of the circuit configuration; and

[0009] Figure 4 Based on some embodiments disclosed herein Figures 1 to 3 A schematic diagram of the circuit configuration. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of elements and arrangements described below are used to simplify one embodiment of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0011] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. Examples used in this specification, including examples of any terms discussed herein, are merely illustrative and are in no way intended to limit the scope or meaning of any embodiment of this invention or any exemplary terminology. Similarly, an embodiment of this invention is not limited to the various embodiments given in this specification.

[0012] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0013] As used herein, "approximately," "about," "approximately," or "substantially" should generally refer to any approximation of a given value or range, which varies depending on the various fields involved, and its scope should be consistent with the broadest interpretation understood by those skilled in the art to cover all such modifications and similar structures. In some embodiments, it should generally refer to within twenty percent of a given value or range, preferably within ten percent, more preferably within five percent. The numerical values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms "approximately," "about," "approximately," or "substantially," or other approximations, can be inferred.

[0014] This disclosure relates to a low-dropout regulator (LDO) circuit. A low-dropout regulator converts a higher input voltage into a lower output voltage. According to some embodiments, the output voltage of the low-dropout regulator can serve as a stable DC voltage power supply.

[0015] refer to Figure 1 , Figure 1 This is a schematic diagram of circuit 10 according to some embodiments of the present disclosure. In application, circuit 10 is a regulator device. In some embodiments, circuit 10 is a low-dropout regulator. In some embodiments, circuit 10 is an integrated circuit (IC).

[0016] Circuit 10 receives voltage VDD, converts VDD into voltage VOUT, and outputs voltage VOUT at its output terminal OUT as a voltage source for the load circuit. In some embodiments, voltage VDD is a power supply voltage. In some embodiments, voltage VDD is a DC power supply. In some embodiments, voltage VDD is higher than the ground voltage.

[0017] The circuit 10 disclosed herein is configured to reduce the power supply rejection ratio (PSRR). In some embodiments, the PSRR of circuit 10 is defined as:

[0018]

[0019] Where ΔVDD represents the change in voltage VDD, and ΔVOUT represents the change in voltage VOUT. PSRR reflects the proportion of the change in voltage VDD corresponding to the change in voltage VOUT. PSRR is expressed in decibels (dB). A higher PSRR indicates a higher ability to suppress power supply fluctuations or noise.

[0020] In terms of description, circuit 10 includes a slow loop circuit 100, a fast loop circuit 200, a fixed current circuit 300, a low-pass filter bias circuit 400, an output capacitor CL, and a load resistor RL.

[0021] The slow-loop circuit 100 is coupled to the output terminal OUT of the circuit 10. The slow-loop circuit 100 is used to regulate the voltage VOUT so that the voltage VOUT has a target voltage value v1. The target voltage value v1 is the voltage value of the voltage source that the circuit 10 wants to provide.

[0022] In some embodiments, the slow-loop circuit 100 is used to adjust the voltage VOUT at the output terminal OUT according to the reference voltage VREF. In some embodiments, the voltage value of the reference voltage VREF is equal to the target voltage value v1. Specifically, when the slow-loop circuit 100 determines that the voltage VOUT is higher than the reference voltage VREF, the slow-loop circuit 100 pulls the voltage VOUT low. Conversely, when the slow-loop circuit 100 determines that the voltage VOUT is lower than the reference voltage VREF, the slow-loop circuit 100 pulls the voltage VOUT high.

[0023] The slow-loop circuit 100 is coupled to the fixed-current circuit 300. Specifically, as follows... Figure 1 As shown, the slow-loop circuit 100 and the fixed-current circuit 300 are coupled to each other at node N1. The output terminal OUT is coupled to ground through the slow-loop circuit 100, node N1, and the fixed-current circuit 300. In some embodiments, the slow-loop circuit 100 is used to adjust its conductivity between the output terminal OUT and node N1 to adjust the voltage VOUT. In some embodiments, the fixed-current circuit 300 provides the current flowing through the output terminal OUT, node N1, and ground between node N1 and ground. In some embodiments, ground has a voltage value of 0 volts.

[0024] In some embodiments, the slow-loop circuit 100 includes a transistor 101 and an amplifier EA. In some embodiments, the transistor 101 is a P-type metal-oxide-semiconductor field-effect transistor (PMOS). The amplifier EA is an operational amplifier (OP amp). In some embodiments, the amplifier EA is an error amplifier.

[0025] like Figure 1 As shown, amplifier EA has a positive input terminal, a negative input terminal, and an output terminal. Amplifier EA generates its output voltage based on the difference between the voltages received at the positive and negative input terminals. For example, amplifier EA subtracts the voltage value at the negative input terminal from the voltage value at the positive input terminal to generate a difference, and generates the output voltage of amplifier EA based on this difference. The value of this output voltage is equal to or proportional to this difference.

[0026] The negative input terminal of amplifier EA is coupled to the output terminal OUT, and the positive input terminal of amplifier EA is coupled to the reference voltage VREF. The control terminal (e.g., gate) of transistor 101 is coupled to the output terminal of amplifier EA. A first terminal (e.g., source) of transistor 101 is coupled to the output terminal OUT, and a second terminal (e.g., drain) of transistor 101 is coupled to node N1.

[0027] Operationally, amplifier EA compares the voltage VOUT at its output terminal OUT with a reference voltage VREF and adjusts the voltage at the control terminal of transistor 101 based on the difference between VOUT and VREF. The conductivity of transistor 101 changes according to the voltage at its control terminal. Simultaneously, the voltage VOUT changes according to the conductivity of transistor 101.

[0028] For example, when the difference between the reference voltage VREF and the voltage VOUT increases, the output voltage of amplifier EA increases. The conduction of transistor 101 decreases in response to the increase in the output voltage of amplifier EA. The voltage VOUT increases in response to the decrease in the conduction of transistor 101. Conversely, when the difference between the reference voltage VREF and the voltage VOUT decreases, the output voltage of amplifier EA decreases. The conduction of transistor 101 increases in response to the decrease in the output voltage of amplifier EA. The voltage VOUT decreases in response to the increase in the conduction of transistor 101.

[0029] In some embodiments, the fixed current circuit 300 includes a transistor 301, a resistor R0, and a capacitor C0. In some embodiments, the transistor 301 is an N-type metal-oxide-semiconductor field-effect transistor (NMOS).

[0030] like Figure 1As shown, a first terminal (e.g., the source) of transistor 301 is coupled to ground, and a second terminal (e.g., the drain) of transistor 301 is coupled to node N1. A resistor R0 is coupled between the control terminal (e.g., the gate) of transistor 301 and a voltage VBN. A capacitor C0 is coupled between the control terminal of transistor 301 and ground. Resistor R0 and capacitor C0 act as a low-pass filter between voltage VBN and transistor 301 to provide bias to transistor 301. Transistor 301 turns on in response to this bias, diverting current from node N1 to ground. In some embodiments, voltage VBN is a bias voltage.

[0031] The output capacitor CL and the load resistor RL are connected in parallel between the output terminal OUT and ground. The load resistor RL is the load resistance of circuit 10, representing the load impedance of the circuit connected downstream of the output terminal. In some embodiments, the load resistor RL may vary depending on the circuit application. The output capacitor CL filters out ripple at the output terminal OUT.

[0032] Fast-loop circuit 200 is coupled to output terminal OUT and slow-loop circuit 100. Fast-loop circuit 200 is used to adjust the output voltage VOUT in response to instantaneous voltage transients at output terminal OUT. Specifically, when voltage VOUT rises, fast-loop circuit 200 pulls voltage VOUT down, and when voltage VOUT falls, fast-loop circuit 200 pulls voltage VOUT up.

[0033] According to some embodiments, compared to the slow-loop circuit 100, the fast-loop circuit 200 has a faster response speed, that is, it adjusts the output voltage VOUT more quickly according to the voltage change at the output terminal OUT. Therefore, when a large instantaneous voltage change occurs at the output terminal OUT, the circuit 10 can adjust the voltage VOUT in real time by means of the fast-loop circuit 200.

[0034] In some embodiments, the fast-loop circuit 200 is coupled to node N1 and adjusts the output voltage VOUT in response to voltage changes at node N1.

[0035] In some embodiments, the fast-loop circuit 200 includes a plurality of power circuits 210. The plurality of power circuits 210 are connected in parallel between node N1 and output terminal OUT. Each power circuit 210 includes transistors 211, 212, and 213. In some embodiments, transistors 211, 212, and 213 are PMOS transistors. In some embodiments, transistor 213 is a power transistor (power MOS).

[0036] like Figure 1As shown, the control terminal (e.g., gate) of transistor 211 is coupled to node N1. A first terminal (e.g., source) of transistor 211 is coupled to a node N2 of each of the power circuits 210, and a second terminal (e.g., drain) of transistor 211 is coupled to ground.

[0037] The control terminal (e.g., gate) of transistor 212 is coupled to a low-pass filter bias circuit 400. A first terminal (e.g., source) of transistor 212 is coupled to a voltage VDD. In some embodiments, voltage VDD is a power supply voltage. In some embodiments, voltage VDD is higher than ground. A second terminal (e.g., drain) of transistor 212 is coupled to node N2.

[0038] The control terminal (e.g., gate) of transistor 213 is coupled to node N2. A first terminal (e.g., source) of transistor 213 is coupled to voltage VDD, and a second terminal (e.g., drain) of transistor 213 is coupled to output terminal OUT.

[0039] Transistor 211 and transistor 212 are connected in series between voltage VDD and ground. Transistor 212 provides current flowing through node N2 via transistor 211 to ground, thereby generating a voltage at node N2 between transistor 211 and transistor 212.

[0040] Transistor 211 adjusts the voltage value of node N2 based on the voltage value of node N1. According to some embodiments, transistor 211 acts as a source follower, with its source voltage following fluctuations in the gate voltage. In some embodiments, the conduction of transistor 211 decreases in response to a rise in the voltage of node N1, and the voltage of node N2 rises in response to a decrease in the conduction of transistor 211. Conversely, the conduction of transistor 211 rises in response to a fall in the voltage of node N1, and the voltage of node N2 falls in response to a rise in the conduction of transistor 211.

[0041] The conduction of transistor 212 is determined by a bias voltage provided to the control terminal of transistor 212 by a low-pass filter bias circuit 400. In some embodiments, the low-pass filter bias circuit 400 includes a resistor R1 and a capacitor C1. Resistor R1 is coupled between the control terminal of transistor 212 in each power circuit 210 and a voltage VBP, and capacitor C1 is coupled between the control terminal of transistor 212 in each power circuit 210 and ground. Resistor R1 and capacitor C1 act as a low-pass filter between voltage VBP and transistor 212 to provide bias voltage to transistor 212. Transistor 212 conducts in response to this bias voltage to generate a voltage at node N2. In some embodiments, voltage VBP is a bias voltage.

[0042] Transistor 213, slow-loop circuit 100, and fixed-current circuit 300 are connected in series between voltage VDD and ground, and generate voltage VOUT at output terminal OUT through the slow loop. Transistor 213 conducts according to the voltage at node N2. Specifically, the conduction of transistor 213 decreases in response to an increase in the voltage at node N2, and voltage VOUT decreases in response to a decrease in the conduction of transistor 211. The conduction of transistor 211 increases in response to a decrease in the voltage at node N1, and the voltage at node N2 decreases in response to an increase in the conduction of transistor 211.

[0043] In some embodiments, the fast-loop circuit 200 suppresses higher-frequency voltage VDD fluctuations or noise compared to the slow-loop circuit 100.

[0044] By configuring transistors 211 to 213 in the fast-loop circuit 200, when the voltage VDD fluctuates at high frequencies, the voltage at node N2 follows the fluctuations of the voltage VDD. For example, when the voltage VDD fluctuates at high frequencies, the low-pass filter bias circuit 400 provides a relatively constant bias voltage to the gate terminal of transistor 212. Therefore, the high-frequency fluctuations of VDD can be reflected at node N2, allowing the gate voltage of transistor 213 to follow the high-frequency fluctuations of VDD. This ensures that the output voltage OUT is not affected by the high-frequency fluctuations of VDD, achieving a good power supply rejection ratio.

[0045] According to some embodiments, by having the voltage of node N2 follow the fluctuations of voltage VDD, the power circuit 210 maintains a fixed voltage difference between the source and gate voltages of transistor 213 to maintain voltage VOUT with a target voltage value v1, thereby improving the PSRR of circuit 10. In some embodiments, the voltage fluctuation of node N2 is equal to the voltage fluctuation of voltage VDD, and the voltage difference between the source and gate voltages of transistor 213 is zero.

[0046] By connecting multiple power circuits 210 in parallel, the gate parasitic capacitance of the power transistor (e.g., transistor 213) observed from node N2 is reduced, and the pole of node N2 on the Bode plot shifts to higher frequencies, making circuit 10 more stable. Furthermore, the reduction in parasitic capacitance at node N2 improves the ability of the voltage at node N2 to follow voltage fluctuations at high frequencies, further enhancing the PSRR of circuit 10.

[0047] Compared to some methods, the parallel architecture of multiple power circuits 210 avoids the need for power transistors connected in series. This avoids the accumulation of offset voltage between power transistors, thus preventing poor yield problems caused by differences in current among each power transistor.

[0048] refer to Figure 2 , Figure 2 Based on some embodiments disclosed herein Figure 1 A schematic diagram of circuit 20 configured with circuit 10. Relative to... Figure 1 In the embodiments described, for ease of understanding, Figure 2 Similar components are identified by the same reference number. For the sake of brevity, the specific operations of similar components, which have been discussed in detail in the preceding paragraphs, are omitted in this article.

[0049] Compared to Figure 1 Circuit 10, Figure 2 The circuit 20 further includes transistor 501, transistors 511-513, transistor 521, resistor R2, and capacitor C2. In some embodiments, transistor 501 is an NMOS. Transistors 511-513 and 521 are PMOS. Transistor 513 is a power transistor.

[0050] In other words, unlike the slow-loop circuit 100 of circuit 10, the slow-loop circuit 100 of circuit 20 is coupled between transistors 501 and 513. For example... Figure 2 As shown, the first terminal (e.g., the source) of transistor 101 is coupled to node N3 between transistors 101 and 513, and the second terminal (e.g., the drain) of transistor 101 is coupled to the first terminal (e.g., the drain) of transistor 501. The second terminal (e.g., the source) of transistor 501 is coupled to ground.

[0051] The negative input terminal of amplifier EA is coupled to node N3. The positive input terminal of amplifier EA is coupled to the reference voltage VREF. The output terminal of amplifier EA is coupled to the control terminal (e.g., gate) of transistor 101.

[0052] The control terminal (e.g., gate) of transistor 511 is coupled to the second terminal of transistor 101 and the first terminal of transistor 501. The first terminal (e.g., source) of transistor 511 is coupled to node N4, and the second terminal (e.g., drain) of transistor 511 is coupled to ground.

[0053] The control terminal (e.g., gate) of transistor 512 is coupled to voltage VBP. The first terminal (e.g., source) of transistor 512 is coupled to voltage VDD, and the second terminal (e.g., drain) of transistor 512 is coupled to node N4.

[0054] The control terminal (e.g., gate) of transistor 513 is coupled to node N4. The first terminal (e.g., source) of transistor 513 is coupled to voltage VDD, and the second terminal (e.g., drain) of transistor 512 is coupled to node N3.

[0055] The first terminal (e.g., the source) of transistor 521 is output as OUT, and the second terminal (e.g., the drain) of transistor 521 is coupled to a fixed-current circuit 300. For example, the second terminal of transistor 521 is coupled to the second terminal (e.g., the drain) of transistor 301.

[0056] Resistor R2 is coupled between the control terminal (e.g., gate) of transistor 521 and the output terminal of amplifier EA. Capacitor C2 is coupled between the control terminal of transistor 521 and ground.

[0057] In operation, unlike the slow-loop circuit 100 of circuit 10, the slow-loop circuit 100 of circuit 20 adjusts the voltage of node N3 and voltage VOUT simultaneously based on the comparison between the reference voltage VREF and the voltage of node N3.

[0058] Specifically, amplifier EA compares the voltage at node N3 with the reference voltage VREF and generates its output voltage based on the difference between the voltage at node N3 and the reference voltage VREF. The conduction of transistor 101 changes according to the output voltage of amplifier EA. The voltage at node N3 changes according to the conduction of transistor 101.

[0059] Simultaneously, the control terminal of transistor 521 receives the output voltage of amplifier EA through resistor R2. The conduction of transistor 521 changes according to the output voltage of amplifier EA. The voltage VOUT changes according to the conduction of transistor 521.

[0060] For example, when the difference between the reference voltage VREF and the voltage at node N3 increases, the output voltage of amplifier EA increases. The conduction of transistors 101 and 521 decreases in response to the increase in the output voltage of amplifier EA. The voltage at node N3 and voltage VOUT increase in response to the decrease in the conduction of transistor 101. Conversely, when the difference between the reference voltage VREF and the voltage at node N3 decreases, the output voltage of amplifier EA decreases. The conduction of transistors 101 and 521 increases in response to the decrease in the output voltage of amplifier EA. The voltage at node N3 and voltage VOUT decrease in response to the increase in the conduction of transistor 101.

[0061] Transistors 511-513 are used in concert to adjust the voltage of node N3. The operation of transistors 511-513 is similar to that of transistors 211-213, the difference being that transistors 511-513 are used to adjust the voltage of node N3.

[0062] For example, transistor 512 turns on in response to voltage VBP, and transistor 511 adjusts the voltage of node N4 according to the voltage between transistors 101 and 501. The voltage of node N4 is adjusted by transistor 512 following the fluctuation of voltage VDD.

[0063] In addition, resistor R2 and capacitor C2 serve as a low-pass filter between amplifier EA and transistor 521, which can filter out noise from amplifier EA.

[0064] refer to Figure 3 , Figure 3 Based on some embodiments disclosed herein Figures 1 to 2 A schematic diagram of circuit 30 configured with circuits 10 and 20. Relative to... Figures 1 to 2 In the embodiments described, for ease of understanding, Figure 3 Similar components are identified by the same reference number.

[0065] Compared to Figure 2 Circuit 20, Figure 3 The circuit 30 further includes a transistor 531. In some embodiments, the transistor 531 is a PMOS.

[0066] Unlike circuit 20, the slow-loop circuit 100 of circuit 30 is coupled between voltage VDD and transistor 531. For example, as Figure 3 As shown, the first terminal (e.g., the source) of transistor 101 is coupled to voltage VDD, and the second terminal (e.g., the drain) of transistor 101 is coupled to node N5. The negative input terminal of amplifier EA is coupled to reference voltage VREF. The positive input terminal of amplifier EA is coupled to node N5.

[0067] The first terminal (e.g., source) of transistor 531 is coupled to node N5, and the second terminal (e.g., drain) of transistor 531 is coupled to the first terminal (e.g., drain) of transistor 501. The control terminal (e.g., gate) of transistor 531 is coupled to the second terminal of transistor 531 and resistor R2.

[0068] In operation, unlike the slow-loop circuit 100 of circuit 20, the slow-loop circuit 100 of circuit 30 adjusts the voltage of node N5 based on the comparison between the reference voltage VREF and the voltage of node N5 to maintain the voltage VOUT having the target voltage value v1.

[0069] For example, when voltage VREF decreases, and the difference between the voltage at node N5 and the reference voltage VREF increases, the output voltage of amplifier EA increases. The conduction of transistor 101 decreases in response to the increase in the output voltage of amplifier EA. The voltage at node N5 decreases in response to the decrease in the conduction of transistor 101. The voltage at the control terminal of transistor 521 decreases, and its conduction increases. The voltage VOUT decreases in response to the increase in the conduction of transistor 521.

[0070] Conversely, as voltage VREF rises, the difference between the voltage at node N5 and the reference voltage VREF decreases, causing the output voltage of amplifier EA to decrease. The conduction of transistor 101 increases in response to the decrease in the output voltage of amplifier EA. The voltage at node N5 increases in response to the increase in the conduction of transistor 101. As the voltage at the control terminal of transistor 521 rises, its conduction decreases. The voltage VOUT increases in response to the decrease in the conduction of transistor 521.

[0071] According to some embodiments, the slow loop circuit 100 of circuits 20 and 30 is connected to transistor M521 after passing through a low-pass filter. Therefore, the amplifier OP of circuits 20 and 30 has lower specification requirements, that is, the noise can be lower, thus reducing the circuit area.

[0072] refer to Figure 4 , Figure 4 Based on some embodiments disclosed herein Figures 1 to 3 A schematic diagram of circuit 40 configured with circuits 10 to 30. Relative to Figure 1 To Figure 3 In the embodiments described, for ease of understanding, Figure 4 Similar components are identified by the same reference number.

[0073] According to some embodiments, Figure 1 To Figure 3 The fixed current circuit 300 of circuits 10 to 30 includes a resistor R3, but not a transistor 301, a resistor R0, and a capacitor C0. Resistor R3 is coupled between node N1 and ground.

[0074] Figures 1 to 4 The configuration is provided for illustrative purposes. Figures 1 to 4 Various implementations are within the scope of one embodiment of this invention. For example, in some embodiments, the number of power circuits 210 in the fast-loop circuit 200 is less than four. For instance, the fast-loop circuit 200 includes three power circuits 210 connected in parallel.

[0075] In summary, this disclosure provides a voltage regulator circuit. The voltage regulator circuit employs a feedback control loop architecture to regulate the output voltage. The circuit features a slow-loop circuit to suppress low-frequency power supply fluctuations and noise, and a fast-loop circuit to address high-frequency power supply fluctuations and noise. By connecting multiple source followers and power transistors in parallel, the fast-loop circuit exhibits better power supply fluctuation tracking capability at high frequencies, contributing to improved PSRR of the voltage regulator circuit.

[0076] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this application. Those skilled in the art will understand that one embodiment of this application can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of one embodiment of this application, and that various changes, substitutions, and modifications can be made to one embodiment of this application without departing from the spirit and scope of that application.

[0077] [Symbol Explanation]

[0078] 10: Circuit

[0079] 100: Slow-loop circuit

[0080] 101: Transistor

[0081] 200: Fast-loop circuit

[0082] 210: Power Circuit

[0083] 211: Transistor

[0084] 212: Transistor

[0085] 213: Transistor

[0086] 300: Fixed current circuit

[0087] 301: Transistor

[0088] 400: Low-pass filter bias circuit

[0089] 501: Transistor

[0090] 511: Transistor

[0091] 512: Transistor

[0092] 513: Transistor

[0093] 521: Transistor

[0094] 531: Transistor

[0095] C0: Capacitor

[0096] C1: Capacitor

[0097] C2: Capacitor

[0098] CL: Load capacitor

[0099] EA: Amplifier

[0100] N1: Node

[0101] N2: Node

[0102] N3: Node

[0103] N4: Node

[0104] N5: Node

[0105] OUT: Output terminal

[0106] R0: Resistor

[0107] R1: Resistor

[0108] R2: Resistor

[0109] R3: Resistor

[0110] RL: Load resistor

[0111] VBN: Voltage

[0112] VBP: Voltage

[0113] VDD: Voltage

[0114] VREF: Reference Voltage

Claims

1. A voltage regulator circuit, comprising: A slow-loop circuit includes: A first transistor, coupled between an output terminal and a first node, is used to adjust a first voltage at the output terminal, the first voltage serving as a regulated power supply voltage; and A fast-loop circuit includes: A plurality of power circuits are connected in parallel between the output terminal and the first node, wherein each of the power circuits comprises: A power transistor is coupled between a supply voltage and the output terminal, wherein the power circuit is used to adjust the conduction of the power transistor to adjust the first voltage according to a second voltage of the first node.

2. The voltage regulator circuit according to claim 1, further comprising: A fixed-current circuit for providing a fixed current flowing through the first transistor, wherein the fixed-current circuit includes: A second transistor is coupled between the first node and a ground; A first resistor is coupled between a first bias voltage and a control terminal of the second transistor; and A first capacitor is coupled between the ground and a control terminal of the second transistor.

3. The voltage regulator circuit according to claim 1, wherein the slow loop circuit further comprises: An amplifier, coupled to the output terminal and a reference voltage, wherein one output terminal of the amplifier is coupled to a control terminal of the first transistor. The amplifier is used to adjust the conduction of the first transistor to adjust the first voltage based on a comparison between the first voltage and the reference voltage.

4. The voltage regulator circuit according to claim 1, wherein the power circuit further comprises: A second transistor and a third transistor are connected in series between the supply voltage and ground, wherein a control terminal of the power transistor is coupled to a second node between the second and third transistors. The second transistor adjusts the voltage of the second node according to the second voltage to adjust the conduction of the power transistor.

5. The voltage regulator circuit of claim 4, wherein the second transistor, in response to the increase in the second voltage, increases the voltage of the second node to decrease the first voltage.

6. A voltage regulator circuit, comprising: A first transistor is coupled between an output terminal of the voltage regulator circuit and a first node, wherein an output voltage of the output terminal is used as a regulated power supply voltage. An operational amplifier is used to adjust the voltage at a control terminal of a first transistor according to fluctuations in a reference voltage, thereby adjusting the output voltage; and A fast-loop circuit includes a plurality of power circuits, which are connected in parallel and coupled between the output terminal of the voltage regulator circuit and the first node. The power circuits are used to receive the supply voltage and adjust the continuity between the supply voltage and the output terminal of the voltage regulator circuit according to the voltage of the first node to adjust the output voltage.

7. The voltage regulator circuit according to claim 6, further comprising: A first power transistor is coupled between the supply voltage and a second node; and A second transistor is coupled to the first power transistor, wherein a control terminal of the second transistor is coupled to an output terminal of the operational amplifier. The operational amplifier adjusts the voltage at its output terminal based on the voltage of the second node to adjust the voltage of the second node.

8. The voltage regulator circuit according to claim 7, further comprising: A third transistor is coupled between a ground and a control terminal of the first power transistor, wherein the conduction of the third transistor is based on the voltage at a first terminal of the second transistor; A fourth transistor is coupled between the supply voltage and the control terminal of the first power transistor, wherein the fourth transistor turns on in response to a first bias voltage.

9. The voltage regulator circuit according to claim 6, wherein the power circuit comprises: A first power transistor is coupled between the supply voltage and the output terminal of the voltage regulator circuit; and A second transistor is coupled between a ground and a control terminal of the first power transistor. The first transistor is coupled between the output terminal of the voltage regulator circuit and a control terminal of the second transistor.

10. The voltage regulator circuit according to claim 6, further comprising: A second transistor is coupled between the supply voltage and a second node, wherein a first input terminal of the operational amplifier is coupled to a reference voltage, a second input terminal of the operational amplifier is coupled to the second node, and an output terminal of the operational amplifier is coupled to a control terminal of the second transistor; and A third transistor, wherein a first terminal of the third transistor is coupled to the second node, and a second terminal and a control terminal of the third transistor are coupled to the control terminal of the first transistor through a filter.

Images