Parallel clock interrupt processing method and device suitable for kylin operating system, electronic equipment and storage medium

Abstract

The invention provides a parallel clock interrupt processing method and device suitable for a kylin operating system, electronic equipment and a storage medium, which are applied to a server system connected with a clock interrupt card through a PCIe bus, and can be used for realizing more stable response time of clock interrupt, reduction of interrupt loss conditions and high reliability in a multi-thread multi-frequency parallel scene. The periodical execution of tasks with different frequencies is kept consistent; under the conditions of system load fluctuation and PCIe bus transmission condition change, the continuity and reliability of the interrupt processing process are improved; and the overall interrupt processing efficiency is improved, so that the system has better stability and resource utilization rate when processing a multi-frequency parallel clock task.

Description

Technical Field

[0001] This disclosure relates to the field of server clock interrupt handling technology, and more specifically, to a parallel clock interrupt handling method, apparatus, electronic device, and storage medium applicable to the Kylin operating system. Background Technology

[0002] Server systems typically need to handle clock interrupt signals from external devices or expansion cards to drive applications to perform periodic tasks. In the Kylin operating system environment, clock interrupt handling is jointly handled by user-mode threads and kernel-mode interrupt handling mechanisms. When multiple parallel threads exist in the system and each thread has different frequency requirements for clock interrupts (e.g., high-frequency task threads and low-frequency task threads running simultaneously), the allocation method, processing order, and processing timing of clock interrupts among multiple threads will affect the overall response performance.

[0003] In servers connected to external clock interrupt cards via the PCIe bus, the triggering method, transmission path, and PCIe bus bandwidth usage of the clock interrupt signal all affect the arrival time of the clock interrupt to the processor. Because the transmission delay of the PCIe bus varies under different load conditions, multiple frequency clock interrupts may experience overlapping arrival times, altered arrival order, or unbalanced responses during transmission, thus affecting the execution cycle and stability of application tasks.

[0004] Furthermore, variations in load, CPU core usage, thread priorities, and real-time requirements of different threads during operation can complicate the scheduling of clock interrupts among different threads. When high-frequency and low-frequency threads need to handle clock interrupts simultaneously within a similar timeframe, a lack of proper scheduling management can lead to thread contention for CPU core resources, increased interrupt response latency, or some interrupts failing to be processed on time.

[0005] With the increasing number of applications with high real-time requirements in server systems, the handling, fairness, and stability of clock interrupts in multi-threaded, multi-frequency parallel scenarios have become key factors in system operation. How to maintain interrupt response balance while ensuring the needs of tasks at different frequencies has become one of the typical problems faced by existing technologies. Summary of the Invention

[0006] This disclosure provides at least one parallel clock interrupt handling method, apparatus, electronic device, and storage medium applicable to the Kylin operating system. In multi-threaded, multi-frequency parallel scenarios, the clock interrupt response time is more stable, interrupt loss is reduced, and the periodic execution of tasks at different frequencies remains consistent. Under system load fluctuations and changes in PCIe bus transmission conditions, the continuity and reliability of the interrupt handling process are improved. The overall interrupt handling efficiency is improved, enabling the system to have better stability and resource utilization when handling multi-frequency parallel clock tasks.

[0007] This disclosure provides a parallel clock interrupt handling method suitable for the Kylin operating system, applied to a server system connected to a clock interrupt card via a PCIe bus. The method includes: Obtain clock interrupt handling requirements for multiple threads from the application layer. Based on the clock interrupt handling requirements and thread running status, establish a mapping relationship between clock interrupt lines, CPU cores, and threads. Configure interrupt affinity according to the mapping relationship so that clock interrupt requests from the clock interrupt card are allocated to the target thread according to the mapping relationship. Based on the interrupt frequency of each thread, each interrupt handling thread is assigned to a scheduling queue of the corresponding frequency layer, and the interrupt handling thread is scheduled according to the priority of the frequency layer, so that the interrupt handling thread with a higher frequency will be given priority in resource contention. Based on the interrupt frequency and bus transmission delay, the next trigger time of each clock interrupt is predicted and a corresponding trigger time window is formed. The overlap between the trigger time windows of different frequencies is detected. When the overlap meets the preset conditions, a preset timing avoidance strategy is executed. Based on the number of clock interrupts received per unit time and the bus transmission status, the interrupt trigger configuration of the clock interrupt card is adaptively adjusted in the driver layer, and a scheduling compensation time corresponding to the bus transmission delay is set in the scheduling logic of the interrupt handling thread. Based on the amount of data transmitted in a single clock interrupt at different frequencies and the interrupt frequency, the bandwidth requirement for the PCIe bus is calculated, and bandwidth configuration parameters are sent to the PCIe controller to allocate guaranteed bandwidth for high-frequency interrupts and configure weighted shared bandwidth for medium-frequency and low-frequency interrupts.

[0008] In one optional implementation, obtaining clock interrupt handling requirements for multiple threads at the application layer specifically includes: A requirement parsing module is set up at the application layer to obtain thread creation operation and thread parameter change information by hooking the thread creation interface and the thread configuration interface. Each time a thread is created or its parameters are changed, the thread identifier, target interrupt frequency, task priority, and real-time level of the corresponding thread are read to form the clock interrupt handling requirement information. The clock interrupt handling requirement information is encapsulated into structured data, converted from user mode to kernel mode, and sent to the collaborative scheduling module of the Kylin operating system kernel. The structured data includes at least a thread identifier field, a target interruption frequency field, a task priority field, and a real-time performance level field. The requirement parsing module verifies the target interruption frequency of each thread at a fixed period and immediately triggers a data transmission operation when it detects a change in the target interruption frequency.

[0009] In one optional implementation, establishing a mapping relationship between clock interrupt lines, CPU cores, and threads specifically includes: A multi-factor matching degree model is used to calculate the matching degree between the thread and the clock interrupt resource; The mapping relationship is generated by sorting the clock interrupt line, the CPU core and the thread according to the matching degree; The multi-factor matching model includes: an interrupt frequency requirement factor, which characterizes the level of the target interrupt frequency for each thread; a thread real-time load factor, which characterizes the current load of the CPU core where each thread resides; and a task priority factor, which characterizes the scheduling priority of the application task corresponding to each thread in the operating system.

[0010] In one optional implementation, each interrupt handling thread is assigned a scheduling queue corresponding to its frequency layer based on the interrupt frequency of each thread, specifically including: Based on the interrupt frequency corresponding to each thread, the interrupt handling threads are divided into high-frequency interrupt handling threads, medium-frequency interrupt handling threads, and low-frequency interrupt handling threads: Specifically, threads with interrupt frequencies greater than a first frequency threshold are classified as high-frequency interrupt processing threads, threads with interrupt frequencies less than a second frequency threshold are classified as low-frequency interrupt processing threads, and threads with interrupt frequencies between the first and second frequency thresholds are classified as medium-frequency interrupt processing threads. Independent scheduling queues are established for the high-frequency interrupt handling thread, the medium-frequency interrupt handling thread, and the low-frequency interrupt handling thread, respectively.

[0011] In one optional implementation, the interrupt handling thread is scheduled according to the priority of the frequency layer, specifically including: The scheduling queue containing the high-frequency interrupt handling thread adopts a preemptive scheduling method, the scheduling queue containing the medium-frequency interrupt handling thread adopts a scheduling method combining preemptive scheduling and time-slice round-robin, and the scheduling queue containing the low-frequency interrupt handling thread adopts a time-slice round-robin scheduling method. Queue priorities are set in the order of high frequency layer, medium frequency layer, and low frequency layer. When there is a ready thread in the high frequency layer, the running thread in the medium frequency layer and the low frequency layer is preempted. The time slice length of the medium frequency layer scheduling queue is proportional to the interrupt period corresponding to the thread with the highest interrupt frequency in the queue. The time slice length of the low frequency layer scheduling queue is a fixed time length.

[0012] In one optional implementation, based on the interrupt frequency and bus transmission delay, the next trigger time for each clock interrupt is predicted and a corresponding trigger time window is formed. The overlap between the trigger time windows of different frequencies is detected, specifically including: The corresponding interrupt cycle is calculated based on the interrupt frequency. The trigger time of the previous cycle is superimposed with the interrupt cycle and the current bus transmission delay to obtain the next trigger time. The trigger time window is set with the next trigger time as the center and based on the historical interrupt processing time. Calculate the ratio of the intersection duration of the two trigger time windows to the duration of any one window, compare the ratio with an overlap threshold, and determine that the overlap of the trigger time windows satisfies the preset condition when the ratio is greater than the overlap threshold.

[0013] In one optional implementation, for the detected multi-frequency clock interrupts whose trigger time windows overlap and satisfy the preset conditions, one of the preset timing avoidance strategies is executed: When the real-time performance level of the low-frequency interrupt handling thread is lower than the real-time performance level threshold, the processing start time of the low-frequency interrupt handling thread is postponed to the time point after the corresponding high-frequency interrupt triggering time window ends, and the postponed processing cycle does not exceed the target cycle of the low-frequency interrupt. When the real-time performance level of the low-frequency interrupt handling thread is higher than or equal to the real-time performance level threshold, the high-frequency interrupt handling thread in the conflict window is temporarily suspended, provided that the suspension duration does not exceed the suspension duration threshold. The low-frequency interrupt handling thread is executed first, and the suspended high-frequency interrupt handling thread is resumed after the processing is completed.

[0014] In one optional implementation, the interrupt triggering configuration of the clock interrupt card is adaptively adjusted at the driver layer based on the number of clock interrupts received per unit time and the bus transmission status, specifically including: A sampling period is set in the driver layer, and the number of clock interrupts received from the clock interrupt card is counted in each sampling period to obtain the interrupt flow. When the interrupt traffic is greater than or equal to the first traffic threshold, the interrupt triggering mode of the clock interrupt card is set to edge-triggered mode; When the interrupt flow is less than the second flow threshold, the interrupt triggering mode of the clock interrupt card is set to level triggering mode.

[0015] In one optional implementation, the bandwidth requirement for the PCIe bus is calculated based on the amount of data transmitted in a single clock interrupt at different frequencies and the interrupt frequency, and bandwidth configuration parameters are sent to the PCIe controller, specifically including: The bandwidth requirements of the high-frequency interrupt processing thread, the medium-frequency interrupt processing thread, and the low-frequency interrupt processing thread are calculated based on the interrupt frequency and the corresponding amount of data transmitted in a single interrupt. The high-frequency interrupt handling thread is allocated an independent bandwidth channel through the QoS configuration interface of the PCIe controller, and the bandwidth ratio of the independent bandwidth channel is set to be greater than the bandwidth ratio threshold. Configure weighted round-robin scheduling parameters for the intermediate frequency interrupt handling thread and the low frequency interrupt handling thread, so that the intermediate frequency interrupt handling thread and the low frequency interrupt handling thread share the remaining bandwidth according to the weight of their respective bandwidth requirements.

[0016] In one optional implementation, the method further includes: The interrupt response latency and interrupt loss rate of each interrupt handling thread are statistically analyzed at fixed intervals, and the PCIe bus bandwidth utilization is also statistically analyzed. The statistical results are compared with the response latency threshold, interrupt loss rate threshold, and PCIe bus load threshold issued by the application layer. When the interrupt response delay is greater than the response delay threshold, adjust the clock interrupt line, the mapping relationship between CPU cores and threads, and the corresponding interrupt affinity configuration. When the interrupt loss rate is greater than the interrupt loss rate threshold, the overlap threshold and timing adjustment strategy parameters used to determine the overlap of trigger time windows are adjusted. When the PCIe bus load exceeds the PCIe bus load threshold, adjust the bandwidth configuration parameters.

[0017] This disclosure also provides a parallel clock interrupt handling device suitable for the Kylin operating system, applied to a server system connected to a clock interrupt card via a PCIe bus. The device includes: The requirement parsing module is used to obtain clock interrupt handling requirement information for multiple threads from the application layer. Based on the clock interrupt handling requirement information and the thread running status, it establishes a mapping relationship between clock interrupt lines, CPU cores and threads, and configures interrupt affinity according to the mapping relationship so that clock interrupt requests from the clock interrupt card are allocated to the target thread according to the mapping relationship. The collaborative scheduling module is used to allocate each interrupt handling thread to a scheduling queue corresponding to the frequency layer according to the interrupt frequency of each thread, and to schedule the interrupt handling threads according to the priority of the frequency layer, so that the interrupt handling thread with a higher frequency will be given priority in resource contention. The timing control module is used to predict the next trigger time of each clock interrupt based on the interrupt frequency and bus transmission delay and form a corresponding trigger time window, detect the overlap between the trigger time windows of different frequencies, and execute a preset timing avoidance strategy when the overlap meets a preset condition. The interrupt trigger configuration module is used to adaptively adjust the interrupt trigger configuration of the clock interrupt card in the driver layer according to the number of clock interrupts received per unit time and the bus transmission status, and to set the scheduling compensation time corresponding to the bus transmission delay in the scheduling logic of the interrupt handling thread. The PCIe adapter module is used to calculate the bandwidth requirement of the PCIe bus based on the amount of data transmitted in a single clock interrupt at different frequencies and the interrupt frequency, and to send bandwidth configuration parameters to the PCIe controller to allocate guaranteed bandwidth for high-frequency interrupts and configure weighted shared bandwidth for medium-frequency and low-frequency interrupts.

[0018] This disclosure also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the above-described parallel clock interrupt handling method applicable to the Kylin operating system, or any possible implementation of the above-described parallel clock interrupt handling method applicable to the Kylin operating system, are performed.

[0019] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the above-described parallel clock interrupt handling method applicable to the Kylin operating system, or any possible implementation of the above-described parallel clock interrupt handling method applicable to the Kylin operating system.

[0020] This disclosure also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the parallel clock interrupt handling method applicable to the Kylin operating system described above, or any possible implementation of the parallel clock interrupt handling method applicable to the Kylin operating system described above.

[0021] This disclosure provides a parallel clock interrupt handling method, apparatus, electronic device, and storage medium applicable to the Kylin operating system. Applied to a server system connected to a clock interrupt card via a PCIe bus, it enables more stable clock interrupt response time and reduces interrupt loss in multi-threaded, multi-frequency parallel scenarios, maintaining consistency in the periodic execution of tasks at different frequencies. Under conditions of system load fluctuations and changes in PCIe bus transmission conditions, the continuity and reliability of the interrupt handling process are improved. Overall interrupt handling efficiency is enhanced, resulting in better stability and resource utilization when the system handles multi-frequency parallel clock tasks.

[0022] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. These drawings are incorporated in and constitute a part of this specification. They illustrate embodiments conforming to this disclosure and, together with the specification, serve to explain the technical solutions of this disclosure. It should be understood that the following drawings only show some embodiments of this disclosure and should not be considered as limiting the scope. Those skilled in the art can obtain other related drawings based on these drawings without creative effort.

[0024] Figure 1 A flowchart of a parallel clock interrupt handling method applicable to the Kylin operating system provided in an embodiment of this disclosure is shown; Figure 2 A flowchart is shown for another parallel clock interrupt handling method applicable to the Kylin operating system provided by an embodiment of this disclosure; Figure 3 A schematic diagram of a parallel clock interrupt handling device for the Kylin operating system provided in an embodiment of this disclosure is shown. Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0027] In this document, the term "and / or" merely describes a relationship, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0028] Research has shown that as more applications with high real-time requirements are used in server systems, the handling, fairness, and stability of clock interrupts in multi-threaded, multi-frequency parallel scenarios have become key factors in system operation. How to maintain interrupt response balance while ensuring the needs of tasks at different frequencies has become one of the typical problems faced by existing technologies.

[0029] Based on the above research, this disclosure provides a parallel clock interrupt handling method, device, electronic device, and storage medium suitable for the Kylin operating system. Applied to server systems connected to clock interrupt cards via PCIe bus, it can improve the response time of clock interrupts in multi-threaded, multi-frequency parallel scenarios, reduce interrupt loss, and maintain consistency in the periodic execution of tasks at different frequencies. Under system load fluctuations and changes in PCIe bus transmission conditions, the continuity and reliability of the interrupt handling process are improved. The overall interrupt handling efficiency is improved, enabling the system to have better stability and resource utilization when handling multi-frequency parallel clock tasks.

[0030] To facilitate understanding of this embodiment, a parallel clock interrupt handling method for the Kylin operating system disclosed in this disclosure will first be described in detail. The executing entity of the parallel clock interrupt handling method for the Kylin operating system provided in this disclosure is generally a computer device with a certain computing capability. This computer device may include, for example, a terminal device, a server, or other processing devices. The terminal device may be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. In some possible implementations, this parallel clock interrupt handling method for the Kylin operating system can be implemented by the processor calling computer-readable instructions stored in memory.

[0031] See Figure 1 The diagram shows a flowchart of a parallel clock interrupt handling method applicable to the Kylin operating system provided in this embodiment of the present disclosure. The method includes steps S101 to S105, wherein: S101. Obtain clock interrupt handling requirements for multiple threads from the application layer. Based on the clock interrupt handling requirements and thread running status, establish a mapping relationship between clock interrupt lines, CPU cores, and threads. Configure interrupt affinity according to the mapping relationship so that clock interrupt requests from the clock interrupt card are allocated to the target thread according to the mapping relationship.

[0032] In practical implementation, the application layer of the Kylin operating system deploys a requirement parsing module to obtain clock interrupt handling requirements for multiple threads. When the application software calls the thread creation interface when creating a thread, the requirement parsing module captures the thread creation behavior and thread parameter configuration changes in real time by hooking the thread creation function. Each time a thread is created or its parameters change, it reads the thread identifier, target interrupt frequency, task priority, and real-time level of that thread, and encapsulates this information into a structured multi-threaded interrupt requirement dataset.

[0033] Here, the multi-threaded interruption requirement dataset is organized in JSON format and includes at least a thread identifier field, a frequency requirement field, and a task attribute field. The thread identifier field is used to identify a specific thread, the frequency requirement field records the target interruption frequency, and the task attribute field records the task priority and real-time level.

[0034] The requirement parsing module uses the netlink communication mechanism provided by the Kylin system to send the multi-threaded interrupt requirement dataset from user space to the kernel-space collaborative scheduling module, so that the matching and scheduling between clock interrupt resources and thread requirements can be completed in the kernel.

[0035] Furthermore, after receiving the multi-threaded interrupt request dataset in the kernel, the collaborative scheduling module calculates the mapping relationship between each thread and the clock interrupt resource by combining the thread running status information maintained by the Kylin system kernel.

[0036] Specifically, the collaborative scheduling module constructs a matching model between interrupt resources and threads based on multi-dimensional mapping decision factors. These decision factors include thread interrupt frequency, thread real-time load, task priority, and historical interrupt processing latency. The thread interrupt frequency factor quantifies different frequency demands into numerical ranges within a preset range, reflecting the importance of high-frequency demands in the mapping decision. The thread real-time load factor calculates the current CPU utilization of each thread by reading the `cpu_load` field from the `task_struct` structure of the Kylin system and converts the utilization into a score reflecting available processing capacity. The task priority factor maps the Kylin system task priority values ​​to a normalized score, reflecting the importance of scheduling. The historical interrupt processing latency factor is quantified based on the average response latency of several recent interrupt handling events and a preset latency threshold, reflecting the efficiency of the thread in handling interrupts. The collaborative scheduling module uses the analytic hierarchy process (AHP) to compare the relative importance of each factor pairwise, calculates the weight vector of each factor, normalizes the four factor values ​​for each thread, and then sums them according to their weights to obtain the matching score between the thread and each interrupt resource.

[0037] It should be noted that the collaborative scheduling module uses the analytic hierarchy process (AHP) to determine the weights of each decision factor. After normalizing the values ​​of each factor, the matching degree is obtained by weighted summation according to the weights. The sum of the weights of each decision factor is equal to 1.

[0038] As one possible implementation, when any of the following triggering conditions are met, the collaborative scheduling module recalculates the matching degree and updates the mapping relationship between the clock interrupt line, CPU core and thread: the change in the thread's target interrupt frequency relative to the previous statistical period is greater than the frequency change threshold; the change in the real-time load of the CPU core where the thread is located within the load monitoring period is greater than the load change threshold; the average historical interrupt handling latency of the thread is greater than the latency threshold; and after updating the mapping relationship, the interrupt affinity mask is reset through the interrupt affinity configuration interface of the Kylin operating system.

[0039] Here, after obtaining the matching score between each thread and the clock interrupt resource, the collaborative scheduling module sorts the clock interrupt lines, CPU cores, and threads according to the matching score from high to low, generating an interrupt-thread mapping table. The interrupt-thread mapping table includes at least fields such as interrupt line ID, CPU core ID, and thread ID, used to specify the CPU core and target thread that each clock interrupt line preferentially corresponds to. When the matching score of a thread is higher than a preset high matching threshold, the collaborative scheduling module preferentially allocates the thread to an independent clock interrupt line and an independent CPU core to meet the needs of high-frequency or high-real-time tasks; when the thread matching score is in the low to medium range, multiple such threads can be allocated to a shared interrupt line and a shared CPU core, and the subsequent scheduling mechanism will perform round-robin processing on this shared resource.

[0040] Once the mapping table is generated, the collaborative scheduling module calls the set_irq_affinity interface or irqbalance related interface provided by the Kylin system to configure the interrupt affinity mask of each interrupt line according to the interrupt-thread mapping table. This ensures that the clock interrupt request generated by a specific interrupt line is directed to the CPU core specified in the mapping table and processed by the target thread bound to that CPU core, thus avoiding additional scheduling latency caused by the disordered migration of interrupt requests between multiple cores.

[0041] During system operation, the collaborative scheduling module continuously collects real-time data on thread load changes, interrupt frequency demand changes, and historical interrupt handling latency. When it detects that the change in the thread's target interrupt frequency relative to the previous cycle exceeds the frequency change threshold, or the load fluctuation of the CPU core where the thread resides exceeds the load change threshold, or the average historical interrupt handling latency of the thread exceeds the latency threshold, the collaborative scheduling module triggers a recalculation of the matching degree and updates the interrupt-thread mapping table. Subsequently, it calls the interrupt affinity configuration interface again to adjust the interrupt affinity mask.

[0042] In this way, through the above dynamic mapping mechanism, clock interrupt requests from the PCIe clock interrupt card can always be allocated to the target thread according to the latest interrupt-thread mapping relationship at different stages of operation, realizing dynamic adaptation between interrupt resources and thread processing capabilities and requirements, and improving the real-time performance and stability of interrupt processing in multi-threaded and multi-frequency scenarios.

[0043] S102. Based on the interrupt frequency of each thread, each interrupt handling thread is assigned to a scheduling queue corresponding to the frequency layer, and the interrupt handling threads are scheduled according to the priority of the frequency layer, so that the interrupt handling threads with higher frequencies are given priority in resource contention.

[0044] In practice, in order to enable the Kylin operating system to reasonably allocate the processing resources of the CPU core in a multi-threaded and multi-frequency parallel environment, the collaborative scheduling module, after establishing the mapping relationship between interrupt lines, CPU cores and threads, will further divide the interrupt handling threads into scheduling queues of different frequency layers according to the target interrupt frequency corresponding to each thread.

[0045] Specifically, the system reads the target interrupt frequency field of the thread in the multi-threaded interruption demand dataset, and combines it with the preset frequency division rules to classify threads with higher target interrupt frequencies into the high-frequency layer scheduling queue, threads with target interrupt frequencies in the middle range into the medium-frequency layer scheduling queue, and threads with lower target interrupt frequencies into the low-frequency layer scheduling queue.

[0046] Here, the high-frequency layer, mid-frequency layer, and low-frequency layer each maintain an independent scheduling queue structure. The scheduling queue stores information such as the thread identifier of the corresponding thread, the pointer to the task to be executed, and the current state of the thread, so that the kernel can accurately know the set of interrupt handling threads in the ready state in each frequency layer at any point in time.

[0047] Furthermore, the Kylin operating system kernel sets fixed scheduling priorities for different frequency layers, with higher frequency layers having higher scheduling priority than mid-frequency layers, and mid-frequency layers having higher scheduling priority than low-frequency layers. When multiple interrupt handling threads at different frequency layers are simultaneously in a ready state and competing for CPU cores, the kernel scheduler first selects a thread from the high-frequency layer scheduling queue for execution; if there are no ready threads at the high-frequency layer, it then selects a thread from the mid-frequency layer scheduling queue; if there are also no executable threads in the mid-frequency layer scheduling queue, it selects a thread from the low-frequency layer scheduling queue for execution.

[0048] To ensure that high-frequency threads can continue to receive priority processing in resource contention, the Kylin operating system kernel adopts a preemptive scheduling strategy: when a high-frequency interrupt handling thread becomes ready, if the current CPU core is executing a mid-frequency or low-frequency thread, scheduling preemption is immediately triggered, and the execution right of the CPU core is switched to the high-frequency thread, so that the clock interrupt of the high-frequency task can be processed in the shortest possible time.

[0049] In actual operation, the kernel scheduler's frequency layer scheduling mechanism not only ensures that high-frequency interrupt handling threads have priority to obtain CPU cores in resource contention scenarios, but also ensures that threads within each frequency layer execute fairly according to their preset scheduling strategies (including preemptive scheduling and time-slice round-robin scheduling).

[0050] For example, the mid-frequency layer thread uses a combination of time-slice round-robin and preemptive scheduling in the scheduler. When the mid-frequency layer thread is executing and there are no executable threads in the high-frequency layer, the mid-frequency layer thread continues to run according to the set time slice; once an executable thread appears in the high-frequency layer, the mid-frequency layer thread is immediately preempted.

[0051] It should be noted that the low-frequency layer threads adopt a fixed time slice rotation method, and obtain CPU cores in sequence when there are no executable threads in the high-frequency layer and the mid-frequency layer.

[0052] As one possible implementation, threads with interrupt frequencies greater than a first frequency threshold are classified as high-frequency interrupt handling threads, threads with interrupt frequencies less than a second frequency threshold are classified as low-frequency interrupt handling threads, and threads with interrupt frequencies between the first and second frequency thresholds are classified as medium-frequency interrupt handling threads. The time slice length of the medium-frequency layer scheduling queue is in a fixed proportion to the interrupt period corresponding to the thread with the highest interrupt frequency in the queue, and the time slice length of the low-frequency layer scheduling queue is a fixed time length.

[0053] In one specific implementation, after collecting the interrupt handling threads, the collaborative scheduling module first stratifies the threads according to their corresponding interrupt frequencies. To achieve this, the system presets a first frequency threshold and a second frequency threshold. The first frequency threshold distinguishes high-frequency interrupt handling threads from medium-frequency and low-to-medium-frequency threads, while the second frequency threshold distinguishes low-frequency interrupt handling threads from medium-frequency and high-to-medium-frequency threads. The collaborative scheduling module reads the target interrupt frequency parameter for each interrupt handling thread. When a thread's interrupt frequency is greater than the first frequency threshold, it is classified as a high-frequency interrupt handling thread; when its interrupt frequency is less than the second frequency threshold, it is classified as a low-frequency interrupt handling thread; and when its interrupt frequency is between the first and second frequency thresholds, it is classified as a medium-frequency interrupt handling thread. Through this method, interrupt handling threads with different frequency requirements are logically categorized into three frequency levels: high-frequency, medium-frequency, and low-frequency, laying the foundation for subsequent hierarchical queue management and scheduling strategy configuration.

[0054] After completing frequency layering, the Kylin operating system kernel creates corresponding scheduling queues for the high-frequency, mid-frequency, and low-frequency layers, adding the interrupt handling threads belonging to each frequency layer to the corresponding scheduling queue for unified management. The high-frequency layer scheduling queue stores all high-frequency interrupt handling threads, the mid-frequency layer scheduling queue stores all mid-frequency interrupt handling threads, and the low-frequency layer scheduling queue stores all low-frequency interrupt handling threads. The kernel configures different scheduling priorities for each frequency layer scheduling queue, giving the high-frequency layer scheduling queue the highest priority, followed by the mid-frequency layer, and then the low-frequency layer. When multiple ready threads in the three layers simultaneously compete for CPU resources, the scheduler always prioritizes selecting a thread from the high-frequency layer scheduling queue, then from the mid-frequency layer, and finally from the low-frequency layer.

[0055] To further ensure the reasonable allocation of time among threads within the mid-frequency and low-frequency layers, the mid-frequency layer scheduling queue adopts a time-slice configuration strategy related to the interrupt cycle, while the low-frequency layer scheduling queue adopts a fixed time-slice configuration strategy. Specifically, the time slice length of the mid-frequency layer scheduling queue is proportional to the interrupt cycle corresponding to the thread with the highest interrupt frequency in the queue. When initializing the mid-frequency layer scheduling queue, the collaborative scheduling module first counts the target interrupt frequencies of all interrupt handling threads in the mid-frequency layer, selects the interrupt cycle corresponding to the highest frequency as the reference cycle, and calculates the uniform time slice length of the mid-frequency layer scheduling queue according to a preset proportional coefficient. For example, when the highest interrupt frequency in the mid-frequency layer is 1kHz, the corresponding interrupt cycle is 1ms, and the time slice length can be set to a fixed proportion of this interrupt cycle to avoid different threads in the mid-frequency layer blocking each other due to excessively long time slices. The low-frequency layer scheduling queue is configured with a fixed time slice, such as 10ms or other durations set according to the actual scenario. This fixed time slice length is preset during system initialization and remains unchanged during operation, enabling low-frequency interrupt handling threads to take turns obtaining CPU core execution opportunities in a stable and balanced manner. This reduces scheduling overhead and improves CPU utilization while meeting the real-time requirements of low-frequency tasks.

[0056] In this way, through the frequency layer division and priority scheduling mechanism described above, the system can maintain the real-time performance and stability of the overall processing in multi-frequency concurrent interruption scenarios, enabling high-frequency tasks to have lower response latency, while ensuring that medium-frequency and low-frequency tasks obtain processing time according to their periodic needs.

[0057] S103. Based on the interrupt frequency and bus transmission delay, predict the next trigger time of each clock interrupt and form a corresponding trigger time window. Detect the overlap between the trigger time windows of different frequencies. When the overlap meets a preset condition, execute a preset timing avoidance strategy.

[0058] In practice, after completing the frequency layering and scheduling queue division of the interrupt handling threads, the collaborative scheduling module will predict the next trigger time of each clock interrupt based on the interrupt frequency corresponding to each clock interrupt and the currently detected bus transmission delay in order to identify potential timing conflicts in advance in the scenario of parallel multi-frequency clock interrupts.

[0059] Specifically, after each interrupt is processed or within a preset timing calculation period, the collaborative scheduling module reads the most recent actual trigger time of the current interrupt, uses this trigger time as the current trigger time, calculates the theoretical interrupt period based on the interrupt frequency corresponding to the interrupt, and then adds the PCIe bus transmission delay compensation value to the theoretical interrupt period to obtain the expected trigger time of the next interrupt signal arriving at the CPU.

[0060] By combining frequency periodicity and bus transmission delay, the above-mentioned joint prediction enables each frequency clock interrupt to form a clear next trigger moment in the kernel before it actually arrives, providing a time basis for subsequent timing conflict detection.

[0061] Here, after obtaining the predicted trigger time of each clock interrupt, the collaborative scheduling module uses the predicted trigger time as the center and combines it with the average interrupt processing time of the frequency interrupt in the historical processing process to construct a corresponding trigger time window for each clock interrupt.

[0062] The starting boundary of the trigger time window is determined by subtracting a portion of the historical processing time from the predicted trigger time, and the ending boundary is determined by adding another portion of the historical processing time to the predicted trigger time. This allows the time window to cover the entire process from the arrival of the interrupt signal at the CPU to the completion of the interrupt processing, thus characterizing the time period occupied by the interrupt in the system.

[0063] It should be noted that for any two clock interrupts of different frequencies, the collaborative scheduling module calculates the overlap interval length of their respective trigger time windows, and uses the ratio of the overlap interval length to the shorter window length of the two trigger time windows as a quantitative indicator of the overlap degree of the two trigger time windows; when the overlap degree is greater than or equal to the preset overlap degree threshold, it is determined that the two clock interrupts have a timing conflict in the next cycle.

[0064] Furthermore, after detecting that the overlap of the trigger time window meets the preset conditions, the collaborative scheduling module executes the preset timing avoidance strategy before the actual interrupt arrives, and adjusts the processing order and processing start time of multi-frequency clock interrupts with conflicting relationships.

[0065] Specifically, for low-frequency clock interrupts with low real-time requirements, the collaborative scheduling module can use a delay avoidance approach, postponing the start time of their processing to after the end of the triggering time window of the high-frequency interrupt that conflicts with it. The delay duration is constrained based on the period parameters of the low-frequency interrupt and the target processing cycle to ensure that the adjusted delay remains within the allowable time range of the next interrupt cycle, thus preventing the low-frequency interrupt from being discarded or experiencing severe processing delays. For low-frequency critical interrupts with high real-time requirements, the collaborative scheduling module can use a short-term preemption approach. Under the condition that the suspension duration does not exceed a preset suspension duration threshold, a temporary suspension instruction is sent to the high-frequency interrupt processing thread within the conflict window, prioritizing the execution of the critical low-frequency interrupt processing thread. After the critical low-frequency interrupt processing thread completes its processing, the suspended high-frequency thread is resumed.

[0066] As one possible implementation, the corresponding interrupt cycle is calculated based on the interrupt frequency. The trigger time of the previous cycle is superimposed with the interrupt cycle and the current bus transmission delay to obtain the next trigger time. The trigger time window is set with the next trigger time as the center and based on the historical interrupt processing duration. The ratio of the intersection duration of the two trigger time windows to the duration of any window is calculated. The ratio is compared with the overlap threshold. When the ratio is greater than the overlap threshold, it is determined that the trigger time window overlap meets the preset condition.

[0067] In one specific implementation, after completing the frequency layering of multi-frequency clock interrupts, the cooperative scheduling module, in order to predict the interrupt trigger time of the next cycle in kernel mode, first calculates the interrupt cycle based on the interrupt frequency corresponding to each clock interrupt. For any clock interrupt to be processed, its actual trigger time in the current cycle is used as the trigger time of the previous cycle. The cooperative scheduling module obtains the corresponding interrupt cycle based on the interrupt frequency, and combines it with the currently detected PCIe bus transmission delay. The trigger time of the previous cycle is then superimposed with the interrupt cycle and the current bus transmission delay to obtain the next trigger time.

[0068] By using the above method, each clock interrupt at each frequency has a clearly defined predicted trigger time within the system, which reflects the expected arrival time of the interrupt signal at the CPU after taking into account bus transmission delay.

[0069] Subsequently, the collaborative scheduling module takes the next trigger time as the center and sets the trigger time window of the clock interrupt according to the average interrupt processing time recorded in the historical processing interrupt log for this frequency interrupt. The start and end boundaries of the trigger time window are limited to the predicted trigger time minus part of the historical processing time and the predicted trigger time plus part of the historical processing time, thereby covering the time interval from arrival to completion of the interrupt in the expected next cycle.

[0070] Furthermore, after constructing the trigger time windows for all frequency clock interrupts, the collaborative scheduling module performs a quantitative analysis of the timing relationships between clock interrupts of different frequencies. Specifically, for any two clock interrupts with different clock frequencies, the collaborative scheduling module first calculates the length of the intersection interval of their trigger time windows, and then uses the ratio of the intersection length to the shorter trigger time window length as the overlap index.

[0071] Here, the overlap reflects the degree of overlap in the time that two clock interrupts occupy CPU processing resources in the expected next trigger cycle. When the overlap index is greater than the preset overlap threshold, it is determined that the trigger time windows of the two clock interrupts overlap to meet the preset conditions, and there is a significant risk of timing conflict.

[0072] When the above conditions are met, the collaborative scheduling module triggers a preset timing avoidance strategy corresponding to the pair of interrupts, and adjusts the processing start time or processing order of at least one of the interrupts. For example, it delays the processing start point of low real-time interrupts, or inserts a short-term preemption for critical interrupts with priority execution under the condition of meeting the suspension duration constraint. In this way, the time overlap between high-frequency and low-frequency clock interrupts is reduced without interrupt loss, and the impact of multi-frequency parallel processing interrupt timing conflicts on the real-time performance and stability of the system is reduced.

[0073] As another possible implementation, for multi-frequency clock interrupts whose trigger time windows overlap and meet preset conditions, one of the following preset timing avoidance strategies is executed: when the real-time level of the low-frequency interrupt handling thread is lower than the real-time level threshold, the processing start time of the low-frequency interrupt handling thread is postponed to the time point after the corresponding high-frequency interrupt trigger time window ends, and the delayed processing cycle does not exceed the target cycle of the low-frequency interrupt; when the real-time level of the low-frequency interrupt handling thread is higher than or equal to the real-time level threshold, under the condition that the suspension time does not exceed the suspension time threshold, the high-frequency interrupt handling thread in the conflict window is temporarily suspended, the low-frequency interrupt handling thread is executed first, and the suspended high-frequency interrupt handling thread is restored after the processing is completed.

[0074] In one specific implementation, when the collaborative scheduling module determines that there is a timing conflict between multiple frequency clock interrupts based on the overlap of the trigger time windows, in order to ensure the real-time performance of critical tasks while avoiding interrupt loss, a preset timing avoidance strategy is executed for the detected multiple frequency clock interrupts whose trigger time window overlap meets the preset conditions.

[0075] Specifically, the collaborative scheduling module first classifies and identifies low-frequency interrupt handling threads and high-frequency interrupt handling threads that are in conflict based on the real-time level information transmitted from the application layer. The real-time level of the low-frequency interrupt handling thread is used to reflect the sensitivity of its task to response latency, while the high-frequency interrupt handling thread usually undertakes interrupt tasks with shorter cycles and higher triggering frequencies.

[0076] When a low-frequency interrupt handling thread in a detected conflict combination has a real-time level lower than the real-time level threshold, the cooperative scheduling module treats the low-frequency interrupt handling thread as a non-critical task with low real-time requirements and adjusts its processing start time using a delay avoidance strategy.

[0077] To this end, the collaborative scheduling module reads the end time of the high-frequency interrupt triggering time window that conflicts with the low-frequency interrupt, uses the end time as the new processing start time of the low-frequency interrupt, and calculates whether the delayed low-frequency interrupt processing cycle still falls within the target cycle of the low-frequency interrupt.

[0078] When the processing cycle of the low-frequency interrupt after the delay adjustment does not exceed the target cycle of the low-frequency interrupt, it is confirmed that the delay avoidance meets the cycle constraint condition. In actual execution, the scheduler starts the low-frequency interrupt processing thread according to the adjusted time point, so that the low-frequency interrupt processing thread can obtain the CPU execution opportunity after the high-frequency interrupt is processed, thereby reducing the competition for processing resources between the two interrupts in the same time period.

[0079] When the real-time performance level of the low-frequency interrupt handling thread is higher than or equal to the real-time performance level threshold in the detected conflict combination, the cooperative scheduling module regards the low-frequency interrupt as a critical low-frequency interrupt. To avoid affecting the periodicity of its task execution through simple delay processing, a short-term preemption strategy is adopted to adjust the processing order of the high-frequency interrupt handling threads within the conflict window.

[0080] Specifically, the collaborative scheduling module sends a temporary suspension instruction to the high-frequency interrupt handling thread currently in the conflict window, provided that the suspension duration does not exceed the suspension duration threshold. This switches the high-frequency interrupt handling thread from the running state to the suspended state, and immediately transfers the CPU execution right to the corresponding critical low-frequency interrupt handling thread, prioritizing the execution of the low-frequency interrupt task.

[0081] After the critical low-frequency interrupt handling thread completes its interrupt handling for the current cycle, the collaborative scheduling module removes the suspension status of the high-frequency interrupt handling thread, restoring it to a ready or runnable state, allowing the high-frequency interrupt handling thread to re-participate in scheduling. Through this short-term preemption method, while ensuring controlled suspension duration, priority execution opportunities are provided for critical low-frequency interrupts, preventing them from being lost or severely overdue due to conflicts with high-frequency interrupts.

[0082] In this way, by choosing between a delay avoidance strategy and a short-term preemption strategy, differentiated timing avoidance control is achieved for low-frequency interrupt handling threads with different real-time requirements: for low-frequency interrupts with lower real-time requirements, their processing start time is appropriately delayed to stagger the high-frequency interrupt handling window; for low-frequency interrupts with higher real-time requirements, the high-frequency interrupt handling thread is briefly suspended within a limited suspension duration and the low-frequency interrupt handling thread is executed first, thereby reducing the risk of resource contention and processing misalignment caused by timing conflicts during parallel processing of multiple frequency interrupts.

[0083] S104. In the driver layer, based on the number of clock interrupts received per unit time and the bus transmission status, the interrupt trigger configuration of the clock interrupt card is adaptively adjusted, and a scheduling compensation time corresponding to the bus transmission delay is set in the scheduling logic of the interrupt handling thread.

[0084] In practical implementation, in order to match the PCIe bus transmission characteristics with the real-time performance of multi-threaded clock interrupt processing, a bus matching and trigger control module is deployed in the driver layer to adaptively adjust the interrupt output behavior from the clock interrupt card.

[0085] Specifically, the driver layer uses a sampling period timer to count the number of clock interrupts received per unit time. At the end of each sampling period, it calculates the total number of interrupt triggers within that period to obtain interrupt flow parameters characterizing the current interrupt flow. Simultaneously, the driver layer reads the status registers of the PCIe clock interrupt card and the PCIe bus controller to obtain current bus transmission status information, including PCIe bus bandwidth utilization, link congestion flags, and error retransmission counts.

[0086] Here, the driver layer adaptively adjusts the interrupt trigger configuration of the clock interrupt card based on the interrupt flow parameters and bus transmission status: when the interrupt flow is detected to be in a high-frequency scenario and the bus bandwidth utilization is close to the preset upper limit, the interrupt trigger mode is set to edge trigger by writing a configuration control word to the clock interrupt card's trigger mode control register, so that the interrupt request is triggered instantaneously on the rising edge of the interrupt signal, reducing the duration of the interrupt signal on the bus and reducing the continuous bus occupancy; when the interrupt flow is detected to be low or the bus bandwidth utilization is within a safe range, the interrupt trigger mode is set to level trigger, ensuring that the interrupt request can still be reliably identified even in the presence of signal jitter by maintaining the interrupt signal level, thereby balancing transmission efficiency and signal integrity in different scenarios.

[0087] The aforementioned trigger mode switching is completed by the driver accessing the relevant registers in the PCIe device configuration space. The switching response is completed in microseconds, and during the switching process, the driver-level interrupt cache mechanism temporarily stores the incoming interrupt requests to avoid interrupt loss during the trigger mode switching.

[0088] Furthermore, in order to offset the impact of PCIe bus transmission latency on interrupt handling timing, the driver layer and kernel layer work together to periodically detect bus transmission latency and introduce scheduling compensation time corresponding to the detection results into the scheduling logic of the interrupt handling thread.

[0089] Specifically, the Kylin operating system kernel periodically sends latency detection commands to the PCIe bus controller and records the time of command transmission as a transmission timestamp. Upon receiving the latency detection command, the PCIe clock interrupt card immediately provides feedback via an interrupt signal. When the kernel receives the interrupt signal, it records the reception timestamp and uses the difference between the reception timestamp and the transmission timestamp as the round-trip latency. The PCIe bus transmission latency is calculated based on half of the round-trip latency.

[0090] Here, the bus transmission delay detection results are updated at fixed intervals and provided to the interrupt handling scheduling module to correct the interrupt handling triggering timing. In the scheduling triggering logic of the interrupt handling thread, the kernel adds an advance based on the current bus transmission delay to the original scheduled time, shifting the overall scheduling time of the interrupt handling thread forward by the scheduling compensation time corresponding to the bus transmission delay. This ensures that when the PCIe bus completes the transmission and the interrupt signal reaches the CPU and triggers the interrupt, the corresponding interrupt handling thread is already in a ready state and can be scheduled for execution immediately.

[0091] By adaptively adjusting the interrupt trigger configuration at the driver layer and introducing a scheduling compensation time corresponding to the bus transmission delay in the scheduling logic, the coordination of dynamic trigger mode selection and bus delay software compensation is achieved. This aligns the transmission process of the interrupt signal with the scheduling process of the interrupt handling thread in time, reduces the impact of bus transmission uncertainty on the interrupt response time, and improves the overall real-time performance and stability of multi-frequency clock interrupt processing.

[0092] S105. Calculate the bandwidth requirement of the PCIe bus based on the single data transmission amount of the clock interrupt at different frequencies and the interrupt frequency, and send bandwidth configuration parameters to the PCIe controller to allocate guaranteed bandwidth for high-frequency interrupts and configure weighted shared bandwidth for medium-frequency and low-frequency interrupts.

[0093] In practice, in order to match the PCIe bus transmission resources with the transmission requirements of multi-frequency clock interrupts, the kernel layer or driver layer first calculates the bandwidth requirements of various clock interrupts on the PCIe bus based on the amount of data transmitted in a single interrupt and the interrupt frequency of different frequency clock interrupts.

[0094] Specifically, for any clock interrupt at any frequency, let Dirq (in bytes) be the amount of data transmitted in a single interrupt, and f (in seconds) be the interrupt frequency. Then, the bandwidth requirement B of this type of interrupt on the PCIe bus is calculated as B = f × Dirq × 8, where 8 is the conversion coefficient from bytes to bits. Through the above calculation, the bandwidth requirements of high-frequency interrupts, medium-frequency interrupts, and low-frequency interrupts per unit time can be obtained, which can be used as a quantitative basis for subsequent bandwidth allocation.

[0095] Here, after obtaining the bandwidth requirements of clock interrupts at each frequency, the kernel layer sends parameters to the QoS configuration interface of the PCIe bus controller based on the frequency layering results and bandwidth requirements. For high-frequency interrupts with large bandwidth requirements and high frequency, the kernel allocates an independent bandwidth channel for them through the QoS configuration interface of the PCIe bus controller, sets the QoS level corresponding to the channel to the highest level, and sets a guaranteed bandwidth of no less than the total bandwidth percentage threshold for high-frequency interrupts in the bandwidth allocation table, for example, setting it to no less than 30%, to ensure that high-frequency clock interrupts have stable and continuous bandwidth resources during bus transmission and will not be preempted by fluctuations in other interrupt traffic. For mid-frequency and low-frequency interrupts, the kernel configures weighted shared bandwidth for them in the PCIe bus controller, assigns all mid-frequency and low-frequency interrupts to the shared channel, and sets a weighted round-robin scheduling weight proportional to their bandwidth requirements for different interrupt types. This allows mid-frequency and low-frequency interrupts to obtain transmission time slots in turn according to their weights while sharing the remaining bus bandwidth, thus avoiding bandwidth crowding out of high-frequency interrupts and ensuring that mid- and low-frequency interrupts complete data transmission within their period requirements.

[0096] It should be noted that the above bandwidth configuration parameters are written into the QoS configuration register group of the PCIe bus controller in the form of register configuration or configuration table. The issuance and effect of bandwidth allocation instructions are completed in microseconds. After the allocation takes effect, the bandwidth utilization of the PCIe bus is improved, which can reduce the probability of interrupt data congestion on the bus under high load conditions.

[0097] See Figure 2 The diagram shows a flowchart of another parallel clock interrupt handling method applicable to the Kylin operating system provided in this embodiment of the present disclosure. The method includes steps S201 to S205, wherein: S201. Calculate the interrupt response latency and interrupt loss rate of each interrupt handling thread according to a fixed period, and calculate the PCIe bus bandwidth utilization rate.

[0098] S202. Compare the statistical results with the response latency threshold, interrupt loss rate threshold and PCIe bus load threshold issued by the application layer.

[0099] S203. When the interrupt response delay is greater than the response delay threshold, adjust the clock interrupt line, the mapping relationship between the CPU core and the thread, and the corresponding interrupt affinity configuration.

[0100] S204. When the interrupt loss rate is greater than the interrupt loss rate threshold, adjust the overlap threshold and timing adjustment strategy parameters used to determine the overlap of the trigger time window.

[0101] S205. When the PCIe bus load exceeds the PCIe bus load threshold, adjust the bandwidth configuration parameters.

[0102] In practice, in order to achieve closed-loop control of the multi-threaded, multi-frequency clock interrupt handling process, the Kylin operating system kernel sets up a performance monitoring and adaptive adjustment module to periodically statistically analyze the interrupt handling performance and PCIe bus load.

[0103] Specifically, this module statistically analyzes the operation of each interrupt handling thread within the previous monitoring period according to a fixed monitoring cycle. It records the time interval between the arrival of the interrupt signal at the CPU and the start of execution of the corresponding interrupt handling thread for each interrupt. It calculates the interrupt response delay statistics of the thread within the monitoring cycle and calculates the ratio of the number of interrupts lost to the number of interrupts that should have arrived for the thread within the monitoring cycle to obtain the interrupt loss rate of the thread.

[0104] Building upon this, the performance monitoring and adaptive adjustment module also obtains the bus bandwidth usage during the monitoring period from the PCIe bus controller, including the ratio of total transmitted data to total available bandwidth, thereby obtaining the PCIe bus bandwidth utilization rate. This statistical process is repeated at fixed intervals, enabling the kernel to continuously monitor the response performance and interrupt reliability of each interrupt handling thread, as well as changes in bus-level load.

[0105] Furthermore, during the initialization phase, the application layer sends target performance parameters to the kernel, including the allowed interrupt response latency threshold, interrupt loss rate threshold, and PCIe bus load threshold. At the end of each monitoring cycle, the performance monitoring and adaptive adjustment module compares and analyzes the statistically obtained interrupt response latency, interrupt loss rate, and PCIe bus bandwidth utilization of each interrupt handling thread with the corresponding thresholds.

[0106] Here, when the interrupt response latency of a certain interrupt handling thread exceeds the response latency threshold, it is determined that the current interrupt handling path of the thread cannot meet the predetermined real-time requirements. The module triggers the mapping adjustment process, updates the interrupt-thread mapping table by recalculating the matching relationship between the clock interrupt line, CPU core and thread, and calls the interrupt affinity configuration interface to modify the interrupt affinity mask of the corresponding interrupt line, so that the clock interrupt request corresponding to the thread is assigned to a more suitable CPU core or thread binding relationship, thereby shortening the interrupt response path.

[0107] Here, when the interrupt loss rate of a certain thread or a certain type of interrupt exceeds the interrupt loss rate threshold, it is determined that the current multi-frequency timing coordination strategy is insufficient to avoid frequent conflicts. The module adjusts the overlap threshold used to determine the overlap of the trigger time window accordingly, tightens or relaxes the timing conflict determination conditions, and updates the timing adjustment strategy parameters according to the loss situation. For example, it adjusts the maximum allowable delay for low-frequency interrupt delay processing or the upper limit of the suspension time when critical interrupts are preempted, so as to reduce the probability of interrupt loss in subsequent cycles.

[0108] Here, when the PCIe bus bandwidth utilization rate obtained from statistics is greater than the PCIe bus load threshold, the performance monitoring and adaptive adjustment module determines that the current bus resource allocation is not conducive to the transmission of multi-frequency clock interrupt data and there is a risk of congestion. At this time, the bandwidth reconfiguration process is initiated.

[0109] Specifically, while preserving the necessary bandwidth for high-frequency interrupts, the module adjusts the bandwidth configuration parameters among high-frequency, mid-frequency, and low-frequency interrupts. This includes recalculating the bandwidth weights of various interrupts, modifying the bandwidth ratio and weighted polling parameters of the corresponding channels in the PCIe controller's QoS configuration register, so that the proportion of mid-frequency and low-frequency interrupts in the shared bandwidth is more in line with actual needs, and reserving sufficient transmission space for high-frequency interrupts, thereby reducing bus congestion.

[0110] In this way, through the aforementioned closed-loop mechanism of monitoring, comparison, and adjustment, the system can automatically adjust the interrupt mapping relationship, interrupt timing coordination parameters, and bandwidth configuration parameters according to changes in interrupt response latency, interrupt loss rate, and PCIe bus load, thereby maintaining the overall real-time performance and stability during multi-threaded, multi-frequency clock interrupt processing.

[0111] The above scheme will now be described in conjunction with specific implementation methods.

[0112] Define the decision factor set ,in For thread interrupt frequency, For real-time load balancing of threads, Prioritize application tasks, To address the latency in handling historical interruptions, the weights of each factor are determined using the Analytic Hierarchy Process (AHP), quantifying the interrupt-thread mapping matching degree.

[0113] Interruption frequency demand factor , to different frequencies The demand (1Hz-1MHz) is quantized into a range of [0.1, 1.0] to ensure that high-frequency demand accounts for a higher proportion in the mapping decision, while avoiding low-frequency demand being ignored due to low scores. The formula is as follows:

[0114] Among them, 1MHz is the maximum frequency supported by the system. After quantization, the score for high-frequency requirements approaches 1. Low-frequency requirements (such as 1Hz) need to retain the basic weight to avoid factor failure, so the minimum score is set to 0.1.

[0115] Thread real-time load factor Calculate thread CPU utilization based on cpu_load in the task_struct of the Kylin system. The quantification formula is:

[0116] The lower the load, the higher the score, indicating that the thread is more capable of handling interrupted tasks.

[0117] Task priority factor Mapping the task priority of the Kylin system The formula is for the range (0-99) to [0.5, 1.0]:

[0118] The higher the priority, the higher the score.

[0119] Historical delay factor Based on the average delay of the last 10 interrupt handling events With threshold ( Quantization (50μs) is performed using the following formula:

[0120] The efficiency of thread interrupt handling is evaluated based on historical interrupt handling latency. The lower the latency, the higher the processing efficiency and the higher the score. The minimum guarantee is set to 0.1 to avoid factor failure.

[0121] The weights of the four factors were determined using the Analytic Hierarchy Process (AHP) to ensure that the weight allocation met the objective of "optimal real-time performance of interruption handling".

[0122] With the goal of "optimal real-time performance", the importance of factors is compared pairwise (using a 1-9 scale: 1 = equally important, 3 = slightly important, 5 = significantly important, 2 / 4 = median): Interrupt frequency requirements It is the core of multi-frequency scenarios, and has a higher thread load. Clearly more important (3), than task priority Significantly important (5), compared to historical delay Slightly important (2); Thread load Prioritize tasks Slightly more important (3), compared to historical delay Secondary (1 / 2); Task Priority Compared to historical delay Secondary (1 / 4), final judgment matrix :

[0123] The rows / columns are as follows: Calculate the largest eigenvalue Consistency indicators =0.0067, random consistency ratio This demonstrates that the logical contradictions in weight allocation are far less than those in random allocation, indicating that weights are reliable, and only scores and decisions calculated based on them are credible.

[0124] The weights W = [0.45, 0.20, 0.10, 0.25] are obtained through eigenvalue decomposition. (Highest weight, meeting the core requirement of multi-frequency parallel processing).

[0125] Matching degree between a single thread and interrupt resources For weighted summation:

[0126] Optimal allocation of interrupt resources is achieved based on S-sorting.

[0127] A mapping and scheduling module is deployed at the kernel layer of the Kylin system to collect decision factor data in real time. When the application thread frequency requirement changes or the thread load fluctuation exceeds the threshold, the mapping is updated.

[0128] Initialize the mapping. When the application thread is created, initial factor data is collected, the matching degree is calculated, and high matching degrees are assigned ( High-frequency threads are bound to independent interrupt lines and CPU cores, while medium- to low-matching threads are assigned to thread pools and shared interrupt lines.

[0129] Dynamic triggering conditions. A mapping update is triggered when any of the following conditions are met, with the thread frequency requiring a change in the amount of change. Thread load fluctuations Historical average latency .

[0130] Mapping update strategy. High-frequency threads. If the matching degree drops to Reallocate idle CPU cores and interrupt lines to ensure exclusive resource usage; low- and mid-frequency threads It adopts "dynamic scheduling of thread pool + interrupt sharing", and processes threads in rotation based on real-time matching degree to avoid overload of a single thread.

[0131] Interrupt affinity adaptive configuration. Based on the mapping results, the interrupt affinity mask is dynamically adjusted through the Kylin system's irqbalance interface to direct interrupt requests of different frequencies to the CPU cores bound to the corresponding processing threads, avoiding latency fluctuations caused by cross-core scheduling. The interrupt-thread mapping response latency is controlled within 10μs.

[0132] Scheduling levels are divided based on frequency differences to match different real-time requirements and ensure that high-frequency tasks are processed first.

[0133] High frequency layer The system has the highest real-time requirements. The processing cycle for a 1kHz interrupt is 1ms. If it is blocked by a low-priority task for 1ms, the interrupt loss rate may exceed 50%. A preemptive scheduling queue is adopted, with a scheduling priority of 1 (highest). The thread priority is bound to the real-time priority of the Kylin system (90-99).

[0134] Mid-frequency layer The 100Hz interrupt handling cycle is 10ms, allowing short-term blocking (<2ms), employing a hybrid queue (preemptive + time-slice round-robin), with a scheduling priority of 2, thread priority (70-89), and a time slice size of 1 / (e.g., maximum intermediate frequency 1kHz, time slice 1ms) to avoid task blocking within the same queue.

[0135] Low frequency layer It has low real-time performance, uses a time-slice round-robin queue, has a scheduling priority of 3, a thread priority of (50-69), and a time slice size of 10ms.

[0136] A hierarchical scheduler is deployed at the kernel level, where high-frequency queues can preempt medium- and low-frequency queues, and medium-frequency queues can preempt low-frequency queues. Within the same queue, high-frequency interrupt threads have priority in obtaining scheduling rights, ensuring that high real-time tasks are processed first.

[0137] Conflicts can be detected and proactively avoided in advance by predicting the trigger time.

[0138] The trigger timing prediction model predicts the next trigger timing based on the periodicity of the interrupt frequency:

[0139] in, The current trigger time, The bus delay compensation value (from the PCIe adapter module) has a prediction error ≤1μs.

[0140] Timing conflict detection uses a quantized overlap criterion. When the overlap O of the trigger windows of two frequency interrupts satisfies:

[0141] The issue is determined to be a timing conflict (W1 and W2 are the trigger windows for two interrupts). Trigger window W is... ( The interrupt handling time is calculated using historical averages, with high-frequency interrupts as the primary factor. low frequency ).

[0142] For non-critical low-frequency interrupts (real-time level < 3), a delay avoidance mechanism is adopted, delaying the trigger time until the end of the high-frequency interrupt window, with a delay duration of [duration missing]. ( The end time of the high-frequency window. For low-frequency predicted trigger times, ensure that the delay does not exceed the next low-frequency cycle; for critical low-frequency interrupts (real-time level ≥ 3), use short-time preemption to send a temporary suspension signal to the high-frequency thread (suspend duration ≤ 10 ... , (For low-frequency processing time), after processing, the high-frequency thread resumes operation to ensure that low-frequency interrupts are not lost; the avoidance algorithm response time is ≤5μs, and the interrupt loss rate after conflict resolution is ≤0.5%.

[0143] Priorities are optimized in real time based on task requirements and queue status to avoid waiting and blocking. Based on the real-time level (levels 1-5) passed from the application layer, the initial interrupt priority is: level 5 → priority 1 (highest), level 1 → priority 5 (lowest).

[0144] Real-time monitoring of the wait queue length L for interrupts at various frequencies, when (When threshold = 5) initiate priority correction. , Based on the basic priority, the smaller the priority value, the higher the priority; when the queue length... If necessary, restore the basic priority; correct the response time to ≤2μs to ensure that the waiting queue does not overflow and critical tasks are not blocked.

[0145] The optimal triggering method is dynamically selected based on interrupted traffic to balance transmission efficiency and signal integrity.

[0146] The driver layer collects the number of interrupt triggers per unit time in real time, and the interrupt traffic calculation model Q is as follows: ,in, The sampling period is The number of interrupts within 1ms, Q is measured in times / ms.

[0147] when (In high-frequency scenarios, such as 10kHz interrupts), switch to edge triggering, triggering the interrupt only on the rising edge of the signal, avoiding continuous bus occupation caused by level triggering, reducing bus bandwidth usage by 30%; when (In low-to-medium frequency scenarios), switch to level triggering to ensure that the interrupt signal remains valid and avoid interrupt loss due to signal jitter caused by edge triggering.

[0148] The driver layer writes the trigger mode control word through the configuration register (address 0x100-0x104) of the PCIe clock interrupt card. The switching response time is ≤5μs. During the switching process, the interrupt buffer mechanism ensures that no interrupt is lost.

[0149] Timing alignment is achieved through software scheduling compensation based on real-time bus latency detection.

[0150] The kernel layer sends a latency detection command to the PCIe bus controller and records the command transmission time. Upon receiving the instruction, the PCIe clock interrupt card immediately feeds back via an interrupt signal and records the interrupt reception time. Bus transmission delay (Half of the round-trip time), detection accuracy ≤1μs, detection cycle = 10ms.

[0151] In the scheduling triggering logic of the interrupt handling thread, a compensation factor is introduced. Advance the scheduling time : Ensure that the processing thread is ready when the interrupt signal arrives at the CPU, offsetting the timing offset caused by bus transmission, and the compensated synchronization error is ≤3μs.

[0152] Based on the bandwidth requirements of multiple frequency interrupts, bandwidth is allocated on demand through QoS configuration. The formula for calculating the bus bandwidth requirement B for different frequency interrupts is: B = ×Dirq×8, where Dirq is the amount of data (in bytes) in a single interrupt, and 8 is the byte-to-bit conversion factor. High-frequency interrupt Allocate dedicated bandwidth channels with a bandwidth ratio of ≥30% to ensure that high-frequency interruption transmission is not preempted; for medium and low frequency interruptions... They share the remaining bandwidth and use weighted round-robin scheduling, with the weights being positively correlated with bandwidth demand.

[0153] Configure the bandwidth allocation table through the QoS configuration interface (addresses 0x200-0x20C) of the PCIe bus controller. Set the QoS level of high-frequency interrupts to the highest (Level 7), and set the QoS level of medium and low frequencies to Level 3-6. The bandwidth allocation response time is ≤10μs, and the bus bandwidth utilization rate is increased to over 85% after allocation.

[0154] The closed-loop optimization algorithm triggers adaptive optimization adjustments based on the deviation between the feedback state and the demand threshold. The deviation determination model defines the deviation ΔKPI for the key performance indicators (KPIs).

[0155] when When δ is the deviation threshold, such as 5%, it is determined that the requirement is not met.

[0156] If the response delay deviation : Triggers a dynamic mapping scheduling algorithm update, reallocating CPU cores and interrupt lines; if the interrupt loss rate deviates... : Trigger timing coordination algorithm optimization, adjust conflict avoidance threshold or priority; if bus load deviation This triggers a bandwidth scheduling algorithm update, reallocating QoS bandwidth.

[0157] This disclosure provides a parallel clock interrupt handling method suitable for the Kylin operating system, applied to a server system connected to a clock interrupt card via a PCIe bus. In multi-threaded, multi-frequency parallel scenarios, the clock interrupt response time is more stable, interrupt loss is reduced, and the periodic execution of tasks at different frequencies remains consistent. Under conditions of system load fluctuations and changes in PCIe bus transmission conditions, the continuity and reliability of the interrupt handling process are improved. Overall interrupt handling efficiency is enhanced, resulting in better stability and resource utilization when the system handles multi-frequency parallel clock tasks.

[0158] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0159] Based on the same inventive concept, this disclosure also provides a parallel clock interrupt processing device for the Kylin operating system, corresponding to the parallel clock interrupt processing method for the Kylin operating system. This device is applied to a server system connected to a clock interrupt card via a PCIe bus. Since the principle of the device in this disclosure for solving the problem is similar to the parallel clock interrupt processing method for the Kylin operating system described above, the implementation of the device can refer to the implementation of the method, and repeated details will not be described again.

[0160] Please see Figure 3 , Figure 3 This is a schematic diagram of a parallel clock interrupt handling device suitable for the Kylin operating system, provided as an embodiment of this disclosure. Figure 3 As shown in the embodiments of this disclosure, the parallel clock interrupt handling device 300 for the Kylin operating system includes: The requirement parsing module 310 is used to obtain clock interrupt handling requirement information for multiple threads in the application layer, establish a mapping relationship between clock interrupt lines, CPU cores and threads based on the clock interrupt handling requirement information and thread running status, and configure interrupt affinity according to the mapping relationship so that clock interrupt requests from the clock interrupt card are allocated to the target thread according to the mapping relationship.

[0161] The collaborative scheduling module 320 is used to allocate each interrupt handling thread to a scheduling queue corresponding to the frequency layer according to the interrupt frequency of each thread, and to schedule the interrupt handling threads according to the priority of the frequency layer, so that the interrupt handling threads with higher frequencies can be processed first when there is resource contention.

[0162] The timing control module 330 is used to predict the next trigger time of each clock interrupt based on the interrupt frequency and bus transmission delay and form a corresponding trigger time window, detect the overlap between the trigger time windows of different frequencies, and execute a preset timing avoidance strategy when the overlap meets a preset condition.

[0163] The interrupt trigger configuration module 340 is used to adaptively adjust the interrupt trigger configuration of the clock interrupt card in the driver layer according to the number of clock interrupts received per unit time and the bus transmission status, and to set the scheduling compensation time corresponding to the bus transmission delay in the scheduling logic of the interrupt handling thread.

[0164] The PCIe adapter module 350 is used to calculate the bandwidth requirement of the PCIe bus based on the amount of data transmitted in a single clock interrupt at different frequencies and the interrupt frequency, and to send bandwidth configuration parameters to the PCIe controller to allocate guaranteed bandwidth for high-frequency interrupts and configure weighted shared bandwidth for medium-frequency and low-frequency interrupts.

[0165] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0166] This disclosure provides a parallel clock interrupt handling device suitable for the Kylin operating system, applied to a server system connected to a clock interrupt card via a PCIe bus. In multi-threaded, multi-frequency parallel scenarios, the clock interrupt response time is more stable, interrupt loss is reduced, and the periodic execution of tasks at different frequencies remains consistent. Under conditions of system load fluctuations and changes in PCIe bus transmission conditions, the continuity and reliability of the interrupt handling process are improved. Overall interrupt handling efficiency is enhanced, resulting in better stability and resource utilization when the system handles multi-frequency parallel clock tasks.

[0167] Corresponding to Figure 1 and Figure 2 The parallel clock interrupt handling method applicable to the Kylin operating system is disclosed in this disclosure. This embodiment also provides an electronic device 400, such as... Figure 4 The diagram shown is a structural schematic of an electronic device 400 provided in an embodiment of this disclosure, including: Processor 41, memory 42, and bus 43; memory 42 is used to store execution instructions, including main memory 421 and external memory 422; the main memory 421, also called internal memory, is used to temporarily store the computational data in processor 41, as well as the data exchanged with external memory 422 such as hard disk. Processor 41 exchanges data with external memory 422 through main memory 421. When the electronic device 400 is running, processor 41 and memory 42 communicate through bus 43, enabling processor 41 to execute... Figure 1 and Figure 2 The steps of the parallel clock interrupt handling method applicable to the Kylin operating system.

[0168] This disclosure also provides a computer-readable storage medium storing a computer program. When a processor executes the program, it performs the steps of the parallel clock interrupt handling method for the Kylin operating system described in the above-described method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0169] This disclosure also provides a computer program product, which includes computer instructions. When the computer instructions are executed by a processor, they can perform the steps of the parallel clock interrupt handling method applicable to the Kylin operating system described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0170] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0171] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this disclosure, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0172] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0173] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0174] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0175] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit it. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A parallel clock interrupt handling method suitable for the Kylin operating system, applied to a server system connected to a clock interrupt card via a PCIe bus, characterized in that, The method includes: Obtain clock interrupt handling requirements for multiple threads from the application layer. Based on the clock interrupt handling requirements and thread running status, establish a mapping relationship between clock interrupt lines, CPU cores, and threads. Configure interrupt affinity according to the mapping relationship so that clock interrupt requests from the clock interrupt card are allocated to the target thread according to the mapping relationship. Based on the interrupt frequency of each thread, each interrupt handling thread is assigned to a scheduling queue of the corresponding frequency layer, and the interrupt handling thread is scheduled according to the priority of the frequency layer, so that the interrupt handling thread with a higher frequency will be given priority in resource contention. Based on the interrupt frequency and bus transmission delay, the next trigger time of each clock interrupt is predicted and a corresponding trigger time window is formed. The overlap between the trigger time windows of different frequencies is detected. When the overlap meets the preset conditions, a preset timing avoidance strategy is executed. Based on the number of clock interrupts received per unit time and the bus transmission status, the interrupt trigger configuration of the clock interrupt card is adaptively adjusted in the driver layer, and a scheduling compensation time corresponding to the bus transmission delay is set in the scheduling logic of the interrupt handling thread. Based on the amount of data transmitted in a single clock interrupt at different frequencies and the interrupt frequency, the bandwidth requirement for the PCIe bus is calculated, and bandwidth configuration parameters are sent to the PCIe controller to allocate guaranteed bandwidth for high-frequency interrupts and configure weighted shared bandwidth for medium-frequency and low-frequency interrupts.

2. The method according to claim 1, characterized in that, Obtain information on the application layer's clock interrupt handling requirements for multiple threads, specifically including: A requirement parsing module is set up at the application layer to obtain thread creation operation and thread parameter change information by hooking the thread creation interface and the thread configuration interface. Each time a thread is created or its parameters are changed, the thread identifier, target interrupt frequency, task priority, and real-time level of the corresponding thread are read to form the clock interrupt handling requirement information. The clock interrupt handling requirement information is encapsulated into structured data, converted from user mode to kernel mode, and sent to the collaborative scheduling module of the Kylin operating system kernel. The structured data includes at least a thread identifier field, a target interruption frequency field, a task priority field, and a real-time performance level field. The requirement parsing module verifies the target interruption frequency of each thread at a fixed period and immediately triggers a data transmission operation when it detects a change in the target interruption frequency.

3. The method according to claim 1, characterized in that, Establish the mapping relationship between clock interrupt lines, CPU cores, and threads, specifically including: A multi-factor matching degree model is used to calculate the matching degree between the thread and the clock interrupt resource; The mapping relationship is generated by sorting the clock interrupt line, the CPU core and the thread according to the matching degree; The multi-factor matching model includes: an interrupt frequency demand factor, used to characterize the target interrupt frequency of each thread; a thread real-time load factor, used to characterize the current load of the CPU core where each thread resides; and a task priority factor, used to characterize the scheduling priority of the application task corresponding to each thread in the operating system.

4. The method according to claim 1, characterized in that, Based on the interrupt frequency of each thread, each interrupt handling thread is assigned to a scheduling queue corresponding to its frequency layer, specifically including: Based on the interrupt frequency corresponding to each thread, the interrupt handling threads are divided into high-frequency interrupt handling threads, medium-frequency interrupt handling threads, and low-frequency interrupt handling threads: Specifically, threads with interrupt frequencies greater than a first frequency threshold are classified as high-frequency interrupt processing threads, threads with interrupt frequencies less than a second frequency threshold are classified as low-frequency interrupt processing threads, and threads with interrupt frequencies between the first and second frequency thresholds are classified as medium-frequency interrupt processing threads. Independent scheduling queues are established for the high-frequency interrupt handling thread, the medium-frequency interrupt handling thread, and the low-frequency interrupt handling thread, respectively.

5. The method according to claim 4, characterized in that, The interrupt handling thread is scheduled according to the priority of the frequency layer, specifically including: The scheduling queue containing the high-frequency interrupt handling thread adopts a preemptive scheduling method, the scheduling queue containing the medium-frequency interrupt handling thread adopts a scheduling method combining preemptive scheduling and time-slice round-robin, and the scheduling queue containing the low-frequency interrupt handling thread adopts a time-slice round-robin scheduling method. Queue priorities are set in the order of high frequency layer, medium frequency layer, and low frequency layer. When there is a ready thread in the high frequency layer, the running thread in the medium frequency layer and the low frequency layer is preempted. The time slice length of the medium frequency layer scheduling queue is proportional to the interrupt period corresponding to the thread with the highest interrupt frequency in the queue. The time slice length of the low frequency layer scheduling queue is a fixed time length.

6. The method according to claim 1, characterized in that, Based on the interrupt frequency and bus transmission delay, the next trigger time for each clock interrupt is predicted and a corresponding trigger time window is formed. The overlap between the trigger time windows of different frequencies is detected, specifically including: The corresponding interrupt cycle is calculated based on the interrupt frequency. The trigger time of the previous cycle is superimposed with the interrupt cycle and the current bus transmission delay to obtain the next trigger time. The trigger time window is set with the next trigger time as the center and based on the historical interrupt processing time. Calculate the ratio of the intersection duration of the two trigger time windows to the duration of any one window, compare the ratio with an overlap threshold, and determine that the overlap of the trigger time windows satisfies the preset condition when the ratio is greater than the overlap threshold.

7. The method according to claim 4, characterized in that, For multi-frequency clock interrupts whose trigger time windows overlap and satisfy the preset conditions, one of the following preset timing avoidance strategies is executed: When the real-time performance level of the low-frequency interrupt handling thread is lower than the real-time performance level threshold, the processing start time of the low-frequency interrupt handling thread is postponed to the time point after the corresponding high-frequency interrupt triggering time window ends, and the postponed processing cycle does not exceed the target cycle of the low-frequency interrupt. When the real-time performance level of the low-frequency interrupt handling thread is higher than or equal to the real-time performance level threshold, the high-frequency interrupt handling thread in the conflict window is temporarily suspended, provided that the suspension duration does not exceed the suspension duration threshold. The low-frequency interrupt handling thread is executed first, and the suspended high-frequency interrupt handling thread is resumed after the processing is completed.

8. A parallel clock interrupt handling device suitable for the Kylin operating system, applied to a server system connected to a clock interrupt card via a PCIe bus, characterized in that, The device includes: The requirement parsing module is used to obtain clock interrupt handling requirement information for multiple threads from the application layer. Based on the clock interrupt handling requirement information and the thread running status, it establishes a mapping relationship between clock interrupt lines, CPU cores and threads, and configures interrupt affinity according to the mapping relationship so that clock interrupt requests from the clock interrupt card are allocated to the target thread according to the mapping relationship. The collaborative scheduling module is used to allocate each interrupt handling thread to a scheduling queue corresponding to the frequency layer according to the interrupt frequency of each thread, and to schedule the interrupt handling threads according to the priority of the frequency layer, so that the interrupt handling thread with a higher frequency will be given priority in resource contention. The timing control module is used to predict the next trigger time of each clock interrupt based on the interrupt frequency and bus transmission delay and form a corresponding trigger time window, detect the overlap between the trigger time windows of different frequencies, and execute a preset timing avoidance strategy when the overlap meets a preset condition. The interrupt trigger configuration module is used to adaptively adjust the interrupt trigger configuration of the clock interrupt card in the driver layer according to the number of clock interrupts received per unit time and the bus transmission status, and to set the scheduling compensation time corresponding to the bus transmission delay in the scheduling logic of the interrupt handling thread. The PCIe adapter module is used to calculate the bandwidth requirement of the PCIe bus based on the amount of data transmitted in a single clock interrupt at different frequencies and the interrupt frequency, and to send bandwidth configuration parameters to the PCIe controller to allocate guaranteed bandwidth for high-frequency interrupts and configure weighted shared bandwidth for medium-frequency and low-frequency interrupts.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the parallel clock interrupt handling method applicable to the Kylin operating system as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the parallel clock interrupt handling method applicable to the Kylin operating system as described in any one of claims 1 to 7.

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