Data acquisition method and device, equipment, chip, storage medium and program product

Abstract

The invention relates to a data acquisition method and device, equipment, a chip, a storage medium and a program product. The method comprises the following steps: in response to a data acquisition request of a target fragment in a primitive, acquiring a screen coordinate of the target fragment; performing interpolation calculation on the screen coordinates of the target fragment to obtain a logic address of the target fragment in a target fragment processor; and obtaining state management data of the target fragment based on the logic address and the fragment state cache of the target fragment processor. Wherein the target fragment is any fragment in a plurality of fragments to be processed by the target fragment processor. By adopting the method, address calculation resources can be reduced, and the data acquisition speed is increased.

Description

Technical Field

[0001] This application relates to the field of screen mapping technology, and in particular to a data acquisition method, apparatus, device, chip, storage medium, and program product. Background Technology

[0002] During the screen mapping data processing stage, the primitive tile (PB-Tiles) mapping data generated after the primitive set screen mapping processing is completed needs to be compressed to generate control flow instructions for each tile.

[0003] In related technologies, intermediate data required to generate each slice control flow instruction is typically stored in the GPU's off-chip memory. Then, one or more caches inside the GPU read and temporarily store the slice data required to generate each slice control flow instruction based on the slice address. Finally, compression processing is performed to generate the control flow instruction for each slice.

[0004] However, in related technologies, obtaining fragmented data requires consuming a lot of resources to calculate fragment addresses, resulting in slow data acquisition speed. Summary of the Invention

[0005] Therefore, it is necessary to provide a data acquisition method, apparatus, device, chip, storage medium, and program product to address the above-mentioned technical problems, which can reduce the resources required for address calculation and improve the data acquisition speed.

[0006] Firstly, this application provides a data acquisition method, which includes:

[0007] In response to a data acquisition request for a target segment in a graphic element, obtain the screen coordinates of the target segment;

[0008] The screen coordinates of the target fragment are interpolated to obtain the logical address of the target fragment in the target fragment processor; where the target fragment is any fragment among the multiple fragments to be processed by the target fragment processor.

[0009] Based on the logical address and the target shard processor's shard state cache, obtain the target shard's state management data.

[0010] In one embodiment, the screen coordinates include a vertical coordinate and a horizontal coordinate; interpolation calculation is performed on the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor, including:

[0011] Determine the initial logical address corresponding to the target fragment based on the binary index of the screen coordinates;

[0012] Extract the binary values ​​of the ordinate and the x-coordinate at the i-th position in sequence to obtain multiple sets of concatenated binary data;

[0013] According to the binary index corresponding to each group of binary concatenated data, each group of binary concatenated data is filled into the initial logical address to obtain the logical address corresponding to the target fragment.

[0014] In one embodiment, the binary values ​​of the ordinate and the abscissa at the i-th bit are extracted sequentially to obtain multiple sets of concatenated binary data, including:

[0015] The binary value of the ordinate at the i-th bit is taken as the high bit, and the binary value of the x-coordinate at the i-th bit is taken as the low bit. Hardware bit concatenation is performed to obtain a set of concatenated binary data.

[0016] In one embodiment, based on the logical address and the target fragment state cache of the target fragment processor, the state management data of the target fragment is obtained, including:

[0017] Based on the logical address, query whether the target shard's state management data exists in the shard state cache;

[0018] If it does not exist, the logical address is truncated and concatenated according to the number of parallel shard processors and the identifier of the target shard processor to obtain the memory allocation address of the target shard; the number of parallel shard processors is the number of processors that obtain the status management data of each shard in the primitive.

[0019] Based on the memory allocation address, read the status management data of the target slice from the off-chip memory.

[0020] In one embodiment, the number of parallel fragment processors and the identifier of the target fragment processor are used to perform truncation and concatenation operations on the logical address to obtain the memory allocation address of the target fragment, including:

[0021] The logical address is truncated based on the number of parallel fragment processors;

[0022] The truncated logical address and the identifier of the target fragment processor are concatenated to obtain the concatenated address;

[0023] The concatenated address is padded with zeros to obtain the memory allocation address of the target slice.

[0024] In one embodiment, the logical address is truncated based on the number of parallel fragment processors, including:

[0025] The truncation stop bit of the logical address is determined based on the number of parallel fragment processors and the amount of fragment data that can be stored in each cache line in off-chip memory; and the truncation start bit of the logical address is determined based on the sum of the bit widths of the screen coordinates of the target fragment.

[0026] Extract the address between the start and end bits of the truncation from the logical address to obtain the truncated logical address.

[0027] In one embodiment, the concatenated memory allocation address is padded with zeros to obtain the memory allocation address of the target slice, including:

[0028] Based on the amount of fragmented data that can be stored in each cache line in the off-chip memory and the memory access granularity of the target fragment processor, the zero-padding bits are determined, and a binary address matching the zero-padding bits is generated.

[0029] The binary address is used as the low-order address and concatenated with the concatenated memory allocation address to obtain the memory allocation address of the target slice.

[0030] In one embodiment, before determining the number of zero-padding bits based on the amount of fragment data that can be stored in each cache line in off-chip memory and the memory access granularity of the target fragment processor, the method further includes:

[0031] Obtain the data bit width of the off-chip memory and the data bit width of the status management data for a single slice;

[0032] The memory access granularity of the target slice processor is determined by the ratio of the data bit width of the off-chip memory to the data bit width of the state management data of a single slice.

[0033] In one embodiment, the method further includes:

[0034] If the state management data is not present in the shard state cache, write the state management data of the target shard into the shard state cache;

[0035] Based on the state management data of the target fragment in the fragment state cache and the geometric information of the primitives within the target fragment, control instruction data for the target fragment is generated.

[0036] In one embodiment, the method further includes:

[0037] When generating control command data for the target segment, the identification information of the graphic elements is added to the status management data of the target segment, and the status management data is updated.

[0038] The updated state management data is stored in the target shard processor's shard state cache according to the logical address.

[0039] Secondly, this application also provides a data acquisition device, comprising:

[0040] The coordinate acquisition module is used to obtain the screen coordinates of the target segment in response to the data acquisition request of the target segment in the graphic element;

[0041] The interpolation calculation module is used to perform interpolation calculations on the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor; wherein, the target fragment is any fragment among the multiple fragments to be processed by the target fragment processor;

[0042] The data acquisition module is used to acquire the state management data of the target shard based on the logical address and the shard state cache of the target shard processor.

[0043] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method steps in the embodiments of the first aspect described above.

[0044] Fourthly, this application also provides a chip including a processor for performing the method steps in the embodiments of the first aspect.

[0045] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method steps described in the embodiments of the first aspect above.

[0046] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method steps described in the embodiments of the first aspect above.

[0047] The aforementioned data acquisition method, apparatus, device, chip, storage medium, and program product, in response to a data acquisition request for a target slice in a graphic element, acquire the screen coordinates of the target slice; perform interpolation calculations on the screen coordinates of the target slice to obtain the logical address of the target slice in the target slice processor; and acquire the state management data of the target slice based on the logical address and the slice state cache of the target slice processor. Here, the target slice is any one of multiple slices to be processed by the target slice processor. In this way, by performing interpolation calculations on the screen coordinates of the target slice to generate the local logical address of the slice processor, a precise mapping from global screen coordinates to the local logical address of the slice processor is achieved, eliminating address conflicts in multi-slice parallel processing scenarios. Furthermore, interpolation calculations can ensure that spatially adjacent slices remain logically contiguous. Thus, when the target slice processor accesses the state management data of a slice, it can load the data corresponding to the logical addresses of adjacent slices at once through the cache prefetch mechanism, significantly improving the cache hit rate and reducing the access frequency and bandwidth overhead of off-chip memory. In addition, interpolation calculations are a lightweight operation that can be directly implemented by the hardware arithmetic unit of the slice processor without the need for additional address mapping table storage, resulting in faster address calculation speed and faster data retrieval speed. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1a This is a schematic diagram of data address allocation under a single TP in a related technical embodiment;

[0050] Figure 1b This is a schematic diagram of data address allocation under two TPs in a related technical embodiment;

[0051] Figure 1c This is a schematic diagram of data address allocation under four TPs in a related technical embodiment;

[0052] Figure 2 This is a hardware architecture diagram of the graphics processor in one embodiment;

[0053] Figure 3 This is a flowchart illustrating a data acquisition method in one embodiment;

[0054] Figure 4a This is a schematic diagram of data address allocation under a single TP in one embodiment;

[0055] Figure 4b This is a schematic diagram of data address allocation under two TPs in one embodiment;

[0056] Figure 4c This is a schematic diagram of data address allocation under four TPs in one embodiment;

[0057] Figure 5 This is a flowchart illustrating the logical address acquisition step in one embodiment;

[0058] Figure 6 This is a flowchart illustrating the data acquisition method in another embodiment;

[0059] Figure 7 This is a flowchart illustrating the memory allocation address acquisition step in one embodiment;

[0060] Figure 8 This is a flowchart illustrating the control instruction data acquisition step in one embodiment;

[0061] Figure 9 This is a flowchart illustrating the data update steps in one embodiment;

[0062] Figure 10 This is a structural block diagram of a data acquisition device in one embodiment;

[0063] Figure 11 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0065] For the screen mapping data processing stage of a tile-based graphics processing unit (Tile-Based GPU), after the primitive block (PB) screen mapping is completed, the graphics processing unit (GPU) needs to compress all the generated PB-Tiles mapping data, generate control stream instruction data for each tile, and output it.

[0066] During this process, the GPU needs to manage a Tile Poniter Cache (TPC) to temporarily store the intermediate data that is frequently read and written to generate the control flow instructions for each tile, which is the state management data corresponding to each tile. However, due to the limited internal storage space of the GPU, when the cache space in the Tile Poniter Cache is full or a read / write request misses, the data stored in the Tile Poniter Cache needs to be flushed and loaded. This requires the Tile Processor (TP) to interact with external memory via the bus to realize the data storage and update of the Tile Poniter Cache. The external memory includes the intermediate data of all tiles.

[0067] Considering the slow interaction speed between a single slice processor and off-chip memory, GPUs typically employ multi-path parallel processing to simultaneously map and compress a primitive set with multiple slices in order to improve processing speed. For example, in a design with N slice processors operating in parallel, each independent slice processor uses N slice state caches for data management.

[0068] In practical applications, the maximum supported screen size is currently up to 32K (15360×8640 pixels). Assuming... If the screen is divided into segments at the pixel level, then the maximum number of segments a screen can have is [number missing]. Assuming a frame contains 1 million primitives that cover most of the segments, each primitive needs to have its address calculated once for each segment it covers. The number of calculations for the read / write address of each segment is [number missing]. Second-rate.

[0069] Assuming the boundary coordinates of a 32K screen's tile size alignment are (screen_x_max, screen_y_max), and the tile coordinates are (tile_x, tile_y), with a bit width of 10 bits for each tile size alignment coordinate, following the N-type screen traversal method in related technologies, the tile processor will first determine the read / write address of the tile in the tile state cache based on the screen size and tile coordinates. Specifically, this is calculated using the following formula:

[0070]

[0071] in, This represents the read and write addresses of the fragments in the fragment state cache. Characterizes the left shift operation.

[0072] Next, the slice processor retrieves the corresponding slice status management data from its own cache or from an external cache based on the read / write address. It is evident that the above read / write address calculation method requires two adders and one 11-bit multiplier. To meet timing requirements, each calculation requires a delay of at least two clock cycles. In screen mapping processing with a very high number of address calculations, this not only impacts processing performance but also results in high power consumption.

[0073] Furthermore, assuming that one memory cache line in off-chip memory can store the state management data of 8 slices, in slice processor designs with different degrees of parallelism, an N-word address allocation method is used to store the slice state management data. The address allocation of the state management data is as follows: Figures 1a-1c As shown. Figure 1a A schematic diagram illustrating the allocation of state management data addresses for a single fragmented processor; Figure 1b A schematic diagram illustrating the allocation of state management data addresses for two parallel fragmented processors. Figure 1b Fragments with the same background in a given context correspond to the same fragment processor. Figure 1c A schematic diagram illustrating the allocation of state management data addresses for four parallel fragmented processors. Figure 1c Fragments with the same background in a given context correspond to the same fragment processor. Figures 1a-1c In the image, the left side shows a diagram of the global screen coordinates of the fragments cached off-chip, while the right side shows a diagram of the fragment state management data stored on-chip. From... Figure 1b and Figure 1cAs can be seen from this, in the accelerated design of multi-shard processor parallel processing, the shard processors are parallel at the shard granularity. Adjacent shards are assigned to different shard processors, that is, the memory cache lines used by each shard processor are not independent of each other, the addresses allocated to the same shard processor are scattered, the memory hit rate of the shard processor to obtain state management data from off-chip memory is low, and each shard processor needs to frequently interact with off-chip memory.

[0074] Based on this, this application provides a data acquisition method that performs interpolation calculation on the screen coordinates of the target segment to obtain the logical address of the target segment in the target segment processor; then, based on the logical address and the existence status of the target segment in the segment status cache of the target segment processor, the state management data of the target segment is acquired to reduce the resources for address calculation and improve the data acquisition speed.

[0075] The data acquisition method provided in this application embodiment can be applied to any slice processor in an image processor. Figure 2 This is a hardware architecture diagram of the graphics processing unit (GPU), which includes multiple slice processors, each with its own slice state cache. Additionally, the GPU includes a scheduler. Figure 2 Not shown in the diagram, the scheduler stores the mapping relationship between each shard processor and its corresponding shard. This mapping relationship is divided according to the global coordinates of the screen shards and directly bound to a fixed shard processor. The scheduler uses the mapping relationship to batch allocate the global screen shards to different shard processors for parallel processing, avoiding multiple shard processors from processing the same shard repeatedly, and ensuring that each shard has one and only one shard processor responsible for it.

[0076] In one exemplary embodiment, such as Figure 3 As shown, a data acquisition method is provided, which is illustrated using a target fragment processor as an example. The method includes:

[0077] S301, in response to a data acquisition request for a target segment in a graphic element, obtains the screen coordinates of the target segment.

[0078] Primitives refer to the basic geometric units used to construct 3D models in 3D graphics rendering; slices refer to two-dimensional pixel slices obtained by uniformly dividing the screen image space into rectangular areas. A primitive usually covers multiple slices, and a slice may also be covered by multiple primitives. Taking a set of primitives as an example, in the process of rendering 3D primitives to a 2D image, the graphics processor needs to determine the data of each slice based on the mapping data between primitives and slices, and then generate control instructions based on the data of each slice for graphics rendering.

[0079] In this embodiment, the graphics processor includes multiple slice processors and a scheduler. The scheduler in the graphics processor obtains the screen coordinates of each slice based on the primitive-slice mapping data, and determines the slice processor corresponding to each slice based on the mapping relationship between the slice screen coordinates and the slice processor. Then, it allocates the data acquisition requests of each slice to the corresponding slice processor, instructing the slice processor to acquire the slice's state management data in order to generate rendering control instructions for that slice.

[0080] Taking the parallel design of each slice processor in the graphics processing unit (GPU) as an example, in TP designs with different degrees of parallelism, a zigzag address allocation method is used to determine the slice corresponding to each slice processor. The mapping relationship between the screen coordinates stored in the scheduler and the slice processors is as follows: Figures 4a-4c As shown, in Figures 4a-4c The left side of the diagram illustrates the global screen coordinates of the fragments in the off-chip cache, while the right side illustrates the fragment state management data stored on-chip. Figure 4a A schematic diagram illustrating the address allocation for state management data under a single fragment processor; Figure 4b A schematic diagram illustrating address allocation for state management data in a two-parallel-sharded processor architecture. Figure 4b Except for addresses with a solid gray background, fragments with the same background correspond to the same fragment processor, and Figure 4b The address allocation method for the solid gray background is not yet fully reflected in the off-chip memory on the right. Figure 4c A schematic diagram illustrating the address allocation for state management data under four parallel slice processors. Figure 4c Except for addresses with a solid gray background, fragments with the same background correspond to the same fragment processor, and Figure 4b The address allocation method for the solid gray background is not yet fully reflected in the off-chip memory on the right. From Figure 4b and Figure 4c As shown in the off-chip cache diagram, adjacent slices are assigned to the same slice processor.

[0081] The scheduler determines the corresponding target fragment processor based on the screen coordinates of the target fragment, and assigns the data acquisition request of the target fragment to the corresponding target fragment processor, so as to instruct the target fragment processor to acquire the fragment's state management data in order to generate rendering control instructions for that fragment.

[0082] The target processor responds to a data acquisition request for a target tile in the primitive by parsing the data acquisition request to obtain the screen coordinates of the target tile carried in the data acquisition request. The screen coordinates of the target tile refer to the two-dimensional coordinates of the target tile on the screen, which can be represented as (tile_x, tile_y). In this embodiment, the data acquisition request carries the screen coordinates of the target tile. Based on this, the target tile processor can directly parse the content in the data acquisition request to obtain the screen coordinates of the target tile.

[0083] S302 performs interpolation calculations on the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor.

[0084] The target fragment is any one of the multiple fragments to be processed by the target fragment processor.

[0085] It should be noted that the target slice processor typically stores the state management data of the target slice in the form of key-value pairs. The key represents the logical address (one-dimensional address) of the state management data of the target slice in the target slice processor, and the value represents the state management data of the target slice.

[0086] The target fragment processor performs address translation on the screen coordinates of the target fragment to obtain the logical address of the target fragment within the target fragment processor. In this embodiment, interpolation calculation is used to translate the screen coordinates.

[0087] Interpolation calculations enable adjacent spatial fragments to form a continuous address sequence in the logical address space. At this point, the adjacent address data prefetched by the cache is exactly the fragment data to be processed later, which greatly improves the prefetch hit rate and naturally reduces access to low-speed off-chip memory, thereby reducing bandwidth overhead and access latency.

[0088] S303 obtains the state management data of the target slice based on the logical address and the slice state cache of the target slice processor.

[0089] It should be emphasized again that the storage space of the target shard processor's shard state cache is limited. In other words, the shard state cache temporarily stores the shard state management data.

[0090] Based on the logical address, the system queries the slice status cache of the target slice processor to see if there is status management data matching the logical address. This determines whether the target slice has a status in the slice status cache of the target slice processor. If it exists, the system directly retrieves the status management data from the slice status cache of the target slice processor based on the logical address. If it does not exist, the system reads the status management data from the off-chip memory via the bus based on the logical address.

[0091] In this embodiment, in response to a data acquisition request for a target fragment in a graphic element, the screen coordinates of the target fragment are obtained; interpolation calculations are performed on the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor; based on the logical address and the fragment state cache of the target fragment processor, the state management data of the target fragment is obtained. Here, the target fragment is any one of the multiple fragments to be processed by the target fragment processor. In this way, by performing interpolation calculations on the screen coordinates of the target fragment to generate the local logical address of the fragment processor, a precise mapping from global screen coordinates to the local logical address of the fragment processor is achieved, eliminating address conflicts in multi-fragment parallel processing scenarios. Furthermore, interpolation calculations can ensure that spatially adjacent slices remain logically contiguous. Thus, when the target slice processor accesses the state management data of a slice, it can load the data corresponding to the logical addresses of adjacent slices at once through the cache prefetch mechanism, significantly improving the cache hit rate and reducing the access frequency and bandwidth overhead of off-chip memory. In addition, interpolation calculations are a lightweight operation that can be directly implemented by the hardware arithmetic unit of the slice processor without the need for additional address mapping table storage, resulting in faster address calculation speed and faster data retrieval speed.

[0092] Next, one possible implementation method for interpolation calculation in the foregoing embodiments will be described. In an exemplary embodiment, such as... Figure 5 As shown, screen coordinates include vertical and horizontal coordinates; interpolation calculations are performed on the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor, including:

[0093] S501 determines the initial logical address corresponding to the target fragment based on the binary index of the screen coordinates.

[0094] In screen coordinates, the vertical and horizontal coordinates have the same number of binary bits. The binary index i refers to the bit sequence number of the screen coordinate binary number, which is an integer greater than or equal to 0. Taking 5 bits each for the vertical and horizontal coordinates as an example, the binary index i ranges from 0 to 4 (5-1).

[0095] Based on the maximum binary index of the screen coordinates, determine the number of binary bits for the ordinate and the abscissa in the screen coordinates. Then, the sum of the number of binary bits for the ordinate and the abscissa is used to determine the length of the initial logical address. Since the number of binary bits for the ordinate and the abscissa in the screen coordinates is the same, the length of the initial logical address can also be determined by doubling the number of binary bits for the ordinate and the abscissa. This initial logical address is a blank address consisting entirely of zeros.

[0096] Continuing with the example of 5 bits each for the vertical and horizontal coordinates, the initial logical address is a 10-bit blank address consisting of all zeros.

[0097] S502, sequentially extract the binary values ​​of the ordinate and the abscissa at the i-th position to obtain multiple sets of binary concatenated data.

[0098] For each index i, first take the i-th binary value of the vertical coordinate, then take the i-th binary value of the horizontal coordinate, and then concatenate the extracted two binary values ​​into a set of binary concatenation data.

[0099] In an exemplary embodiment, the binary values ​​of the ordinate and the abscissa at the i-th bit are extracted sequentially to obtain multiple sets of concatenated binary data, including:

[0100] The binary value of the ordinate at the i-th bit is taken as the high bit, and the binary value of the x-coordinate at the i-th bit is taken as the low bit. Hardware bit concatenation is performed to obtain a set of concatenated binary data.

[0101] Hardware bit splicing refers to the process of directly splicing specified binary bits from multiple data sources into a new binary number in the order of high and low bits through combinational logic within a hardware circuit. This is done without software computation or arithmetic operations such as multiplication or addition, and is accomplished solely by gate circuits.

[0102] Taking (tile_x, tile_y) as an example to represent the horizontal and vertical coordinates of the screen, we first extract the binary value of the vertical coordinate at the i-th bit, then extract the binary value of the horizontal coordinate at the i-th bit, tile_x[i], and then perform hardware bit concatenation to obtain a set of binary concatenated data {tile_y[i], tile_x[i]}.

[0103] In this embodiment, binary concatenated data is generated by a hardware bit-by-bit concatenation rule that fixes the ordinate as the high-order bit and the abscissa as the low-order bit. This strengthens the correspondence between logical addresses and the two-dimensional spatial arrangement of screen fragments, ensuring continuous distribution of logical addresses in the same row and improving the spatial locality and prefetch hit rate of the fragment state cache. Simultaneously, the hardware concatenation logic is simplified, using single-clock-cycle combinational logic operations to reduce the hardware overhead and latency of address generation, ensuring the uniqueness and predictability of any fragment address mapping, and avoiding address conflicts.

[0104] S503: According to the binary index corresponding to each group of binary concatenated data, fill each group of binary concatenated data into the initial logical address to obtain the logical address corresponding to the target fragment.

[0105] Following the binary index from low to high, each group of binary concatenated data is filled into the initial logical address from right to left, replacing the initial logical address with an initial state of 0, to obtain the logical address corresponding to the target fragment.

[0106] Taking (01, 10) as the screen coordinate of the target fragment as an example, the binary index of the screen coordinate is 0 and 1 respectively. The length of the initial logical address is 4. Extract the binary value "0" of the 0th bit of the vertical coordinate and the binary value "1" of the 0th bit of the horizontal coordinate to get a set of binary concatenated data "01". Then extract the binary value "1" of the 1st bit of the vertical coordinate and the binary value "0" of the 1st bit of the horizontal coordinate to get a set of binary concatenated data "10". Then fill the two sets of binary concatenated data into the initial logical address to get "1001", which is the logical address corresponding to the target fragment.

[0107] Taking (tile_x, tile_y) as an example, representing the horizontal and vertical coordinates of the screen, the logical address corresponding to the target fragment... The calculation formula is as follows:

[0108]

[0109] Where i is the binary index of the screen coordinates.

[0110] In this embodiment, the logical address is generated by extracting and filling the horizontal and vertical bit values ​​of the screen coordinates bit by bit according to the binary index of the screen coordinates. This makes the logical address and the fragment space location strongly correlated, improves the spatial locality and hit rate of the fragment state cache, and reduces the overhead of off-chip memory access. At the same time, it eliminates address discretization conflicts, simplifies the hardware implementation logic, reduces address translation latency, and can also adapt to the expansion of the number of fragments under different resolutions, ensuring the universality of the solution.

[0111] The foregoing embodiments described the method of interpolation calculation and obtaining logical addresses. Next, the feasible method of obtaining the state management data of the target fragment based on the logical address will be described. In an exemplary embodiment, such as... Figure 6 As shown, based on the logical address and the target shard processor's shard state cache, the target shard's state management data is obtained, including:

[0112] S601, based on the logical address, queries whether the target shard's state management data exists in the shard state cache.

[0113] The shard state cache stores data in key-value pairs, where the key refers to the logical address and the value refers to the shard's state management data. Therefore, by traversing each logical address in the shard state cache and checking if it matches the logical address of the target shard, it can be determined whether the shard state cache currently stores the target shard's state management data.

[0114] If it exists, indicating that the target segment's state management data is pre-read from off-chip memory and stored in the segment state cache, then the stored data at that logical address can be directly read from the segment state cache as the target segment's state management data.

[0115] S602, if not present, then based on the number of parallel shard processors and the identifier of the target shard processor, perform truncation and concatenation operations on the logical address to obtain the memory allocation address of the target shard.

[0116] The number of parallel sharding processors is the number of processors that acquire the state management data of each shard in the primitive.

[0117] The memory allocation address of the target slice is the storage address of the target slice's state management data in off-chip memory. If the logical address of the target slice is not stored in the slice state cache, it means that the slice state cache does not currently store the target slice's state management data. In this case, it is necessary to determine the memory allocation address of the target slice's state management data in off-chip memory based on the logical address, the number of parallel slice processors, and the identifier of the target slice processor.

[0118] Optionally, the truncation length is first determined according to the number of parallel slice processors, and the logical address is truncated; then the target slice processor identifier is concatenated to the high bits of the truncated address to generate a globally unique memory allocation address that is efficiently processed by hardware. This ensures that the addresses of multiple slice processors do not conflict during parallel processing and also adapts to the addressing rules of video memory.

[0119] The S603 reads the status management data of the target slice from the off-chip memory based on the memory allocation address.

[0120] The memory allocation address is the storage address of the target slice's state management data in the off-chip memory. When the memory allocation address is obtained, the storage data corresponding to that memory allocation address is read from the off-chip memory to obtain the target slice's state management data.

[0121] Optionally, the target slice processor sends a data read request to off-chip memory, carrying a memory allocation address, to instruct the off-chip memory to return the state management data stored at the memory allocation address to the target slice processor. In this way, the target slice processor can receive the state management data of the target slice stored in off-chip memory.

[0122] In this embodiment, the low latency of on-chip cache is used to improve the efficiency of state management data access and reduce the frequency of off-chip memory access. Based on the address truncation and concatenation operation of the number of parallel shard processors and the target shard processor identifier, the global uniqueness of memory addresses in the parallel scenario of multiple shard processors is guaranteed, and address conflicts are avoided. At the same time, the data acquisition path is dynamically switched to balance the utilization efficiency of cache resources and the data consistency between local cache and off-chip memory, so as to support the shard processor to perform stable and efficient parallel block rendering.

[0123] The method for obtaining the memory allocation address of the target fragment is described below. In an exemplary embodiment, such as... Figure 7 As shown, based on the number of parallel slice processors and the identifier of the target slice processor, the logical address is truncated and concatenated to obtain the memory allocation address of the target slice, including:

[0124] The S701 truncates the logical address based on the number of parallel slice processors.

[0125] For example, the address reservation length is obtained by subtracting the number of parallel shard processors from the number of bits in the target shard processor's identifier; then, the high-order bits of the logical address that match the address reservation length are retained to obtain the truncated logical address. For example, if the number of parallel shard processors is 8 and the number of bits in the target shard processor's identifier is 3, then the first 5 (8-3) bits of the high-order logical address are retained.

[0126] S702 concatenates the truncated logical address with the identifier of the target slice processor to obtain the concatenated address.

[0127] The logical address after truncation is placed in the high-order bits, and the identifier of the target fragment processor is placed in the low-order bits. The two are then concatenated to obtain the concatenated address.

[0128] S703 pads the concatenated address with zeros to obtain the memory allocation address of the target slice.

[0129] According to the standard length of memory allocation addresses, the concatenated memory allocation addresses are padded with zeros at the low bits to ensure that the final address length meets the alignment requirements of off-chip memory.

[0130] In this embodiment, redundant bits of the logical address are removed by truncation, and address conflicts in multi-slice processor parallel scenarios are avoided by splicing the slice processor identifier, thus ensuring the uniqueness and compactness of the global memory address; and zero padding is used to make the address meet the alignment access requirements of the off-chip memory, thereby improving the efficiency of video memory read and write; ultimately, an efficient and standardized conversion from the local logical address of the slice processor to the global memory allocation address is achieved, taking into account both the stability of multi-slice processor parallel processing and the performance of video memory access.

[0131] In an exemplary embodiment, one possible implementation of the aforementioned step S701, "truncating the logical address according to the number of parallel fragment processors," is described, including:

[0132] The truncation stop bit of the logical address is determined based on the number of parallel fragment processors and the amount of fragment data that can be stored in each cache line in the off-chip memory; and the truncation start bit of the logical address is determined based on the sum of the bit widths of the screen coordinates of the target fragment; the address between the truncation start bit and the truncation stop bit in the logical address is truncated to obtain the truncated logical address.

[0133] The number of parallel fragment processors is multiplied by the number of fragment data that can be stored in each cache line in off-chip memory. Then, the logarithm of the product, rounded up to the nearest integer (base 2), is used as the truncation bit of the logical address. The corresponding calculation formula is as follows:

[0134]

[0135] in, This is the truncation stop bit; The number of parallel sharding processors, This represents the number of data segments that can be stored in each cache line in off-chip memory. This is for rounding up.

[0136] The bit widths of the screen coordinates of the target fragments are superimposed, and the difference between the superimposed result and 1 is calculated. This difference is used as the start bit of the truncation in the logical address. The corresponding calculation formula is as follows: ,in, This is the bit width of the horizontal coordinate in the screen coordinate system (which is also the bit width of the vertical coordinate).

[0137] Finally, the logical address containing the start bit of the truncation ( ) and truncation stop bit ( The address between () is used as the truncated logical address, and the corresponding expression is as follows: .

[0138] In this embodiment, the truncation termination bit is determined by combining the number of parallel sharding processors and the cache line capacity, and the truncation start bit is determined by combining the screen coordinate bit width. The effective address segment between the two is then extracted, precisely trimming redundant bits of the logical address and retaining the effective bit segment strongly correlated with the screen coordinates, ensuring the correspondence between the logical address and the sharding space location. Simultaneously, splicing space is reserved for the sharding processor identifier, ensuring the uniqueness and compactness of the global memory address in a multi-sharding processor parallel scenario. Ultimately, this improves address translation efficiency while balancing cache access performance and the stability of multi-sharding processor parallel processing.

[0139] In an exemplary embodiment, one possible implementation of the aforementioned step S703, "padding the concatenated memory allocation address with zeros to obtain the memory allocation address of the target fragment," is described, including:

[0140] Based on the amount of fragment data that can be stored in each cache line in the off-chip memory and the memory access granularity of the target fragment processor, the number of zero-padding bits is determined, and a binary address matching the zero-padding bits is generated. The binary address is used as the low-order address and concatenated with the concatenated memory allocation address to obtain the memory allocation address of the target fragment.

[0141] Here, memory access granularity refers to the amount of fragment status management data that the target fragment processor can read from off-chip memory at one time. In this embodiment, the memory access granularity and the amount of fragment data that can be stored in each cache line in off-chip memory are used together to determine the zero-padding bits for the memory allocation address.

[0142] In an exemplary embodiment, before determining the number of zero-padding bits based on the amount of fragment data that can be stored in each cache line in off-chip memory and the memory access granularity of the target fragment processor, the method further includes:

[0143] Obtain the data bit width of the off-chip memory and the data bit width of the status management data of a single slice; determine the memory access granularity of the target slice processor based on the ratio of the data bit width of the off-chip memory to the data bit width of the status management data of a single slice.

[0144] The data bit width of off-chip memory represents the bit width of each stored data in off-chip memory, and the data bit width of state management data of a single slice represents the bit width of each stored data in the slice state cache.

[0145] by Characterizes the data bit width of off-chip memory. Taking the data bit width representing the state management data of a single slice as an example, the formula for calculating the memory access granularity is as follows:

[0146]

[0147] in, The memory access granularity of the target slice processor.

[0148] In this embodiment, the memory access granularity is determined by calculating the ratio of the data bit width of the off-chip memory to the data bit width of a single slice status management. This accurately matches the single data read volume of the slice processor with the hardware transmission capability of the off-chip memory, avoiding unaligned access or bandwidth waste. This not only improves the utilization rate of the video memory bandwidth and the data read efficiency, but also ensures a high degree of compatibility between the slice processor's read strategy and the memory hardware characteristics, providing efficient and stable underlying data access support for parallel processing by multiple slice processors.

[0149] Given the amount of fragmented data that can be stored in each cache line in off-chip memory and the memory access granularity of the target fragment processor, the ratio of this ratio to the target fragment processor's memory access granularity is calculated to quantify the utilization efficiency of the off-chip memory cache lines in a single read operation. In actual data reading scenarios, a ratio of 1 indicates that the amount of data read in a single operation is exactly equal to the capacity of one cache line, meaning that the target fragment processor can retrieve all the data in the cache line in one read, achieving 100% cache line utilization, which is the ideal state. A ratio less than 1 indicates that the amount of data read in a single operation is less than the capacity of one cache line, resulting in redundant data in the cache line that has not been read, leading to insufficient cache line utilization and wasted video memory bandwidth. A ratio greater than 1 indicates that the amount of data read in a single operation exceeds the capacity of one cache line, meaning that multiple cache lines need to be read to meet the demand, which increases the number of video memory accesses and latency, reducing read efficiency.

[0150] Calculate the ratio of the number of fragmented data that can be stored in each cache line in off-chip memory to the memory access granularity of the target fragment processor, then round up to the base 2 logarithm of this ratio, and use the result as zero-padding. The corresponding calculation formula is:

[0151]

[0152] in, This represents the number of data segments that can be stored in each cache line in off-chip memory. This is the ratio of the memory access granularity of the target fragment processor. This is for rounding up.

[0153] The address containing all zeros that match the padding is used as the low-order address and appended to the identifier of the target slice processor to obtain the memory allocation address of the target slice. The corresponding expression is as follows:

[0154]

[0155] in, The memory allocation address that represents the target slice. The identifier representing the target fragment processor. The character is represented by zero padding.

[0156] In this embodiment, the number of zero-padding bits is determined by combining the fragmented data capacity of the off-chip memory cache line with the memory access granularity of the target fragment processor. The corresponding number of zero-padding binary addresses is then concatenated to the lower bits of the concatenated address. This accurately adapts the cache line alignment rules of the off-chip memory to the memory access granularity of the fragment processor. This ensures the alignment of memory allocation addresses to improve the efficiency of video memory read and write and avoids performance loss caused by unaligned access. It also makes the address format match the single data read capability of the fragment processor, maximizing the utilization of video memory bandwidth, while maintaining the global uniqueness and standardization of addresses in multi-fragment processor parallel scenarios.

[0157] During the screen rendering process, the target fragment's state management data is used to generate control command data for the target fragment. In an exemplary embodiment, such as... Figure 8 As shown, the method also includes:

[0158] S801: If there is no state management data in the fragment state cache, write the state management data of the target fragment into the fragment state cache of the target fragment processor.

[0159] If the target fragment's state management data is not stored in the fragment state cache, the logical address of the target fragment in the target fragment processor is used as the storage address of the target fragment's state management data in the fragment state cache. The state management data is then written into the target fragment processor's fragment state cache according to this logical address, so that the target fragment processor can quickly call the cached data in the fragment and thus quickly generate control instructions.

[0160] S802 generates control instruction data for the target fragment based on the state management data of the target fragment in the fragment state cache and the geometric information of the primitives within the target fragment.

[0161] The geometric information of primitives within the target tile refers to the geometric feature data of the overlapping part of the primitive and the target tile. It is a localized description of the primitive within the tile range, including the local coordinates of the primitive vertices within the tile, the intersection boundary between the primitive and the tile, the covered pixel range, the primitive's depth value, color interpolation coefficients, texture coordinates and other rendering attributes, and the edge and vertex connection relationships of the primitive within the tile.

[0162] By integrating the fragment state management data corresponding to the target fragment with the geometric information of the primitives within the target fragment, and through geometric clipping, state fusion, and instruction encoding, a control instruction flow that can directly drive the fragment processor rendering pipeline is generated, achieving a precise mapping from primitive geometric information to hardware rendering actions.

[0163] In this embodiment, when there is no state management data in the fragment state cache, the state management data of the target fragment is written into the fragment state cache of the target fragment processor to generate a fragment state data access time that takes advantage of the low latency of the on-chip cache. Then, within the cache, the state management data of the target fragment and the geometric information of the primitives in the target fragment are accurately fused to generate control instruction data of the target fragment that is adapted to the current fragment rendering requirements, ensuring the targeting and effectiveness of the rendering operation.

[0164] In one exemplary embodiment, such as Figure 9 As shown, the method also includes:

[0165] S901, when generating control command data for the target segment, adds the identification information of the graphic elements to the status management data of the target segment and updates the status management data.

[0166] After generating control command data for the target piece and sending it to the rendering pipeline, the state of the target piece changes accordingly. For example, a new primitive to be rendered is added, or the coverage area is updated. At this time, the changed data needs to be updated in the state management data, and the state management data of this latest state needs to be recorded.

[0167] S902 stores the updated state management data into the target shard processor's shard state cache according to the logical address.

[0168] It should be noted that the logical address of the target shard in the shard state cache is fixed, that is, a specific location in the target shard processor's shard state cache. Therefore, the updated state management data can be written back to the original storage location according to this address, ensuring data consistency.

[0169] In this embodiment of the application, when generating control instruction data for the target fragment, fragment status management data is synchronously updated and stored in the fragment status cache to maintain the validity of the fragment status in real time. This ensures that subsequent primitive mapping or rendering operations can directly call the valid status data in the cache, avoiding repeated reading from off-chip memory or recalculation of the fragment status, and significantly reducing data access latency and computational overhead.

[0170] In an exemplary embodiment, a data acquisition method is provided, applied to a target slice processor, which is any slice processor in a graphics processor, and the target slice processor corresponds to at least one slice in each primitive. The method includes:

[0171] (1) In response to the data acquisition request of the target segment, obtain the screen coordinates of the target segment.

[0172] Screen coordinates include vertical and horizontal coordinates.

[0173] (2) Determine the initial logical address corresponding to the target fragment based on the binary index of the screen coordinates.

[0174] (3) Extract the binary values ​​of the ordinate and the x-coordinate at the i-th bit in sequence. Take the binary value of the ordinate at the i-th bit as the high bit and the binary value of the x-coordinate at the i-th bit as the low bit, and perform hardware bit concatenation to obtain a set of concatenated binary data. In this way, multiple sets of concatenated binary data are obtained.

[0175] (4) Fill each set of binary concatenated data into the initial logical address according to the binary index corresponding to each set of binary concatenated data to obtain the logical address corresponding to the target fragment.

[0176] (5) Based on the logical address, query the shard state cache to see if the state management data of the target shard exists.

[0177] (6) If not, determine the truncation stop bit of the logical address based on the number of parallel fragment processors and the number of fragment data that can be stored in each cache line in the off-chip memory; and determine the truncation start bit of the logical address based on the sum of the bit widths of the screen coordinates of the target fragment; and truncate the address between the truncation start bit and the truncation stop bit in the logical address to obtain the truncated logical address.

[0178] (7) Concatenate the truncated logical address and the identifier of the target fragment processor to obtain the concatenated address.

[0179] (8) Determine the number of zero-padding bits based on the number of fragment data that can be stored in each cache line in the off-chip memory and the memory access granularity of the target fragment processor, and generate a binary address that matches the number of zero-padding bits.

[0180] The memory access granularity is determined by the ratio of the data bit width of the off-chip memory to the data bit width of the state management data of a single slice.

[0181] (9) Use the binary address as the low-order address and concatenate it with the concatenated memory allocation address to obtain the memory allocation address of the target slice.

[0182] (10) Read the status management data of the target slice from the off-chip memory based on the memory allocation address.

[0183] (11) Write the target fragment's state management data into the target fragment processor's fragment state cache.

[0184] (12) Generate control command data for the target segment based on the status management data of the target segment and the geometric information of the primitives within the target segment.

[0185] (13) Add the identification information of the graphic elements to the status management data of the target segment and update the status management data.

[0186] (14) Store the updated state management data to the target fragment processor’s fragment state cache according to the logical address.

[0187] In this embodiment, interpolation calculations are performed on the screen coordinates of the target slice to generate the local logical address of the slice processor. This achieves a precise mapping from global screen coordinates to the local logical address of the slice processor. Furthermore, the address calculation process requires no computational resources and has no computational delay; the address calculation result can be obtained immediately. For TPC data requiring high-frequency read / write operations, this significantly improves the overall system performance and reduces the power consumption generated by the high-frequency address calculation process. An accelerated design circuit for multi-TP parallel processing enables flexible parameterized design of tile address calculation. The centralized address allocation method improves the hit rate of off-chip memory, reduces the number of data interactions between the TPC and off-chip memory, and further optimizes processing performance.

[0188] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0189] Based on the same inventive concept, this application also provides a data acquisition apparatus for implementing the data acquisition method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data acquisition apparatus embodiments provided below can be found in the limitations of the data acquisition method described above, and will not be repeated here.

[0190] In one exemplary embodiment, such as Figure 10 As shown, a data acquisition device is provided, including: a coordinate acquisition module 1001, an interpolation calculation module 1002, and a data acquisition module 1003, wherein:

[0191] The coordinate acquisition module 1001 is used to obtain the screen coordinates of the target segment in response to the data acquisition request of the target segment in the graphic element;

[0192] The interpolation calculation module 1002 is used to perform interpolation calculation on the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor; wherein, the target fragment is any fragment among the multiple fragments to be processed by the target fragment processor.

[0193] The data acquisition module 1003 is used to acquire the status management data of the target slice based on the logical address and the slice status cache of the target slice processor.

[0194] In an exemplary embodiment, the screen coordinates include a vertical coordinate and a horizontal coordinate; the interpolation calculation module 1002 includes: an initial logical address acquisition unit, a data splicing unit, and an address padding unit, wherein:

[0195] The initial logical address acquisition unit is used to determine the initial logical address corresponding to the target slice based on the binary index of the screen coordinates.

[0196] The data splicing unit is used to extract the binary values ​​of the vertical and horizontal coordinates at the i-th bit in sequence to obtain multiple sets of binary spliced ​​data;

[0197] The address filling unit is used to fill each group of binary concatenated data into the initial logical address according to the binary index corresponding to each group of binary concatenated data, so as to obtain the logical address corresponding to the target fragment.

[0198] In an exemplary embodiment, the data splicing unit is further configured to perform hardware bit splicing by taking the binary value of the vertical coordinate at the i-th bit as the high bit and the binary value of the horizontal coordinate at the i-th bit as the low bit, to obtain a set of binary spliced ​​data.

[0199] In an exemplary embodiment, the data acquisition module 1003 includes: a data query unit, an address concatenation unit, and a memory reading unit, wherein:

[0200] The data query unit is used to query whether the target shard's status management data exists in the shard status cache based on the logical address.

[0201] The address concatenation unit is used to perform truncation and concatenation operations on the logical address based on the number of parallel shard processors and the identifier of the target shard processor if it does not exist, in order to obtain the memory allocation address of the target shard; the number of parallel shard processors is the number of processors that obtain the status management data of each shard in the primitive.

[0202] The memory read unit is used to read the status management data of the target slice from the off-chip memory based on the memory allocation address.

[0203] In an exemplary embodiment, the address concatenation unit includes: an address truncation subunit, an identifier concatenation subunit, and an address zero-padding subunit, wherein:

[0204] The address truncation subunit is used to truncate the logical address according to the number of parallel slice processors;

[0205] The identifier splicing subunit is used to splice the truncated logical address and the identifier of the target slice processor to obtain the spliced ​​address;

[0206] The address padding subunit is used to pad the concatenated address with zeros to obtain the memory allocation address of the target slice.

[0207] In an exemplary embodiment, the address truncation subunit is further configured to determine the truncation termination bit of the logical address based on the number of parallel slicing processors and the amount of slicing data that can be stored in each cache line in the off-chip memory; and to determine the truncation start bit of the logical address based on the sum of the bit widths of the screen coordinates of the target slicing; and to truncate the address between the truncation start bit and the truncation termination bit in the logical address to obtain the truncated logical address.

[0208] In an exemplary embodiment, the address padding subunit is further configured to determine the number of zero-padding bits based on the number of fragment data that can be stored in each cache line in the off-chip memory and the memory access granularity of the target fragment processor, and generate a binary address that matches the number of zero-padding bits; the binary address is used as the low-order address and concatenated with the concatenated memory allocation address to obtain the memory allocation address of the target fragment.

[0209] In an exemplary embodiment, the data acquisition device further includes: a granularity acquisition module, configured to acquire the data bit width of the off-chip memory and the data bit width of the state management data of a single slice; and determine the memory access granularity of the target slice processor based on the ratio of the data bit width of the off-chip memory to the data bit width of the state management data of a single slice.

[0210] In one exemplary embodiment, the data acquisition device further includes: a data caching module and an instruction generation module, wherein:

[0211] The data caching module is used to write the state management data of the target shard into the shard state cache when the state management data does not exist in the shard state cache.

[0212] The instruction generation module is used to generate control instruction data for the target slice based on the state management data of the target slice in the slice state cache and the geometric information of the primitives within the target slice.

[0213] In an exemplary embodiment, the data acquisition device further includes: a data update module and an update data storage module, wherein:

[0214] The data update module is used to add the identification information of the graphic elements to the status management data of the target segment when the control command data of the target segment is generated, and to update the status management data.

[0215] The data storage module is updated to store the updated state management data into the target shard processor's shard state cache according to the logical address.

[0216] Each module in the aforementioned data acquisition device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0217] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 11 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores the data required for executing data acquisition methods. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a data acquisition method.

[0218] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0219] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0220] In one exemplary embodiment, a chip is provided, including a processor that, when executing a computer program, implements the steps in the above-described method embodiments.

[0221] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0222] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0223] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0224] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0225] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0226] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data acquisition method, characterized in that, The method includes: In response to a data acquisition request for a target segment in a graphic element, the screen coordinates of the target segment are obtained; The screen coordinates of the target fragment are interpolated to obtain the logical address of the target fragment in the target fragment processor; wherein, the target fragment is any fragment among the multiple fragments to be processed by the target fragment processor; Based on the logical address and the shard status cache of the target shard processor, the status management data of the target shard is obtained.

2. The method according to claim 1, characterized in that, The screen coordinates include a vertical coordinate and a horizontal coordinate; the interpolation calculation of the screen coordinates of the target fragment to obtain the logical address of the target fragment in the target fragment processor includes: The initial logical address corresponding to the target fragment is determined based on the binary index of the screen coordinates; The binary values ​​of the ordinate and the abscissa at the i-th position are extracted sequentially to obtain multiple sets of binary concatenated data; According to the binary index corresponding to each group of binary concatenated data, each group of binary concatenated data is filled into the initial logical address to obtain the logical address corresponding to the target fragment.

3. The method according to claim 2, characterized in that, The process involves sequentially extracting the binary values ​​of the ordinate and the abscissa at the i-th bit to obtain multiple sets of concatenated binary data, including: The binary value of the ordinate at the i-th bit is used as the high bit, and the binary value of the abscissa at the i-th bit is used as the low bit. Hardware bit concatenation is performed to obtain a set of concatenated binary data.

4. The method according to any one of claims 1-3, characterized in that, The step of obtaining the state management data of the target shard based on the logical address and the shard state cache of the target shard processor includes: Based on the logical address, query whether the target shard's state management data exists in the shard state cache; If it does not exist, the logical address is truncated and concatenated according to the number of parallel shard processors and the identifier of the target shard processor to obtain the memory allocation address of the target shard; the number of parallel shard processors is the number of processors that obtain the status management data of each shard in the primitive. Based on the memory allocation address, the status management data of the target slice is read from the off-chip memory.

5. The method according to claim 4, characterized in that, The step of performing truncation and concatenation operations on the logical address based on the number of parallel shard processors and the identifier of the target shard processor to obtain the memory allocation address of the target shard includes: The logical address is truncated based on the number of parallel fragment processors; The truncated logical address and the identifier of the target fragment processor are concatenated to obtain the concatenated address; The concatenated address is padded with zeros to obtain the memory allocation address of the target slice.

6. The method according to claim 5, characterized in that, The step of truncating the logical address based on the number of parallel fragment processors includes: The truncation stop bit of the logical address is determined based on the number of parallel fragment processors and the amount of fragment data that can be stored in each cache line in the off-chip memory; and the truncation start bit of the logical address is determined based on the sum of the bit widths of the screen coordinates of the target fragment. Extract the address between the start and end bits of the truncation from the logical address to obtain the truncated logical address.

7. The method according to claim 5, characterized in that, The step of padding the concatenated memory allocation address with zeros to obtain the memory allocation address of the target slice includes: Based on the number of fragment data that can be stored in each cache line in the off-chip memory and the memory access granularity of the target fragment processor, the zero-padding bits are determined, and a binary address matching the zero-padding bits is generated. The binary address is used as the low-order address and concatenated with the concatenated memory allocation address to obtain the memory allocation address of the target slice.

8. The method according to claim 7, characterized in that, Before determining the number of zero-padding bits based on the amount of fragment data that can be stored in each cache line in the off-chip memory and the memory access granularity of the target fragment processor, the method further includes: Obtain the data bit width of the off-chip memory and the data bit width of the status management data for a single slice; The memory access granularity of the target slice processor is determined based on the ratio of the data bit width of the off-chip memory to the data bit width of the state management data of a single slice.

9. The method according to any one of claims 1-3, characterized in that, The method further includes: If the state management data is not present in the shard state cache, the state management data of the target shard is written into the shard state cache. Based on the state management data of the target segment in the segment state cache and the geometric information of the primitive within the target segment, control instruction data for the target segment is generated.

10. The method according to claim 9, characterized in that, The method further includes: When generating control command data for the target segment, the identification information of the graphic element is added to the status management data of the target segment, and the status management data is updated. According to the logical address, the updated state management data is stored in the shard state cache of the target shard processor.

11. A data acquisition device, characterized in that, The device includes: The coordinate acquisition module is used to acquire the screen coordinates of the target segment in response to a data acquisition request for the target segment in the graphic element; An interpolation calculation module is used to perform interpolation calculations on the screen coordinates of the target segment to obtain the logical address of the target segment in the target segment processor; wherein, the target segment is any one of the multiple segments to be processed by the target segment processor; The data acquisition module is used to acquire the status management data of the target shard based on the logical address and the shard status cache of the target shard processor.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 10.

13. A chip, characterized in that, The chip includes a processor for performing the method of any one of claims 1 to 10.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 10.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 10.

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