Turn-off protection circuit for negative voltage signal transmission

Abstract

The invention discloses a turn-off protection circuit for negative voltage signal transmission. The turn-off protection circuit comprises an NMOS switching circuit, a grid voltage selection circuit and a pull-down control circuit, two ends of the NMOS switch circuit are respectively used as an input end and an output end of a transmission signal; the input end and the output end of the NMOS switch circuit are electrically connected with the first input ends of the two grid voltage selection circuits through a pull-down control circuit respectively, and the input end and the output end of the NMOS switch circuit are electrically connected with the second input ends of the two grid voltage selection circuits respectively. The output ends of the two grid voltage selection circuits are electrically connected with the two control ends of the NMOS switching circuit respectively. Under a normal power-on condition, the grid voltage selection circuit controls the on and off of the NMOS switching circuit according to a received EN control signal; under the condition of power failure, when a VIN input signal transmitted by the NMOS switching circuit is a negative voltage signal, based on a VSHUTDOWN signal output by the pull-down control circuit, the gate voltage selection circuit selects the VIN input signal to control the NMOS switching circuit to be switched off.

Description

Technical Field

[0001] This invention relates to the technical field of protection circuits, and more particularly to a shutdown protection circuit for negative pressure signal transmission. Background Technology

[0002] In analog switch design, the Ipoweroff metric is sometimes introduced, which is the leakage current of the switching channel when an external signal is applied to the chip in the absence of power. Traditional circuit switches, even when not in operation due to power failure, still generate leakage current when an external signal is input. This leakage current can be transmitted to subsequent chips, potentially damaging them. Therefore, IC engineers need to design additional shutdown protection circuits to limit leakage current, protect the chip from overcurrent damage, reduce system power consumption, and prevent interference with other powered modules. However, in practical applications, some analog switches, such as audio switches, require the transmission of negative voltage signals, making shutdown protection design more challenging and significantly increasing in complexity. Currently, most analog switches on the market can only implement shutdown protection when transmitting positive voltage signals, which has significant limitations when dealing with scenarios requiring the transmission of negative voltage signals. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the shortcomings of the prior art, the present invention provides a shutdown protection circuit for negative pressure signal transmission. Under normal power-on conditions, the gate voltage selection circuit controls the opening and closing of the NMOS switching circuit according to the received EN control signal. Under power-off conditions, the gate voltage selection circuit controls the closing of the NMOS switching circuit by selecting the VIN input signal, thereby realizing the shutdown protection of the NMOS switching circuit when transmitting negative or positive pressure signals.

[0004] Technical Solution: To achieve the above objective, the present invention provides a shutdown protection circuit for negative voltage signal transmission, comprising an NMOS switch circuit, a first gate voltage selection circuit, a second gate voltage selection circuit, and a pull-down control circuit; one end of the NMOS switch circuit serves as the input terminal for transmitting the signal, connected to an external VIN input signal; the other end of the NMOS switch circuit serves as the output terminal for transmitting the signal, connected to the input terminal of a chip; both the input and output terminals of the NMOS switch circuit are electrically connected to the first input terminals of the first and second gate voltage selection circuits respectively through a pull-down control circuit; both the input and output terminals of the NMOS switch circuit are electrically connected to the second input terminals of the first and second gate voltage selection circuits respectively; and the output terminals of the first and second gate voltage selection circuits are electrically connected to the two control terminals of the NMOS switch circuit respectively.

[0005] Under normal power-on conditions, the gate voltage selection circuit controls the NMOS switching circuit to turn on and off based on the received EN control signal; under power-off conditions, when the VIN input signal transmitted by the NMOS switching circuit is a negative voltage signal, the gate voltage selection circuit controls the NMOS switching circuit to turn on and off based on the V output of the pull-down control circuit. SHUTDOWN The signal causes the gate voltage selection circuit to select the VIN input signal to control the NMOS switching circuit to turn off.

[0006] Furthermore, the NMOS switching circuit includes an NMOS1 switch and an NMOS2 switch; the drain of the NMOS1 switch serves as the input terminal of the NMOS switching circuit, the source of the NMOS1 switch is electrically connected to the source of the NMOS2 switch, and the drain of the NMOS2 switch serves as the output terminal of the NMOS switching circuit; the gates of the NMOS1 switch and the NMOS2 switch serve as the two control terminals of the NMOS switching circuit, respectively.

[0007] Furthermore, the pull-down control circuit includes a first pull-down control circuit and a second pull-down control circuit; the input terminal of the NMOS switching circuit is electrically connected to the input terminal of the first pull-down control circuit, the output terminal of the first pull-down control circuit is electrically connected to the first input terminal of the first gate voltage selection circuit, and the output terminal of the first gate voltage selection circuit is electrically connected to the gate of the NMOS1 switching transistor; the output terminal of the NMOS switching circuit is electrically connected to the input terminal of the second pull-down control circuit, the output terminal of the second pull-down control circuit is electrically connected to the first input terminal of the second gate voltage selection circuit, and the output terminal of the second gate voltage selection circuit is electrically connected to the gate of the NMOS2 switching transistor; the first gate voltage selection circuit and the second gate voltage selection circuit jointly control the turning on and off of the NMOS switching circuit.

[0008] Furthermore, the first and second pull-down control circuits have the same circuit structure, both including a first low-voltage selection circuit, a first inverter, and a second inverter. The input terminal of the first low-voltage selection circuit serves as the input terminal of the pull-down control circuit and is electrically connected to either the input or output terminal of the NMOS switching circuit. The output terminal of the first low-voltage selection circuit is electrically connected to the low-potential input terminals of the first and second inverters, respectively. The input terminal of the first inverter is grounded, and its output terminal is electrically connected to the input terminal of the second inverter. The output terminal of the second inverter serves as the output terminal of the pull-down control circuit, outputting V. SHUTDOWN Signal.

[0009] Furthermore, the first low-voltage selection circuit includes a transistor MN1 and a transistor MN2; the drain of the transistor MN1 is electrically connected to the gate of the transistor MN2 and serves as the input terminal of the first low-voltage selection circuit; the drain of the transistor MN2 is electrically connected to the gate of the transistor MN1, and the drain of the transistor MN2 is grounded; the source of the transistor MN1 is electrically connected to the source of the transistor MN2 and serves as the output terminal of the first low-voltage selection circuit; the first low-voltage selection circuit selects the lower voltage signal from the two input signals, ground GND and VIN, as the low potential of the first inverter and the second inverter.

[0010] Furthermore, the first inverter includes transistors MP1, MN3, MN4, MN5, and MN6; the second inverter includes transistors MP2 and MN7; transistors MN3, MN4, MN5, and MN6 are connected in series, with the source of transistor MN3 electrically connected to the source of transistor MN1, and the drain of transistor MN6 electrically connected to the drain of transistor MP1; the gates of transistors MP1, MN3, MN4, MN5, and MN6 all serve as the input terminals of the first inverter, and the drain of transistor MP1 serves as the output terminal of the first inverter; the source of transistor MN7 is electrically connected to the source of transistor MN2, and the drain of transistor MN7 is electrically connected to the drain of transistor MP2; the gates of transistors MP2 and MN7 both serve as the input terminals of the second inverter, and the drain of transistor MP2 serves as the output terminal of the second inverter.

[0011] Furthermore, the first and second gate voltage selection circuits have the same circuit structure, both including a second low-voltage selection circuit, a third inverter, a fourth inverter, a latch circuit, and a fifth inverter. The input terminal of the third inverter is connected to the EN control signal via a NOT gate circuit, and the input terminal of the fourth inverter is also connected to the EN control signal. The output terminals of the third and fourth inverters are electrically connected to the first and second ports of the latch circuit, respectively, and the third port of the latch circuit is connected to the VIN input signal. The second port of the latch circuit is electrically connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter serves as the output terminal of the gate voltage selection circuit, outputting VIN. G The input terminal of the second low-voltage selection circuit is connected to the VIN input signal, and the output terminal of the second low-voltage selection circuit is electrically connected to the first port of the latch circuit through the MN10 transistor; the gate of the MN10 transistor serves as the first input terminal of the gate voltage selection circuit, receiving VIN. SHUTDOWNSignal; the first port of the Latch circuit is electrically connected to the gate of the MP8 transistor, the source of the MP8 transistor is electrically connected to the output of the fifth inverter, and the drain of the MP8 transistor is connected to the VIN input signal.

[0012] Furthermore, the third inverter includes an MP3 transistor, an MN11 transistor, and a D1 diode; the fourth inverter includes an MP6 transistor, an MN12 transistor, and a D2 diode; the gate of the MP3 transistor is electrically connected to the gate of the MN11 transistor and serves as the input terminal of the third inverter; the drain of the MP3 transistor is electrically connected to the drain of the MN11 transistor through the D1 diode, and the drain of the MP3 transistor serves as the output terminal of the third inverter; the gate of the MP6 transistor is electrically connected to the gate of the MN12 transistor and serves as the input terminal of the fourth inverter; the drain of the MP6 transistor is electrically connected to the drain of the MN12 transistor through the D2 diode, and the drain of the MP6 transistor serves as the output terminal of the fourth inverter.

[0013] Furthermore, the Latch circuit includes an MP4 transistor, an MP5 transistor, an MN13 transistor, an MN14 transistor, an MN15 transistor, and an MN16 transistor; the drain of the MP4 transistor is electrically connected to the gate of the MP5 transistor and the drain of the MN13 transistor, and the drain of the MP5 transistor is electrically connected to the gate of the MP4 transistor and the drain of the MN15 transistor; the drain of the MP4 transistor serves as the first port of the Latch circuit, and the drain of the MP5 transistor serves as the second port of the Latch circuit; the gate of the MN13 transistor is electrically connected to the gate of the MN16 transistor, and the gate of the MN15 transistor is electrically connected to the gate of the MN14 transistor; the source of the MN13 transistor is electrically connected to the drain of the MN14 transistor, and the source of the MN15 transistor is electrically connected to the drain of the MN16 transistor; the source of the MN14 transistor is electrically connected to the source of the MN16 transistor and serves as the third port of the Latch circuit.

[0014] Furthermore, the fifth inverter includes an MP7 transistor, an MN17 transistor, and a D3 diode; the gate of the MP7 transistor is electrically connected to the gate of the MN17 transistor and serves as the input terminal of the fifth inverter; the source of the MP7 transistor is electrically connected to the negative terminal of the D3 diode, and the positive terminal of the D3 diode is electrically connected to the VCC power supply; the drain of the MP7 transistor is electrically connected to the drain of the MN17 transistor, the source of the MN17 transistor is connected to the VIN input signal, and the drain of the MP7 transistor serves as the output terminal of the fifth inverter.

[0015] Beneficial effects: The present invention provides a shutdown protection circuit for negative voltage signal transmission. Under normal power-on conditions, the gate voltage selection circuit controls the opening and closing of the NMOS switching circuit according to the received EN control signal. Under power-off conditions, when the NMOS switching circuit transmits a negative voltage signal, the voltage is controlled by the V signal output by the pull-down control circuit. SHUTDOWN The signal enables the gate voltage selection circuit to select the VIN input signal to control the turn-off of the NMOS switching circuit; the circuit design occupies a small area and does not affect the normal operation of the analog switch; it balances speed and stability and does not introduce static power consumption, thus solving the shortcomings of traditional turn-off protection circuits that cannot turn off negative voltage signals. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of a shutdown protection circuit used for negative pressure signal transmission.

[0017] Figure 2 This is the circuit diagram for the pull-down control circuit;

[0018] Figure 3 Circuit diagram for the gate voltage selection circuit. Detailed Implementation

[0019] The invention will now be further described with reference to the accompanying drawings.

[0020] like Figure 1 As shown, a shutdown protection circuit for negative voltage signal transmission includes an NMOS switch circuit 1, a first gate voltage selection circuit 22, a second gate voltage selection circuit 24, and a pull-down control circuit. One end of the NMOS switch circuit 1 serves as the input terminal for the transmission signal, connected to an external VIN input signal. The other end of the NMOS switch circuit 1 serves as the output terminal for the transmission signal, connected to the input terminal of a chip. Both the input and output terminals of the NMOS switch circuit 1 are electrically connected to the first input terminals of the first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 respectively via a pull-down control circuit. The input and output terminals of the NMOS switch circuit 1 are also electrically connected to the second input terminals of the first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 respectively. The output terminals of the first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 are electrically connected to the two control terminals of the NMOS switch circuit 1. The control terminals of both the first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 are connected to the EN control signal.

[0021] Under normal power-on conditions, the gate voltage selection circuit controls the NMOS switching circuit 1 to turn on and off based on the received EN control signal; under power-off conditions, when the VIN input signal transmitted by the NMOS switching circuit 1 is a negative voltage signal, the gate voltage selection circuit controls the NMOS switching circuit 1 to turn on and off based on the VIN output by the pull-down control circuit. SHUTDOWNThe signal causes the gate voltage selection circuit to select the VIN input signal to control the NMOS switch circuit 1 to turn off, thus achieving turn-off protection. When the VIN input signal transmitted by the NMOS switch circuit 1 is a positive voltage signal, the MP8 transistor in the gate voltage selection circuit is turned on, and the VIN input signal is used as the output signal V. G The signal controls the NMOS switching circuit 1 to turn off, thus achieving shutdown protection.

[0022] The NMOS switching circuit 1 includes an NMOS1 switch 11 and an NMOS2 switch 12. The drain of the NMOS1 switch 11 serves as the input terminal of the NMOS switching circuit 1, the source of the NMOS1 switch 11 is electrically connected to the source of the NMOS2 switch 12, and the drain of the NMOS2 switch 12 serves as the output terminal of the NMOS switching circuit 1. The gates of the NMOS1 switch 11 and the NMOS2 switch 12 serve as the two control terminals of the NMOS switching circuit 1. The NMOS switching circuit 1 is used for the transmission of the external VIN input signal. Through the two NMOS switches in the NMOS transistor, bidirectional blocking capability is achieved, and a fast response to the turn-off signal is possible.

[0023] The pull-down control circuit includes a first pull-down control circuit 21 and a second pull-down control circuit 23; the input terminal of the NMOS switching circuit 1 is electrically connected to the input terminal of the first pull-down control circuit 21, the output terminal of the first pull-down control circuit 21 is electrically connected to the first input terminal of the first gate voltage selection circuit 22, and the output terminal of the first gate voltage selection circuit 22 is electrically connected to the gate of the NMOS1 switch transistor 11 in the NMOS switching circuit 1; the output terminal of the NMOS switching circuit 1 is electrically connected to the input terminal of the second pull-down control circuit 23, the output terminal of the second pull-down control circuit 23 is electrically connected to the first input terminal of the second gate voltage selection circuit 24, and the output terminal of the second gate voltage selection circuit 24 is electrically connected to the gate of the NMOS2 switch transistor 12 in the NMOS switching circuit 1; the first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 jointly control the turning on and off of the NMOS switching circuit 1.

[0024] The first pull-down control circuit 21 and the second pull-down control circuit 23 have the same circuit structure, both including a first low-voltage selection circuit, a first inverter, and a second inverter. The input terminal of the first low-voltage selection circuit serves as the input terminal of the pull-down control circuit and is electrically connected to either the input or output terminal of the NMOS switching circuit 1. The output terminal of the first low-voltage selection circuit is electrically connected to the low-potential input terminals of the first and second inverters, respectively, and the high-potential input terminals of the first and second inverters are electrically connected to the VCC power supply. The input terminal of the first inverter is grounded, and the output terminal of the first inverter is electrically connected to the input terminal of the second inverter. The output terminal of the second inverter serves as the output terminal of the pull-down control circuit, outputting VCC. SHUTDOWNThe pull-down control circuit is used to determine whether to transmit a negative voltage signal when the power is off. When the NMOS switching circuit 1 transmits a negative voltage signal, the pull-down control circuit provides pull-down control to the gate voltage selection circuit.

[0025] The first low-voltage selection circuit includes transistors MN1 and MN2. The drain of transistor MN1 is electrically connected to the gate of transistor MN2 and serves as the input terminal of the first low-voltage selection circuit, connected to the VIN input signal. The drain of transistor MN2 is electrically connected to the gate of transistor MN1, and the drain of transistor MN2 is grounded. The source of transistor MN1 is electrically connected to the source of transistor MN2 and serves as the output terminal of the first low-voltage selection circuit. The first low-voltage selection circuit selects the lower voltage signal from the two signals, ground (GND) and the VIN input signal, as the low potential of the first inverter and the second inverter. Transistors MN1 and MN2 are low-threshold NMOS transistors, which can reduce voltage loss and achieve the lowest voltage value V. MIN It is closer to the lower values ​​in the ground GND and VIN input signals.

[0026] The first inverter includes transistors MP1, MN3, MN4, MN5, and MN6; the second inverter includes transistors MP2 and MN7; transistors MN3, MN4, MN5, and MN6 are connected in series, with the source of transistor MN3 electrically connected to the source of transistor MN1, the drain of transistor MN6 electrically connected to the drain of transistor MP1, and the source of transistor MP1 electrically connected to the VCC power supply; the gates of transistors MP1, MN3, MN4, MN5, and MN6 all serve as the input terminals of the first inverter, and the drain of transistor MP1 serves as the output terminal of the first inverter; the source of transistor MN7 is electrically connected to the source of transistor MN2, the drain of transistor MN7 is electrically connected to the drain of transistor MP2, and the source of transistor MP2 is electrically connected to the VCC power supply; the gates of transistors MP2 and MN7 both serve as the input terminals of the second inverter, and the drain of transistor MP2 serves as the output terminal of the second inverter. The MN3, MN4, MN5, and MN6 transistors are all NMOS transistors, and the MP1 transistor is a PMOS transistor; the MP2 transistor is a PMOS transistor, and the MN7 transistor is an NMOS transistor.

[0027] In the first inverter, transistors MN3, MN4, MN5, and MN6 are connected in series. The drain of transistor MN3 is electrically connected to the source of transistor MN4, the drain of transistor MN4 is electrically connected to the source of transistor MN5, and the drain of transistor MN5 is electrically connected to the source of transistor MN6. The series connection of transistors MN3, MN4, MN5, and MN6 increases the threshold voltage. Therefore, the output of the first inverter will only be pulled down when the power is off (VCC=0) and the VIN input signal is a negative voltage signal, thus causing the VIN output of the second inverter to be lower. SHUTDOWN The signal is pulled up from the negative voltage signal of the VIN input signal to VCC=0.

[0028] The first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 have the same circuit structure, both including a second low-voltage selection circuit, a third inverter, a fourth inverter, a latch circuit, and a fifth inverter. The input terminal of the third inverter is connected to the EN control signal through a NOT gate circuit, and the input terminal of the fourth inverter is also connected to the EN control signal. The output terminals of the third and fourth inverters are electrically connected to the first and second ports of the latch circuit, respectively. The third port of the latch circuit is connected to the VIN input signal. The second port of the latch circuit is electrically connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter serves as the output terminal of the gate voltage selection circuit, outputting VIN. G Signal, via V G The signal controls the on / off state of NMOS1 switch 11 and NMOS2 switch 12 in NMOS switching circuit 1. The input terminal of the second low-voltage selection circuit is connected to the VIN input signal, and the output terminal of the second low-voltage selection circuit is electrically connected to the first port of the latch circuit through the MN10 transistor; the gate of the MN10 transistor serves as the first input terminal of the gate voltage selection circuit, and the gate of the MN10 transistor is electrically connected to the output terminal of the pull-down control circuit, receiving VIN. SHUTDOWN The first port of the latch circuit is electrically connected to the gate of the MP8 transistor, the source of the MP8 transistor is electrically connected to the output of the fifth inverter, and the drain of the MP8 transistor is connected to the VIN input signal. The MP8 transistor is a PMOS transistor, and the MN10 transistor is an NMOS transistor.

[0029] The second low-voltage selection circuit includes an MN8 transistor and an MN9 transistor. The drain of the MN8 transistor is electrically connected to the gate of the MN9 transistor and serves as the input terminal of the second low-voltage selection circuit, connected to the VIN input signal. The drain of the MN9 transistor is electrically connected to the gate of the MN8 transistor, and the drain of the MN9 transistor is grounded. The source of the MN8 transistor is electrically connected to the source of the MN9 transistor and serves as the output terminal of the second low-voltage selection circuit. The second low-voltage selection circuit selects the lower voltage signal from the two input signals, ground (GND) and VIN, as its output signal. The MN8 and MN9 transistors are low-threshold NMOS transistors, which can reduce voltage loss.

[0030] The third inverter includes an MP3 transistor, an MN11 transistor, and a D1 diode; the fourth inverter includes an MP6 transistor, an MN12 transistor, and a D2 diode. The gate of the MP3 transistor is electrically connected to the gate of the MN11 transistor and serves as the input terminal of the third inverter. The drain of the MP3 transistor is electrically connected to the drain of the MN11 transistor through the D1 diode, and the drain of the MP3 transistor serves as the output terminal of the third inverter. The source of the MP3 transistor is electrically connected to the VCC power supply, and the source of the MN11 transistor is grounded. The gate of the MP6 transistor is electrically connected to the gate of the MN12 transistor and serves as the input terminal of the fourth inverter. The drain of the MP6 transistor is electrically connected to the drain of the MN12 transistor through the D2 diode, and the drain of the MP6 transistor serves as the output terminal of the fourth inverter. The source of the MP6 transistor is electrically connected to the VCC power supply, and the source of the MN12 transistor is grounded. The MP3 and MP6 transistors are PMOS transistors, and the MN11 and MN12 transistors are NMOS transistors. Under normal conditions, the third and fourth inverters correctly identify the EN control signal of the control logic from 0 to VCC.

[0031] The drain of the MP3 transistor is electrically connected to the anode of the D1 diode, and the cathode of the D1 diode is electrically connected to the drain of the MN11 transistor; the drain of the MP6 transistor is electrically connected to the anode of the D2 diode, and the cathode of the D2 diode is electrically connected to the drain of the MN12 transistor; the D1 and D2 diodes are configured to prevent a leakage path from the ground (GND) to the VIN input signal when the VIN input signal transmitted by the NMOS switching circuit 1 is a negative voltage signal, by forming a leakage path from the ground (GND) to the VIN input signal through the parasitic diode of the MN11 transistor.

[0032] The latch circuit includes transistors MP4, MP5, MN13, MN14, MN15, and MN16. The drain of transistor MP4 is electrically connected to the gate of transistor MP5 and the drain of transistor MN13, and the drain of transistor MP5 is electrically connected to the gate of transistor MP4 and the drain of transistor MN15. The drain of transistor MP4 serves as the first port of the latch circuit, and the drain of transistor MP5 serves as the second port. The sources of transistors MP4 and MP5 are both electrically connected to the VCC power supply. The gate of transistor MN13 is electrically connected to the gate of transistor MN16, and the gate of transistor MN15 is electrically connected to the gate of transistor MN14. The source of transistor MN13 is electrically connected to the drain of transistor MN14, and the source of transistor MN15 is electrically connected to the drain of transistor MN16. The source of transistor MN14 is electrically connected to the source of transistor MN16 and serves as the third port of the latch circuit, connected to the VIN input signal. The MP4 and MP5 transistors are both PMOS transistors, while the MN13, MN14, MN15, and MN16 transistors are all NMOS transistors. Under normal power-on conditions, the latch circuit uses a positive feedback loop to lock the two ends of the first and second ports to the VCC and VIN input signals, respectively.

[0033] The fifth inverter includes an MP7 transistor, an MN17 transistor, and a D3 diode. The gate of the MP7 transistor is electrically connected to the gate of the MN17 transistor and serves as the input terminal of the fifth inverter. The source of the MP7 transistor is electrically connected to the cathode of the D3 diode, and the anode of the D3 diode is electrically connected to the VCC power supply. The drain of the MP7 transistor is electrically connected to the drain of the MN17 transistor, the source of the MN17 transistor is connected to the VIN input signal, and the drain of the MP7 transistor serves as the output terminal of the fifth inverter. The MP7 transistor is a PMOS transistor, and the MN17 transistor is an NMOS transistor.

[0034] The fifth inverter and the MP8 transistor form the output stage. The function of the MP8 transistor is to turn on the circuit when the power is off and the VIN input signal is a positive voltage signal, preventing the latch circuit from operating. In this case, the gate of the MP8 transistor is at a low voltage, causing the MP8 transistor to conduct and switch the VIN input signal to a positive voltage. G The signal is pulled to the VIN input signal, thereby controlling the NMOS switching circuit 1 to turn off. The purpose of diode D3 is to output a V signal when the VIN input signal is positive in the power-off state. B Voltage is applied to the MP8 transistor, providing a floating potential V to the substrate of the MP8 transistor. BVoltage; if the substrate of the MP8 transistor is directly connected to the VCC power supply, a leakage path will be generated through the parasitic diode to form the VIN input signal to the VCC power supply. Therefore, diode D3 is set to avoid this situation.

[0035] The gate of the MN10 transistor is electrically connected to the output of the pull-down control circuit, receiving V. SHUTDOWN The signal; wherein the gate of transistor MN10 serves as the first input terminal of either the first gate voltage selection circuit 22 or the second gate voltage selection circuit 24. The input terminal of the third inverter is connected to the EN control signal via a NOT gate circuit, and the input terminal of the fourth inverter is also connected to the EN control signal; the input terminal of the third inverter is electrically connected to the output terminal of the NOT gate circuit, and the input terminal of the NOT gate circuit is connected to the EN control signal; both the input terminal of the NOT gate circuit and the input terminal of the fourth inverter serve as control terminals for the first gate voltage selection circuit 22 and the second gate voltage selection circuit 24, receiving the EN control signal. The input terminal of the second low-voltage selection circuit is connected to the VIN input signal, the third port of the Latch circuit is connected to the VIN input signal, the drain of transistor MP8 is connected to the VIN input signal, and the source of transistor MN17 is connected to the VIN input signal; wherein the input terminal of the second low-voltage selection circuit, the third port of the Latch circuit, the drain of transistor MP8, and the source of transistor MN17 all serve as the second input terminals for either the first gate voltage selection circuit 22 or the second gate voltage selection circuit 24.

[0036] The first gate voltage selection circuit 22 and the second gate voltage selection circuit 24 are used to provide the gate voltage for turning on or off the NMOS switching circuit 1 under normal power-on conditions, and to provide the gate voltage for turning off the NMOS switching circuit 1 when the chip is powered off. Under normal power-on conditions, when the EN control signal is high, V G The signal is pulled up to the VCC signal through the MP7 transistor of the fifth inverter, thus turning on NMOS switch circuit 1; when the EN control signal is low, V... G The signal is pulled down to the VIN input signal by the MN17 transistor of the fifth inverter, which turns off the NMOS switch circuit 1.

[0037] In the event of a power outage, when the VIN input signal transmitted by NMOS switching circuit 1 is a positive voltage signal, the MP8 transistor is turned on, switching V... G The signal is pulled to the VIN input signal, which in turn controls the NMOS switching circuit 1 to turn off.

[0038] In the event of a power outage, when the VIN input signal transmitted by the NMOS switching circuit 1 is a negative voltage signal, the latch circuit starts to operate. The pull-down control circuit provides the latch circuit of the gate voltage selection circuit with an initial pull-down state. At this time, the signal V output by the pull-down control circuit is... SHUTDOWN=0, causing transistor MN10 to conduct; the second low-voltage selection circuit transmits the VIN input signal to the first port of the latch circuit, pulling down the potential of the first port of the latch circuit to the VIN input signal, and pulling up the potential of the second port of the latch circuit to 0, and pulling down the VG signal output by the gate voltage selection circuit to the VIN input signal through transistor MN17; thus, the VG signal of NMO1 switch 11 and NMO2 switch 12 in NMOS switching circuit 1 is turned on. GS =0, NMOS switch circuit 1 is turned off.

[0039] The above description is merely a preferred embodiment of the present invention. Those skilled in the art can make several modifications and optimizations based on the above disclosure without departing from the basic principles described above. These modifications and optimizations should be considered as being within the scope of protection of the present invention.

Claims

1. A shutdown protection circuit for negative pressure signal transmission, characterized in that: The circuit includes an NMOS switch circuit (1), a first gate voltage selection circuit (22), a second gate voltage selection circuit (24), and a pull-down control circuit. One end of the NMOS switch circuit (1) serves as the input terminal for transmitting signals and is connected to an external VIN input signal. The other end of the NMOS switch circuit (1) serves as the output terminal for transmitting signals and is connected to the input terminal of the chip. The input and output terminals of the NMOS switch circuit (1) are electrically connected to the first input terminals of the first gate voltage selection circuit (22) and the second gate voltage selection circuit (24) respectively through a pull-down control circuit. The input and output terminals of the NMOS switch circuit (1) are electrically connected to the second input terminals of the first gate voltage selection circuit (22) and the second gate voltage selection circuit (24) respectively. The output terminals of the first gate voltage selection circuit (22) and the second gate voltage selection circuit (24) are electrically connected to the two control terminals of the NMOS switch circuit (1) respectively. Under normal power-on conditions, the gate voltage selection circuit controls the NMOS switching circuit (1) to turn on and off according to the received EN control signal; under power-off conditions, when the VIN input signal transmitted by the NMOS switching circuit (1) is a negative voltage signal, the gate voltage selection circuit controls the NMOS switching circuit (1) to turn on and off according to the received EN control signal. SHUTDOWN The signal causes the gate voltage selection circuit to select the VIN input signal to control the NMOS switching circuit (1) to turn off.

2. The shutdown protection circuit for negative pressure signal transmission according to claim 1, characterized in that: The NMOS switching circuit (1) includes an NMOS1 switch (11) and an NMOS2 switch (12); the drain of the NMOS1 switch (11) serves as the input terminal of the NMOS switching circuit (1), the source of the NMOS1 switch (11) is electrically connected to the source of the NMOS2 switch (12), and the drain of the NMOS2 switch (12) serves as the output terminal of the NMOS switching circuit (1); the gates of the NMOS1 switch (11) and the NMOS2 switch (12) serve as the two control terminals of the NMOS switching circuit (1).

3. The shutdown protection circuit for negative pressure signal transmission according to claim 2, characterized in that: The pull-down control circuit includes a first pull-down control circuit (21) and a second pull-down control circuit (23); the input terminal of the NMOS switch circuit (1) is electrically connected to the input terminal of the first pull-down control circuit (21), the output terminal of the first pull-down control circuit (21) is electrically connected to the first input terminal of the first gate voltage selection circuit (22), and the output terminal of the first gate voltage selection circuit (22) is electrically connected to the gate of the NMOS1 switch (11); the output terminal of the NMOS switch circuit (1) is electrically connected to the input terminal of the second pull-down control circuit (23), the output terminal of the second pull-down control circuit (23) is electrically connected to the first input terminal of the second gate voltage selection circuit (24), and the output terminal of the second gate voltage selection circuit (24) is electrically connected to the gate of the NMOS2 switch (12); the first gate voltage selection circuit (22) and the second gate voltage selection circuit (24) jointly control the opening and closing of the NMOS switch circuit (1).

4. The shutdown protection circuit for negative pressure signal transmission according to claim 3, characterized in that: The first pull-down control circuit (21) and the second pull-down control circuit (23) have the same circuit structure, both including a first low-voltage selection circuit, a first inverter, and a second inverter; the input terminal of the first low-voltage selection circuit serves as the input terminal of the pull-down control circuit and is electrically connected to the input or output terminal of the NMOS switching circuit (1); the output terminal of the first low-voltage selection circuit is electrically connected to the low-potential input terminals of the first inverter and the second inverter respectively; the input terminal of the first inverter is grounded, the output terminal of the first inverter is electrically connected to the input terminal of the second inverter, and the output terminal of the second inverter serves as the output terminal of the pull-down control circuit, outputting V SHUTDOWN Signal.

5. The shutdown protection circuit for negative pressure signal transmission according to claim 4, characterized in that: The first low-voltage selection circuit includes transistors MN1 and MN2; the drain of transistor MN1 is electrically connected to the gate of transistor MN2 and serves as the input terminal of the first low-voltage selection circuit; the drain of transistor MN2 is electrically connected to the gate of transistor MN1, and the drain of transistor MN2 is grounded; the source of transistor MN1 is electrically connected to the source of transistor MN2 and serves as the output terminal of the first low-voltage selection circuit; the first low-voltage selection circuit selects the lower voltage signal from the two input signals, ground GND and VIN, as the low potential of the first inverter and the second inverter.

6. The shutdown protection circuit for negative pressure signal transmission according to claim 4, characterized in that: The first inverter includes transistors MP1, MN3, MN4, MN5, and MN6; the second inverter includes transistors MP2 and MN7; transistors MN3, MN4, MN5, and MN6 are connected in series, with the source of transistor MN3 electrically connected to the source of transistor MN1, and the drain of transistor MN6 electrically connected to the drain of transistor MP1; the gates of transistors MP1, MN3, MN4, MN5, and MN6 all serve as the input terminals of the first inverter, and the drain of transistor MP1 serves as the output terminal of the first inverter; the source of transistor MN7 is electrically connected to the source of transistor MN2, and the drain of transistor MN7 is electrically connected to the drain of transistor MP2; the gates of transistors MP2 and MN7 both serve as the input terminals of the second inverter, and the drain of transistor MP2 serves as the output terminal of the second inverter.

7. The shutdown protection circuit for negative pressure signal transmission according to claim 3, characterized in that: The first gate voltage selection circuit (22) and the second gate voltage selection circuit (24) have the same circuit structure, both including a second low-voltage selection circuit, a third inverter, a fourth inverter, a Latch circuit, and a fifth inverter; the input terminal of the third inverter is connected to the EN control signal through a NOT gate circuit, and the input terminal of the fourth inverter is connected to the EN control signal; the output terminals of the third and fourth inverters are electrically connected to the first and second ports of the Latch circuit, respectively, and the third port of the Latch circuit is connected to the VIN input signal; the second port of the Latch circuit is electrically connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter serves as the output terminal of the gate voltage selection circuit, outputting VIN. G The input terminal of the second low-voltage selection circuit is connected to the VIN input signal, and the output terminal of the second low-voltage selection circuit is electrically connected to the first port of the latch circuit through the MN10 transistor; the gate of the MN10 transistor serves as the first input terminal of the gate voltage selection circuit, receiving VIN. SHUTDOWN Signal; the first port of the Latch circuit is electrically connected to the gate of the MP8 transistor, the source of the MP8 transistor is electrically connected to the output of the fifth inverter, and the drain of the MP8 transistor is connected to the VIN input signal.

8. The shutdown protection circuit for negative pressure signal transmission according to claim 7, characterized in that: The third inverter includes an MP3 transistor, an MN11 transistor, and a D1 diode; the fourth inverter includes an MP6 transistor, an MN12 transistor, and a D2 diode; the gate of the MP3 transistor is electrically connected to the gate of the MN11 transistor and serves as the input terminal of the third inverter; the drain of the MP3 transistor is electrically connected to the drain of the MN11 transistor through the D1 diode, and the drain of the MP3 transistor serves as the output terminal of the third inverter; the gate of the MP6 transistor is electrically connected to the gate of the MN12 transistor and serves as the input terminal of the fourth inverter; the drain of the MP6 transistor is electrically connected to the drain of the MN12 transistor through the D2 diode, and the drain of the MP6 transistor serves as the output terminal of the fourth inverter.

9. A shutdown protection circuit for negative pressure signal transmission according to claim 7, characterized in that: The latch circuit includes an MP4 transistor, an MP5 transistor, an MN13 transistor, an MN14 transistor, an MN15 transistor, and an MN16 transistor. The drain of the MP4 transistor is electrically connected to the gate of the MP5 transistor and the drain of the MN13 transistor, and the drain of the MP5 transistor is electrically connected to the gate of the MP4 transistor and the drain of the MN15 transistor. The drain of the MP4 transistor serves as the first port of the latch circuit, and the drain of the MP5 transistor serves as the second port of the latch circuit. The gate of the MN13 transistor is electrically connected to the gate of the MN16 transistor, and the gate of the MN15 transistor is electrically connected to the gate of the MN14 transistor. The source of the MN13 transistor is electrically connected to the drain of the MN14 transistor, and the source of the MN15 transistor is electrically connected to the drain of the MN16 transistor. The source of the MN14 transistor is electrically connected to the source of the MN16 transistor and serves as the third port of the latch circuit.

10. A shutdown protection circuit for negative pressure signal transmission according to claim 7, characterized in that: The fifth inverter includes an MP7 transistor, an MN17 transistor, and a D3 diode; the gate of the MP7 transistor is electrically connected to the gate of the MN17 transistor and serves as the input terminal of the fifth inverter; the source of the MP7 transistor is electrically connected to the cathode of the D3 diode, and the anode of the D3 diode is electrically connected to the VCC power supply; the drain of the MP7 transistor is electrically connected to the drain of the MN17 transistor, the source of the MN17 transistor is connected to the VIN input signal, and the drain of the MP7 transistor serves as the output terminal of the fifth inverter.

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