Micro power supply management circuit based on charge pump

Abstract

The invention discloses a micro power supply management circuit based on a charge pump, and the circuit comprises a first charge pump, a level conversion module, a non-overlapping phase generation module, and a negative voltage inverter module. The first charge pump is additionally arranged to provide long-term stable grid negative voltage for the grid of the connected external circuit working module, so that the effect that the external circuit working module has relatively low power consumption in a sleep mode is realized; the micro power supply management circuit solves the problem that in the prior art, leakage current of components in a micro power supply management circuit is gradually increased due to working characteristics of a charge pump, so that power consumption of the circuit is increased, and the effect of reducing power consumption of the micro power supply management circuit in a sleep mode is achieved.

Description

Technical Field

[0001] This application relates to the field of power supply circuits, and more particularly to a micro power management circuit based on a charge pump. Background Technology

[0002] A charge pump is a DC-DC converter that uses capacitors as energy storage elements. It is mostly used to generate an output voltage that is higher than the input voltage or to generate a negative output voltage. Charge pump circuits have high electrical efficiency, about 90%-95%, and the circuits are quite simple.

[0003] In existing applications, charge pumps utilize switching elements to control the voltage connected to the capacitor. For example, a two-stage cycle can be used to generate a higher pulse voltage output from a lower input voltage. In the first stage of the cycle, the capacitor is connected to the power supply and thus charged to the same voltage. During this first stage, the circuit configuration is adjusted so that the capacitor and the power supply voltage are connected in series. Ignoring leakage current and assuming no load, the output voltage will be twice the input voltage (the original power supply voltage plus the voltage across the capacitor). The pulse characteristic of the higher output voltage can be filtered using an output filter capacitor.

[0004] However, traditional charge pumps in micro power management circuits mainly focus on how to boost DC voltage and manage power consumption. But under sub-nanometer process conditions, the leakage current of the device will increase due to the operating characteristics of the charge pump itself, leading to an increase in circuit power consumption. Therefore, how to reduce the leakage current generated in micro power management circuits has become an urgent problem to be solved. Application content

[0005] Therefore, it is necessary to address the above problems and propose a method to reduce leakage current generated in micro power management circuits, which has become an urgent problem to be solved.

[0006] This application provides a micro power management circuit based on a charge pump, including a first charge pump, a level conversion module, a non-overlapping phase generation module, and a negative voltage inverter module;

[0007] The first charge pump, the level conversion module, the non-overlapping phase generation module, and the negative voltage inverter module are arranged in two sets in the charge pump-based micro power management circuit. The input terminal of the first charge pump is connected to the external data terminal, the power supply terminal of the first charge pump is connected to the external power supply, the signal terminal of the first charge pump is connected to the input terminal of the level conversion module, and the signal terminal of the level conversion module is connected to the input terminal of the non-overlapping phase generation module, thereby realizing the effect of level signal conversion through the level conversion module. The output terminal of the non-overlapping phase generation module is connected to the signal of the negative voltage inverter unit, thereby realizing the function of generating the corresponding voltage signal through the non-overlapping phase generation module. The power supply terminal of the negative voltage inverter module is connected to the external power supply, and the output terminals of the negative voltage inverter module, the level conversion module, and the non-overlapping phase generation module are interconnected and connected to the gate of the external circuit working module, thereby outputting a constant gate negative voltage and realizing the effect of maintaining low power consumption in the sleep mode of the external circuit working module.

[0008] Furthermore, the negative voltage inverter module includes two inverter modules. The input terminals of the inverter modules are respectively connected to the output terminals of the non-overlapping phase generation module, and the output terminals of the inverter modules are interconnected and connected to the external circuit working module.

[0009] The output terminal of the non-overlapping phase generation module includes a first phase signal output terminal and a second phase signal output terminal, and the inverter module includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a first capacitor, and a second capacitor.

[0010] The gates of the first and second field-effect transistors are connected to the first phase signal output terminal. The drain of the first field-effect transistor is connected to the drain of the seventh field-effect transistor. The source of the first field-effect transistor is connected to the positive terminal of the first capacitor and the drain of the second field-effect transistor. The source of the second field-effect transistor is grounded. The negative terminal of the first capacitor is connected to the drain of the third and fourth field-effect transistors. The source of the third field-effect transistor is grounded. The drain of the fourth field-effect transistor is connected to the external circuit working module and the drain of the sixth field-effect transistor. The gate of the transistor is connected to the gate of the fifth field-effect transistor and the first phase signal output terminal. The gate of the third field-effect transistor is connected to the gate of the sixth field-effect transistor and the second phase signal output terminal. The source of the fifth field-effect transistor is grounded. The drain of the fifth field-effect transistor is connected to the source of the sixth field-effect transistor and the negative terminal of the second capacitor. The positive terminal of the second capacitor is connected to the source of the seventh field-effect transistor and the drain of the eighth field-effect transistor. The drain of the eighth field-effect transistor is grounded. The gates of the seventh and eighth field-effect transistors are connected and connected to the second phase signal output terminal.

[0011] Furthermore, the level conversion module includes a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, and a twelfth field-effect transistor;

[0012] The gate of the ninth field-effect transistor is connected to the clock signal output by the first charge pump, the drain of the ninth field-effect transistor is connected to an external power supply, the source of the ninth field-effect transistor is connected to the drain of the tenth field-effect transistor and the gate of the twelfth field-effect transistor and serves as the clock signal output terminal of the level conversion module, the source of the tenth field-effect transistor is connected to the external circuit working module, the drain of the eleventh field-effect transistor is connected to an external power supply, the gate of the eleventh field-effect transistor is connected to the clock signal output by the first charge pump, the source of the eleventh field-effect transistor is connected to the drain of the twelfth field-effect transistor and the gate of the tenth field-effect transistor and serves as the clock signal output terminal of the level conversion module, and the source of the twelfth field-effect transistor is connected to the external circuit working module.

[0013] Furthermore, the non-overlapping phase generation module includes a first NOR gate, a second NOR gate, a first inverter, a second inverter, a third inverter, and a fourth inverter.

[0014] The power supply terminals of the first NOR gate, the second NOR gate, the first inverter, the second inverter, the third inverter, and the fourth inverter are all connected to an external power supply. The output terminals of the first NOR gate, the second NOR gate, the first inverter, the second inverter, the third inverter, and the fourth inverter are all connected to the external circuit module. The first input terminal of the first NOR gate is connected to the clock signal output by the first charge pump. The output terminal of the first NOR gate is connected to the data input terminal of the first inverter. The data output terminal of the first inverter is connected to the data input terminal of the second inverter. The data output terminal of the second inverter is connected to the second input terminal of the first NOR gate.

[0015] The first input terminal of the second NOR gate is connected to the clock signal output by the first charge pump, the output terminal of the second NOR gate is connected to the data input terminal of the third inverter, the data output terminal of the third inverter is connected to the data input terminal of the fourth inverter, and the data output terminal of the fourth inverter is connected to the second input terminal of the second NOR gate.

[0016] Furthermore, the charge pump-based micro power management circuit also includes a master switch unit, a phase-locked loop unit, and a logic voltage power supply unit;

[0017] The power supply terminals of the main switch unit, the phase-locked loop unit, and the logic voltage power supply unit are all connected to an external power supply. The output terminal of the main switch unit is connected to the external circuit working module, thereby providing a start-up voltage to the external circuit working module. The output terminal of the phase-locked loop unit is connected to the external circuit working module, thereby providing a monitored phase-locked loop conversion voltage to the external circuit working module. The output terminal of the logic voltage power supply unit is connected to the external circuit working module, thereby providing a monitored logic voltage to the external circuit working module.

[0018] Furthermore, the main switching unit includes a first rectifier module, a second charge pump, a first operational amplifier, a first resistor, a second resistor, a thirteenth field-effect transistor, a first diode, and a second diode;

[0019] The first rectifier module contains several rectifier modules, and several rectifiers are connected in series within each rectifier module. The input terminal of the first rectifier module is connected to an external power supply and the voltage output terminal of the second charge pump. The signal terminal of the second charge pump is connected to the signal terminal of the rectifier module. The ground terminal of the second charge pump is grounded. The voltage input terminal of the second charge pump is connected to the drain of the thirteenth field-effect transistor. The source of the thirteenth field-effect transistor is connected to an external power supply. The gate of the thirteenth field-effect transistor is connected to the output terminal of the first operational amplifier. The power supply terminal of the first operational amplifier is connected to an external power supply. The ground terminal of the first operational amplifier is grounded. The first input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor. The second input terminal of the first operational amplifier is connected to an external power supply. The other end of the first resistor is connected to an external power supply. The other end of the second resistor is grounded. The output terminal of the first rectifier module is connected to the anode of the first diode and serves as the output terminal of the main switch unit. The cathode of the first diode is connected to the anode of the second diode. The cathode of the second diode is connected to an external power supply.

[0020] Furthermore, the logic voltage power supply unit includes a second rectifier module, a third charge pump, a second operational amplifier, a third resistor, a fourth resistor, a fourteenth field-effect transistor, a third diode, and a fourth diode;

[0021] The second rectifier module contains several parallel rectifier modules, and each rectifier module contains several rectifiers connected in series. The input terminal of the second rectifier module is connected to an external power supply and the voltage output terminal of the third charge pump. The signal terminal of the third charge pump is connected to the signal terminal of the rectifier module. The ground terminal of the third charge pump is grounded. The voltage input terminal of the third charge pump is connected to the drain of the fourteenth field-effect transistor. The source of the fourteenth field-effect transistor is connected to an external power supply. The gate of the fourteenth field-effect transistor is connected to the output terminal of the second operational amplifier. The power supply terminal is connected to an external power supply. The ground terminal of the second operational amplifier is grounded. The positive input terminal of the second operational amplifier is connected to one end of the third resistor and one end of the fourth resistor. The negative input terminal of the second operational amplifier is connected to an external power supply. The other end of the third resistor is connected to an external power supply. The other end of the fourth resistor is grounded. The output terminal of the second rectifier module is connected to the positive terminal of the third diode and serves as the output terminal of the logic voltage power supply unit. The negative terminal of the third diode is connected to the positive terminal of the fourth diode. The negative terminal of the fourth diode is connected to an external power supply.

[0022] Furthermore, the phase-locked loop unit includes a third rectifier module, a fourth charge pump, a third operational amplifier, and a fifteenth field-effect transistor;

[0023] The third rectifier module contains several rectifiers connected in parallel. The voltage output terminal of the fourth charge pump is connected to the input terminal of the third rectifier module and an external power supply. The signal output terminal of the fourth charge pump is connected to the signal terminal of the third rectifier module. The voltage input terminal of the fourth charge pump is connected to the drain of the fifteenth field-effect transistor. The source of the fifteenth field-effect transistor is connected to an external power supply. The gate of the fifteenth field-effect transistor is connected to the output terminal of the third operational amplifier. The power supply terminal of the third operational amplifier is connected to an external power supply. The ground terminal of the third operational amplifier is grounded. The positive input terminal of the third operational amplifier is connected to an external power supply. The negative input terminal of the third operational amplifier is connected to the output terminal of the third rectifier module and serves as the output terminal of the phase-locked loop unit.

[0024] This application, through the above structure, achieves the effect of lower power consumption of the external circuit working module in sleep mode by additionally setting a first charge pump to provide a long-term stable gate negative voltage to the gate of the connected external circuit working module. This solves the problem in the prior art that the leakage current of the components in the micro power management circuit will gradually increase due to the working characteristics of the charge pump itself, leading to an increase in circuit power consumption, and reduces the power consumption of the micro power management circuit in sleep mode. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] in:

[0027] Figure 1 This is a schematic diagram of a micro power management circuit based on a charge pump in one embodiment;

[0028] Figure 2 This is a schematic diagram of a micro power management circuit based on a charge pump in one embodiment;

[0029] Figure 3 This is a circuit diagram of a level conversion module in one embodiment;

[0030] Figure 4 This is a circuit diagram of a non-overlapping phase generation module in one embodiment;

[0031] Figure 5 This is a circuit diagram of the main switch unit in one embodiment;

[0032] Figure 6 This is a circuit diagram of a logic voltage power supply unit in one embodiment;

[0033] Figure 7 This is a circuit diagram of a phase-locked loop unit in one embodiment;

[0034] The labels in the diagram are as follows: 1-Level conversion module, 2-Non-overlapping phase generation module, 3-Negative voltage inverter module, 31-Inverter module, 4-Main switch unit, 5-Phase-locked loop unit, 6-Logic voltage power supply unit, 41-First rectifier module, 61-Second rectifier module, 51-Third rectifier module. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0036] refer to Figure 1 and Figure 2 This application provides a micro power management circuit based on a charge pump, including a first charge pump CP1, a level conversion module 1, a non-overlapping phase generation module 2, and a negative voltage inverter module 3;

[0037] The charge pump-based micro power management circuit has two sets of components: a first charge pump CP1, a level conversion module 1, a non-overlapping phase generation module 2, and a negative voltage inverter module 3. The input terminal of the first charge pump CP1 is connected to an external data terminal, the power supply terminal of the first charge pump CP1 is connected to an external power supply, the signal terminal of the first charge pump CP1 is connected to the input terminal of the level conversion module 1, and the signal terminal of the level conversion module 1 is connected to the input terminal of the non-overlapping phase generation module 2, thereby achieving the effect of level signal conversion through the level conversion module 1. The output terminal of the non-overlapping phase generation module 2 is connected to the signal of the negative voltage inverter unit, thereby achieving the function of generating the corresponding voltage signal through the non-overlapping phase generation module 2. The power supply terminal of the negative voltage inverter module 3 is connected to an external power supply, and the output terminals of the negative voltage inverter module 3, the level conversion module 1, and the non-overlapping phase generation module 2 are interconnected and connected to the gate of the external circuit working module, thereby outputting a constant gate negative voltage and achieving the effect of maintaining low power consumption in the sleep mode of the external circuit working module.

[0038] As described in the above embodiments, the first charge pump CP1, level conversion module 1, non-overlapping phase generation module 2, and negative voltage inverter module 3 are grouped together in the charge pump-based micro power management circuit. The charge pump-based micro power management circuit has two groups of these components. The input terminal of the first charge pump CP1 is connected to an external data terminal, and the signal terminal of the first charge pump CP1 is connected to the input terminal of the level conversion module 1. At this time, the first charge pump CP1 sends a 6kHz clock signal to the level conversion module 1 based on the acquired external data. In this embodiment, the external data is an input voltage of 0.3V. The level conversion module 1, non-overlapping phase generation module 2, and negative voltage inverter module 3 then perform voltage conversion based on the 0.3V input voltage, thereby combining and outputting a set value of gate negative voltage to the gate of the external circuit working module. This allows the external circuit working module to maintain low power consumption in sleep mode based on the gate negative voltage, achieving the effect of maintaining low power consumption in sleep mode.

[0039] This embodiment, through the above structure, achieves the effect of low power consumption of the external circuit working module in sleep mode by additionally setting a first charge pump to provide a long-term stable gate negative voltage to the gate of the connected external circuit working module. This solves the problem in the prior art where the leakage current of the components in the micro power management circuit gradually increases due to the working characteristics of the charge pump itself, leading to an increase in circuit power consumption, and reduces the power consumption of the micro power management circuit in sleep mode.

[0040] Referring to Figure 2, in one embodiment, the negative voltage inverter module 3 includes two inverter modules 31. The input terminals of the inverter modules 31 are respectively connected to the output terminals of the non-overlapping phase generation module 2, and the output terminals of the inverter modules 31 are interconnected and connected to the external circuit working module.

[0041] The output of the non-overlapping phase generation module 2 includes a first phase signal output terminal and a second phase signal output terminal. The inverter module 31 includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a first capacitor C1, and a second capacitor C2.

[0042] The gates of the first field-effect transistor M1 and the second field-effect transistor M2 are connected to the first phase signal output terminal. The drain of the first field-effect transistor M1 is connected to the drain of the seventh field-effect transistor M7. The source of the first field-effect transistor M1 is connected to the positive terminal of the first capacitor C1 and the drain of the second field-effect transistor M2. The source of the second field-effect transistor M2 is grounded. The negative terminal of the first capacitor C1 is connected to the drain of the third field-effect transistor M3 and the source of the fourth field-effect transistor M4. The source of the third field-effect transistor M3 is grounded. The drain of the fourth field-effect transistor M4 is connected to the external circuit working module and the drain of the sixth field-effect transistor M6. The gate of transistor 4 is connected to the gate of the fifth field-effect transistor M5 and the first phase signal output terminal. The gate of the third field-effect transistor M3 is connected to the gate of the sixth field-effect transistor M6 and the second phase signal output terminal. The source of the fifth field-effect transistor M5 is grounded. The drain of the fifth field-effect transistor M5 is connected to the source of the sixth field-effect transistor M6 and the negative terminal of the second capacitor C2. The positive terminal of the second capacitor C2 is connected to the source of the seventh field-effect transistor M7 and the drain of the eighth field-effect transistor M8. The drain of the eighth field-effect transistor M8 is grounded. The gates of the seventh field-effect transistor M7 and the eighth field-effect transistor M8 are connected and connected to the second phase signal output terminal.

[0043] As described in the above embodiments, the negative voltage inverter module 3 is provided with two inverter modules 31, and the inverter module 31 is provided with a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a seventh field-effect transistor M7, and an eighth field-effect transistor M8. The negative voltage inverter module 3 can control the charging and discharging of the first capacitor C1 and the second capacitor C2 according to the above-mentioned field-effect transistors, thereby realizing the voltage conversion of the input voltage and the output of the corresponding gate negative voltage.

[0044] refer to Figure 3 In one embodiment, the level conversion module 1 includes a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, and a twelfth field-effect transistor M12.

[0045] The gate of the ninth field-effect transistor M9 is connected to the clock signal output by the first charge pump CP1. The drain of the ninth field-effect transistor M9 is connected to the external power supply. The source of the ninth field-effect transistor M9 is connected to the drain of the tenth field-effect transistor M10 and the gate of the twelfth field-effect transistor M12 and serves as the clock signal output terminal of the level conversion module 1. The source of the tenth field-effect transistor M10 is connected to the external circuit working module. The drain of the eleventh field-effect transistor M11 is connected to the external power supply. The gate of the eleventh field-effect transistor M11 is connected to the clock signal output by the first charge pump CP1. The source of the eleventh field-effect transistor M11 is connected to the drain of the twelfth field-effect transistor M12 and the gate of the tenth field-effect transistor M10 and serves as the clock signal output terminal of the level conversion module 1. The source of the twelfth field-effect transistor M12 is connected to the external circuit working module.

[0046] As described in the above embodiments, the ninth field-effect transistor M9, the tenth field-effect transistor M10, the eleventh field-effect transistor M11, and the twelfth field-effect transistor M12 in the level conversion module 1 are used to convert the input voltage signal to a corresponding gate negative voltage after level conversion.

[0047] refer to Figure 4 In one embodiment, the non-overlapping phase generation module 2 is provided with a first NOR gate G1, a second NOR gate G2, a first inverter I1, a second inverter I2, a third inverter I3 and a fourth inverter I4.

[0048] The power supply terminals of the first NOR gate G1, the second NOR gate G2, the first inverter I1, the second inverter I2, the third inverter I3, and the fourth inverter I4 are all connected to an external power supply. The output terminals of the first NOR gate G1, the second NOR gate G2, the first inverter I1, the second inverter I2, the third inverter I3, and the fourth inverter I4 are all connected to an external circuit module. The first input terminal of the first NOR gate G1 is connected to the clock signal output by the first charge pump CP1. The output of G1 is connected to the data input of the first inverter I1. The data output of the first inverter I1 is connected to the data input of the second inverter I2. The data output of the second inverter I2 is connected to the second input of the first NOR gate G1. The first input of the second NOR gate G2 is connected to the clock signal output by the first charge pump CP1. The output of the second NOR gate G2 is connected to the data input of the third inverter I3. The data output of the third inverter I3 is connected to the data input of the fourth inverter I4. The data output of the fourth inverter I4 is connected to the second input of the second NOR gate G2.

[0049] As described in the above embodiments, the non-overlapping phase generation module 2 is used to generate two non-overlapping clock signals based on the built-in logic gates (i.e., the first NOR gate G1 and the second NOR gate G2) and delay devices (i.e., the first inverter I1, the second inverter I2, the third inverter I3 and the fourth inverter I4), thereby enabling the input of the above two clock signals into the negative voltage inverter module 3, so that the negative voltage inverter module 3 can convert the input voltage and output the corresponding gate negative voltage.

[0050] refer to Figure 1 In one embodiment, the charge pump-based micro power management circuit further includes a master switch unit 4, a phase-locked loop unit 5, and a logic voltage power supply unit 6.

[0051] The power supply terminals of the main switch unit 4, the phase-locked loop unit 5, and the logic voltage power supply unit 6 are all connected to an external power supply. The output terminal of the main switch unit 4 is connected to an external circuit working module, thereby providing a start-up voltage to the external circuit working module. The output terminal of the phase-locked loop unit 5 is connected to an external circuit working module, thereby providing a monitored phase-locked loop conversion voltage to the external circuit working module. The output terminal of the logic voltage power supply unit 6 is connected to an external circuit working module, thereby providing a monitored logic voltage to the external circuit working module.

[0052] As described in the above embodiments, the main switch unit 4 is used to convert the input voltage into an output voltage with a high positive power supply rejection ratio, thereby serving as the start-up voltage and power supply voltage for the external circuit working module. The phase-locked loop unit 5 is used to convert the input voltage into a monitored phase-locked loop power supply voltage, and the power supply current is below 200uA. The logic voltage power supply unit 6 is used to convert the input voltage into a monitored logic voltage and output it. It can be understood that in this embodiment, the voltage value of the input voltage is 0.3V.

[0053] refer to Figure 5 In one embodiment, the main switch unit 4 includes a first rectifier module 41, a second charge pump CP2, a first operational amplifier U1, a first resistor R1, a second resistor R2, a thirteenth field-effect transistor M13, a first diode D1, and a second diode D2.

[0054] The first rectifier module 41 contains several rectifier modules 42, and several rectifiers are connected in series within each rectifier module 42. The input terminal of the first rectifier module 41 is connected to the external power supply and the voltage output terminal of the second charge pump CP2. The signal terminal of the second charge pump CP2 is connected to the signal terminal of the rectifier module. The ground terminal of the second charge pump CP2 is grounded. The voltage input terminal of the second charge pump CP2 is connected to the drain of the thirteenth field-effect transistor M13. The source of the thirteenth field-effect transistor M13 is connected to the external power supply. The gate of the thirteenth field-effect transistor M13 is connected to the output terminal of the first operational amplifier U1. The power supply terminal of the first operational amplifier U1 is connected to an external power supply. The ground terminal of the first operational amplifier U1 is grounded. The first input terminal of the first operational amplifier U1 is connected to one end of the first resistor R1 and one end of the second resistor R2. The second input terminal of the first operational amplifier U1 is connected to an external power supply. The other end of the first resistor R1 is connected to an external power supply. The other end of the second resistor R2 is grounded. The output terminal of the first rectifier module 41 is connected to the positive terminal of the first diode D1 and serves as the output terminal of the main switch unit 4. The negative terminal of the first diode D1 is connected to the positive terminal of the second diode D2. The negative terminal of the second diode D2 is connected to an external power supply.

[0055] As described in the above embodiments, the first rectifier module 41 is provided with a plurality of parallel rectifier modules 42, and the rectifier module 42 is provided with a plurality of series rectifiers, thereby realizing the function of voltage conversion of the input voltage. The second charge pump CP2 is used to convert the input voltage into a lower DC voltage. In addition, the first operational amplifier U1 and the thirteenth field-effect transistor M13 are both used to amplify the input voltage, thereby realizing the accurate output of the set parameters of the output voltage, thereby converting the input voltage into an output voltage with a high positive power supply rejection ratio, thus serving as the start-up voltage and power supply voltage of the external circuit working module.

[0056] refer to Figure 6 In one embodiment, the logic voltage power supply unit 6 includes a second rectifier module 61, a third charge pump CP3, a second operational amplifier U2, a third resistor R3, a fourth resistor R4, a fourteenth field-effect transistor M14, a third diode D3, and a fourth diode D4.

[0057] The second rectifier module 61 contains several parallel rectifier modules 42, and several rectifiers are connected in series within each rectifier module 42. The input terminal of the second rectifier module 61 is connected to the external power supply and the voltage output terminal of the third charge pump CP3. The signal terminal of the third charge pump CP3 is connected to the signal terminal of the rectifier module. The ground terminal of the third charge pump CP3 is grounded. The voltage input terminal of the third charge pump CP3 is connected to the drain of the fourteenth field-effect transistor M14. The source of the fourteenth field-effect transistor M14 is connected to the external power supply. The gate of the fourteenth field-effect transistor M14 is connected to the output terminal of the second operational amplifier U2. The power supply terminal of the second operational amplifier U2 is connected to an external power supply. The ground terminal of the second operational amplifier U2 is grounded. The positive input terminal of the second operational amplifier U2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4. The negative input terminal of the second operational amplifier U2 is connected to an external power supply. The other end of the third resistor R3 is connected to an external power supply. The other end of the fourth resistor R4 is grounded. The output terminal of the second rectifier module 61 is connected to the positive terminal of the third diode D3 and serves as the output terminal of the logic voltage power supply unit 6. The negative terminal of the third diode D3 is connected to the positive terminal of the fourth diode D4. The negative terminal of the fourth diode D4 is connected to an external power supply.

[0058] As described in the above embodiments, the second rectifier module 61 is provided with a plurality of parallel rectifier modules 42, and the rectifier module 42 is provided with a plurality of series rectifiers, thereby realizing the function of voltage conversion of the input voltage. The third charge pump CP3 is used to convert the input voltage into a lower DC voltage. In addition, the second operational amplifier U2 and the fourteenth field-effect transistor M14 are both used to amplify the input voltage, thereby realizing the accurate output of the set parameters of the output voltage, and achieving the effect of converting the input voltage into the monitored phase-locked loop power supply voltage.

[0059] refer to Figure 7 In one embodiment, the phase-locked loop unit 5 includes a third rectifier module 51, a fourth charge pump CP4, a third operational amplifier U3, and a fifteenth field-effect transistor M15.

[0060] The third rectifier module 51 contains several parallel rectifiers. The voltage output terminal of the fourth charge pump CP4 is connected to the input terminal of the third rectifier module 51 and the external power supply. The signal output terminal of the fourth charge pump CP4 is connected to the signal terminal of the third rectifier module 51. The voltage input terminal of the fourth charge pump CP4 is connected to the drain of the fifteenth field-effect transistor M15. The source of the fifteenth field-effect transistor M15 is connected to the external power supply. The gate of the fifteenth field-effect transistor M15 is connected to the output terminal of the third operational amplifier U3. The power supply terminal of the third operational amplifier U3 is connected to the external power supply. The ground terminal of the third operational amplifier U3 is grounded. The positive input terminal of the third operational amplifier U3 is connected to the external power supply. The negative input terminal of the third operational amplifier U3 is connected to the output terminal of the third rectifier module 51 and serves as the output terminal of the phase-locked loop unit 5.

[0061] As described in the above embodiments, the third rectifier module 51 is provided with several rectifiers connected in series, thereby realizing the function of voltage conversion of the input voltage. At the same time, the fourth charge pump CP4 is used to convert the input voltage into a lower DC voltage. In addition, the third operational amplifier U3 and the fifteenth field-effect transistor M15 are used to amplify the input voltage, thereby realizing the accurate output of the set parameters of the output voltage, and achieving the effect of converting the input voltage into a monitored logic voltage.

[0062] As can be seen from the above embodiments, the greatest benefit of this application is that by additionally setting a first charge pump to provide a long-term stable gate negative voltage to the gate of the connected external circuit working module, the external circuit working module achieves a low power consumption effect in sleep mode. This solves the problem in the prior art where the leakage current of the components in the micro power management circuit gradually increases due to the working characteristics of the charge pump itself, leading to an increase in circuit power consumption, and reduces the power consumption of the micro power management circuit in sleep mode.

[0063] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, the above embodiments are not described in detail.

[0064] All possible combinations of the various technical features in the examples are described; however, only if these technical features are...

[0065] There is no contradiction in the combinations, and all combinations should be considered to be within the scope of this specification.

[0066] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A micro power management circuit based on a charge pump, characterized in that, It includes a first charge pump, a level conversion module, a non-overlapping phase generation module, and a negative voltage inverter module; The first charge pump, the level conversion module, the non-overlapping phase generation module, and the negative voltage inverter module are arranged in two sets in the charge pump-based micro power management circuit. The input terminal of the first charge pump is connected to the external data terminal, the power supply terminal of the first charge pump is connected to the external power supply, the signal terminal of the first charge pump is connected to the input terminal of the level conversion module, and the signal terminal of the level conversion module is connected to the input terminal of the non-overlapping phase generation module, thereby realizing the effect of level signal conversion through the level conversion module. The output terminal of the non-overlapping phase generation module is connected to the signal of the negative voltage inverter unit, thereby realizing the function of generating the corresponding voltage signal through the non-overlapping phase generation module. The power supply terminal of the negative voltage inverter module is connected to the external power supply, and the output terminals of the negative voltage inverter module, the level conversion module, and the non-overlapping phase generation module are interconnected and connected to the gate of the external circuit working module, thereby outputting a constant gate negative voltage and realizing the effect of maintaining low power consumption in the sleep mode of the external circuit working module.

2. The micro power management circuit based on a charge pump as described in claim 1, characterized in that, The negative voltage inverter module includes two inverter modules. The input terminals of the inverter modules are respectively connected to the output terminals of the non-overlapping phase generation module. The output terminals of the inverter modules are interconnected and connected to the external circuit working module. The output terminal of the non-overlapping phase generation module includes a first phase signal output terminal and a second phase signal output terminal, and the inverter module includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a first capacitor, and a second capacitor. The gates of the first and second field-effect transistors are connected to the first phase signal output terminal. The drain of the first field-effect transistor is connected to the drain of the seventh field-effect transistor. The source of the first field-effect transistor is connected to the positive terminal of the first capacitor and the drain of the second field-effect transistor. The source of the second field-effect transistor is grounded. The negative terminal of the first capacitor is connected to the drain of the third and fourth field-effect transistors. The source of the third field-effect transistor is grounded. The drain of the fourth field-effect transistor is connected to the external circuit working module and the drain of the sixth field-effect transistor. The gate of the transistor is connected to the gate of the fifth field-effect transistor and the first phase signal output terminal. The gate of the third field-effect transistor is connected to the gate of the sixth field-effect transistor and the second phase signal output terminal. The source of the fifth field-effect transistor is grounded. The drain of the fifth field-effect transistor is connected to the source of the sixth field-effect transistor and the negative terminal of the second capacitor. The positive terminal of the second capacitor is connected to the source of the seventh field-effect transistor and the drain of the eighth field-effect transistor. The drain of the eighth field-effect transistor is grounded. The gates of the seventh and eighth field-effect transistors are connected and connected to the second phase signal output terminal.

3. The micro power management circuit based on a charge pump as described in claim 1, characterized in that, The level conversion module includes a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, and a twelfth field-effect transistor; The gate of the ninth field-effect transistor is connected to the clock signal output by the first charge pump, the drain of the ninth field-effect transistor is connected to an external power supply, the source of the ninth field-effect transistor is connected to the drain of the tenth field-effect transistor and the gate of the twelfth field-effect transistor and serves as the clock signal output terminal of the level conversion module, the source of the tenth field-effect transistor is connected to the external circuit working module, the drain of the eleventh field-effect transistor is connected to an external power supply, the gate of the eleventh field-effect transistor is connected to the clock signal output by the first charge pump, the source of the eleventh field-effect transistor is connected to the drain of the twelfth field-effect transistor and the gate of the tenth field-effect transistor and serves as the clock signal output terminal of the level conversion module, and the source of the twelfth field-effect transistor is connected to the external circuit working module.

4. The micro power management circuit based on a charge pump as described in claim 1, characterized in that, The non-overlapping phase generation module includes a first NOR gate, a second NOR gate, a first inverter, a second inverter, a third inverter, and a fourth inverter. The power supply terminals of the first NOR gate, the second NOR gate, the first inverter, the second inverter, the third inverter, and the fourth inverter are all connected to an external power supply. The output terminals of the first NOR gate, the second NOR gate, the first inverter, the second inverter, the third inverter, and the fourth inverter are all connected to the external circuit module. The first input terminal of the first NOR gate is connected to the clock signal output by the first charge pump. The output terminal of the first NOR gate is connected to the data input terminal of the first inverter. The data output terminal of the first inverter is connected to the data input terminal of the second inverter. The data output terminal of the second inverter is connected to the second input terminal of the first NOR gate. The first input terminal of the second NOR gate is connected to the clock signal output by the first charge pump, the output terminal of the second NOR gate is connected to the data input terminal of the third inverter, the data output terminal of the third inverter is connected to the data input terminal of the fourth inverter, and the data output terminal of the fourth inverter is connected to the second input terminal of the second NOR gate.

5. The micro power management circuit based on a charge pump as described in claim 1, characterized in that, The charge pump-based micro power management circuit also includes a master switch unit, a phase-locked loop unit, and a logic voltage power supply unit. The power supply terminals of the main switch unit, the phase-locked loop unit, and the logic voltage power supply unit are all connected to an external power supply. The output terminal of the main switch unit is connected to the external circuit working module, thereby providing a start-up voltage to the external circuit working module. The output terminal of the phase-locked loop unit is connected to the external circuit working module, thereby providing a monitored phase-locked loop conversion voltage to the external circuit working module. The output terminal of the logic voltage power supply unit is connected to the external circuit working module, thereby providing a monitored logic voltage to the external circuit working module.

6. The micro power management circuit based on a charge pump as described in claim 5, characterized in that, The main switching unit includes a first rectifier module, a second charge pump, a first operational amplifier, a first resistor, a second resistor, a thirteenth field-effect transistor, a first diode, and a second diode; The first rectifier module contains several rectifier modules, and several rectifiers are connected in series within each rectifier module. The input terminal of the first rectifier module is connected to an external power supply and the voltage output terminal of the second charge pump. The signal terminal of the second charge pump is connected to the signal terminal of the rectifier module. The ground terminal of the second charge pump is grounded. The voltage input terminal of the second charge pump is connected to the drain of the thirteenth field-effect transistor. The source of the thirteenth field-effect transistor is connected to an external power supply. The gate of the thirteenth field-effect transistor is connected to the output terminal of the first operational amplifier. The power supply terminal of the first operational amplifier is connected to an external power supply. The ground terminal of the first operational amplifier is grounded. The first input terminal of the first operational amplifier is connected to one end of the first resistor and one end of the second resistor. The second input terminal of the first operational amplifier is connected to an external power supply. The other end of the first resistor is connected to an external power supply. The other end of the second resistor is grounded. The output terminal of the first rectifier module is connected to the anode of the first diode and serves as the output terminal of the main switch unit. The cathode of the first diode is connected to the anode of the second diode. The cathode of the second diode is connected to an external power supply.

7. The micro power management circuit based on a charge pump as described in claim 5, characterized in that, The logic voltage power supply unit includes a second rectifier module, a third charge pump, a second operational amplifier, a third resistor, a fourth resistor, a fourteenth field-effect transistor, a third diode, and a fourth diode; The second rectifier module contains several parallel rectifier modules, and each rectifier module contains several rectifiers connected in series. The input terminal of the second rectifier module is connected to an external power supply and the voltage output terminal of the third charge pump. The signal terminal of the third charge pump is connected to the signal terminal of the rectifier module. The ground terminal of the third charge pump is grounded. The voltage input terminal of the third charge pump is connected to the drain of the fourteenth field-effect transistor. The source of the fourteenth field-effect transistor is connected to an external power supply. The gate of the fourteenth field-effect transistor is connected to the output terminal of the second operational amplifier. The power supply terminal is connected to an external power supply. The ground terminal of the second operational amplifier is grounded. The positive input terminal of the second operational amplifier is connected to one end of the third resistor and one end of the fourth resistor. The negative input terminal of the second operational amplifier is connected to an external power supply. The other end of the third resistor is connected to an external power supply. The other end of the fourth resistor is grounded. The output terminal of the second rectifier module is connected to the positive terminal of the third diode and serves as the output terminal of the logic voltage power supply unit. The negative terminal of the third diode is connected to the positive terminal of the fourth diode. The negative terminal of the fourth diode is connected to an external power supply.

8. The micro power management circuit based on a charge pump as described in claim 5, characterized in that, The phase-locked loop unit includes a third rectifier module, a fourth charge pump, a third operational amplifier, and a fifteenth field-effect transistor; The third rectifier module contains several rectifiers connected in parallel. The voltage output terminal of the fourth charge pump is connected to the input terminal of the third rectifier module and an external power supply. The signal output terminal of the fourth charge pump is connected to the signal terminal of the third rectifier module. The voltage input terminal of the fourth charge pump is connected to the drain of the fifteenth field-effect transistor. The source of the fifteenth field-effect transistor is connected to an external power supply. The gate of the fifteenth field-effect transistor is connected to the output terminal of the third operational amplifier. The power supply terminal of the third operational amplifier is connected to an external power supply. The ground terminal of the third operational amplifier is grounded. The positive input terminal of the third operational amplifier is connected to an external power supply. The negative input terminal of the third operational amplifier is connected to the output terminal of the third rectifier module and serves as the output terminal of the phase-locked loop unit.

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