High-performance unidirectional transmission card based on FPGA

Abstract

The application discloses a high-performance one-way transmission card based on FPGA, which comprises a sending end and a receiving end, the sending end comprises a sending one-way transmission card and a sending optical module, and a sending FPGA chip is arranged on the sending one-way transmission card; the receiving end comprises a receiving optical module, a receiving one-way transmission card and a storage module, and a receiving FPGA chip is arranged on the sending one-way transmission card; a host computer of the sending end is in bidirectional communication connection with the sending one-way transmission card, the sending one-way transmission card is in one-way communication connection with the sending optical module, the sending optical module is in one-way communication connection with the receiving optical module through an optical fiber, the receiving optical module is in one-way communication connection with the receiving one-way transmission card, and the receiving one-way transmission card is in bidirectional communication connection with the host computer of the receiving end and the storage module. The application can realize one-way transmission of data from the host computer of the sending end to the host computer of the receiving end, guarantee physical one-way isolation of data in an internal network and an external network, and obviously distinguish a safety boundary.

Description

Technical Field

[0001] This invention relates to the field of unidirectional transmission technology. Specifically, it relates to a high-performance unidirectional transmission card based on FPGA. Background Technology

[0002] In various classified organizations, there are typically enterprise and internal networks. Due to data security and confidentiality requirements, these networks cannot be isolated from external networks. In this environment, there is a need to transfer data and files from the external network to the internal network. This requirement necessitates unidirectional migration of files and data, thus necessitating that devices connecting the internal and external networks possess unidirectional data transmission capabilities.

[0003] Currently, there are two main methods for implementing one-way transmission. One is protocol-based one-way transmission, usually based on the UDP protocol. Because the UDP protocol is prone to packet loss at high data transmission rates and in poor network environments, the reliability of data transmission is low. Some solutions add data verification and feedback mechanisms on top of this. This approach cannot guarantee absolutely one-way transmission; once the data transmission protocol is compromised, the internal and external networks can completely communicate, posing a significant security risk. The other approach involves modifying the fiber optic network card into a one-way transmission card, forcing the receiving network card into an abnormal state, which can easily lead to packet loss. This approach typically operates at gigabit network speeds. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to provide a high-performance unidirectional transmission optical card based on FPGA. The physical connection uses only unidirectional optical fiber connection, which can realize the unidirectional transmission of data from the sending end host computer to the receiving end host computer, ensuring physical unidirectional isolation of internal and external network data, with clear security boundary distinction. It does not use Ethernet protocol, thus eliminating the possibility of protocol tampering into network communication.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A high-performance unidirectional transmission card based on FPGA includes a transmitter and a receiver. The transmitter includes a unidirectional transmission card for transmitting and a transmitting optical module, with the unidirectional transmission card having a transmitting FPGA chip. The receiver includes a receiving optical module, a receiving unidirectional transmission card, and a storage module, with the unidirectional transmission card having a receiving FPGA chip. The transmitter's host computer is bidirectionally connected to the transmitting unidirectional transmission card, and the transmitting unidirectional transmission card is unidirectionally connected to the transmitting optical module. The transmitting optical module is unidirectionally connected to the receiving optical module via optical fiber, and the receiving optical module is unidirectionally connected to the receiving unidirectional transmission card. The receiving unidirectional transmission card is bidirectionally connected to both the receiving host computer and the storage module.

[0007] The aforementioned high-performance unidirectional transmission card based on FPGA enables unidirectional communication between the transmitting unidirectional transmission card and the transmitting optical module through the transmitting FPGA chip and the SerDes interface.

[0008] The aforementioned high-performance unidirectional transmission card based on FPGA enables unidirectional communication between the receiving unidirectional transmission card and the receiving optical module through the receiving FPGA chip and the SerDes interface.

[0009] The aforementioned high-performance unidirectional transmission card based on FPGA connects the transmitting unidirectional transmission card to the transmitting host computer via a PCIe interface.

[0010] The aforementioned high-performance unidirectional transmission card based on FPGA connects the receiving unidirectional transmission card to the receiving host computer via a PCIe interface.

[0011] The aforementioned high-performance unidirectional transmission card based on FPGA also includes a load balancing module on the transmitting unidirectional transmission card. The transmitting FPGA chip on the transmitting unidirectional transmission card is communicatively connected to the load balancing module, and the load balancing module is communicatively connected to the transmitting optical module. The load balancing module performs load balancing through the following steps:

[0012] S1) Collect data packaging information, analyze and confirm the relationship between the packaged data packet and the original packet;

[0013] S2) Determine the number N of data packets formed by directly repackaging the original packets and the number M of data packets formed by repackaging the original packets into smaller packets from the queued data packets to be transmitted. Then allocate the bandwidth of the transmission channel according to the following formula:

[0014] ;

[0015] In the formula, Band1 is the bandwidth allocated for the transmission of data packets formed by directly packaging the original packet; Band2 is the bandwidth allocated for the transmission of data packets formed by repackaging the original packet.

[0016] In the aforementioned high-performance unidirectional transmission card based on FPGA, the load balancing module has the following relationship between the total bandwidth Band0 and Band1, Band0, and the spare bandwidth Band3 during load balancing:

[0017] Band0 = Band1 + Band2 + Band3;

[0018] The spare bandwidth Band3 is calculated using the following formula:

[0019] ;

[0020] In the formula, δ is the redundancy adjustment coefficient, with a value range of [0.07, 0.16].

[0021] The above-mentioned high-performance unidirectional transmission card based on FPGA has a δ value range of [0.11, 0.14].

[0022] The aforementioned high-performance unidirectional transmission card based on FPGA has optical modules for both transmitting and receiving, each with a receiving terminal and a transmitting terminal.

[0023] The aforementioned high-performance unidirectional transmission card based on FPGA has indicator lights on both the transmitting and receiving ends. On the transmitting end, the indicator lights are electrically connected to the transmitting FPGA chip; on the receiving end, the indicator lights are electrically connected to the receiving FPGA chip.

[0024] The technical solution of the present invention achieves the following beneficial technical effects:

[0025] 1. The transmitting and receiving ends are connected unidirectionally by a single optical fiber, ensuring the unidirectionality of the physical transmission path and making the transmission more secure.

[0026] 2. By sending data packets that can be packaged without repackaging and data packets that need to be repackaged separately, and by controlling the bandwidth for sending the two types of data packets, packet loss during the transmission of data packets that need to be repackaged can be reduced. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the high-performance unidirectional transmission card based on FPGA of the present invention;

[0028] Figure 2 This is a flowchart illustrating the information transmission using a high-performance unidirectional transmission card based on FPGA in this invention. Detailed Implementation

[0029] The present invention will be further explained below with reference to examples.

[0030] like Figure 1 As shown, the present invention relates to a high-performance unidirectional transmission card based on FPGA, comprising a transmitting end and a receiving end. The transmitting end includes a transmitting unidirectional transmission card and a transmitting optical module, with a transmitting FPGA chip mounted on the transmitting unidirectional transmission card. The receiving end includes a receiving optical module, a receiving unidirectional transmission card, and a storage module, with a receiving FPGA chip mounted on the transmitting unidirectional transmission card. The transmitting end host computer is bidirectionally connected to the transmitting unidirectional transmission card, and the transmitting unidirectional transmission card is unidirectionally connected to the transmitting optical module. The transmitting optical module is unidirectionally connected to the receiving optical module via optical fiber, and the receiving optical module is unidirectionally connected to the receiving end unidirectional transmission card. The receiving end unidirectional transmission card is bidirectionally connected to both the receiving end host computer and the storage module.

[0031] The transmitting unidirectional transmission card achieves unidirectional communication with the transmitting optical module through the transmitting FPGA chip and SerDes interface; the receiving unidirectional transmission card achieves unidirectional communication with the receiving optical module through the receiving FPGA chip and SerDes interface; the transmitting unidirectional transmission card communicates with the transmitting host computer through a PCIe interface; the receiving unidirectional transmission card communicates with the receiving host computer through a PCIe interface; both the transmitting and receiving optical modules are optical modules with receiving and transmitting terminals.

[0032] Because some data packets may exceed the MTU limit during data transmission, these packets need to be fragmented and packaged before transmission. Therefore, to reduce the mutual interference between the transmission of data packets that do not need to be fragmented and those that do, this invention includes a load balancing module on the transmitting unidirectional transmission card. The transmitting FPGA chip on the transmitting unidirectional transmission card is communicatively connected to the load balancing module, and the load balancing module is communicatively connected to the transmitting optical module. The load balancing module performs load balancing through the following steps:

[0033] S1) Collect data packaging information, analyze and confirm the relationship between the packaged data packet and the original packet;

[0034] S2) Determine the number N of data packets formed by directly repackaging the original packets and the number M of data packets formed by repackaging the original packets into smaller packets from the queued data packets to be transmitted. Then allocate the bandwidth of the transmission channel according to the following formula:

[0035] ;

[0036] In the formula, Band1 is the bandwidth allocated for the transmission of data packets formed by directly packaging the original packet; Band2 is the bandwidth allocated for the transmission of data packets formed by repackaging the original packet.

[0037] To ensure the relative stability of Band1 and Band2 within a certain timeframe and reduce the impact of frequent simultaneous adjustments to the bandwidth used for both data packet transmissions on data transmission stability, this invention allocates a portion of the total bandwidth Band0 as a reserve bandwidth Band3 during load balancing. The total bandwidth Band0, Band1, and the reserve bandwidth Band3 are related as follows:

[0038] Band0 = Band1 + Band2 + Band3;

[0039] The spare bandwidth Band3 is calculated using the following formula:

[0040] ;

[0041] In the formula, δ is the redundancy adjustment coefficient, with a value range of [0.07, 0.16], and preferably [0.11, 0.14].

[0042] In practical applications, Band1 and Band2 are significantly affected by the size and number of data packets to be transmitted. Fluctuations in the size and number of these data packets have a noticeable impact on the adjustment of Band1 and Band2. Specifically, when the size and number of data packets fluctuate little or not at all, Band1 and Band2 are relatively stable and require no adjustment. In this case, the backup bandwidth Band3 can be set relatively small as a precaution. Conversely, when the size and number of data packets fluctuate significantly, the backup bandwidth Band3 can be set relatively large. Therefore, the size of the backup bandwidth Band3 varies depending on the application environment, and the ratio of the backup bandwidth Band3 to the total bandwidth Band0—the redundancy adjustment coefficient δ—will also differ. Users can set the redundancy adjustment coefficient δ according to their own circumstances to fix the size of the backup bandwidth Band3.

[0043] At this point, when it is necessary to increase Band1 or / and Band2, a portion of the spare bandwidth Band3 can be allocated to Band1 or Band2. This avoids the data transmission impact caused by having to reduce the other bandwidth when increasing one bandwidth. Compared to data transmission without spare bandwidth, the packet loss rate of data transmission with spare bandwidth is reduced by about 30%.

[0044] Data transmission was performed on four data packets using three methods: hybrid transmission, non-redundant classified transmission, and redundant classified transmission. The packet loss rate during transmission is shown in Table 1. Hybrid transmission involves queuing all data packets together for transmission. Non-redundant classified transmission involves classifying data packets by size and transmitting them separately when there is no backup bandwidth. Redundant classified transmission involves classifying data packets by size and transmitting them separately when there is backup bandwidth.

[0045] Table 1 Packet loss rate under different transmission modes

[0046]

[0047] To allow for direct external visualization of equipment malfunctions, this invention includes indicator lights at both the transmitting and receiving ends. At the transmitting end, the indicator light is electrically connected to the transmitting FPGA chip; at the receiving end, the indicator light is electrically connected to the receiving FPGA chip. Specifically, at either the transmitting or receiving end, if any problem occurs in the PCIe interface link status or the SerDes interface data transmission status, the indicator light will flash or turn off.

[0048] When using the aforementioned FPGA-based high-performance unidirectional transmission card for information transmission, such as Figure 2 As shown, this can be achieved through the following steps:

[0049] Step 1. The sending host computer calls the sending PCIe driver to transmit the data to be transmitted to the sending unidirectional transmission card;

[0050] Step 2. The transmitting unidirectional transmission card transmits the received data to the transmitting optical module through the SerDes interface;

[0051] Step 3. The transmitting terminal of the transmitting optical module sends the data to the receiving terminal of the receiving optical module through the optical fiber;

[0052] Step 4. The receiving terminal of the receiving optical module transmits the received data to the receiving unidirectional transmission card through the SerDes interface;

[0053] Step 5. The receiving one-way transmission card can directly send the received data to the receiving host computer, or it can store the received data in the storage module and send a data reception notification to the receiving host computer. When the receiving host computer receives data through the PCIe interface at a speed that is less than the receiving terminal transmits data to the receiving one-way transmission card through the SerDes interface, the receiving one-way transmission card will store the received data in the storage module.

[0054] Step 6. After receiving the data reception notification, the host computer at the receiving end retrieves the data stored in the storage module through the PCIe interface and the receiving unidirectional transmission card, thereby completing the data transmission.

[0055] During data transmission, the receiving host computer can only receive data from the sending host computer and cannot send any data to the sending host computer through the FPGA-based high-performance unidirectional transmission card. This ensures physical unidirectional isolation between internal and external network data, making security and convenience clearly distinguishable.

[0056] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of the claims of this patent application.

Claims

1. A high-performance unidirectional transmission card based on FPGA, characterized in that, The system comprises a transmitter and a receiver. The transmitter includes a one-way transmission card and a transmitting optical module. The one-way transmission card has a transmitting FPGA chip. The receiver includes a receiving optical module, a receiving one-way transmission card, and a storage module. The one-way transmission card has a receiving FPGA chip. The transmitter's host computer has a bidirectional communication connection with the one-way transmission card. The one-way transmission card has a unidirectional communication connection with the transmitting optical module. The transmitting optical module has a unidirectional communication connection with the receiving optical module via optical fiber. The receiving optical module has a unidirectional communication connection with the receiving one-way transmission card. The receiving one-way transmission card has bidirectional communication connections with both the receiving one-way computer and the storage module. The one-way transmission card also has a load balancing module. The transmitting FPGA chip on the one-way transmission card communicates with the load balancing module. The load balancing module communicates with the transmitting optical module. The load balancing module performs load balancing through the following steps: S1) Collect data packaging information, analyze and confirm the relationship between the packaged data packet and the original packet; S2) Determine the number N of data packets formed by directly repackaging the original packets and the number M of data packets formed by repackaging the original packets into smaller packets from the queued data packets to be transmitted. Then allocate the bandwidth of the transmission channel according to the following formula: ； In the formula, Band1 is the bandwidth allocated for the transmission of data packets formed by directly packaging the original packet; Band2 is the bandwidth allocated for the transmission of data packets formed by repackaging the original packet.

2. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, The transmitting unidirectional transmission card establishes a unidirectional communication connection with the transmitting optical module through the transmitting FPGA chip and the SerDes interface.

3. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, The receiving unidirectional transmission card achieves unidirectional communication connection with the receiving optical module through the receiving FPGA chip and SerDes interface.

4. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, The unidirectional transmission card for sending communicates with the host computer at the sending end via a PCIe interface.

5. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, The receiving unidirectional transmission card communicates with the receiving host computer via a PCIe interface.

6. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, When the load balancing module performs load balancing, the total bandwidth Band0, Band1, Band0, and the spare bandwidth Band3 have the following relationship: Band0 = Band1 + Band2 + Band3; The spare bandwidth Band3 is calculated using the following formula: ； In the formula, δ is the redundancy adjustment coefficient, with a value range of [0.07, 0.16].

7. The high-performance unidirectional transmission card based on FPGA according to claim 6, characterized in that, The value of δ ranges from [0.11, 0.14].

8. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, Both the transmitting optical module and the receiving optical module are optical modules with receiving terminals and transmitting terminals.

9. The high-performance unidirectional transmission card based on FPGA according to claim 1, characterized in that, Both the transmitting and receiving ends are equipped with indicator lights; at the transmitting end, the indicator lights are electrically connected to the transmitting FPGA chip; at the receiving end, the indicator lights are electrically connected to the receiving FPGA chip.

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