Digital beam forming directional diagram testing method and system based on FPGA and upper computer
By combining FPGA and host computer, and utilizing adaptive calibration and vector superposition calculation, the problem of insufficient accuracy in digital beamforming pattern testing is solved, achieving high-precision digital pattern generation that is applicable to various antenna types.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF REMOTE SENSING EQUIP
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-24
AI Technical Summary
Existing digital beamforming pattern testing systems struggle to achieve high-precision amplitude, phase, and vector synthesis during digital signal processing, leading to inaccurate pattern testing.
A combination of FPGA and host computer is used to generate digital radiation patterns through adaptive calibration and vector superposition calculation.
It improves the accuracy of digital radiation patterns and the versatility of the testing system, and is applicable to both analog-digital hybrid antennas and purely digital antennas, achieving high-precision digital radiation pattern generation.
Smart Images
Figure CN121923735A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of communication technology, and more specifically, relates to a digital beamforming pattern testing method and system based on FPGA and host computer. Background Technology
[0002] In the process of digital beamforming pattern testing, digital signal processing is generally required on the signal sampled by analog-to-digital conversion (AD). Traditional antenna test systems can only perform pattern testing at the RF analog end; the digital pattern generated at the digital end requires a series of processing steps, including amplitude, phase, and vector synthesis, on the processed data.
[0003] Digital beamforming pattern testing systems offer advantages over analog pattern testing platforms in that they generate more accurate digital patterns. Furthermore, digital pattern testing platforms have a wider range of applications, providing universal applicability for testing the patterns of current hybrid analog-digital antennas and purely digital antennas.
[0004] Therefore, how to generate digital directional patterns becomes a key issue. Summary of the Invention
[0005] The purpose of this application is to provide a digital beamforming pattern testing method and system based on FPGA and host computer to form a digital beamforming pattern.
[0006] A first aspect of this application provides a digital beamforming pattern testing method based on an FPGA and a host computer, applied to a digital beamforming pattern testing system. The system includes an FPGA platform, a host computer, and a turntable. The FPGA platform is communicatively connected to the host computer, and the host computer is communicatively connected to the turntable. The method is executed by the host computer and includes:
[0007] After adaptive calibration is completed, the turntable is controlled to rotate based on the target rotation accuracy and the target scanning range. The target rotation accuracy is the angle of each rotation of the turntable, and the target scanning range represents the maximum and minimum rotation angles of the turntable.
[0008] Each time the turntable rotates, the target operation is executed, and the target operation result corresponding to that moment is obtained. Each rotation of the turntable corresponds to the target operation result at one moment.
[0009] A digital direction map is generated based on the target operation results at each time point.
[0010] The target operation includes:
[0011] Send a data interception command to the FPGA platform so that the FPGA platform can intercept the multi-channel orthogonal signal values after adaptive calibration at the corresponding time.
[0012] The system receives the multi-channel orthogonal signal values sent by the FPGA platform, performs vector superposition calculation based on the multi-channel orthogonal signal values, obtains the vector superposition result at that moment, and draws the vector superposition result at that moment.
[0013] A second aspect of this application provides a digital beamforming pattern testing system based on an FPGA and a host computer. The system includes an FPGA platform, a host computer, and a turntable. The FPGA platform is communicatively connected to the host computer, and the host computer is communicatively connected to the turntable.
[0014] After adaptive calibration is completed, the host computer controls the turntable to rotate based on the target rotation accuracy and target scanning range. Each time the turntable rotates, it sends a data interception command to the FPGA platform, enabling the FPGA platform to intercept the adaptively calibrated multi-channel orthogonal signal values at the corresponding moment. The host computer receives the multi-channel orthogonal signal values from the FPGA platform and performs vector superposition calculations based on these values to obtain the vector superposition result at that moment. The host computer then plots the vector superposition result to obtain the target operation result at that moment. The target rotation accuracy is the angle of each turntable rotation, and the target scanning range represents the maximum and minimum rotation angles of the turntable. Each turntable rotation corresponds to a target operation result at a given moment.
[0015] The FPGA platform is used to receive data interception instructions, intercept the multi-channel orthogonal signal values after adaptive calibration at the corresponding time based on the data interception instructions, and send the multi-channel orthogonal signal values to the host computer.
[0016] The host computer is used to generate a digital direction map based on the target operation results at each time point.
[0017] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the above-described digital beamforming pattern testing method based on FPGA and host computer.
[0018] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described digital beamforming pattern testing method based on FPGA and host computer.
[0019] A fifth aspect of this application provides a computer program product, including a computer program or computer-executable instructions, wherein when the computer program or computer-executable instructions are executed by a processor, the steps of the above-described digital beamforming pattern testing method based on FPGA and host computer are implemented.
[0020] The beneficial effects of the digital beamforming pattern testing method and system based on FPGA and host computer provided in this application are as follows:
[0021] This application provides a digital beamforming pattern testing method based on FPGA and host computer, applied to a digital beamforming pattern testing system. The system includes an FPGA platform, a host computer, and a turntable. After adaptive calibration, the host computer controls the turntable to rotate based on the target rotation accuracy and target scanning range. Each time the turntable rotates, the host computer sends a data interception command to the FPGA platform, enabling the FPGA platform to intercept the adaptively calibrated multi-channel orthogonal signal values at the corresponding moment. The host computer receives the multi-channel orthogonal signal values from the FPGA platform and performs vector superposition calculations based on these values to obtain the vector superposition result at that moment. This result is then plotted, allowing the generation of a digital beamforming pattern based on the vector superposition results at each moment. This pattern characterizes the signal radiation intensity (transmit mode) or receiver sensitivity (receive mode) of the antenna in different spatial directions. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 A flowchart illustrating the digital beamforming pattern testing method based on FPGA and host computer provided in this application embodiment;
[0024] Figure 2 A flowchart illustrating the digital beamforming pattern testing method based on FPGA and host computer provided in this application embodiment;
[0025] Figure 3 The time-domain waveform of the received signals provided in the embodiments of this application is obtained after adaptive digital calibration.
[0026] Figure 4 A schematic diagram of the digital end calibration and digital radiation pattern host computer operation interface provided in this application embodiment;
[0027] Figure 5A schematic diagram of the digital radiation pattern host computer operation interface for analog terminal calibration provided in this application embodiment;
[0028] Figure 6 This is a structural block diagram of a digital beamforming pattern testing system based on FPGA and host computer provided in an embodiment of this application.
[0029] Figure 7 A schematic block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0030] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.
[0032] Figure 1 This application provides a flowchart of a digital beamforming pattern testing method based on FPGA and a host computer, which includes the following steps: The FPGA platform receives signals via an antenna, performs multi-channel analog-to-digital (AD) signal sampling on the received signals, performs digital down-conversion digital signal processing to obtain multiple orthogonal zero-IF signals, adaptively calibrates the multiple orthogonal zero-IF signals using an AD multi-channel adaptive calibration algorithm, and transmits each interface I through a data transmission module between the FPGA platform and the host computer. i Q i The data undergoes phase difference calculation to determine whether calibration is complete. After calibration, the turntable is controlled to rotate, and the host computer performs vector synthesis and generates a digital radiation pattern. This digital radiation pattern can be applied to various antenna modes such as analog-digital hybrid antennas and pure digital antennas. See the following embodiments for details.
[0033] This application provides a digital beamforming pattern testing method based on FPGA and a host computer. This method can be executed by the host computer, such as... Figure 2 As shown, the method may include:
[0034] Step S101: After adaptive calibration is completed, the turntable is controlled to rotate based on the target rotation accuracy and target scanning range.
[0035] In this embodiment, the radiation pattern can only be generated when the phase difference between the multiple channels is 0°. If the consistency of all channels cannot be guaranteed, the vector synthesis will produce errors, which may lead to errors in the generated radiation pattern. Therefore, before generating the digital radiation pattern, each channel must be adaptively calibrated to ensure that the phase difference between the multiple channels is 0°.
[0036] After adaptive calibration, the host computer controls the turntable to rotate based on the target rotation accuracy and the target scanning range. In this embodiment, the target rotation accuracy is the angle of each rotation of the turntable, and the target scanning range represents the maximum and minimum rotation angles of the turntable. For example, if the target scanning range is -40° to 40° and the target rotation accuracy is 1°, then the host computer controls the turntable to rotate within the scanning range of -40° to 40°, rotating 1° each time.
[0037] Step S102: Execute the target operation each time the turntable rotates, and obtain the target operation result corresponding to that moment.
[0038] Each rotation of the turntable corresponds to the target operation result at a given moment.
[0039] In this embodiment, the target operation may specifically include: sending a data interception instruction to the FPGA platform so that the FPGA platform can intercept the multi-channel orthogonal signal values after adaptive calibration at the corresponding time; receiving the multi-channel orthogonal signal values sent by the FPGA platform, and performing vector superposition calculation based on the multi-channel orthogonal signal values to obtain the vector superposition result at that time and drawing the vector superposition result at that time.
[0040] Continuing the previous example, each time the turntable rotates 1°, the host computer sends a data interception command to the FPGA platform. After receiving the data interception command, the FPGA platform intercepts the adaptively calibrated multi-channel orthogonal signal values at the current moment and sends them to the host computer. After receiving the adaptively calibrated multi-channel orthogonal signal values at the current moment, the host computer performs vector superposition calculation to obtain the vector superposition result at that moment. At the same time, the vector superposition result at each moment is drawn on the turntable control interface of the host computer.
[0041] Step S103: Generate a digital direction map based on the target operation results at each time point.
[0042] After plotting the vector superposition results at each time point through the above embodiments, that is, plotting the vector superposition results corresponding to each time point respectively, a digital direction pattern is generated.
[0043] In another possible implementation, after obtaining the vector superposition result at each moment, it is not necessary to draw it on the host computer turntable control interface first. Instead, after obtaining the vector superposition result at each moment, the corresponding vector superposition result at each moment is drawn to generate a digital radiation pattern.
[0044] Specifically, adaptive calibration is implemented on an FPGA platform through the following steps: receiving signals via an antenna; sampling the received signals into multiple analog-to-digital signals; performing digital down-conversion digital signal processing on the multiple analog-to-digital signals to obtain multiple orthogonal zero-IF signals; and performing inter-channel digital calibration based on the multiple orthogonal zero-IF signals to obtain calibrated multiple orthogonal zero-IF signals, thus achieving adaptive calibration. In this embodiment, the FPGA is used as the development platform for calculating the phase and amplitude of the array signal processing. Because the analog phase-shift accuracy of the phased array TR component is only 5.625°, while the accuracy of digital processing, if calculated using fixed-point numbers, theoretically reaches infinity after the decimal point, assuming sufficient resources, ensuring that the digital calibration accuracy is far higher than that of analog antenna calibration.
[0045] In this embodiment, a single-carrier signal generated in the antenna normal direction is acquired, which will be referred to as the received signal below.
[0046] In this embodiment, the received signal is sampled using multiple analog-to-digital (ADC) signals to obtain multiple ADC signals. Specifically, this may include: based on the Nyquist sampling theorem, sampling the received signal using multiple analog-to-digital (ADC) signals to ensure that the signal falls within the first Nyquist interval. In this embodiment, the received signal is sampled using multiple ADC signals, and the sign bit and sampling precision of the ADC chip are determined. The sign bit and sampling precision of the ADC chip can be obtained from the chip datasheet; alternatively, the sign bit and sampling precision of the ADC chip can be obtained from the input of the administrator.
[0047] Furthermore, in addition to using the Nyquist sampling theorem, the bandpass sampling theorem can also be used for sampling.
[0048] Furthermore, after sampling the received signal into multiple analog-to-digital signals to obtain multiple analog-to-digital signals, digital down-conversion digital signal processing is performed on the multiple analog-to-digital signals to obtain multiple orthogonal zero-IF signals.
[0049] In the embodiments of this application, digital down-conversion is one of the core technologies of software-defined radio systems. Through digital mixing, filtering, and decimation processes, the intermediate frequency (IF) signal after mixing by the receiver is converted into a baseband signal. Quadrature zero IF signal is a key baseband signal form in radio frequency communication systems. Essentially, it directly down-converts the radio frequency (RF) signal to a baseband signal with a center frequency of 0Hz through "quadrature mixing," outputting a pair of in-phase (I) and quadrature (Q) signals.
[0050] In this embodiment, digital down-conversion digital signal processing of multiple analog-to-digital signals may specifically include: mixing the multiple analog-to-digital signals and then passing them through an FIR low-pass filter to obtain multiple zero-IF signals I. i Q i For example, multiple zero-IF signals I at 1MHz can be obtained. i Q i .
[0051] Specifically, for each analog-to-digital (ADC) signal, digital down-conversion and digital signal processing are performed to obtain orthogonal zero-IF signals. This can be achieved by: performing multiplication and mixing on the ADC signal to obtain two orthogonal baseband signals; and then processing these two orthogonal baseband signals through their respective finite impulse response (FIR) low-pass filters to obtain the corresponding orthogonal zero-IF signal. The multiple received signals undergo adaptive digital calibration, and their time-domain waveforms are shown below. Figure 3 As shown.
[0052] Furthermore, after obtaining the orthogonal zero-IF signals, inter-channel digital calibration is performed based on the multiple orthogonal zero-IF signals to obtain calibrated multiple orthogonal zero-IF signals. Specifically, this may include: calculating the amplitude and phase values corresponding to each channel based on the multiple orthogonal zero-IF signals; using any channel as a reference channel, calculating each phase difference in parallel based on the phase values corresponding to each channel and the phase value of the reference channel; calculating each amplitude compensation value in parallel based on the amplitude corresponding to each channel and the amplitude of the reference channel; calculating the calibration coefficient corresponding to each channel based on each phase difference and each amplitude compensation value; and calibrating the multiple orthogonal zero-IF signals using their respective calibration coefficients to obtain calibrated multiple orthogonal zero-IF signals.
[0053] In this embodiment, since the amplitude and phase calculations are performed in the time domain, the amplitude and phase values corresponding to each channel are calculated based on multiple orthogonal zero-IF signals. Specifically, this can include: calculating the amplitude and phase values corresponding to each channel in parallel and in real time based on multiple orthogonal zero-IF signals.
[0054] In this embodiment, the reference channel can be any channel, such as the first channel, or the channel with the most stable performance. In this embodiment, no limitation is made.
[0055] Specifically, firstly through I i Q i Calculate the amplitude and phase values of all channels, and select any one channel I. i Q i The calculated phase value of the signal is used as a reference phase, and the phase difference between other channels and the reference channel is calculated to obtain the channel phase difference θ. i Amplitude compensation A i . Calculate all phase differences and their corresponding I i Q i The channels are processed to obtain the I signals for each channel. i Q i The calibration coefficients corresponding to each signal are used for calibration, and the specific calculation method is as follows:
[0056] Calibration coefficient calculation method:
[0057] Multi-channel calibration calculation method: U i _I=Z i I i U i _Q=Z i Q i Among them, U i _I and U i _Q represents the calibrated i-channel quadrature zero-IF signal.
[0058] Furthermore, the FPGA platform transmits each interface I via a 422 interface (115200 baud rate) through a data transmission module. i Q i The data is transmitted to the host computer, and the amplitude, phase, and phase difference are calculated using the following formulas. When the amplitude value remains constant at each moment and the phase difference value is 0, it indicates that the self-calibration is complete.
[0059] The specific calculation method is as follows:
[0060] Amplitude value calculation method: Among them, AMP i Characterizes the amplitude value of the i-th interface;
[0061] Phase value calculation method: Among them, Q i I represents the i-th orthogonal component. i Characterizes the i-th in-phase component;
[0062] Phase difference calculation method: θ i =PHASE i -PHASE i-1 =0;
[0063] After self-calibration is complete, the turntable interacts with the host computer, which controls the turntable's rotation. In this embodiment, the turntable rotation is controlled based on the target rotation accuracy and target scanning range. Prior to this, the system also includes: acquiring the target rotation accuracy and target scanning range set by the administrator on the host computer interface; or, acquiring pre-set target rotation accuracy and target scanning range. In this embodiment, the target rotation accuracy and target scanning range can be set by the administrator on the host computer interface. Specific configuration parameters can be viewed in the parameter configuration dialog box. Figure 4 The parameter configuration dialog box shows a start angle of 40°, an end angle of -40°, and a scan interval of 1. This means the target scanning range is -40° to 40°, and the target rotation accuracy is 1°. The preset target rotation accuracy and target scanning range can also be set by the target administrator via the host computer interface.
[0064] Furthermore, when the host computer controls the turntable to rotate 1 degree each time, the host computer sends a data interception command to the FPGA platform, and simultaneously intercepts the multi-channel calibrated I at that moment. i Q i The signal value is recorded and packaged into a single long data frame, which is then returned to the host computer. The host computer automatically extracts the multi-channel data information contained in this frame. Since the 422 communication transmission rate is 115200 baud, the pause time for each turn of the turntable needs to be greater than the data transmission time. The data transmission time is 115200 baud, and a return frame is generated after each data transmission command is sent. The turntable pause time can be set to 1 second, ensuring that the data transmission time to the host computer is less than 1 second. In this embodiment, because the data transmission time is fixed, this fixed time can be used to set a turntable pause time for the host computer that is greater than the transmission time, which is simple and accurate.
[0065] The host computer sends a data capture command to the FPGA platform every time the turntable rotates, causing the FPGA platform to capture the adaptively calibrated multi-channel orthogonal signal values at that moment. The host computer receives the multi-channel orthogonal signal values from the FPGA platform and performs vector superposition calculations based on these values to obtain the vector superposition result for that moment, which is then plotted. For example, when the host computer controls the turntable to rotate 1 degree each time, it sends a data capture command to the FPGA platform and simultaneously captures the multi-channel calibrated I values at that moment. i Q iThe signal values are processed and packaged into a single long data frame, which is then returned to the host computer. The host computer automatically extracts the multi-channel data information contained in the frame, performs vector superposition calculations based on the extracted orthogonal signal values, and obtains the vector superposition result at that moment, which is then plotted. Since the interface between the FPGA and the host computer is a common transmission interface, the development difficulty is relatively low. Furthermore, because the processing is performed in the time domain, the amount of IQ data acquired each time is very small, so a high-speed interface is not required for data transmission; ordinary serial communication is sufficient. This effectively solves the coordination difficulties between signal processing calculation result transmission, host computer vector synthesis, and turntable control, and the communication method is simple, reducing development difficulty.
[0066] Specifically, vector superposition calculation is performed based on multiple orthogonal signal values to obtain the vector superposition result at that moment. This can include: calculating the phase value and amplitude value corresponding to each orthogonal signal value; and vector synthesizing the phase value and amplitude value corresponding to each orthogonal signal value to obtain the vector superposition result at that moment.
[0067] In this embodiment, the host computer will extract the multi-channel I i Q i The signal value is calculated to determine its phase and amplitude at this moment. Then, a vector synthesis calculation is performed on the phase and amplitude values at this moment, as detailed below.
[0068] Vector composition calculation formula: F Mi =F M1 e j(i-1)θ .
[0069] Among them, F M1 The signal received by the first antenna element is represented by the power of e, which represents the antenna array factor, i represents the number of channels, and θ represents the phase difference. Here, FMi indicates that the amplitude values at each moment are multiplied, and the phase difference is added to e.
[0070] After obtaining the vector superposition results at each time point, a digital radiation pattern is generated. The performance parameters of the digital radiation pattern can be directly displayed in the target area. In another possible implementation, if a performance parameter viewing command triggered by an administrator is detected, the performance parameters corresponding to the digital radiation pattern are displayed in the target area.
[0071] The target area can be a parameter configuration dialog box, which displays the performance parameters corresponding to the digital radiation pattern. The performance parameters corresponding to the digital radiation pattern can include: frequency, power, intermediate frequency bandwidth, main lobe, beamwidth, test speed, maximum sidelobe, and first sidelobe, as detailed below. Figure 4 As shown.
[0072] Furthermore, such as Figure 5 As shown, Figure 5 The calibration results are displayed on the host computer's digital radiation pattern interface at the analog end. It also includes some performance parameters. Analysis of two sets of measured data shows that the present invention can perform digital radiation pattern scanning on various antenna types. Furthermore, the digital radiation pattern formed by calibration at the digital end is superior to that calibrated at the analog end in terms of main lobe width, null depth, and beamwidth.
[0073] Corresponding to the FPGA-based and host computer-based digital beamforming pattern testing method in the above embodiment, Figure 6 This is a schematic diagram of a digital beamforming pattern testing system based on FPGA and a host computer, provided as an embodiment of this application. For ease of explanation, only the parts relevant to the embodiment of this application are shown. References Figure 6 The FPGA-based digital beamforming pattern testing system 20 includes: an FPGA platform 21, a host computer 22, and a turntable 23. The FPGA platform 21 is communicatively connected to the host computer 22, and the host computer 22 is communicatively connected to the turntable 23.
[0074] After adaptive calibration is completed, the host computer 22 controls the turntable 23 to rotate based on the target rotation accuracy and target scanning range. Each time the turntable rotates, it sends a data interception command to the FPGA platform 21, enabling the FPGA platform 21 to intercept the adaptively calibrated multi-channel orthogonal signal values at the corresponding moment. The host computer 22 receives the multi-channel orthogonal signal values sent by the FPGA platform 21 and performs vector superposition calculations based on these values to obtain the vector superposition result at that moment. The host computer then plots the vector superposition result to obtain the target operation result at that moment. The target rotation accuracy is the angle of each turntable rotation, and the target scanning range represents the maximum and minimum rotation angles of the turntable. Each turntable rotation corresponds to the target operation result at one moment.
[0075] FPGA platform 21 is used to receive data interception instructions, intercept the multi-channel orthogonal signal values after adaptive calibration at the corresponding time based on the data interception instructions, and send the multi-channel orthogonal signal values to the host computer 22.
[0076] The host computer 22 is used to generate a digital direction map based on the target operation results at each time point.
[0077] In another possible implementation of this application embodiment, when the host computer 22 receives the multiple orthogonal signal values sent by the FPGA platform 21, it is specifically used for:
[0078] Receives multiple orthogonal signal values sent by the FPGA platform 21 in a data frame format.
[0079] In another possible implementation of this application embodiment, when the host computer 22 performs vector superposition calculation based on multiple orthogonal signal values to obtain the vector superposition result at that moment, it specifically performs the following: calculates the phase value and amplitude value corresponding to each orthogonal signal value; and performs vector synthesis on the phase value and amplitude value corresponding to each orthogonal signal value to obtain the vector superposition result at that moment.
[0080] In another possible implementation of this application embodiment, the host computer 22 is further used to: obtain the target rotation accuracy and target scanning range set by the administrator on the host computer interface; or, obtain the pre-set target rotation accuracy and target scanning range.
[0081] In another possible implementation of this application embodiment, the FPGA platform 21 is used for:
[0082] Receive signals via antenna;
[0083] The received signal is sampled using multiple analog-to-digital signals to obtain multiple analog-to-digital signals;
[0084] Multiple analog-to-digital signals are digitally down-converted to digital signals to obtain multiple orthogonal zero-IF signals.
[0085] Digital calibration between channels is performed based on multiple orthogonal zero-IF signals to obtain calibrated multiple orthogonal zero-IF signals, thereby achieving adaptive calibration.
[0086] In another possible implementation of this application embodiment, when the FPGA platform 21 performs inter-channel digital calibration based on multiple orthogonal zero-IF signals to obtain calibrated multiple orthogonal zero-IF signals, it is specifically used for:
[0087] Calculate the amplitude and phase values of each channel based on multiple orthogonal zero-IF signals;
[0088] Using any one channel as a reference channel, calculate each phase difference in parallel based on the phase value corresponding to each channel and the phase value of the reference channel, and calculate each amplitude compensation value in parallel based on the amplitude corresponding to each channel and the amplitude of the reference channel.
[0089] Based on each phase difference and each amplitude compensation value, calculate the calibration coefficient corresponding to each channel;
[0090] The multiple orthogonal zero-IF signals are calibrated using their respective calibration coefficients to obtain calibrated multiple orthogonal zero-IF signals.
[0091] Another possible implementation of this application embodiment is that the host computer 22 is used to display the performance parameters corresponding to the digital direction graph on the target area when a performance parameter viewing command triggered by an administrator is detected.
[0092] See Figure 7 , Figure 7 This is a schematic block diagram of an electronic device provided according to an embodiment of this application. Figure 7 The electronic device 300 in this embodiment may include one or more processors 301, one or more input devices 302, one or more output devices 303, and one or more memories 304. The processors 301, input devices 302, output devices 303, and memories 304 communicate with each other via a communication bus 305. The memories 304 store computer programs, including program instructions. The processors 301 execute the program instructions stored in the memories 304. Specifically, the processors 301 are configured to invoke the program instructions to execute the aforementioned digital beamforming pattern testing method based on FPGA and a host computer, which is executed by a host computer. In other words, in this embodiment, the electronic device 300 can be the host computer described above.
[0093] It should be understood that, in the embodiments of this application, the processor 301 may be a central processing unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0094] Input device 302 may include a touchpad, a fingerprint sensor (for collecting the user's fingerprint information and fingerprint orientation information), a microphone, etc., and output device 303 may include a display (LCD, etc.), a speaker, etc.
[0095] The memory 304 may include read-only memory and random access memory, and provides instructions and data to the processor 301. A portion of the memory 304 may also include non-volatile random access memory. For example, the memory 304 may also store target rotation accuracy and target scanning range.
[0096] In specific implementations, the processor 301, input device 302, and output device 303 described in the embodiments of this application can execute the implementation method described in the digital beamforming pattern testing method based on FPGA and host computer provided in the embodiments of this application, or they can execute the implementation method of the electronic device described in the embodiments of this application, which will not be repeated here.
[0097] In another embodiment of this application, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions implement all or part of the processes in the methods described above. Alternatively, the computer program can instruct related hardware to complete the process. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.
[0098] The computer-readable storage medium can be an internal storage unit of the electronic device in any of the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device. Furthermore, the computer-readable storage medium can include both internal and external storage units of the electronic device. The computer-readable storage medium is used to store computer programs and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.
[0099] This application provides a computer program product, which includes computer-executable instructions or a computer program. The computer-executable instructions or computer program are stored in a computer-readable storage medium. The processor of an electronic device reads the computer-executable instructions from the computer-readable storage medium and executes the computer-executable instructions, causing the electronic device to perform the digital beamforming pattern testing method based on FPGA and host computer described in this application embodiment.
[0100] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.
[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the electronic devices and units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0102] In the several embodiments provided in this application, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces or units, or it may be an electrical, mechanical, or other form of connection.
[0103] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.
[0104] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0105] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A digital beamforming pattern testing method based on FPGA and host computer, characterized in that, An application is provided in a digital beamforming pattern testing system. The system includes an FPGA platform, a host computer, and a turntable. The FPGA platform is communicatively connected to the host computer, and the host computer is communicatively connected to the turntable. The method is executed by the host computer and includes: After adaptive calibration is completed, the turntable is controlled to rotate based on the target rotation accuracy and the target scanning range. The target rotation accuracy is the angle of each rotation of the turntable, and the target scanning range represents the maximum and minimum rotation angles of the turntable. Each time the turntable rotates, the target operation is executed, and the target operation result corresponding to that moment is obtained. Each rotation of the turntable corresponds to the target operation result at one moment. A digital direction map is generated based on the target operation results at each time point. The target operation includes: Send a data interception command to the FPGA platform so that the FPGA platform can intercept the multi-channel orthogonal signal values after adaptive calibration at the corresponding time. The system receives the multi-channel orthogonal signal values sent by the FPGA platform, performs vector superposition calculation based on the multi-channel orthogonal signal values, obtains the vector superposition result at that moment, and draws the vector superposition result at that moment.
2. The method according to claim 1, characterized in that, The receipt of the multi-channel orthogonal signal values sent by the FPGA platform includes: Receive the multi-channel orthogonal signal values sent by the FPGA platform in a data frame format.
3. The method according to claim 1, characterized in that, The vector superposition calculation based on the multi-channel orthogonal signal values to obtain the vector superposition result at that moment includes: Based on the orthogonal signal values of each path, calculate the phase value and amplitude value corresponding to each path; The phase and amplitude values corresponding to each path are vector synthesized to obtain the vector superposition result at that moment.
4. The method according to claim 1, characterized in that, The method of controlling the turntable to rotate based on the target rotation accuracy and the target scanning range also includes, prior to: Obtain the target rotation accuracy and target scanning range set by the administrator on the host computer interface; or... Obtain the preset target rotation accuracy and target scanning range.
5. The method according to claim 1, characterized in that, The adaptive calibration is based on the FPGA platform and is implemented in the following way: Receive signals via antenna; The received signal is sampled using multiple analog-to-digital signals to obtain multiple analog-to-digital signals; The multiple analog-to-digital signals are subjected to digital down-conversion digital signal processing to obtain multiple orthogonal zero intermediate frequency signals; Based on the multi-channel orthogonal zero-IF signals, inter-channel digital calibration is performed to obtain calibrated multi-channel orthogonal zero-IF signals, thereby achieving adaptive calibration.
6. The method according to claim 5, characterized in that, The process of performing inter-channel digital calibration based on the multiple orthogonal zero-IF signals to obtain calibrated multiple orthogonal zero-IF signals includes: Calculate the amplitude and phase values corresponding to each channel based on the multiple orthogonal zero-IF signals; Using any one channel as a reference channel, each phase difference is calculated in parallel based on the phase value corresponding to each channel and the phase value of the reference channel, and each amplitude compensation value is calculated in parallel based on the amplitude corresponding to each channel and the amplitude of the reference channel. Based on the phase differences and amplitude compensation values, calculate the calibration coefficients for each channel. The multiple orthogonal zero intermediate frequency signals are calibrated using their respective calibration coefficients to obtain the calibrated multiple orthogonal zero intermediate frequency signals.
7. The method according to claim 1, characterized in that, The method further includes: If a performance parameter viewing command triggered by an administrator is detected, the performance parameters corresponding to the digital directional graph will be displayed on the target area.
8. A digital beamforming pattern testing system based on FPGA and host computer, characterized in that, The system includes: an FPGA platform, a host computer, and a turntable, wherein the FPGA platform is communicatively connected to the host computer, and the host computer is communicatively connected to the turntable, including: After adaptive calibration is completed, the host computer controls the turntable to rotate based on the target rotation accuracy and target scanning range. Each time the turntable rotates, it sends a data interception command to the FPGA platform, enabling the FPGA platform to intercept the adaptively calibrated multi-channel orthogonal signal values at the corresponding moment. The host computer receives the multi-channel orthogonal signal values from the FPGA platform and performs vector superposition calculations based on these values to obtain the vector superposition result at that moment. The host computer then plots the vector superposition result to obtain the target operation result at that moment. The target rotation accuracy is the angle of each turntable rotation, and the target scanning range represents the maximum and minimum rotation angles of the turntable. Each turntable rotation corresponds to a target operation result at a given moment. The FPGA platform is used to receive data interception instructions, intercept the multi-channel orthogonal signal values after adaptive calibration at the corresponding time based on the data interception instructions, and send the multi-channel orthogonal signal values to the host computer. The host computer is used to generate a digital direction map based on the target operation results at each time point.
9. The system according to claim 8, characterized in that, The FPGA platform is used for: Receive signals via antenna; The received signal is sampled using multiple analog-to-digital signals to obtain multiple analog-to-digital signals; The multiple analog-to-digital signals are subjected to digital down-conversion digital signal processing to obtain multiple orthogonal zero intermediate frequency signals; Based on the multi-channel orthogonal zero-IF signals, inter-channel digital calibration is performed to obtain calibrated multi-channel orthogonal zero-IF signals, thereby achieving adaptive calibration.
10. The system according to claim 9, characterized in that, When the FPGA platform performs inter-channel digital calibration based on the multi-channel orthogonal zero-IF signals to obtain the calibrated multi-channel orthogonal zero-IF signals, it is specifically used for: Calculate the amplitude and phase values corresponding to each channel based on the multiple orthogonal zero-IF signals; Using any one channel as a reference channel, each phase difference is calculated in parallel based on the phase value corresponding to each channel and the phase value of the reference channel, and each amplitude compensation value is calculated in parallel based on the amplitude corresponding to each channel and the amplitude of the reference channel. Based on the phase differences and amplitude compensation values, calculate the calibration coefficients for each channel. The multiple orthogonal zero intermediate frequency signals are calibrated using their respective calibration coefficients to obtain the calibrated multiple orthogonal zero intermediate frequency signals.