Communication device with scalable fixed-point numerical format

Abstract

The invention relates to a communication device with a scalable fixed-point numerical format. A circuit for enhancing the resolution of numerical values in existing circuitry using a scalable fixed-point binary format is provided. The scalable fixed point format locates bits representing a lowest value (resolution) at a maximum bit index. The circuitry separates the bits representing the lowest value from the remainder of the binary coded number. A legacy processing may be performed on the remainder of the binary encoded number. The removed bits are used to select between legacy and new processing and / or an output of a circuit. The scalable fixed-point binary format may be used to represent a modulation and coding scheme (MCS) in a wireless communication standard, allowing new MCS identifiers to be added between existing MCS identifiers using enhanced resolution while maintaining a monotonic relationship between the identifiers and the effective data transfer rate of the MCS.

Description

[0001] Cross-reference of related applications

[0002] This disclosure claims priority and benefits to U.S. Provisional Application No. 63 / 710,095, filed October 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a format for representing numerical values ​​using several binary symbols. Background Technology

[0004] In some applications, a number of binary symbols (e.g., logic '0' or '1') in a fixed-point format are used to represent a value, wherein the resolution of the representation is fixed and each position in the fixed-point representation has the same value, regardless of the magnitude of the value. Summary of the Invention

[0005] In one aspect, this disclosure relates to an apparatus including one or more circuits configured to perform operations, the operations including: generating a second binary coded number by removing a bit from a first binary coded number in a fixed-point format; generating a first output based on the first binary coded number; generating a second output based on the second binary coded number; and selecting either the first output or the second output based on the first bit.

[0006] On the other hand, this disclosure relates to a method comprising: generating a second binary coded number by removing a first bit from a first binary coded number in a fixed-point format; generating a second output based on the second binary coded number; generating a first output based on the first bit and the second output; and selecting either the first output or the second output based on the first bit.

[0007] On the other hand, this disclosure relates to an apparatus comprising: a separation circuit configured to separate a first binary coded number in a fixed-point format into one or more first bits and a second binary coded number, the first binary coded number being represented by at least a portion of one or more bytes, wherein the one or more first bits comprise the least significant bit of the first binary coded number and the most significant bit of the portion of the one or more bytes; a first processing circuit configured to generate a first output based on the first binary coded number; a second processing circuit configured to generate a second output based on the second binary coded number; and a selection circuit configured to select either the first output or the second output based on the one or more first bits. Attached Figure Description

[0008] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings, in which similar reference characters identify corresponding elements throughout. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0009] Figure 1A It is a block diagram depicting a network environment comprising one or more access points communicating with one or more devices or stations, according to some embodiments.

[0010] Figure 1B This is a block diagram depicting a computing device that can be used in conjunction with the methods and systems described herein, according to some embodiments.

[0011] Figure 1C This is another block diagram depicting a computing device that can be used in conjunction with the methods and systems described herein, according to some embodiments.

[0012] Figure 2 This describes various fixed-point formats for representing numerical values ​​using binary encoding, according to some embodiments.

[0013] Figure 3 It is a block diagram depicting a circuit that combines an improved resolution of fixed-point representation of numerical values ​​with a legacy circuit system, according to some embodiments.

[0014] Figure 4 According to some embodiments Figure 3 The block diagram of the discrete circuit depicts its input and output.

[0015] Figure 5 According to some embodiments Figure 3 The block diagram of the selection circuit depicts its inputs and outputs.

[0016] Figure 6 It is a block diagram depicting a circuit whose resolution has been increased by two times according to some embodiments of the fixed-point representation.

[0017] Figure 7 According to some embodiments Figure 6 The block diagram of the selection circuit depicts its inputs and outputs.

[0018] Figure 8 This is another block diagram of a circuit, according to some embodiments, for integrating an improved resolution of a fixed-point representation of a numerical value with a legacy circuit system.

[0019] Figure 9 This is a table of modulation and coding schemes for wireless networking according to some embodiments.

[0020] Figure 10This is a table of modulation and coding schemes for wireless networking according to some embodiments, wherein additional schemes have a feature between those from... Figure 9 The bit transfer rate between encoding schemes.

[0021] Figure 11 It is a block diagram depicting a circuit according to some embodiments for incorporating a modulation and coding scheme marked with a value between existing modulation and coding scheme tags.

[0022] Figure 12 It is a block diagram depicting a circuit according to some embodiments for further improving the resolution of values ​​used to mark modulation and coding schemes.

[0023] Figure 13 This is a flowchart, according to some embodiments, for calculating outputs for fixed-point value inputs with improved resolution.

[0024] Figure 14 This is a flowchart, according to some embodiments, for calculating outputs from fixed-point inputs with resolutions increased by two times. Detailed Implementation

[0025] (Several) The following IEEE standards (including any draft versions of such standards) are hereby incorporated herein by reference in their entirety and constitute part of this disclosure for all purposes: WiFi Alliance standards and IEEE 802.11 standards, including but not limited to IEEE 802.11a. TM IEEE 802.11b TM IEEE 802.11g TM IEEE P802.11n TM IEEE P802.11ac TM ; and IEEE P802.11be TM To IEEE P802.11bn TM Standards. Although this disclosure may reference aspects of these standards, it is in no way limited by them.

[0026] Current fixed-point formats use fractional components (e.g., bits representing negative powers of 2) located at the least significant bit index (e.g., the least significant bit of a byte). For example, in the unsigned Q7.1 fixed-point format, bits 1 through 7 can be used to represent numbers between 0 and 127, and bit 0 can be used to represent 0.5. Q7.1 can represent numbers with a resolution of 0.5 between 0 and 127.5. In some applications, higher significant bits may not be used. For example, to represent numbers with a resolution of 0.5 between 0 and 50, the Q7.1 format can be used, but the last bit will always be '0'. In dedicated circuit systems, the full byte (8 bits) is not required, and the circuit may only provide the required number of data lines (e.g., circuit traces, etc.).

[0027] If a new application of similar circuitry requires higher resolution, then the bits must be inserted to the right of the least significant bit in the Q fixed-point format. However, circuitry used to process previous (e.g., lower resolution) fixed-point formats may not function properly with the inserted bits. Hardware and / or software modifications to use a new (e.g., higher resolution) fixed-point format can be expensive, error-prone, and result in circuitry that is not backward compatible with previous numerical formats. In some embodiments, systems and methods use a less error-prone, less expensive, and backward compatible fixed-point format (e.g., with higher resolution).

[0028] This disclosure provides a scalable fixed-point format (denoted by B); that is, in some embodiments, the fixed-point format allows for increased resolution while providing backward compatibility without modifying legacy circuitry. Advantageously, in some embodiments, new products with higher resolution can be released in a shorter development time. In some embodiments, scalability is achieved by positioning the fractional component of the fixed-point format in bits with higher indices relative to the integer components, where higher indices represent smaller fractional values ​​(e.g., powers of 2 with larger fractions). If the resolution of numbers using the fixed-point format described herein is to be increased, additional bits with bit indices higher than the previously highest resolution bits (e.g., least significant bits) are used.

[0029] This disclosure can be implemented for any existing system currently using unsigned integers because, in some embodiments, the unsigned integer format can be the same as the Q fixed-point format (e.g., Q8.0 or Q16.0) and the B fixed-point format. (In some embodiments, for the fixed-point code Xm.n, the letter [e.g., X] indicates the format type, the first number [e.g., m] indicates the number of bits used to represent the non-negative power of 2 or the integer component, and the second number [e.g., n] indicates the number of bits used to represent the fractional component or the negative power of 2.) For example, an integer value using an unsigned 8-bit integer (e.g., uint8) between 0 and 31 can be converted to the B6.1 or B6.2 format without changing any existing circuitry using the methods described herein.

[0030] One application of the B-fixed-point format is the representation of modulation and coding schemes. Modulation and coding schemes in the Wi-Fi standard are currently represented by integers. However, future updates may include additional modulation and coding schemes with effective bit transmission rates (e.g., effective bits transmitted per transmitted symbol) that fall between existing schemes. The B-fixed-point format would allow modulation and coding schemes to be represented by numerical values ​​that monotonically increase the effective bit transmission rate relative to the values ​​used for the modulation and coding scheme.

[0031] Some embodiments of this disclosure relate to an apparatus comprising one or more circuits configured to perform operations. The operations include generating a second binary coded number by removing a first bit from a first binary coded number in a fixed-point format. The operations also include generating a first output based on the first binary coded number. The operations further include generating a second output based on the second binary coded number and selecting either the first output or the second output based on the first bit.

[0032] In some embodiments, the second binary encoded number has a lower resolution than the first binary encoded number.

[0033] In some embodiments, a binary-coded number refers to any sequence of signs '1' and '0' (or 'high' and 'low' levels; or 'true' and 'false', etc.) used to represent a number. For example, a binary-coded number may refer to the sequence '00000101' used to represent the integer 5 (e.g., as an unsigned integer) or '00011001' used to represent 6.25 (e.g., as a Q6.2 fixed-point number). A fixed-point format refers to a class of binary encodings for numbers in which, in some embodiments, specific positions in the binary sequence always have the same value. For example, a fixed-point format may refer to the Q6.2 format or the Q7.1 format. In the Q7.1 fixed-point format, bit 0 (e.g., index 0) always represents 0.5 and bit 7 (e.g., the last index of a byte) always represents 64. In some embodiments, a lower-resolution number (e.g., a reduced-resolution number) refers to a value that represents a larger amount compared to another number for its least significant bits. For example, Q6.1 represents a reduced resolution compared to Q6.2 resolution. In some embodiments, a number with a lower resolution may be referred to as a low-resolution number when relative to another number definition. For example, given a Q7.1 representation and a Q6.2 resolution, the Q7.1 representation is low-resolution because it has fewer decimal places (e.g., one decimal place and a resolution of 0.5) than the Q6.2 representation (e.g., with two decimal places and providing a resolution of 0.25).

[0034] In some embodiments, a bit refers to a single digit of a binary encoded number. For example, a bit may refer to the position of '1' or '0'. In some embodiments, a byte refers to eight bits stored sequentially. For example, a byte may refer to the sequence '00000101'. In some embodiments, at least a portion of one or more bytes refers to any number of bits from one or more bytes that maintain their original order. For example, at least a portion of one or more bytes may refer to '0101' or '0100000101'.

[0035] In some embodiments, the second output is a legacy output (e.g., calculated using a previous version of the circuitry or code). In some embodiments, a legacy output refers to the output of circuitry or software that was previously used (e.g., before an update) or was originally used to process inputs from a previous revision. For example, a legacy output may refer to the output from circuitry operating on lower-resolution inputs (e.g., output from a device upgraded to support higher resolution). In some embodiments, the first output is a contemporary output. In some embodiments, a contemporary output refers to the output of circuitry that processes inputs using the format of the current revision. For example, a contemporary output may refer to the output from circuitry operating on higher-resolution inputs and / or the output from circuitry used to process upgraded inputs.

[0036] In some embodiments, the first bit is the least significant bit of the first binary encoded number and the most significant bit representing a portion of one or more bytes of the first binary encoded number.

[0037] In some embodiments, the least significant bit of a binary encoded number refers to the bit that contributes the least to the total value of the number. For example, the least significant bit may refer to bit 0 of a Q5.3 encoded number, which represents a value of 0.125, or bit 5 of a B4.2 number, which represents a value of 0.25. In some embodiments, the most significant bit of a portion of one or more bytes refers to the bit position that will represent the maximum value in integer format. For example, the most significant portion of one or more bytes may refer to bit 7 of an unsigned 8-bit integer or the maximum index of any bit within a portion of one or more bytes.

[0038] In some embodiments, the first binary encoded digit represents the modulation and coding scheme.

[0039] In some embodiments, the first binary coded number is one of a plurality of binary coded numbers and the modulation and coding scheme is one of a plurality of modulation and coding schemes, and the corresponding effective data transmission rate of the plurality of modulation and coding schemes has a monotonic relationship with the plurality of binary coded numbers.

[0040] In some embodiments, the first output and the second output include a modulation type and a write code rate, and the operation further includes transmitting or receiving signals using the modulation type and the write code rate.

[0041] In some embodiments, the modulation and coding scheme refers to the modulation type and the write code rate. For example, the modulation and coding scheme may refer to 16 quadrature amplitude modulation (QAM) with a write code rate of ¾. In some embodiments, the modulation type refers to the relationship between the binary bit sequence (e.g., symbols) and the amplitude and phase of the transmitted signal (e.g., as on a constellation diagram). For example, the modulation type may refer to binary phase shift keying (BPSK), 16 QAM, or 256 QAM. In some embodiments, the write code rate refers to the fraction of non-redundant (e.g., not used for forward error correction) data in the transmitted data. For example, the write code rate may refer to a 3 / 4 write code rate, which indicates that 25% of the transmitted symbols are redundant and used to detect transmission errors (e.g., 75% are used to transmit data).

[0042] In some embodiments, the effective data transmission rate refers to the information content that can be delivered over a communication channel within a specific time period. For example, the effective data transmission rate may refer to bits per second or bits per sample. Bits per second is related to the length of time (e.g., 12.8 μs) it takes to transmit a single symbol per sample, which is also related to the signal bandwidth. In some embodiments, a monotonic relationship refers to a function, mapping, or other relationship whose gradient takes only one sign (e.g., a non-negative or non-positive gradient). For example, a monotonic relationship may refer to a monotonically increasing function such that if the input (e.g., the domain of the function) increases, then the output (e.g., the upper domain) must not decrease, or a monotonically decreasing function such that if the input increases, then the output must not increase.

[0043] In some embodiments, the integer portion of the first binary encoded number representing a negative power of 2 is stored in a lower significant bit representing a portion of one or more bytes of the first binary encoded number, compared to the fractional portion representing a negative power of 2 in the first binary encoded number.

[0044] In some embodiments, a non-negative power of 2 means that it can be written as 2 n A number in the form , where n is a non-negative number. For example, a non-negative power of 2 can refer to the integers 1, 2, 4, 8, 16, etc., and can be represented by the sign at a certain position in a binary sequence. In some embodiments, a negative power of 2 refers to a number that can be written as 2 n A number in the form of n, where n is negative. For example, negative powers of 2 can refer to decimals such as 1 / 2, 1 / 4, 1 / 8, 1 / 16, etc., and can be represented by a sign at a certain position in a binary sequence. In some embodiments, the integer part of the binary encoded number refers to the position in the binary sequence representing a non-negative power of 2. In some embodiments, the fractional part of the binary encoded number refers to the position in the binary sequence representing a negative power of 2.

[0045] In some embodiments, the consecutive lower significant bits of the fractional portion of the first binary encoded digit are stored in consecutive higher significant bits.

[0046] In some embodiments, the operation further includes reordering the bits of the first binary encoded digit such that, prior to arithmetic operations, consecutive higher significant bits of the first binary encoded digit are stored in consecutive higher significant bits of the portion of the one or more bytes.

[0047] In some embodiments, the operation further includes removing a second bit from a third binary encoded number to produce the first binary encoded number. The second bit represents a less significant second bit of the third binary encoded number than a first bit represented by the first bit, and the second bit is stored in a more significant location representing one or more bytes of the third binary encoded number. The operation further includes generating a third output based on the third binary encoded number and selecting (i) the third output or (ii) the selection of the first output or the second output based on the second bit.

[0048] In some embodiments, the third binary encoded number is a high-resolution number or a higher-resolution number. In some embodiments, a high-resolution number refers to a value having a number of decimal places in a fixed-point format. For example, a high-resolution number may refer to a number represented as Q4.2 or Q5.3. High resolution may be defined relative to another number, for example, given a Q7.1 representation and a Q6.2 resolution, the Q6.2 representation is high-resolution because it has more decimal places (e.g., two decimal places, providing a resolution of 0.25) than the Q7.1 representation (e.g., having one decimal place and providing a resolution of 0.5).

[0049] Some embodiments of this disclosure relate to a method. The method includes generating a second binary encoded number by removing a first bit from a first binary encoded number in a fixed-point format. The method further includes generating a second output based on the second binary encoded number. The method also includes generating a first output based on the first bit and the second output, and selecting either the first output or the second output based on the first bit.

[0050] In some embodiments, the first bit is the least significant bit of the first binary encoded number and the most significant bit representing a portion of one or more bytes of the first binary encoded number.

[0051] In some embodiments, the first binary coded number is one of a plurality of binary coded numbers representing a plurality of modulation and coding schemes, and the corresponding effective data transmission rates of the plurality of modulation and coding schemes have a monotonic relationship with the plurality of binary coded numbers.

[0052] In some embodiments, the first output and the second output include a modulation type and a write code rate, and the method further includes transmitting or receiving signals using the modulation type and the write code rate.

[0053] In some embodiments, the integer portion of the first binary encoded number representing a negative power of 2 is stored in a lower significant bit representing a portion of one or more bytes of the first binary encoded number, compared to the fractional portion representing a negative power of 2 in the first binary encoded number.

[0054] In some embodiments, the consecutive lower significant bits of the fractional portion of the first binary encoded digit are stored in consecutive higher significant bits.

[0055] In some embodiments, the method further includes reordering the bits of the first binary encoded digit such that, prior to arithmetic operations, consecutive higher significant bits of the first binary encoded digit are stored in consecutive higher significant bits of the portion of the one or more bytes.

[0056] In some embodiments, the method further includes removing a second bit from a third binary encoded number to generate the first binary encoded number. The second bit represents a less significant second bit of the third binary encoded number than a first bit represented by the first bit, and the second bit is stored in a more significant location representing one or more bytes of the third binary encoded number. The method further includes generating a third output based on the third binary encoded number and selecting (i) the third output or (ii) the selection of the first output or the second output based on the second bit.

[0057] Some embodiments of this disclosure relate to an apparatus comprising separation circuitry configured to separate a first binary encoded digit in a fixed-point format into one or more first bits and a second binary encoded digit. The first binary encoded digit is represented by at least a portion of one or more bytes, and the one or more first bits comprise the least significant bit of the first binary encoded digit and the most significant bit of the portion of the one or more bytes. The apparatus further comprises a first processing circuitry configured to generate a first output based on the first binary encoded digit. The apparatus further comprises a second processing circuitry configured to generate a second output based on the second binary encoded digit. The apparatus further comprises a selection circuitry configured to select either the first output or the second output based on the one or more first bits.

[0058] In some embodiments, separating a binary-coded number means rerouting one or more bits from the binary-coded number to another memory. For example, bit 4 of a B4.1 fixed-point number (e.g., representing 0.5) can be removed, leaving an integer (e.g., B4.0 or Q4.0).

[0059] In some embodiments, the first binary coded number represents a modulation and coding scheme, and both the first output and the second output include at least one of a modulation type or a coding rate. The apparatus further includes at least one of: a transmitting circuit configured to transmit a first signal using the modulation type or the coding rate; or a receiving circuit configured to receive a second signal using the modulation type or the coding rate.

[0060] Communication Network

[0061] Before discussing certain embodiments, it may be helpful to describe the operating environment and associated system components (e.g., hardware elements) in conjunction with the methods and systems described herein. References Figure 1A This describes an embodiment of a network environment. In simple terms, the network environment includes a wireless communication system comprising one or more access points (APs) or network devices 106, one or more stations or wireless communication devices 102, and network hardware components or network hardware 192. Wireless communication device 102 may, for example, include a laptop computer, tablet computer, personal computer, and / or cellular phone device. (See reference...) Figure 1B and 1C More detailed descriptions are provided for embodiments of each station or wireless communication device 102 and AP or network device 106. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, etc. Network device 106 or AP may be operatively coupled to network hardware 192 via a local area network (LAN) connection. In some embodiments, network device 106 is a 5G base station. Network hardware 192 (which may include routers, gateways, switches, bridges, modems, system controllers, appliances, etc.) may provide LAN connectivity for the communication system. Each of network device 106 or AP may have an associated antenna or antenna array to communicate with wireless communication devices in its area. Wireless communication device 102 may register with a specific network device 106 or AP to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via allocated channels and communication protocols. Some wireless communication devices 102 may be mobile or relatively stationary relative to network device 106 or AP.

[0062] In some embodiments, network device 106 or AP includes means or modules (comprising a combination of hardware and software) that allow wireless communication device 102 to connect to a wired network using Wi-Fi or other standards. Network device 106 or AP may sometimes be referred to as a wireless access point (WAP). Network device 106 or AP may be implemented (e.g., configured, designed, and / or built) for operation in a wireless local area network (WLAN). In some embodiments, network device 106 or AP may be connected to a router as a standalone device (e.g., via a wired network). In other embodiments, network device 106 or AP may be a component of a router. Network device 106 or AP may provide network access to multiple devices. Network device 106 or AP may, for example, connect to a wired Ethernet connection and use a radio frequency link to provide wireless connectivity to other devices 102 so that they can utilize that wired connection. Network device 106 or AP may be implemented to support standards that use one or more radio frequencies to transmit and receive data. Those standards and the frequencies they use may be defined by IEEE (e.g., the IEEE 802.11 standard). Network device 106 or AP may be configured and / or used to support public Internet hotspots and / or may be used on the network to extend the Wi-Fi signal range of the network.

[0063] In some embodiments, access point or network device 106 may be used for (e.g., in a home, vehicle, or building) wireless networks (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency-based network protocol, and / or variations thereof). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access point or network device 106 may operate according to various aspects of this disclosure as presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to networked nodes, such as servers) via one or more access point or network devices 106.

[0064] The network connection may include any type and / or form of network and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, computer network. The network topology may be a bus, star, or ring network topology. The network may have any network topology known to those skilled in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0065] (Several) communication devices 102 and (several) access points or network devices 106 may be deployed as any type and form of computing device and / or perform thereon, such as a computer, network device or appliance capable of communicating on any type and form of network and performing the operations described herein. Figure 1B and 1C A block diagram depicts a computing device 100 useful for embodiments of the practical wireless communication device 102 or network device 106. (See diagram for reference.) Figure 1B and 1C As shown, each computing device 100 includes a processor 121 (e.g., a central processing unit) and a main memory unit 122. Figure 1B As shown, the computing device 100 may include a storage device 128, a mounting device 116, a network interface 118, an I / O controller 123, display devices 124a to 124n, a keyboard 126, and a pointing device 127, such as a mouse. The storage device 128 may include an operating system and / or software. Figure 1C As shown, each computing device 100 may also include additional optional components such as memory port 103, bridge 170, one or more input / output devices 130a to 130n, and cache memory 140 that communicates with the central processing unit or processor 121.

[0066] The central processing unit or processor 121 is any logic circuit system that responds to and processes instructions fetched from main memory unit 122. In many embodiments, the central processing unit or processor 121 is provided by a microprocessor unit, such as those manufactured by Intel Corporation of Santa Clara, California; those manufactured by International Business Machines of White Plains, New York; or those manufactured by Advanced Micro Devices of Sunnyvale, California. The computing device 100 may be based on any of these processors or any other processor capable of operating as described herein.

[0067] Main memory unit 122 may be one or more memory chips capable of storing data and allowing the microprocessor or processor 121 to directly access any memory location, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and solid-state drive (SSD). Main memory unit 122 may be based on any of the aforementioned memory chips or any other available memory chip capable of operating as described herein. Figure 1B In the embodiment shown, the processor 121 communicates with the main memory unit 122 via the system bus 150 (described in more detail below). Figure 1C An embodiment of computing device 100 is depicted, wherein the processor communicates directly with main memory unit 122 via memory port 103. For example, in Figure 1C In this context, the main memory unit 122 can be DRDRAM.

[0068] Figure 1C An embodiment is depicted in which the main processor 121 communicates directly with the cache memory 140 via an auxiliary bus (sometimes referred to as a back-side bus). In other embodiments, the main processor 121 communicates with the cache memory 140 using a system bus 150. The cache memory 140 typically has a faster response time than the main memory cell 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1C In the embodiment shown, processor 121 communicates with various I / O devices 130 via local system bus 150. Various buses can be used to connect the central processing unit or processor 121 to any of the I / O devices 130, such as VESA VL bus, ISA bus, EISA bus, Micro Channel Architecture (MCA) bus, PCI bus, PCI-X bus, Fast PCI bus, or NuBus. In the embodiment where the I / O device is a video display 124, processor 121 may use an Advanced Graphics Port (AGP) to communicate with the display 124. Figure 1C An embodiment of a computer or computer system 100 is depicted, wherein the main processor 121 may communicate directly with the I / O device 130b, for example, via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technologies. Figure 1C An embodiment in which a hybrid local bus and direct communication is also depicted: the processor 121 communicates with I / O device 130a using the local interconnect bus, while simultaneously communicating directly with I / O device 130b.

[0069] The computing device 100 may contain various I / O devices 130a to 130n. Input devices include keyboards, mice, trackpads, trackballs, microphones, dial pads, touchpads, touchscreens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye-to-sublimation printers. The I / O devices can be controlled by the I / O controller 123, such as... Figure 1B As shown in the figure. The I / O controller can control one or more I / O devices, such as keyboard 126 and pointing device 127, such as mouse or light pen. In addition, the I / O devices can also provide storage and / or mounting media for computing device 100. In yet another embodiment, computing device 100 can provide USB connectivity (not shown) to receive handheld USB storage devices, such as the USB flash drive series devices manufactured by Twintech Industry, Inc. of Los Alamitos, California.

[0070] Refer again Figure 1B The computing device 100 may support any suitable installation device 116, such as a disk drive, CD-ROM drive, CD-R / RW drive, DVD-ROM drive, flash memory drive, various forms of tape drive, USB device, hard disk drive, network interface, or any other device suitable for installing software and programs. The computing device 100 may further include storage devices for storing the operating system and other related software, and for storing application software programs (e.g., any program or software 120 for implementing (e.g., configured and / or designed for) the systems and methods described herein), such as one or more hard disk drives or a redundant array of independent disks. Optionally, any of the installation devices 116 may also be used as storage devices. Additionally, the operating system and software may be run from a bootable medium.

[0071] Furthermore, the computing device 100 may include a network interface 118 to connect to a network via various connections, including but not limited to standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), broadband connections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, SONET-based Ethernet), wireless connections, or any combination thereof. Connections can be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and direct asynchronous connections). In one embodiment, computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol (e.g., Secure Sockets Layer (SSL) or Transport Layer Security (TLS)). Network interface 118 may include a built-in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem, or any other means suitable for connecting computing device 100 to any type of network capable of communication and performing the operations described herein.

[0072] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a to 124n. Therefore, any of the I / O devices 130a to 130n and / or I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide computing device 100 with connection to and use of the display devices 124a to 124n. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to dock, communicate, connect to, or otherwise use the display devices 124a to 124n. In one embodiment, a video adapter may include multiple connectors to dock to the display devices 124a to 124n. In other embodiments, computing device 100 may include multiple video adapters, each connected to the display devices 124a to 124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use the multiple display devices 124a to 124n. In a further embodiment, I / O device 130 may be a bridge between system bus 150 and an external communication bus, such as a USB bus, Apple Desktop bus, RS-232 serial connection, SCSI bus, FireWire bus, FireWire 800 bus, Ethernet bus, AppleTalk bus, Gigabit Ethernet bus, Asynchronous Transfer Mode bus, FibreChannel bus, Fiber optic bus, Serial Attached Small Computer System Interface bus, USB connection, or HDMI bus.

[0073] Figure 1B and 1CThe computing device 100 of the type described herein can operate under the control of an operating system that controls task scheduling and access to system resources. The computing device 100 can run any operating system, such as any version of the Microsoft Windows operating system, different versions of Unix and Linux operating systems, any version of MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open-source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include, but are not limited to: Android, produced by Google Inc.; Windows 7, 8, and 10, produced by Microsoft Corporation of Redmond, Washington; MAC OS, produced by Apple Computer of Cupertino, California; WebOS, produced by Research In Motion (RIM); OS / 2, produced by International Business Machines of Armonk, New York; and Linux, a free operating system distributed by Caldera Corp. of Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0074] The computer system or computing device 100 may be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunications device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunications, or media device capable of communication. In some embodiments, the computing device 100 may have a different processor, operating system, and input device consistent with the device described herein. For example, in one embodiment, the computing device 100 is a smartphone, mobile device, tablet computer, or personal digital assistant. Furthermore, the computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunications device capable of communication and having sufficient processor power and memory capacity to perform the operations described herein.

[0075] Circuits with scalable fixed-point numerical formats

[0076] Figure 2 This describes various binary encodings that can be used for numbers in any of the systems and / or methods described herein. For example, wireless communication device 102, network device 106, and / or computing device 100 ( Figure 1A Either of C) can be used Figure 2 The binary encoding described herein may be used by other computing, sensing, or communication devices.

[0077] According to some embodiments, in Figure 2 The image shows the Q-format binary encoded number 201. The Q-format binary encoded number 201 is displayed in Q6.2 format as having a 6-bit integer component and a 2-bit fractional component. The Q-format binary encoded number 201 is displayed as having a total of 8 bits and can be stored in one byte of the computing device 100.

[0078] The Q-format binary encoded number 201 in Q6.2 is represented as having 8 bits, represented by q0 through q7. Q-format is a fixed-point format, and each of the bits q0 through q7 represents a value based on an index (e.g., the position of the bit). If a bit is '1' (e.g., true, high), then that bit contributes a specific amount to the total value of the number. For example, in the Q6.2 format of the Q-format binary encoded number 201, a '1' in bit q0 indicates a 1 / 4 contribution, a '1' in bit q1 indicates a 1 / 2 contribution, as indicated by... Figure 2 The number displayed above the Q-format binary encoded number 201 is an indicator. Generally, the value of any Qm.n number can be derived from the following formula:

[0079]

[0080] Where q i `m` is the value of the bit (e.g., 0 or 1), `m` is the number of integer bits, and `n` is the number of decimal bits. In the Q6.2 format of the Q-format binary encoded number 201, the least significant bit 210 (e.g., bit q0) is also the least significant bit of the binary encoded number and corresponds to a resolution of 1 / 4. The most significant bit 212 (e.g., bit q7) is also the most significant bit of the binary encoded number and represents the value 32. The Q6.2 format can represent numbers with a resolution of 0.25 between 0 and 63.75.

[0081] At least one drawback of the Q fixed-point format is that the resolution of the numbers (e.g., the value associated with the least significant bit) cannot be easily adjusted after the system is designed (e.g., circuitry is created, instruction code is written, etc.). Increasing the resolution might involve adding bits to the right of the least significant bit (e.g., in index -1), which may not be permitted. For example, considering the Q-format binary encoded number 201 in Q6.2, if the resolution is increased to Q6.3, then the value of each bit q0 through q7 is reduced to half its original value. In the Q6.3 format, q0 is associated with a value of 1 / 8 and q1 with a value of 1 / 4, and so on. Because the value associated with each of these bits has changed, downstream circuitry and / or software may have to be modified, resulting in an expensive redesign.

[0082] In some embodiments, the different formats of fixed-point binary encoding disclosed herein and referred to as B format can improve upon certain shortcomings of the Q format illustrated by Q format binary encoded number 201. In some embodiments, B format binary encoded number 202 also has a 2-bit fractional component and a 6-bit integer component, and in some embodiments is referred to herein as B 6.2 (BM.n, where B denotes B format, m is the number of integer bits, and n is the number of fractional bits). In some embodiments, B format is shown as comprising bits b0 to b7. In some embodiments, B format is also a fixed-point format, and thus each bit b0 to b7 has a fixed value associated with said bit. One difference between B format and Q format is the storage location of the fractional component. In B format, the fractional component is stored in the most significant bit of memory (e.g., the highest index). For example, in some embodiments, B format binary encoded number 202 shows fractional bits stored in b6 and b7 and integer components stored in b0 to b5.

[0083] In B format, the least significant bit 2^10 (e.g., the lowest index) can represent the integer value 1, and the most significant bit 2^12 (e.g., the highest index) can represent the resolution (e.g., the least significant bit of the binary encoded number), as shown by... Figure 2 The value of a binary number in B-format binary encoding is indicated by the number above the bit 202. The value of a binary number in B-format binary encoding can be obtained from the following formula:

[0084]

[0085] Where b i Here, m is the value of the bit (e.g., 0 or 1), m is the number of integer bits, and n is the number of decimal bits. In some embodiments, in the B format, the most significant bit (e.g., representing the maximum value) may not be stored in the most significant bit (e.g., having the highest index). In the B fixed-point format, the most significant bit may be stored in b. m-1In some embodiments, in the B fixed-point format, the least significant bit can be stored in the most significant bit b. m+n-1 In some embodiments, a number represented in B fixed-point format is converted to Q fixed-point format before performing arithmetic operations (e.g., multiplication, addition, etc.). For example, the digits of a number in B fixed-point format may be reordered such that, as in Q fixed-point format, consecutive higher significant digits are stored in consecutive higher significant digits (e.g., higher index bits).

[0086] Figure 2 Two additional B-format binary encoded numbers (e.g., B4.1 binary encoded number 203 and B4.2 binary encoded number 204) are shown according to some embodiments. In some embodiments, the binary encoded number may not use all 8 bits of a byte. In some embodiments, the binary encoded number may use more than one byte. Therefore, although the least significant bit of the B fixed-point format binary encoded number may be stored in the most significant bit 212 of the binary encoded number (e.g., the bit with the highest index), the least significant bit may not be the highest index of the byte (e.g., if m+n is not divisible by 8).

[0087] In B format, increasing the resolution of a number represented in B format involves adding another bit to the bit position where the index is greater than 1 and represents a value equal to half the previous resolution. For example, by amplifying a B4.1 binary encoded number 203 with b5, the resolution of B4.1 binary encoded number 203 can be enhanced to 1 / 4. Amplifying B4.1 binary encoded number 203 with b5 can have the effect of converting B4.1 binary encoded number 203 into B4.2 binary encoded number 204. Advantageously, when the resolution is increased (e.g., when B4.1 binary encoded number 203 is converted into B4.2 binary encoded number 204), the values ​​associated with the bits present in B4.1 binary encoded number 203 (e.g., bits b0 to b4) do not change the values ​​they represent. Therefore, after conversion using the circuits and methods described herein, the conversion can be performed without changing the existing (e.g., legacy) circuit system.

[0088] It should be noted that for integer resolution, the B format and Q format are similar. For example, if there is no fractional component, then bits in the B format can represent the same integer value as bits in the Q format. Systems or parts thereof that have numbers represented as integers can be upgraded to higher resolutions using the B fixed-point format without significantly altering the existing system.

[0089] Figure 3This is an illustrative block diagram of a resolution upgrade circuit 300 and its interconnections in a system (e.g., apparatus, device, integrated circuit, etc.) according to some embodiments, the system being configured to operate on digital representations (e.g., binary-coded numbers) using a B-fixed-point format at an improved resolution. The system may be part of a wireless communication network for which a portion of the system has been upgraded to improve resolution. For example, the circuitry may be connected to... Figure 1A The circuitry can be implemented using any of the networks shown or devices communicating with said networks. For example, the circuitry can be implemented within network device 106 and used to communicate with any user device 102. In some embodiments, the circuitry can be implemented using one or more memory devices storing instructions to be executed by one or more processors. In some embodiments, the circuitry can be implemented using application-specific integrated circuits (ASICs), digital signal processing (DSP) integrated circuits, or system-on-a-chip integrated circuits.

[0090] The processor may be a general-purpose or special-purpose processor, an application-specific integrated circuit (ASIC), an artificial intelligence processor, one or more field-programmable gate arrays (FPGAs), a DSP circuit, a group of processing components, or other suitable processing components. The processor may be configured to execute computer code and / or instructions stored in memory or received from other computer-readable media (e.g., CD-ROM, network storage device, remote server, etc.). The processor may be configured with various computer architectures, such as a graphics processing unit (GPU), a distributed computing architecture, a cloud server architecture, a client-server architecture, or various combinations thereof. One or more first processors may be implemented by a first device (e.g., an edge device), and one or more second processors may be implemented by a second device (e.g., a server or other device) communicatively coupled to the first device and having larger processor and / or memory resources.

[0091] The memory may include one or more means (e.g., memory cells, memory devices, storage devices, etc.) for storing data and / or computer code used to perform and / or facilitate the various processes described herein. The memory may include random access memory (RAM), read-only memory (ROM), hard disk drive storage devices, temporary storage devices, non-volatile memory, flash memory, optical memory, or any other suitable memory for storing software objects and / or computer instructions. The memory may include database components, object code components, scripting components, or any other type of information structure for supporting the various activities and information structures described herein. The memory may be communicatively connected to a processor and may contain computer code for performing (e.g., executed by the processor) the one or more processes described herein.

[0092] In some embodiments, the resolution upgrade circuit 300 includes a separation circuit 320, a legacy processing circuit 340, a contemporary processing circuit 360, and a selection circuit 380. The resolution upgrade circuit 300 can be configured to separate (e.g., remove, reassemble, etc.) an appropriate number of bits from B-fixed-point format binary encoded digits to form binary encoded digits of appropriate resolution for processing by previous generations of circuitry systems. The original input (e.g., a higher resolution input) can be processed using circuitry configured for the current code generation, and the output of the processing circuitry can then be selected based on the value of the bits separated from the input B-fixed-point format binary encoded digits.

[0093] Separator circuit 320 can be configured to separate one or more bits from a binary-coded digital input. Separator circuit 320 can separate the most significant bit (e.g., the highest index) of an input byte or a portion thereof. If the input uses the B fixed-point format described herein, then separator circuit 320 can reduce the resolution of the output binary-coded digital by separating the bit with the highest index. After bits have been separated from the B fixed-point format input, the remaining lower-resolution binary-coded digital can be processed by circuitry designed for lower-resolution binary-coded digital. Figure 3 As shown, lower-resolution binary encoded numbers can be output by the legacy processing circuit 340 and used as input, while the original binary encoded numbers input to the resolution upgrade circuit 300 can be processed by the contemporary processing circuit 360.

[0094] Figure 4 A detailed block diagram of a splitting circuit 320 according to some embodiments is shown. The splitting circuit 320 may include a configuration 322 and a splitter 324. For the present application of the splitting circuit 320, the configuration 322 may include parameters related to the bits to be separated from the binary encoded digital input 205. For example, the configuration 322 may include parameters defining the format of the binary encoded digital input 205 (e.g., B6.2, B4.4, etc.) and the format of the low-resolution output 222 (e.g., B6.0, B4.1, etc.). The input and output formats allow the splitting circuit 320 to determine the correct number of bits to be separated from the higher bit index of the binary encoded digital input 205. Additionally or alternatively, the configuration 322 may store the number of bits to be separated.

[0095] Separator 324 can be configured to separate bits of binary-coded digital input 205 at locations defined by configuration 322. For example, configuration 322 can instruct that the separation should include the two bits with the highest index, occurring between b5 and b6, and / or convert the binary-coded digital input 205 (e.g., in B6.2 format) to a low-resolution output 222 (e.g., in B6.0 format). Separator 324 may include two outputs: a first output of one or more first bits 220 separated from the binary-coded digital input 205 and a second output of the low-resolution output 222.

[0096] Refer again Figure 3 The low-resolution output 222 from the separation circuit 320 is applied as input to the legacy processing circuit 340. The legacy processing circuit 340 may include any processing circuitry configured to operate at a lower resolution for the low-resolution output 222. The legacy processing circuit 340 may be a processing circuitry system used prior to upgrading to a higher resolution digital format. For example, the legacy processing circuit 340 may be configured to process integer values, and the resolution upgrade circuit 300 may be upgraded to support 1 / 2 or 1 / 4 resolution. In some embodiments, the legacy processing circuit 340 produces a legacy output that can be output from the resolution upgrade circuit 300 for inputs that do not use higher resolution bits (e.g., one or more separated first bits 220 are '0').

[0097] Use such as Figure 3 The legacy processing circuit 340, connected as shown, allows the resolution upgrade circuit 300 to use the legacy processing circuit 340 without modification, thereby reducing development time. Additionally, when the output of the legacy processing circuit 340 is not transmitted out of the resolution upgrade circuit 300, the contemporary processing circuit 360 may only need to calculate the appropriate output, which simplifies the design.

[0098] The contemporary processing circuitry 360 can be configured to perform processing directly on high-resolution input. For example, the contemporary processing circuitry 360 may include circuitry, instruction sets, etc., for generating output for upgraded or higher resolution fixed-point numerical formats. In some embodiments, the contemporary processing circuitry 360 is configured to generate contemporary output from binary-coded digital input, for example, if one or more first bits 220 are not '0', then the contemporary output may be output to the resolution upgrade circuitry 300.

[0099] Selection circuit 380 can be configured to select between a contemporary output from contemporary processing circuit 360 and a legacy output from legacy processing circuit 340. Figure 5 A selection circuit 380 is shown according to some embodiments. For example, when one or more first bits 220 contain a single bit, a selection circuit 380 can be used. Figure 5The selection circuit 380 may include a multiplexer 382. The multiplexer 382 may select between a legacy output and a contemporary output based on a first bit. If the first bit is '0', indicating that the input binary-coded digits are not using enhanced resolution and therefore the legacy processing circuit 340 can properly process the input, then the multiplexer 382 may select the legacy output from the legacy processing circuit 340. Alternatively, if the first bit is '1', indicating that the binary-coded digits are using additional (e.g., upgraded) resolution and the contemporary processing circuit 360 can be used, then the multiplexer 382 may select the contemporary output from the contemporary processing circuit 360.

[0100] In some embodiments, selection circuit 380 provides control signals back to legacy processing circuit 340 and contemporary processing circuit 360 (e.g., processing circuitry), thereby inducing execution of said circuitry. For example, selection circuit 380 may request only execution of processing circuitry whose outputs might ultimately be used, to reduce the number of computations performed or the energy used (e.g., from switching losses, etc.), thereby allowing signals to propagate through unused processing circuitry. Additionally or alternatively, selection circuit 380 may prevent (e.g., prevent, etc.) execution of unused processing circuitry. Selection circuit 380 may prevent instructions of unused processing circuitry from being executed, or selection circuit 380 may prevent changes to the inputs of unused processing circuitry, thereby preventing any changes from propagating through unused processing circuitry.

[0101] In some embodiments, the legacy processing circuit 340 and the contemporary processing circuit 360 are designed for the same generation of code or circuitry. The configuration of the resolution upgrade circuit 300 can be used to simplify the design of the processing circuitry, for example, rather than for a generational upgrade of resolution. The first processing circuitry (e.g., contemporary processing circuitry 360) can be simplified because the output of the first processing circuitry is discarded when the first bit is zero and the selection circuit 380 selects the output of the first processing circuitry. The second processing circuitry (e.g., legacy processing circuitry 340) can be simplified because it operates on the output of lower resolution numbers. Additionally, and as... Figure 8 As shown, the first processing circuitry can be configured to modify the output of the second processing circuitry, thereby allowing for additional simplification. Such use of the circuitry configurations described herein is within the scope of this disclosure.

[0102] In some embodiments, the resolution upgrade circuit 300 may be nested within another resolution upgrade circuit 300. For example, if an upgrade has been performed to improve the resolution of the binary encoded input, the entire resolution upgrade circuit 300 from the first upgrade may become the legacy processing circuit 340 for the second upgrade. Figure 6A nested resolution upgrade circuit 301 is shown according to some embodiments. The nested resolution upgrade circuit 301 may include multiple separation circuits 320 (e.g., additional separation circuits 320 for each nested layer), legacy processing circuitry 340, contemporary processing circuitry 360, high-resolution processing circuitry 370, and selection circuitry 380.

[0103] In some embodiments, each delimiter 320 of the nested resolution upgrade circuitry 301 may delimit one bit from the high-resolution output. For example, each processing circuit may be configured to process the numerical input using fixed-point encoding that provides twice the resolution (e.g., a resolution value divided by 2). The bit delimited by the delimiter 320 may be provided to (e.g., sent to, communicated to, applied to, etc.) a selection circuit 380 to allow selection between the outputs of the legacy processing circuitry 340, the contemporary processing circuitry 360, or the high-resolution processing circuitry 370. The selection circuitry 380 may be configured as two selection circuits 380, for example, a first selection circuitry 380 configured to select between the legacy output and the contemporary output, and a second selection circuitry 380 configured to select between the output of the first selection circuitry 380 and the high-resolution output from the high-resolution processing circuitry 370. Alternatively, the selection circuitry 380 may be configured to select from the legacy output, the contemporary output, and the high-resolution output based on both the first and second bits from the delimiter 320.

[0104] Figure 7 A selection circuit 380, configured according to some embodiments, to select legacy output, contemporary output, and high-resolution output based on both a first and a second bit from a separation circuit 320, is illustrated. The selection circuit 380 may include two multiplexers (e.g., multiplexer 382 and multiplexer 384). Multiplexer 382 may be configured to select between legacy and contemporary outputs based on the first bit, and multiplexer 384 may be configured to select between the output of multiplexer 382 and a high-resolution output based on the second bit. It should be noted that the second bit may be the least significant bit and may be the bit with the highest index in the input byte. The second bit may refer to a second bit added during a resolution upgrade process. For example, the original circuitry may be legacy processing circuitry 340 and configured to process only low-resolution binary-coded numbers (e.g., integers). The first bit may have been added during a first resolution upgrade process (e.g., to provide 1 / 2 resolution), and then during a second upgrade process, the second bit may be added (e.g., to provide 1 / 4 resolution).

[0105] In some embodiments, processing from legacy processing circuitry 340 may be reused by contemporary processing circuitry 360. In some embodiments, legacy outputs may be applied as inputs to contemporary processing circuitry 360 and used to eliminate the need to duplicate some circuitry systems that would be shared between legacy processing circuitry 340 and contemporary processing circuitry 360. Figure 8 A resolution upgrade circuit 300 is illustrated according to some embodiments, wherein the output from legacy processing circuitry 340 is used by contemporary processing circuitry 360. In some embodiments, binary-coded numbers input to resolution upgrade circuitry 300 are also provided to contemporary processing circuitry 360. Alternatively, contemporary processing circuitry 360 may be configured to modify legacy output based on the first bit, without using the entire binary-coded number. Advantageously, either configuration can reduce redundant processing performed by both legacy processing circuitry 340 and contemporary processing circuitry 360, thereby saving computational and / or energy used by resolution upgrade circuitry 300.

[0106] One application of the resolution upgrade circuit 300 is the processing of modulation and coding schemes used in standard wireless communication technologies. Figure 9 Table 400 illustrates modulation and coding schemes available in a first revision of a wireless communication standard (e.g., Wi-Fi 7) according to some embodiments. For each modulation and coding scheme, Table 400 includes an nMCS (e.g., an integer representation of a binary sequence for a particular modulation and coding scheme), an MCS (e.g., a value for a binary sequence of a particular modulation and coding scheme using the B fixed-point format described herein), and an effective data transmission rate in bits per symbol (bps) (e.g., for a subcarrier frequency).

[0107] More modulation and coding schemes can be added in future revisions of wireless communication standards (such as Wi-Fi 8 or Ultra Reliability (UHR)). Figure 10 Table 410 illustrates modulation and coding schemes according to some embodiments, including those in potential future revisions. Some of the modulation and coding schemes in Table 410 provide an effective data transmission rate between two modulation and coding schemes that are already part of the standard (e.g., in Table 400). For example, 256-QAM with a write code rate of 2 / 3 provides an effective data transmission rate of 5.33 bps (e.g., 8 bits per symbol multiplied by a 2 / 3 write code rate). This effective data transmission rate of 5.33 bps falls between the effective data transmission rate of 64-QAM with a write code rate of 5 / 6 (e.g., 5.0 bps) and the effective data transmission rate of 256-QAM with a write code rate of 3 / 4.

[0108] If MCS numbers are sequentially assigned to new modulation and coding schemes (e.g., by assigning the next available integer (e.g., 14) to 256-QAM with a 2 / 3 write code rate), then the MCS numbers will no longer have a monotonic relationship with the effective data transmission rate. Larger MCS numbers may not indicate higher-capacity communication channels. The loss of monotonicity can cause problems in processing that depends on the MCS numbers. For example, if the MCS selection circuitry is configured to always select the largest available and / or reliable MCS number, then even when a faster modulation and coding scheme is available, the circuitry may select a suboptimal modulation and coding scheme.

[0109] MCS numbers can be represented in the B fixed-point format described herein. The MCS numbers in Table 400 (which are integers between 0 and 16) can be represented in B4.0. To add MCS numbers between the existing MCS numbers in Table 400, the resolution of the underlying numerical format of the MCS numbers can be increased. For example, the B4.1 format can be used to upgrade the MCS numbers to an enhanced resolution. Alternatively, the B5.1 format can be used to upgrade the MCS numbers to an enhanced resolution to allow for additional space for integer expansion. Advantageously, the B4.1 format can be used with the resolution upgrade circuit 300 to reuse any previously used MCS processing circuitry.

[0110] Table 410 shows the MCS numbers of the modulation and coding schemes in Table 400, as well as additional modulation and coding schemes for future revisions of the wireless technology. Table 410 shows the potential MCS numbers of additional modulation and coding schemes that maintain a monotonic relationship with the effective data transmission rate. Table 410 also shows the nMCS numbers defined as the resulting integers when the MCS number represented using B4.1 is evaluated as an integer (e.g., MCS7.5 = '10111' in B4.1, which is 23 when converted to an unsigned integer).

[0111] Figure 11 and 12 Examples of a resolution upgrade circuit 300 and a nested resolution upgrade circuit 301, which can be used to upgrade an integer MCS number with an increased resolution, are shown according to some embodiments. Figure 11 and 12 Resolution upgrade circuits 300 and 301 may be included in a wireless communication device configured to transmit and / or receive messages (e.g., via transmitting and receiving circuits) according to a modulation and coding scheme indicated by an MCS number. Resolution upgrade circuits 300 and 301 may (e.g., from a selected MCS number) determine the modulation and coding scheme and communicate it to the transmitting and receiving circuits for appropriate decoding (or encoding) of the received (or transmitted) signal.

[0112] Figure 11 A resolution upgrade circuit 300, according to some embodiments, is shown for upgrading an integer MCS number to incorporate a digital representation with a resolution of 1 / 2. For example, Figure 11 The resolution upgrade circuit 300 can be configured to allow a pre-UHR circuit system to be incorporated into the resolution upgrade circuit 300 to process MCS numbers that can be represented by integer values ​​used prior to the upgrade. Prior to the upgrade, a Q4.0 binary encoded number (e.g., the same as an integer or B4.0) is applied as input to the pre-UHR MCS logic circuit 340a to produce an output indicating the modulation type (e.g., QAM), write code rate (e.g., R), and effective data transfer rate (e.g., bps). To represent the new 0.5 resolution MCS number in Table 410, the pre-UHR MCS logic circuit 340a can be incorporated into the resolution upgrade circuit 300 as an embodiment of the legacy processing circuit 340.

[0113] The B4.1 number can be used to represent the value 0.5 by incorporating an additional bit b4 (e.g., the most significant bit or highest index of the portion of the input byte) to indicate an additional resolution for the MCS number in Table 410. The B4.1 number can be input to a split circuit 320, where the first bit b4 is separated from the integer component and passed to a selection circuit 380. The integer portion can be applied as input to a pre-UHR MCS logic circuit 340a to produce an output of R, QAM, and bps, as if the resolution had not been updated. The original B4.1 number input to the resolution upgrade circuit 300 can be applied as input to a UHR additional MCS logic circuit 360a (e.g., implementing contemporary processing circuit 360) to produce an output of R, QAM, and bps for any input using the enhanced resolution. The selection circuit 380 can then select R, QAM, and bps from either the pre-UHR MCS logic circuit 340a or the UHR additional MCS logic circuit 360a. If the first bit b4 is '0', indicating that increased resolution is not used and the pre-UHR MCS-logic circuit 340a is configured to calculate the appropriate output, then the output from the pre-UHR MCS-logic circuit 340a can be selected. If the first bit b4 is '1', indicating that increased resolution is necessary and the UHR additional MCS-logic circuit 360a is configured to calculate the appropriate output, then the output from the UHR additional MCS-logic circuit 360a can be selected.

[0114] To upgrade the MCS number resolution, use Figure 8The configuration of the resolution upgrade circuit 300 shown can be appropriate. The UHR additional MCS-logic circuit 360a can be configured to adjust the legacy outputs of R, QAM, and bps. For example, each of the modulation and coding schemes using the enhanced resolution bit b4 in Table 410 has an encoding scheme that is shifted by 1 relative to the modulation and coding scheme that does not use the enhanced resolution bit b4 (e.g., from R=1 / 2 to R=2 / 3, from R=3 / 4 to R=4 / 5, etc.). The UHR additional MCS-logic circuit 360a can be configured to shift the encoding scheme output by the pre-UHR MCS-logic circuit 340a when the first bit b4 is '1', instead of recoding the entire table, thereby advantageously reducing the complexity (and therefore cost, failure rate, etc.) of the resolution upgrade circuit 300 configured to enhance the resolution of the MCS number.

[0115] In some embodiments, more than one modulation and coding scheme has an effective data transfer rate between the effective data transfer rates of two of the modulation and coding schemes shown in Table 400. For example, if 256-QAM with a write code rate of 2 / 3 (e.g., 5.33 bps) and 64-QAM with a write code rate of 7 / 8 (e.g., 5.875 bps) are used, then two MCS numbers can be placed between MCS 7.0 and MCS 8.0 and a resolution of 0.25 may be appropriate. In some embodiments, a nested resolution upgrade circuit 301 can be used to enhance the resolution of the MCS numbering scheme to include a resolution of 0.25. Considering that if the resolution is upgraded from an integer resolution to a resolution of 0.25 all at once, then the separation circuit 320 and the selection circuit 380 can be configured to process two digits simultaneously. However, if the resolution is upgraded in stages (e.g., first upgraded to a resolution of 0.5 and then later upgraded to a resolution of 0.25), then a nested configuration of the nested resolution upgrade circuit 301 may be appropriate.

[0116] Figure 12An embodiment of a nested resolution upgrade circuit 301 is shown, wherein a pre-UHR MCS logic circuit 340a implements legacy processing circuitry 340, a UHR additional MCS logic circuit 360a implements contemporary processing circuitry 360 and is configured to process inputs at a resolution of 0.5, and a future MCS logic circuit 370a implements high-resolution processing circuitry 370. In some embodiments, a first delimiter circuit 320 can extract input delimiter bit b5 to form a B4.1 binary encoded number for processing by the UHR additional MCS logic circuit 360a. A second delimiter circuit 320 can extract output delimiter bit b4 from the first delimiter circuit 320 to generate an integer representation for the pre-UHR MCS logic circuit 340a. Additionally, the original B4.2 number can be input to the future MCS logic circuit 370a. A selection circuit 380 can select appropriate outputs R, QAM, and bps from the processing circuitry. For example, bit b4 can be used at multiplexer 382 to select between the output from pre-UHR MCS logic circuit 340a or UHR additional MCS logic circuit 360a, and bit b5 can be used at multiplexer 384 to select between the output from the output of multiplexer 382 and the output from future MCS logic circuit 370a.

[0117] Operational procedures for improving the resolution of fixed-point numerical formats

[0118] Figure 13 This is an operational flow 500, according to some embodiments, for enhancing the resolution of numerical formats in circuitry without significantly altering existing circuitry or code. Operational flow 500 can be executed by resolution upgrade circuitry 300 or nested resolution upgrade circuitry 301. For example, operational flow 500 can be used to generate write code rate, modulation type, and effective data transmission rate for a wireless communication device that has been upgraded to use an MCS number with a resolution of 0.5 (e.g., instead of an integer).

[0119] After executing operation procedure 500, downstream operations may not change (e.g., from before using enhanced resolution for one or more of the values). For example, an apparatus executing operation procedure 500 to use an MCS number with a resolution of 0.5 can use the write code rate, modulation type, and effective data transmission rate in a manner substantially similar to values ​​used with an integer MCS number. As a transmitter, the apparatus can generate an Orthogonal Frequency Domain Multiple Access (OFDMA) communication signal based on a constellation diagram of the modulation type (e.g., determined using operation procedure 500 and / or resolution upgrade circuit 300), repeat data at a frequency based on the write code rate (e.g., also determined using operation procedure 500 and / or resolution upgrade circuit 300), modulate the communication signal at a carrier frequency, and transmit the modulated signal. Similarly, as a receiver, the apparatus can execute operation procedure 500 to generate a modulation type and write code rate, decode the received signal into binary symbols according to the modulation type, and perform fault detection (e.g., for communication channel interference, etc.) at a frequency based on the write code rate. Additionally, the B4.1 fixed-point format can be used to maintain a monotonic relationship between the MCS number and the effective data transmission rate, thereby allowing downstream optimizations to remain unchanged or similar.

[0120] Operation 500 may include, in operation 520, generating a low-resolution binary encoded number by removing the first bit from a binary encoded number in a fixed-point format. The low-resolution binary encoded number may be in a B fixed-point format, and the fractional component may be stored in a bit position with a higher index. The low-resolution binary encoded number is formed by multiplying (e.g., downgrading) the resolution by 2 by removing the first bit from the binary encoded number in the B fixed-point format described herein. In some embodiments, more than one bit is removed from the binary encoded number, and the resolution is downgraded by a factor of 2.

[0121] The low-resolution binary-coded number output from operation 520 can be used as input for subsequent operations that process lower-resolution binary-coded numbers (e.g., operations from legacy codes or prior to upgrades to enhanced resolution). For example, in some embodiments, the binary-coded number represents an MCS number of a modulation and coding scheme containing 0.5 in a B4.1 fixed-point format with enhanced resolution. Operation 520 can be used to remove the first bit to produce a B4.0 (e.g., or integer representation) value, which can be processed using previous instructions and / or circuitry configured to operate using legacy codes (e.g., integer-based MCS numbers). Decoupling circuitry 320 can be configured to perform operation 520 to produce an output for the first bit (or all removed bits) and the remaining low-resolution binary-coded number, as previously described.

[0122] Operation 500 may include generating a legacy output based on a low-resolution binary-encoded number in operation 530. In some embodiments, operation 500 is performed after the resolution of the numerical value is enhanced (e.g., made smaller to form a high-resolution value). Operation 530 may be performed using the same or substantially similar method or process as before the enhanced resolution. Removing the first bit in operation 520 allows similar operations to be performed.

[0123] Operation 530 can be performed by legacy processing circuitry 340. In some embodiments, the binary encoded number represents an MCS number comprising an enhanced 0.5 resolution modulation and write coding scheme in B4.1 fixed-point format, with the first low-resolution digit removed in B4.0 format (e.g., an integer). For the low-resolution B4.0 format, the modulation type, write code rate, and effective data transmission rate can be determined using pre-UHR MCS logic circuitry 340a.

[0124] Operation 500 may include generating a contemporary output based on binary-coded numbers in operation 540. Operation 540 may include performing operations for processing binary-coded numbers. In some embodiments, the binary-coded numbers may represent numerical values ​​with enhanced resolution and operation 530 may be modified to process values ​​with enhanced resolution. In some embodiments, several steps of operation 530 may be reused to process (higher resolution) binary-coded numbers. Operation 540 may use the first bit as input (e.g., using...) Figure 8 The illustrated embodiment of the resolution upgrade circuit 300 is used to process (e.g., adjust, modify, etc.) the output of operation 530.

[0125] Operation 540 may be performed by contemporary processing circuitry 360, or by additional UHR MCS logic circuitry 360a in an embodiment where binary-coded numbers represent the MCS number of the modulation and coding scheme.

[0126] Operation 500 may include in operation 560 selecting either the legacy output or the current output based on the first bit. For example, operation 560 may be performed by selection circuitry 380 as described herein. If the first bit is '0', then it is appropriate not to use the enhanced resolution and to use the legacy output generated from the low-resolution binary-encoded digits in operation 530. However, if the first bit is '1', then the current output from operation 540 is appropriate.

[0127] In some embodiments, the legacy output of operation 530 and the contemporary output of operation 540 are for the same generation of code and / or circuitry. Operation flow 500 can be used to simplify the design of operations that produce specific outputs, for example, rather than generational upgrades in resolution. A first output (e.g., the current output of operation 540) can be simplified because, in operation 560, some values ​​for the first bit are discarded. A second output (e.g., the legacy output of operation 530) can be simplified because it operates on lower-resolution numbers (e.g., with fewer bits). Additionally, operation 540 can modify the second output of operation 530, thereby allowing for further simplification. Such uses of the operation flow described herein are within the scope of this disclosure.

[0128] Figure 14 This is another operational flow 501, according to some embodiments, for enhancing the resolution numerical format in circuitry without significantly altering existing circuitry or code. For example, operational flow 501 may be executed if the resolution of a numerical value has previously been enhanced (e.g., using resolution upgrade circuitry 300 and / or operational flow 500) and a second enhancement of resolution is desired. In some embodiments, operational flow 500 may be nested (e.g., recursively) each time the resolution of a numerical value is enhanced. Due to the nested configuration, many operations of operational flow 501 are similar to those of operational flow 500.

[0129] Operation 501 may include generating a binary encoded number in operation 510 by removing a second bit from a high-resolution binary encoded number in fixed-point format. Operation 510 may be performed by decoupling circuitry 320. It should be noted that although the bit removed in operation 510 is referred to as the second bit, the second bit may be removed from the high-resolution binary encoded number before the first bit and may refer to the bit with the highest index of the byte or a portion thereof representing the high-resolution binary encoded number. For example, the high-resolution binary encoded number may be in B4.2 fixed-point format. When the second bit is removed (e.g., bit b5), the result is a B4.1 fixed-point format value, and when the first bit is subsequently removed (e.g., bit b4), the result is a B4.0 fixed-point format value.

[0130] Operation flow 501 may include generating a low-resolution binary encoded number by removing the first bit from a binary encoded number in a fixed-point format in operation 520, generating a legacy output based on the low-resolution binary encoded number in operation 530, and generating a contemporary output based on the binary encoded number in operation 540. These operations may be substantially similar to those in operation flow 500 and are performed by the second separation circuit 320, the legacy processing circuit 340, and the contemporary processing circuit 360, respectively.

[0131] Operation flow 501 may include generating a high-resolution output based on a high-resolution binary encoded number in operation 550. Operation 550 may include steps specific to processing the high-resolution binary encoded number. In some embodiments, for example, the high-resolution binary encoded number represents an MCS number comprising an enhanced 0.25 resolution modulation and coding scheme in B4.2 fixed-point format, and the operation may be performed by future MCS logic circuitry 370a. Operation flow 501 may include selecting (i) a high-resolution output or (ii) a selection of an older or contemporary output based on a second bit in operation 570.

[0132] After executing operation procedure 501, downstream operations may not change (e.g., from the resolution of one or more of the enhanced values). For example, an apparatus executing operation procedure 501 to use an MCS number with a resolution of 0.25 can use the write code rate, modulation type, and effective data transmission rate in a manner substantially similar to values ​​used with an integer MCS number. As a transmitter, the apparatus can generate an Orthogonal Frequency Domain Multiple Access (OFDMA) communication signal based on a constellation diagram of the modulation type (e.g., determined using operation procedure 501 and / or resolution upgrade circuit 301), repeat data at a frequency based on the write code rate (e.g., also determined using operation procedure 501 and / or resolution upgrade circuit 301), modulate the communication signal at the carrier frequency, and transmit the modulated signal. Similarly, as a receiver, the apparatus can execute operation procedure 501 to generate a modulation type and write code rate, decode the received signal into binary symbols according to the modulation type, and perform fault detection (e.g., for communication channel interference, etc.) at a frequency based on the write code rate. Additionally, the B4.2 fixed-point format can be used to maintain a monotonic relationship between the MCS number and the effective data transmission rate, thereby allowing downstream optimizations to remain unchanged or similar.

[0133] Configuration of exemplary embodiments

[0134] As used herein, the terms “approximately,” “about,” “substantially,” and similar terms are intended to have a broad meaning consistent with common and acceptable usage by one of ordinary skill in the art to which this disclosure pertains in relation to the subject matter. Those skilled in the art who review this disclosure will understand that these terms are intended to allow for the description of certain features described and claimed, without limiting the scope of these features to the precise numerical ranges provided. Therefore, these terms should be interpreted as indicating that non-substantial or unreasonable modifications or alterations to the described and claimed subject matter are considered to be within the scope of this disclosure as set forth in the appended claims.

[0135] It should be noted that the terms “illustrative” and variations thereof used herein to describe various embodiments are intended to indicate that such embodiments are possible instances, representations or illustrations of possible embodiments (and such terms are not intended to mean that such embodiments are necessarily unusual or superlative instances).

[0136] The construction and arrangement of the systems and methods shown in the various exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, many modifications are possible (e.g., the number of ports or destinations, data types, methods of reinsertion, reintroduction, etc., parameter values, changes in arrangement, etc.). For example, the positions of elements may be reversed or otherwise changed, the connections between elements may be direct or indirect, such that one or more intermediate elements may be connected between them, and the nature or number of discrete elements or positions may be altered or changed. Therefore, all such modifications are intended to be included within the scope of this disclosure. According to alternative embodiments, the order or sequence of any process or method steps may be changed or reordered. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions, and arrangement of the exemplary embodiments without departing from the scope of this disclosure. For example, embodiments of this disclosure may be implemented by a single device and / or system or by a combination of single devices and / or systems.

[0137] As used herein, the term "or" is used in its inclusive sense (rather than its exclusive sense) such that when used to connect a list of elements, the term "or" indicates one, some, or all of the elements in the list. Unless specifically stated otherwise, conjunction language (e.g., the phrase "at least one of X, Y, and Z") is understood to express that the elements may be X, Y, Z; X and Y; X and Z; Y and Z; or X, Y, and Z (i.e., any combination of X, Y, and Z). Therefore, unless otherwise indicated, this conjunction language is generally not intended to imply that certain embodiments require the existence of at least one of X, at least one of Y, and at least one of Z.

[0138] References to element positions (i.e., “top,” “bottom,” “above,” “below”) in this document are used only to describe the orientation of the various elements in the accompanying drawings. It should be noted that the orientation of the various elements may differ according to other exemplary embodiments, and such variations are intended to be covered by this disclosure.

[0139] Although the accompanying drawings illustrate a specific order of method steps, the order of steps may differ from the depicted order. Furthermore, two or more steps may be performed concurrently or partially concurrently. This variation will depend on the chosen software and hardware system and the designer's choices. All such variations are within the scope of this disclosure. Similarly, software implementations may be implemented using standard programming techniques with rule-based logic and other logic to perform various connection steps, processing steps, comparison steps, and decision steps.

[0140] This disclosure contemplates methods, systems, and program products on any machine-readable medium for performing various operations. Embodiments of this disclosure may use existing computer processors, or dedicated computer processors incorporated for suitable systems for this or another purpose, or be implemented by hardwired systems. Embodiments within the scope of this disclosure include program products comprising machine-readable media for carrying or storing machine-executable instructions or data structures thereon. This machine-readable medium may be any available medium accessible by a general-purpose or special-purpose computer or other machine having a processor. For example, this machine-readable medium may include RAM, ROM, EPROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of machine-executable instructions or data structures and is accessible by a general-purpose or special-purpose computer (i.e., ASIC or FPGA) or any other machine having a processor. Combinations of the above are also included within the scope of machine-readable media. Machine-executable instructions include, for example, instructions and data that cause a general-purpose computer, special-purpose computer, or special-purpose processor to perform a function or group of functions.

Claims

1. An apparatus comprising one or more circuits configured to perform operations, the operations including: The second binary coded number is generated by removing the first bit from the first binary coded number in a fixed-point format; A first output is generated based on the first binary encoded number; A second output is generated based on the second binary encoded number; and The first output or the second output is selected based on the first bit.

2. The apparatus of claim 1, wherein the second binary coded number has a lower resolution than the first binary coded number.

3. The apparatus of claim 1, wherein the first bit is the least significant bit of the first binary coded number and the most significant bit representing a portion of one or more bytes of the first binary coded number.

4. The apparatus according to claim 3, wherein the first binary coded number represents the modulation and coding scheme.

5. The apparatus according to claim 4, wherein the first binary coded number is one of a plurality of binary coded numbers and the modulation and coding scheme is one of a plurality of modulation and coding schemes, and the corresponding effective data transmission rate of the plurality of modulation and coding schemes has a monotonic relationship with the plurality of binary coded numbers.

6. The apparatus according to claim 4, wherein: The first output and the second output include modulation type and write code rate; and The operation further includes transmitting or receiving signals using the modulation type and the write code rate.

7. The apparatus of claim 1, wherein the integer portion of the first binary encoded number representing a negative power of 2 is stored in a lower significant bit representing a portion of one or more bytes of the first binary encoded number, compared to the fractional portion representing a negative power of 2 in the first binary encoded number.

8. The apparatus of claim 7, wherein the consecutive lower significant bits of the fractional portion of the first binary encoded digit are stored in consecutive higher significant bits.

9. The apparatus of claim 8, wherein the operation further comprises reordering the bits of the first binary encoded digit such that, prior to arithmetic operations, consecutive higher significant bits of the first binary encoded digit are stored in consecutive higher significant bits of the portion of the one or more bytes.

10. The apparatus of claim 1, wherein the operation further comprises: The first binary digit is generated by removing a second bit from the third binary digit, wherein the second bit represents a less significant second bit of the third binary digit than the first bit represented by the first bit, and the second bit is stored in a more significant position in one or more bytes representing the third binary digit. A third output is generated based on the third binary encoded number; and Based on the second bit selection (i) the third output or (ii) the selection of the first output or the second output.

11. A method comprising: The second binary coded number is generated by removing the first bit from the first binary coded number in a fixed-point format; A second output is generated based on the second binary encoded number; A first output is generated based on the first bit and the second output; and The first output or the second output is selected based on the first bit.

12. The method of claim 11, wherein the first bit is the least significant bit of the first binary coded number and the most significant bit representing a portion of one or more bytes of the first binary coded number.

13. The method according to claim 12, wherein the first binary coded number is one of a plurality of binary coded numbers representing a plurality of modulation and coding schemes, and the corresponding effective data transmission rate of the plurality of modulation and coding schemes has a monotonic relationship with the plurality of binary coded numbers.

14. The method of claim 11, wherein: The first output and the second output include modulation type and write code rate; and The method further includes transmitting or receiving signals using the modulation type and the write code rate.

15. The method of claim 11, wherein the integer portion of the first binary encoded number representing a negative power of 2 is stored in a lower significant bit representing a portion of one or more bytes of the first binary encoded number, compared to the fractional portion representing a negative power of 2 in the first binary encoded number.

16. The method of claim 15, wherein consecutive lower significant bits of the fractional portion of the first binary encoded digit are stored in consecutive higher significant bits.

17. The method of claim 16, further comprising reordering the bits of the first binary encoded digit such that, prior to arithmetic operations, consecutive higher significant bits of the first binary encoded digit are stored in consecutive higher significant bits of the portion of the one or more bytes.

18. The method of claim 11, further comprising: The first binary digit is generated by removing a second bit from the third binary digit, wherein the second bit represents a less significant second bit of the third binary digit than the first bit represented by the first bit, and the second bit is stored in a more significant position in one or more bytes representing the third binary digit. A third output is generated based on the third binary encoded number; and Based on the second bit selection (i) the third output or (ii) the selection of the first output or the second output.

19. An apparatus comprising: A separation circuit configured to separate a first binary coded number in a fixed-point format into one or more first bits and second binary coded numbers, the first binary coded number being represented by at least a portion of one or more bytes, wherein the one or more first bits contain the least significant bit of the first binary coded number and the most significant bit of the portion of the one or more bytes. A first processing circuit is configured to generate a first output based on the first binary encoded number; A second processing circuit is configured to generate a second output based on the second binary encoded number; and The selection circuit is configured to select the first output or the second output based on one or more first bits.

20. The apparatus according to claim 19, wherein: The first binary coded number represents the modulation and coding scheme, and both the first output and the second output include at least one of the modulation type or the coding rate; and The device further includes at least one of the following: A transmitting circuit configured to transmit a first signal using the modulation type or the write code rate; or A receiving circuit configured to receive a second signal using the modulation type or the write code rate.

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