Internet-of-things equipment edge security access authentication method based on domestic SoC

Abstract

The invention relates to the technical field of network security, and particularly discloses an Internet of Things equipment edge security access authentication method based on a domestic SoC (System on Chip), which reconstructs a root key in real time by using an SRAM (Static Random Access Memory) physical fingerprint when a chip is powered on, thoroughly abandons static storage of a private key, and completely eradicates a physical cloning risk from the source. On the basis, according to the scheme, a root key and gateway challenge are deeply bound through an SM3 algorithm, and key derivation is carried out by adopting an avalanche linkage mechanism based on cross feedback. The mechanism forcibly determines the one-way dependence of the verification tag on the integrity of the session key, so that any key error caused by hardware faults such as single event upset inevitably causes tag verification failure, thereby effectively blocking the establishment of an invalid secure channel under zero extra hardware cost, and improving the security of the security channel. Therefore, the safe access of the edge device with the self-immunity capability is realized.

Description

Technical Field

[0001] This application relates to the field of network security technology, and more specifically, to a method for edge security access authentication of IoT devices based on domestically developed SoCs. Background Technology

[0002] With the rapid development of the Industrial Internet and ubiquitous sensing technologies, massive numbers of IoT devices are being deployed at the network edge at an unprecedented pace. This not only supports the operation of critical infrastructure such as smart cities and intelligent manufacturing, but also makes edge data security a crucial barrier to national information security. In this process, adopting domestically produced SoCs as core processing units has become an inevitable trend for achieving technological self-reliance and control. To ensure the authenticity and reliability of devices accessing the network and prevent unauthorized intrusion or data tampering, building an edge access authentication system that is compatible with the characteristics of domestic chip architectures and meets the requirements of high real-time performance and high security is a core issue that urgently needs to be addressed in the current IoT security field.

[0003] However, existing IoT device access authentication schemes still face many serious challenges in practical applications. Traditional authentication methods mostly rely on statically burning pre-set keys into the chip's non-volatile memory (such as Flash or EEPROM). This "hold-and-authenticate" model has inherent physical security vulnerabilities. Once a device is lost in an uncontrolled outdoor environment, attackers can easily extract static data from the storage medium through chip decapsulation, micro-probe detection, or side-channel attacks, thereby achieving physical cloning and identity forgery of the device. Although this problem can be mitigated by using external dedicated security chips, this undoubtedly increases the BOM cost and hardware design complexity of massive edge devices, making it difficult to promote on a large scale in low-cost domestic SoC applications. More importantly, existing lightweight authentication protocols often use a relatively simple static truncation mechanism in the key derivation stage, that is, directly physically dividing the hash digest into a session key and a verification tag. This parallel and independent generation path is extremely vulnerable to environmental disturbances such as single-event upsets: if cosmic rays or voltage fluctuations cause bit flips in the register storing the temporary key, while the verification tag portion remains unaffected, the edge gateway will mistakenly authenticate based on the correct tag, thus establishing a failed security channel based on the corrupted key, leading to subsequent communication paralysis that is difficult to trace. Furthermore, this static physical segmentation method also creates a strong linear correlation between the publicly transmitted verification tag and the confidential session key, making it an easy target for differential power analysis attacks.

[0004] Therefore, an optimized edge security access authentication scheme for IoT devices is desired. Summary of the Invention

[0005] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a method for edge security access authentication of IoT devices based on a domestically developed SoC.

[0006] According to one aspect of this application, a method for edge security access authentication of IoT devices based on a domestically developed SoC is provided, comprising: In response to the domestic SoC receiving the power-on reset signal, the original value of the SRAM physical fingerprint is obtained; The device root key is reconstructed from the original value of the SRAM physical fingerprint and the stored auxiliary error correction data. The domestically developed SoC parses authentication request packets from the edge gateway to obtain a gateway challenge random number; Perform an SM3 hash operation on the gateway challenge random number and the device root key to obtain the authentication digest hash value; The session key and authentication label are derived from the authentication digest hash value to obtain the current session key and authentication label. The authentication tag is encapsulated in the device response protocol message and sent back to the edge gateway through the physical layer interface.

[0007] Compared with existing technologies, this application provides a secure edge access authentication method for IoT devices based on a domestically developed SoC. It utilizes the SRAM physical fingerprint generated upon chip power-on to reconstruct the root key in real time, completely eliminating the static storage of the private key and eradicating the risk of physical cloning at its source. Furthermore, the solution deeply binds the root key to the gateway challenge using the SM3 algorithm and employs a cross-feedback avalanche linkage mechanism for key derivation. This mechanism enforces a one-way dependency of the verification tag on the integrity of the session key, ensuring that any key error caused by hardware failures such as single-event upsets will inevitably lead to tag verification failure. Thus, with zero additional hardware cost, it effectively blocks the establishment of invalid secure channels, achieving secure edge device access with self-immunity. Attached Figure Description

[0008] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0009] Figure 1 This is a flowchart of an edge security access authentication method for IoT devices based on a domestically developed SoC, according to an embodiment of this application. Figure 2This is a schematic diagram of data flow in the IoT device edge security access authentication method based on a domestically developed SoC according to an embodiment of this application; Figure 3 This is a flowchart illustrating the process of performing SM3 hash operations on a gateway challenge random number and a device root key to obtain an authentication digest hash value in an edge security access authentication method for IoT devices based on a domestically developed SoC, according to an embodiment of this application. Figure 4 This is a flowchart illustrating the process of deriving the current session key and authentication tag from the session key and authentication tag based on the authentication digest hash value in the edge security access authentication method for IoT devices based on domestic SoC according to the embodiments of this application. Detailed Implementation

[0010] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0011] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0012] While this application makes various references to certain modules of the systems according to embodiments of this application, any number of different modules can be used and run on user terminals and / or servers. The modules described are merely illustrative, and different aspects of the systems and methods may use different modules.

[0013] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0014] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0015] To address the risks of physical cloning in existing domestic SoC IoT devices due to static key storage in Flash memory, and the limitations of traditional simple parallel key derivation mechanisms in resisting key corruption caused by single-event upsets and side-channel attacks, this application proposes a secure edge access authentication method for IoT devices based on domestic SoCs. In implementation, this method first utilizes the unique physical metastable fingerprint of the SRAM unit at power-on instant of the domestic SoC, combined with pre-stored auxiliary data, to reconstruct the device root key in real time, achieving key generation upon use and destruction upon power loss. Then, the SM3 hardware engine is used to hash and aggregate the gateway challenge random number and the root key. Instead of the traditional static truncation method, a session key is generated using orthogonal decomposition of global entropy and a forward diffusion strategy. Crucially, the generated session key is directly used as necessary feedback input in the projection calculation of the authentication tag, forcibly constructing a directed dependency chain of the public tag on the integrity of the private key. This ensures that any minor hardware fault or attack disturbance can be instantly identified and blocked by the gateway through tag verification.

[0016] Figure 1 This is a flowchart of an edge security access authentication method for IoT devices based on a domestically developed SoC, according to an embodiment of this application. Figure 2 The data flow diagram of the edge security access authentication method for IoT devices based on domestically developed SoC according to the embodiments of this application is as follows: Figure 1 and Figure 2 As shown, the edge security access authentication method for IoT devices based on a domestically developed SoC according to an embodiment of this application includes: S100, in response to the domestically developed SoC receiving a power-on reset signal, obtaining the original value of the SRAM physical fingerprint; S200, reconstructing the device root key by performing device root key reconstruction on the original value of the SRAM physical fingerprint and the stored auxiliary error correction data to obtain the device root key; S300, parsing the authentication request data packet from the edge gateway by the domestically developed SoC to obtain the gateway challenge random number; S400, performing SM3 hash operation on the gateway challenge random number and the device root key to obtain the authentication digest hash value; S500, deriving the session key and verification tag based on the authentication digest hash value to obtain the current session key and identity authentication tag; S600, encapsulating the identity authentication tag into a device response protocol message, and sending the device response protocol message back to the edge gateway through the physical layer interface.

[0017] Specifically, in step S100, in response to the domestic SoC receiving a power-on reset signal, the original value of the SRAM physical fingerprint is acquired. It should be understood that due to microscopic random physical deviations in the complementary metal-oxide-semiconductor (CMOS) manufacturing process, the metastable level characteristics exhibited by the static random access memory (SRAM) cells at the moment of power-on are extremely weak, and these initial characteristics are highly susceptible to electromagnetic interference from power ripple, ground bounce noise, and digital logic flipping generated by the concurrent operation of other functional modules within the chip. Therefore, in the technical solution of this application, in response to the domestic SoC receiving a power-on reset signal, the original value of the SRAM physical fingerprint is acquired. This allows for the accurate capture of the chip's unique physical characteristics during the initial silent phase of system reset, before any unnecessary hardware modules start up and application layer software runs. This fundamentally eliminates the impact of environmental noise on the quality of the entropy source of the physical non-cloning function, ensuring that the acquired fingerprint data has a high signal-to-noise ratio and reproducibility stability, thereby providing a reliable hardware trust anchor for the subsequent construction of a device root key without static storage.

[0018] More specifically, in the embodiments of this application, in response to the domestic SoC receiving a power-on reset signal, obtaining the original value of the SRAM physical fingerprint includes: in response to the domestic SoC receiving a power-on reset signal, actively turning off all unnecessary peripheral clocks except for the SRAM controller and CPU core domain and disabling global interrupts to obtain an environment ready flag; after detecting that the environment ready flag is valid, performing SRAM array traversal reading to obtain the original SRAM word sequence; and serializing and constructing a binary vector from the original SRAM word sequence to obtain the original value of the SRAM physical fingerprint.

[0019] Specifically, in a concrete example of this application, the data acquisition process strictly adheres to the principle of silent acquisition. First, the bootloader inside the domestic SoC immediately takes over control after the reset interrupt vector is triggered. It forcibly cuts off the clock supply to all peripheral modules except the SRAM controller and CPU core domain, such as the general-purpose input / output interface, general-purpose asynchronous transceiver, and direct memory access controller, by writing instructions to specific registers of the clock management unit. Simultaneously, it configures the interrupt controller to mask all global interrupt sources except for reset and non-maskable interrupts. After confirming that the chip has entered the minimum system operating state, it generates an environment-ready flag. Subsequently, based on the valid environment-ready flag, the central processing unit uses the loading instructions to perform a continuous linear traversal read of the reserved SRAM physical address segment on-chip. It extracts the logic 0 or 1 state of each SRAM memory cell, which is randomly latched due to process deviations at the moment of power-on, and temporarily stores it as the original SRAM word sequence. Finally, the processing unit performs bit-width alignment and bit-stream concatenation operations on the original SRAM word sequence in the linear growth order of the address space, integrating the discrete storage words into a continuous and fixed-length binary vector, thereby constructing the original value of the SRAM physical fingerprint for subsequent key reconstruction.

[0020] Specifically, in step S200, the original value of the SRAM physical fingerprint and the stored auxiliary error correction data are reconstructed using a device root key to obtain the device root key. It should be understood that although the SRAM physical fingerprint originates from inherent microscopic differences in chip manufacturing processes, its actual powered logic state is highly susceptible to random bit flips caused by physical factors such as ambient temperature, core voltage fluctuations, and component aging. This results in a Hamming distance deviation between each collected data and the baseline data at the time of registration, and cryptographic systems require keys to possess absolute precision and consistency. Therefore, in the technical solution of this application, the original value of the SRAM physical fingerprint and the stored auxiliary error correction data are further reconstructed using a device root key to obtain the device root key. This utilizes a fuzzy extractor mechanism to dynamically eliminate environmental noise in the current physical characteristics without directly exposing the key information, through publicly available auxiliary data. This ensures that the device can stably recover a unique and definitive trusted root credential under various harsh physical environments without needing to statically store the private key in non-volatile memory, thereby completely eliminating the risk of static key extraction or cloning.

[0021] More specifically, in the embodiments of this application, the device root key is reconstructed from the original SRAM physical fingerprint value and the stored auxiliary error correction data, including: constructing and aligning noisy codeword vectors from the original SRAM physical fingerprint value and the stored auxiliary error correction data to obtain noisy codeword vectors; performing BCH / RS error correction decoding operations on the noisy codeword vectors to obtain corrected codeword vectors; and performing entropy extraction and root key generation on the corrected codeword vectors to obtain the device root key.

[0022] Specifically, in one particular example of this application, the processor first reads pre-programmed auxiliary error correction data from the common area of ​​the on-chip Flash. This data is generated during the device registration stage by XORing the standard fingerprint and the error correction codeword. The processor then executes a codeword offset construction process, performing a bitwise XOR alignment between the currently acquired SRAM physical fingerprint and the stored auxiliary error correction data. This linear operation transfers the difference between the current fingerprint and the registered fingerprint to the codeword domain, thereby constructing a noisy codeword vector with error bits. Next, the SoC calls its internally integrated hardware error correction engine or software algorithm library, using this noisy codeword vector as input to perform BCH error correction decoding. The BCH algorithm's ability to correct random errors is used to calculate the syndrome and solve the error position polynomial, accurately locating and flipping the bits that are erroneous due to physical noise, thus restoring a mathematically accurate corrected codeword vector. Finally, the system performs privacy amplification processing based on hash functions (such as SHA-256 or SM3) on the recovered codeword vector, filtering out the predictability brought by the error correction code structure and compressing the data length. Through this entropy extraction and transformation operation, a high-entropy and fixed-length device root key is generated.

[0023] Specifically, in step S300, the domestically developed SoC parses the authentication request data packet from the edge gateway to obtain a gateway challenge random number. It should be understood that due to the complex and open communication links in the IoT edge environment, it is highly susceptible to replay attacks, where attackers intercept and repeatedly send historically valid messages to deceive the device into re-establishing a connection. Furthermore, relying solely on static credentials cannot effectively distinguish between historically valid messages and current real-time requests, making it difficult to guarantee the freshness and non-repudiation of the session. Therefore, in the technical solution of this application, the domestically developed SoC is further used to parse the authentication request data packet from the edge gateway to obtain a gateway challenge random number, thereby introducing a real-time changing and unpredictable challenge factor as a freshness credential for this authentication session. This ensures that the subsequently generated authentication hash value has unique time sensitivity, rendering any attack attempts based on historical data ineffective due to challenge value mismatch, thus guaranteeing the freshness and anti-replay capability of the access authentication process.

[0024] More specifically, in the embodiments of this application, the domestic SoC parses the authentication request data packet from the edge gateway to obtain the gateway challenge random number, including: performing communication protocol integrity verification and unpacking on the authentication request data packet to obtain the application layer protocol payload; locating and parsing the challenge field on the application layer protocol payload to obtain the original random number data segment; and extracting data and standardizing the byte sequence on the original random number data segment to obtain the gateway challenge random number.

[0025] Specifically, in a concrete example of this application, the SoC's network protocol stack first receives the authentication request data packet uploaded from the physical layer and performs a cyclic redundancy check (CRC) according to a preset communication protocol standard to confirm that no bit errors occurred during the wireless or wired transmission of the data packet. After the check passes, the physical MAC header, IP header, and TCP / UDP header, and other transport layer encapsulation information are removed, thus extracting the pure application layer protocol payload. Subsequently, the application layer parser, according to specific industrial IoT protocol specifications (such as the TLV format Tag-Length-Value), traverses the data structure of the application layer protocol payload, retrieves the specific tag ID identified as the challenge random number, and after accurately locating the field, reads its length information and subsequent payload content to obtain the unprocessed raw random number data segment. Finally, the processor performs a byte order conversion operation on the raw random number data segment, converting the big-endian format commonly used in network transmission to the little-endian format adapted to the domestic SoC processor architecture, and maps it to a memory-aligned buffer. Through this standardized data extraction process, a gateway challenge random number that can ultimately participate in subsequent cryptographic operations is generated.

[0026] Specifically, in step S400, an SM3 hash operation is performed on the gateway challenge random number and the device root key to obtain the authentication digest hash value. It should be understood that unencrypted plaintext communication exposes the device's core identity credentials to the risk of direct eavesdropping, and static key verification mechanisms lacking time-varying factors cannot effectively defend against spoofing attacks by replaying historical messages. Furthermore, there are mandatory compliance requirements for the independent controllability of cryptographic algorithms in domestically developed critical information infrastructure. Therefore, in the technical solution of this application, an SM3 hash operation is further performed on the gateway challenge random number and the device root key to obtain the authentication digest hash value. This utilizes the irreversible unidirectional compression characteristics and the avalanche effect, which is extremely sensitive to input, of the SM3 cryptographic hash algorithm to deeply and irrevocably bind the static key data representing the device's unique identity with the dynamic random number representing the current session's validity at the mathematical logic level. This generates a dynamic credential that implicitly contains a zero-knowledge proof of the device's held key and has a one-time validity characteristic, thereby achieving high-strength identity authentication with both confidentiality and anti-replay capabilities while strictly ensuring that the root key is not leaked in the communication link.

[0027] Figure 3 This is a flowchart illustrating the process of performing an SM3 hash operation on a gateway challenge random number and a device root key to obtain an authentication digest hash value, according to an embodiment of this application for an edge security access authentication method for IoT devices based on a domestically developed SoC. Figure 3 As shown, step S400 includes: S410, concatenating the gateway challenge random number and the device root key to obtain a concatenated message sequence; S420, performing SM3 hardware acceleration engine scheduling and compression on the concatenated message sequence to obtain a hash operation completion signal; S430, extracting the hash operation completion signal and reading back the register to obtain the authentication digest hash value.

[0028] More specifically, in a concrete example of this application, the operation process achieves closed-loop protection and high-speed processing of the data flow through a hardware-software collaborative mechanism. First, the system kernel allocates a dedicated contiguous buffer within an isolated memory region protected by a hardware firewall. The processor writes the previously reconstructed device root key to the starting address of this buffer using a memory copy instruction. Then, the gateway challenge random number is appended to the key data. This physical concatenation operation constructs an unpadded concatenated message sequence. Subsequently, the driver configures the control register of the SM3 hardware acceleration engine to reset the engine's internal state machine and intermediate variables, and establishes a direct memory access channel, mapping the memory address of the concatenated message sequence to the engine's data input source. While receiving data, the hardware engine automatically performs bit stuffing and length stuffing operations according to the GM / T0004 standard, performs standard iterative compression calculations on the stuffed data blocks, and pulls the completion interrupt line high after completing the compression logic of all groups to generate a hash operation completion signal. Finally, the central processing unit responds to the interrupt signal, sequentially accesses the hardware engine's digest output register group through the memory-mapped I / O bus, reads the 256-bit binary data latched in the register into the general-purpose register file, thereby extracting the final authentication digest hash value, and immediately sends a state clear instruction to the hardware engine to erase the remaining intermediate state information after the reading is completed.

[0029] Specifically, in step S500, the session key and authentication tag are derived based on the authentication digest hash value to obtain the current session key and authentication tag. It should be understood that in resource-constrained edge authentication scenarios for domestically developed SoCs, the traditional key derivation mechanism—which directly physically divides the 256-bit SM3 hash digest into a high 128-bit session key and a low 128-bit authentication tag—has a profound inherent flaw. This mechanism fails to fully consider the special relationship between the key and tag as data objects; that is, a publicly verifiable tag should indirectly guarantee the integrity of the private key during its generation. Specifically, this simple static division results in two parallel and unrelated derivation paths for the session key and authentication tag. This design is particularly vulnerable in the actual operating environment of edge devices. For example, when the SoC chip is struck by high-energy particles such as cosmic rays, it is highly susceptible to single-event upsets in its internal RAM or registers. If this effect happens to occur in the register that temporarily stores the high 128 bits of data (i.e., the session key portion), it will lead to key data corruption. However, because the lower 128 bits of data (the verification tag portion) are unaffected, the SoC will still send out this incorrect key along with the correct tag. Upon receiving the correct verification tag, the edge gateway will mistakenly interpret the device authentication as successful, thus establishing a secure channel based on the corrupted key. All subsequent encrypted communications based on this key will fail, leading to service interruption and making troubleshooting extremely difficult. Furthermore, this static physical truncation also creates vulnerabilities for side-channel attacks, particularly power analysis attacks. Since the verification tag is transmitted as public data, attackers can easily obtain it. Given that it originates from the adjacent output block of the same hash operation as the session key, its internal state has a cryptographic correlation. Attackers may analyze the device's power consumption curve during the generation and processing of this public tag to deduce some intermediate states of the hash operation, significantly reducing the effective search space for the confidential session key and lowering key security. Simultaneously, this mechanism also suffers from insufficient entropy utilization. The generation of the session key relies only on the first half of the hash digest, completely ignoring the entropy information contained in the second half. This violates the principle of maximizing the avalanche effect in cryptography, failing to ensure that any small change in the input digest will cause a global, unpredictable change in the output key, i.e., it lacks sufficient forward diffusion.

[0030] To overcome the aforementioned shortcomings, a cross-feedback avalanche linkage derivation mechanism is proposed in a preferred embodiment of this solution. This mechanism, by introducing global dependency and directed dependency chains, forces a cryptographically entangled relationship of integrity between the session key and the authentication label. Specifically, in the technical solution of this application, the session key and authentication label are further derived based on the authentication digest hash value to obtain the current session key and authentication label. This introduces a global entropy orthogonal decomposition and cross-feedback avalanche linkage mechanism, forcibly constructing a unidirectional dependency chain of public label to private key integrity. This ensures that any hardware bit errors during the key generation process will inevitably propagate to the authentication label through the feedback path, enabling the gateway to immediately identify and reject authentication requests with corrupted keys, while significantly enhancing its resistance to differential power analysis attacks.

[0031] Figure 4 This is a flowchart illustrating the process of deriving the current session key and authentication label from the session key and verification label based on the authentication digest hash value in the edge security access authentication method for IoT devices based on a domestically developed SoC, according to an embodiment of this application. Figure 4 As shown, step S500 includes: S510, performing orthogonal decomposition of the global entropy value on the authentication digest hash value to obtain a high-order entropy vector and a low-order entropy vector; S520, generating a session key by introducing forward diffusion on the high-order entropy vector and the low-order entropy vector to obtain a current session key; S530, projecting a verification label based on key feedback onto the current session key and the low-order entropy vector to obtain an identity authentication label.

[0032] Accordingly, in step S510, the authentication digest hash value is orthogonally decomposed using global entropy values ​​to obtain a high-order entropy vector and a low-order entropy vector. It should be understood that in resource-constrained edge authentication scenarios for domestically developed SoCs, traditional key derivation methods often directly employ static physical truncation. This approach not only results in a lack of deep cryptographic connection between the session key and the verification tag, but also makes the system highly susceptible to single-event flip attacks, leading to the establishment of incorrect trust channels due to high-order register data corruption. Furthermore, because it does not fully utilize global entropy values, it cannot effectively resist differential power analysis. Therefore, in the technical solution of this application, the authentication digest hash value is orthogonally decomposed using global entropy values ​​to obtain a high-order entropy vector and a low-order entropy vector, thereby replacing simple physical segmentation. This logically reconstructs the single linear digest stream into two orthogonal components that are both independent and mutually computationally based. This breaks the static storage structure of the original data, laying the necessary data foundation for the subsequent construction of a cross-feedback-based avalanche linkage mechanism, ensuring that each bit of the generated key is associated with the full digest information.

[0033] Specifically, in one example of this application, the processing unit performs a logical entropy extraction operation, rather than a simple bit-field segmentation. The system first reads the complete 256-bit authentication digest hash value temporarily stored in the register. Based on a predefined orthogonal decomposition rule, it extracts and locks the high 128 bits of the data segment into a high-entropy vector with high entropy properties, serving as the primary entropy source for subsequent key generation. Simultaneously, it maps the low 128 bits of the data segment into a low-entropy vector, serving as a feedback factor for subsequently introducing nonlinear perturbations. The specific formula for this execution process is defined as follows: in, It is a high-order entropy vector, which carries the entropy information of the first half of the original summary; It is a low-order entropy vector, which carries the entropy information of the latter half of the original summary; and These represent the truncation functions for the high 128 bits and the low 128 bits, respectively. The input is a 256-bit authentication digest hash value. The physical significance of the above process lies not only in the dimensionality split, but also in the construction of two independent operators capable of algebraic interaction. This orthogonal decomposition is the mathematical prerequisite for realizing an avalanche linkage mechanism based on cross-feedback. By decomposing the original hash value into... and The system enables subsequent steps (i.e., the XOR and shift operations during key generation) to utilize... right Dynamic pollution is applied, ensuring that the final generated session key no longer depends solely on the high-order bits of the hash value, but rather on a complex function of the global hash value. This approach effectively extends the avalanche effect of the original SM3 digest to the key derivation stage. Even if an attacker obtains a portion of the data (such as publicly available tags), they cannot deduce the key due to the lack of complete state information for the remaining portion. This significantly improves the anti-interference capability of domestically produced SoCs in harsh electromagnetic environments and the confidentiality of core data.

[0034] Accordingly, in step S520, a forward-diffusion-based session key generation is performed on the high-bit entropy vector and the low-bit entropy vector to obtain the current session key. It should be understood that because the simple truncated key generation strategy only utilizes the entropy value of the first half of the hash digest, completely ignoring the randomness information contained in the second half, the generated session key lacks sufficient forward diffusion. That is, small changes in the input digest cannot cause global unpredictable fluctuations in the key space. This allows attackers to significantly reduce the key search space if they obtain high-bit data features through side-channel analysis. Therefore, in the technical solution of this application, a forward-diffusion-based session key generation is further performed on the high-bit entropy vector and the low-bit entropy vector to obtain the current session key, thereby utilizing the randomness of the low-bit data to nonlinearly and dynamically perturb the high-bit data. This establishes a global dependency of the session key on the original 256-bit hash digest, ensuring that the final generated key actually contains all the entropy information of the original digest, significantly enhancing the key's avalanche effect and resistance to side-channel attacks.

[0035] Specifically, in one example of this application, the processing unit executes a lightweight yet efficient hybrid operation logic designed to maximize bit spread with minimal computational overhead. The system uses the low-entropy vector obtained in the preceding steps as a perturbation source and performs a cyclic left shift operation on it by a specific number of bits. The specific shift amount is preferably a prime number (e.g., 31 bits). This operation aims to actively disrupt the byte alignment characteristics of data in memory, allowing bit flips that originally only affected local bytes to spread non-linearly across byte boundaries. Subsequently, the shifted vector is XORed with the high-entropy vector, thereby irreversibly superimposing the low-entropy information into the high-entropy vector. This calculation process is defined by the following formula: in, The current session key; It is a high-order entropy vector; It is a low-order entropy vector; This represents a bitwise operation that circularly shifts left by 31 bits. This is a bitwise XOR operation. It is achieved by introducing... This transformation term, which involves prime number shifts, enforces the final... Each one no longer simply depends on The original state, but all were affected Dynamic modulation of data. This design ensures that even if an attacker can precisely observe the physical state of the high 128 bits of the hash digest, they will be unable to predict the final session key due to the lack of complexly transformed low 128 bits of interference information. Thus, in an environment where domestic SoC resources are limited, it achieves a confusion and diffusion effect similar to that in advanced block cipher algorithms with extremely low instruction cycle overhead.

[0036] Accordingly, in step S530, a verification tag projection based on key feedback is performed on the current session key and the low-entropy vector to obtain an authentication tag. It should be understood that, in traditional parallel structures, there is no direct arithmetic relationship between the public authentication tag and the confidential session key. This means that when a domestic SoC is exposed to high-energy particle radiation or suffers a fault injection attack, if only the register storing the key is damaged without affecting the tag generation logic, the device will still send a legitimate tag, inducing the gateway to establish an immediately invalid encrypted channel. This passive response mechanism, where survival is key, cannot actively detect runtime errors in the key. Therefore, in the technical solution of this application, a verification tag projection based on key feedback is further performed on the current session key and the low-entropy vector to obtain an authentication tag. This forces the construction of a directed dependency chain from the private key to the public tag at the algorithm level, strictly defining the tag generation logic as a function of the key state. In this way, any bit-level error in the session key can be irreversibly projected onto the authentication tag through the feedback path, so that the publicly transmitted tag itself carries a zero-knowledge proof of key integrity. Thus, without increasing the number of handshake interactions, the gateway's verification of the tag enables remote integrity confirmation of the key status on the device side.

[0037] Specifically, in one particular example of this application, the processing unit performs a projection operation with timing-locked characteristics. The system must, after confirming that the current session key has been calculated and latched, call it back to the processing unit as the sole feedback input source. To eliminate the direct linear correspondence between the key and the tag in the bit structure to prevent reverse analysis, the processor first performs a circular right shift operation (e.g., right shift by 17 bits) on the key for permutation, and then performs a bitwise XOR operation with the original low-entropy vector to synthesize the final authentication tag. This calculation process is defined by the following formula: in, The authentication label is sent to the gateway as a public credential. It is a low-bit entropy vector, used as the basic mask; The current session key is used as feedback input; This represents a bitwise operation that performs a circular right shift of 17 bits. This is a bitwise XOR operation. At the physical level, this step mandates that the SoC must adhere to a strict computational order: "the current session key must be calculated correctly before the correct authentication tag can be calculated." This feedback-based construction method effectively establishes a closed-loop control system at the cryptographic level. Any faults introduced during key generation (such as bit errors caused by single-event flips) or side-channel probing interference are fed back as error signals. In the calculation, the correct key is transformed into a necessary and sufficient condition for the correct tag. This allows the gateway to be mathematically certain, once the tag is verified, that the device not only possesses legitimate root trust but also that the currently generated session key is complete and error-free, thus completely blocking the risk of invalid connections based on faulty keys.

[0038] Through the technical means implemented in the above preferred embodiments, this mechanism achieves the following technical effects and objectives. First, it completely solves the problem of authentication still succeeding despite key corruption caused by hardware failures such as single-event upsets. Upon receiving an incorrect verification tag, the gateway directly rejects the authentication request, thereby avoiding the establishment of an invalid secure channel and ensuring the reliability of subsequent business communications. Second, through the global information diffusion during key generation and key feedback during tag generation, this mechanism greatly enhances immunity to side-channel attacks and protects the confidentiality of session keys. Finally, without increasing additional hardware costs, this mechanism, through pure data and algorithmic innovation, provides a more robust and secure security access authentication solution for domestically developed SoCs in harsh IoT edge environments, achieving self-verification of the authentication process's integrity.

[0039] Specifically, in step S600, the authentication tag is encapsulated into a device response protocol message, and the device response protocol message is sent back to the edge gateway through the physical layer interface. It should be understood that since the identity calculation on the edge side only completes unilateral self-verification, if the generated credentials are not fed back to the control end using a standardized communication protocol, the gateway cannot perceive the device's legitimacy. Furthermore, if the session key generated in the previous step is not immediately put into practical application, its validity and availability cannot be proven to the gateway. Therefore, in the technical solution of this application, the authentication tag is further encapsulated into a device response protocol message, and the device response protocol message is sent back to the edge gateway through the physical layer interface. This completes the closed-loop response of the authentication interaction protocol, transforming the cryptographic credentials calculated internally by the SoC into a network-transmittable protocol payload. In this way, the edge gateway can confirm the device's identity based on the received tag and successfully decrypt the accompanying service data using the synchronously negotiated key, thereby simultaneously completing identity authentication and secure channel establishment in a single handshake interaction.

[0040] More specifically, in this embodiment of the application, the identity authentication tag is encapsulated into a device response protocol message, and the device response protocol message is sent back to the edge gateway through the physical layer interface. This includes: formatting the identity authentication tag with authentication credentials to obtain a formatted identity credential segment; encrypting the formatted identity credential segment with business data and concatenating it with a security payload to obtain an application layer response payload; and encapsulating the application layer response payload with a complete protocol stack and physically sending it to obtain a security authentication response message.

[0041] Specifically, in a concrete example of this application, the message construction and transmission process follows a layered encapsulation principle. The processor first calls the construction function of the application layer protocol stack, writing the authentication tag calculated in the previous steps into the dedicated authentication field of the protocol header according to the big-endian network byte order, and setting the response flag to generate a formatted identity credential segment conforming to the communication interface specification. Subsequently, the system uses the newly generated current session key to drive the AES hardware encryption engine, performing symmetric encryption on the device's current sensor readings or status information, and tightly concatenating the output ciphertext data block after the formatted identity credential segment. This method of combining plaintext tags to guide ciphertext data constructs a complete application layer response payload. Finally, the network protocol stack core, following the OSI model from top to bottom, adds transport layer port information, network layer IP routing information, and data link layer MAC frame headers to the application layer response payload. After calculating and filling the frame check sequence, the finally encapsulated security authentication response message is modulated into an electrical signal and transmitted to the transmission medium via a radio frequency or wired physical layer interface for capture and verification by the edge gateway.

[0042] In summary, the edge security access authentication method for IoT devices based on domestically developed SoCs, as described in the embodiments of this application, is explained. It utilizes the SRAM physical fingerprint generated upon chip power-up to reconstruct the root key in real time, completely eliminating the static storage of the private key and fundamentally preventing the risk of physical cloning. Based on this, the scheme deeply binds the root key to the gateway challenge using the SM3 algorithm and employs a cross-feedback avalanche linkage mechanism for key derivation. This mechanism enforces a one-way dependency of the verification tag on the integrity of the session key, ensuring that any key error caused by hardware failures such as single-event upsets will inevitably lead to tag verification failure. Thus, without additional hardware costs, it effectively blocks the establishment of invalid security channels, achieving secure access for edge devices with self-immunity.

[0043] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for edge security access authentication of IoT devices based on domestically produced SoC, characterized in that, include: In response to the domestic SoC receiving the power-on reset signal, the original value of the SRAM physical fingerprint is obtained; The device root key is reconstructed from the original value of the SRAM physical fingerprint and the stored auxiliary error correction data. The domestically developed SoC parses authentication request packets from the edge gateway to obtain a gateway challenge random number; Perform an SM3 hash operation on the gateway challenge random number and the device root key to obtain the authentication digest hash value; The session key and authentication label are derived from the authentication digest hash value to obtain the current session key and authentication label. The authentication tag is encapsulated in the device response protocol message and sent back to the edge gateway through the physical layer interface.

2. The IoT device edge security access authentication method based on domestically produced SoC according to claim 1, characterized in that, In response to the domestic SoC receiving a power-on reset signal, the original SRAM physical fingerprint value is obtained, including: In response to the domestic SoC receiving the power-on reset signal, it actively shuts down all unnecessary peripheral clocks except for the SRAM controller and CPU core domain and masks global interrupts to obtain the environment ready flag. After the environment ready flag is detected as valid, the SRAM array is traversed and read to obtain the original SRAM word sequence; The original SRAM word sequence is serialized and constructed into a binary vector to obtain the original value of the SRAM physical fingerprint.

3. The IoT device edge security access authentication method based on domestically produced SoC according to claim 1, characterized in that, The device root key is reconstructed from the original SRAM physical fingerprint value and the stored auxiliary error correction data, including: Noisy codeword vectors are constructed and aligned from the original value of the SRAM physical fingerprint and the stored auxiliary error correction data. Perform BCH / RS error correction decoding on the noisy codeword vector to obtain the error-corrected codeword vector; The device root key is obtained by entropy extraction and root key generation from the error-corrected codeword vector.

4. The IoT device edge security access authentication method based on domestically produced SoC according to claim 1, characterized in that, The domestically developed SoC parses authentication request packets from the edge gateway to obtain a gateway challenge random number, including: The authentication request data packet is subjected to communication protocol integrity verification and unpacking to obtain the application layer protocol payload; Challenge fields are located and parsed in the application layer protocol payload to obtain the original random number data segment; Data extraction and byte sequence standardization are performed on the original random number data segment to obtain gateway challenge random numbers.

5. The IoT device edge security access authentication method based on domestically produced SoC according to claim 1, characterized in that, Perform an SM3 hash operation on the gateway challenge random number and the device root key to obtain the authentication digest hash value, including: The gateway challenge random number and the device root key are concatenated to obtain the concatenated message sequence; The spliced ​​message sequence is scheduled and compressed using the SM3 hardware acceleration engine to obtain the hash operation completion signal; The hash result of the hash operation is extracted and the register is read back to obtain the authentication digest hash value.

6. The IoT device edge security access authentication method based on domestically produced SoC according to claim 1, characterized in that, The session key and authentication tag are derived from the authentication digest hash value to obtain the current session key and authentication tag, including: The authentication digest hash value is orthogonally decomposed into high-bit entropy vector and low-bit entropy vector by the global entropy value. The current session key is obtained by introducing forward diffusion into the high-bit entropy vector and the low-bit entropy vector; An authentication label is obtained by projecting the current session key and low-entropy vector onto the verification label based on key feedback.

7. The IoT device edge security access authentication method based on domestically produced SoC according to claim 1, characterized in that, The authentication tag is encapsulated in the device response protocol message and sent back to the edge gateway through the physical layer interface, including: The authentication credentials of the identity authentication tag are formatted according to the protocol to obtain a formatted identity credential segment; The formatted identity credential segment is encrypted with business data and concatenated with a security payload to obtain the application layer response payload. The application layer response payload is fully encapsulated in the protocol stack and physically transmitted to obtain a security authentication response message.

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