Tspc type d flip-flop against single event upsets and single event transients

Abstract

The application discloses a TSPC type D flip-flop resistant to single event upset and single event transient, comprising: a first stage of reverse logic, a second stage of reverse logic, a first stage of shadow reverse logic, a second stage of shadow reverse logic, and a third stage of reverse logic, which are controlled by a clock signal CLK; a delay unit inputs an input data signal D after delay to generate a signal S in the first stage of shadow reverse logic; the first stage of reverse logic generates MS1 under the control of the clock signal CLK; the second stage of reverse logic generates a signal MS2 under the control of the clock signal CLK; the first stage of shadow reverse logic generates a signal SS1 under the control of the clock signal CLK; the second stage of shadow reverse logic generates a signal SS2 under the control of the clock signal CLK; the third stage of reverse logic generates a signal FS under the control of the clock signal CLK; and a fourth stage of reverse logic generates an output signal Q after reversing the signal FS. The TSPC type D flip-flop designed in the application has the ability of resisting single event upset and single event transient, and is suitable for high-reliability application scenarios.

Description

Technical Field

[0001] This invention belongs to the field of D flip-flops, specifically a TSPC (True Single Phase Clock) type D flip-flop that is resistant to single-event flips and single-event transients. Background Technology

[0002] The continuous advancement of manufacturing technology has led to a continuous reduction in the size of integrated circuit transistors, making it easier for radiation effects to introduce soft errors into integrated circuits. This is mainly due to the continuous reduction in the node capacitance of transistors, which in turn leads to a continuous reduction in the critical charge. When radiated particles interact with the atoms of the materials constituting the device, they release a large number of electron-hole pairs, causing changes in the node potential of the device, ultimately resulting in Single Event Upset (SEU) and Single Event Transient (SET).

[0003] Flip-flops are key storage elements in digital integrated systems, occupying a significant proportion of the chip area. Furthermore, their power consumption is a crucial component of the overall system power consumption. Therefore, flip-flop design plays a vital role when considering both power consumption and performance. Master-slave flip-flops widely employ transmission gate designs, requiring bidirectional clocks. TSPC flip-flops successfully overcome this drawback, eliminating the need for complementary clocks and thus reducing power consumption. Consequently, TSPC flip-flops are essential in the design of high-speed, high-performance integrated circuits. However, traditional TSPC D flip-flops lack resistance to single-event upsets and transient events, making them unsuitable for high-reliability systems. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by proposing a TSPC type D flip-flop that is resistant to single-event upsets and single-event transients, thus solving the reliability problem that traditional TSPC type D flip-flops cannot simultaneously resist single-event upsets and single-event transients. The present invention can be applied to the design of high-reliability integrated circuit chips.

[0005] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0006] A TSPC-type D flip-flop resistant to single-event upsets and single-event transients includes: a first-stage inverting logic unit, a second-stage inverting logic unit, a third-stage inverting logic unit, and a fourth-stage inverting logic unit connected in sequence; a delay unit, a first-stage shadow inverting logic unit, and a second-stage shadow inverting logic unit connected in sequence; the second-stage shadow inverting logic unit being connected to the third-stage inverting logic unit; the first-stage inverting logic unit, the second-stage inverting logic unit, the third-stage inverting logic unit, the first-stage shadow inverting logic unit, and the second-stage shadow inverting logic unit being controlled by the same clock signal CLK; and the inputs of the first-stage inverting logic unit and the delay unit being the same input data signal D.

[0007] The delay unit includes:

[0008] The gate and drain of PMOS transistor P1, the gate of PMOS transistor P2, the gate and drain of NMOS transistor N1, and the gate of NMOS transistor N2 are connected together as the input terminal of the delay unit, receiving the input data signal D. The source of PMOS transistor P1, the gate of PMOS transistor P3, the source of NMOS transistor N1, and the gate of NMOS transistor N3 are connected together. The source of PMOS transistor P2 is connected to the power supply VDD, the drain of PMOS transistor P2 is connected to the source of PMOS transistor P3, and the source of NMOS transistor N2 is grounded. The drain of transistor N2 is connected to the source of NMOS transistor N3, and the drain of NMOS transistor N2 is connected to the source of NMOS transistor N3. The source of NMOS transistor N2 is grounded. The drain of PMOS transistor P3, the gate of PMOS transistor P4, the drain of NMOS transistor N3, and the gate of NMOS transistor N4 are connected. The source of PMOS transistor P4 is connected to the power supply VDD, the source of NMOS transistor N4 is grounded, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4. This serves as the output terminal of the delay unit, outputting the signal S.

[0009] The first-level inverse logic unit includes:

[0010] The gate of PMOS transistor P5 is connected to the gate of NMOS transistor N5, serving as the input terminal of the first-stage inverting logic unit, receiving the input data signal D. The source of PMOS transistor P5 is connected to the power supply VDD, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6. The gate of PMOS transistor P6 serves as the clock input terminal of the first-stage inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N5 is grounded, and the drain of PMOS transistor P6 is connected to the drain of NMOS transistor N5, serving as the output terminal of the first-stage inverting logic unit, outputting the signal MS1.

[0011] The second-level inverse logic unit includes:

[0012] The gate of NMOS transistor N7 serves as the input of the second-stage inverting logic unit, receiving signal MS1. The drain of NMOS transistor N7 is connected to the drain of PMOS transistor P7, and the source of PMOS transistor P7 is connected to the power supply VDD. The gates of PMOS transistor P7 and NMOS transistor N6 together serve as the clock input of the second-stage inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N6 is grounded, and the source of NMOS transistor N7 is connected to the drain of NMOS transistor N6, serving as the output of the second-stage inverting logic unit, outputting signal MS2.

[0013] The first-level shadow inversion logic unit includes:

[0014] The gate of PMOS transistor P8 is connected to the gate of NMOS transistor N8, serving as the input terminal of the first-stage shadow inverting logic unit, receiving the input data signal S. The source of PMOS transistor P8 is connected to the power supply VDD, and the drain of PMOS transistor P8 is connected to the source of PMOS transistor P9. The gate of PMOS transistor P9 serves as the clock input terminal of the first-stage shadow inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N8 is grounded, and the drain of PMOS transistor P9 is connected to the drain of NMOS transistor N8, serving as the output terminal of the first-stage shadow inverting logic unit, outputting the signal SS1.

[0015] The second-level shadow inversion logic unit includes:

[0016] The gate of NMOS transistor N9 serves as the input of the second-stage shadow inverting logic unit, receiving signal SS1. The drain of NMOS transistor N9 is connected to the drain of PMOS transistor P9, and the source of PMOS transistor P9 is connected to the power supply VDD. The gates of PMOS transistor P9 and NMOS transistor N8 together serve as the clock input of the second-stage shadow inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N8 is grounded, and the source of NMOS transistor N9 is connected to the drain of NMOS transistor N8, serving as the output of the second-stage shadow inverting logic unit, outputting signal SS2.

[0017] The third-level inverse logic unit includes:

[0018] The gate of PMOS transistor P10 is connected to the gate of NMOS transistor N10, serving as the first input of the third-stage inverting logic unit, receiving signal MS2. The gate of PMOS transistor P11 is connected to the gate of NMOS transistor N11, serving as the second input of the third-stage inverting logic unit, receiving signal SS2. The gate of NMOS transistor N12 serves as the clock input of the third-stage inverting logic unit, receiving clock signal CLK. The source of PMOS transistor P10 is connected to power supply VDD. The drain of PMOS transistor P10 is connected to the source of PMOS transistor P11. The drain of PMOS transistor P11 is connected to the drain of NMOS transistor N12, serving as the output of the third-stage inverting logic unit, outputting signal FS. The source of NMOS transistor N12 is connected to the drain of NMOS transistor N11. The source of NMOS transistor N11 is connected to the drain of NMOS transistor N10. The source of NMOS transistor N10 is grounded.

[0019] The fourth-level inverse logic unit includes:

[0020] The gate of PMOS transistor P12 is connected to the gate of NMOS transistor N13, serving as the input terminal of the fourth-stage inverting logic unit to receive the signal FS. The source of PMOS transistor P12 is connected to the power supply VDD, and the drain of PMOS transistor P12 is connected to the drain of NMOS transistor N13, serving as the output terminal of the fourth-stage inverting logic unit to output the signal Q. The source of NMOS transistor N13 is grounded.

[0021] The present invention has the following beneficial effects and advantages:

[0022] 1. The present invention provides a TSPC-type D flip-flop that resists single-event upsets and single-event transients. When the data input signal D is affected by a single-event transient, resulting in glitches or ripples, the data input terminal is connected to the first-stage inverting logic, the second-stage inverting logic, the first-stage shadow inverting logic, the second-stage shadow inverting logic, and the delay unit, respectively. The data then passes through the third-stage inverting logic controlled by the clock signal CLK. When the two input signals of the third-stage inverting logic are different, the output signal remains unchanged, thereby suppressing the single-event transient.

[0023] 2. The present invention provides a TSPC type D flip-flop that is resistant to single-event upsets and single-event transients. When a single-event upset occurs in the sensitive node inside the D flip-flop, the output logic level will not be affected by the single-event upset due to the existence of the shadow reverse logic path, thus maintaining the original output value unchanged. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall logical structure of the present invention;

[0025] Figure 2 This is a schematic diagram of the delay unit in this invention;

[0026] Figure 3 This is a schematic diagram of the first-stage inverting logic circuit in this invention;

[0027] Figure 4 This is a schematic diagram of the second-stage inverting logic circuit in this invention;

[0028] Figure 5 This is a schematic diagram of the first-stage shadow inverting logic circuit in this invention;

[0029] Figure 6 This is a schematic diagram of the second-stage shadow inverting logic circuit in this invention;

[0030] Figure 7 This is a schematic diagram of the third-stage inverting logic circuit in this invention;

[0031] Figure 8 This is a schematic diagram of the fourth-stage inverting logic circuit in this invention;

[0032] Figure 9 A schematic diagram of the SEU fault injection simulation results for a standard TSPC type D trigger that does not have resistance to single-event upsets and single-event transients.

[0033] Figure 10 This is a schematic diagram of the SEU fault injection simulation results of the TSPC type D trigger that resists single-event upsets and single-event transients of the present invention.

[0034] Figure 11 A schematic diagram of the simulation results for SET fault injection at the data terminal of a standard TSPC type D flip-flop that does not have resistance to single-event upsets and single-event transients;

[0035] Figure 12 This is a schematic diagram of the simulation results of the SET fault injection at the data terminal of the TSPC type D trigger that resists single-event upsets and single-event transients according to the present invention. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0037] Figure 1 This is a schematic diagram of the overall logic structure of the TSPC type D flip-flop that resists single-event upsets and single-event transients according to the present invention. The present invention consists of delay units (such as...) Figure 2 As shown), the first inverse logic (such as...) Figure 3 As shown), the second inverse logic (as shown) Figure 4 As shown), the first shadow reverse logic (such as...) Figure 5 As shown), the second shadow direction logic (such as...) Figure 6 As shown), the third inverse logic (such as...) Figure 7 (as shown), fourth inverse logic (as shown) Figure 8The system consists of four stages (shown in the diagram). The first-stage inverting logic, second-stage inverting logic, first-stage shadow inverting logic, second-stage shadow inverting logic, and third-stage inverting logic are all controlled by the clock signal CLK. The delay unit delays the input data signal D and inputs it to the first-stage shadow inverting logic to generate signal S. The first-stage inverting logic generates MS1 under the control of the clock signal CLK, the second-stage inverting logic generates signal MS2 under the control of the clock signal CLK, the first-stage shadow inverting logic generates signal SS1 under the control of the clock signal CLK, the second-stage shadow inverting logic generates signal SS2 under the control of the clock signal CLK, the third-stage inverting logic generates signal FS under the control of the clock signal CLK, and the fourth-stage inverting logic inverts signal FS to generate the output signal Q.

[0038] This invention relates to a TSPC-type D flip-flop resistant to single-event upsets and single-event transients. It has two inputs and one output. The two inputs are a clock signal input (CLK) and a data signal input (D); the output is Q. The clock signal CLK controls the first inverting logic, the second inverting logic, the first shadow inverting logic, the second shadow inverting logic, and the third inverting logic. The data signal D is input to the delay unit and the first inverting logic. When a single-event transient occurs at the flip-flop's data input D or a single-event upset occurs in the internal storage node, the dual-mode redundancy structure composed of the first inverting logic, the second inverting logic link, the delay unit, the first shadow inverting logic, and the second shadow inverting logic link can shield the propagation of error pulses to the output node, maintaining output stability.

[0039] like Figure 2As shown, the delay unit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg1 and drain Pd1 of the first PMOS transistor are connected to the input signal D, and the source Ps1 is connected to the source Ns1 of the first NMOS transistor and the third PMOS transistor. The gate of the first PMOS transistor is Pg3, and the gate of the third NMOS transistor is Ng3; the gate of the second PMOS transistor is Pg2, which is connected to the input signal D, and its drain is Pd2, which is connected to the source of the third PMOS transistor, Ps3, which is connected to the power supply VDD; the gate of the third PMOS transistor is Pg3, which is connected to the source of the first PMOS transistor, the source of the first NMOS transistor, Ns1, and the gate of the third NMOS transistor, Ps3, which is connected to the drain of the second PMOS transistor, Pd2; the gate of the fourth PMOS transistor is Pg4, which is connected to the drain of the third PMOS transistor. d3, the drain Nd3 of the third NMOS transistor and the gate Ng4 of the fourth NMOS transistor, the source Ps4 are connected to the power supply VDD, and the drain Pd4 is connected to the drain Nd4 of the fourth NMOS transistor; the gate Ng1 and drain Nd1 of the first NMOS transistor are connected to the input signal D, and the source Ns1 is connected to the source Ps1 of the first PMOS transistor, the gate Pg3 of the third PMOS transistor, and the gate Ng3 of the third NMOS transistor; the gate Ng2 of the second NMOS transistor is connected to the input signal D, and the drain Pd2 is connected to the source Ns3 of the third NMOS transistor. The source Ns2 is connected to ground VSS; the gate Ng3 of the third NMOS transistor is connected to the source Ps1 of the first PMOS transistor, the source Ns1 of the first NMOS transistor, and the gate Pg3 of the third PMOS transistor, and the source Ns3 is connected to the drain Nd2 of the second NMOS transistor; the gate Ng4 of the fourth NMOS transistor is connected to the drain Pd3 of the third PMOS transistor, the drain Nd3 of the third NMOS transistor, and the gate Pg4 of the fourth PMOS transistor, the source Ns4 is connected to ground VSS, and the drain Nd4 is connected to the drain Pd4 of the fourth PMOS transistor.

[0040] like Figure 3As shown, the first-stage inverting logic includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a fifth NMOS transistor N5. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg5 of the fifth PMOS transistor is connected to the gate Ng5 of the fifth NMOS transistor and the input data signal D. The drain Pd5 of the fifth PMOS transistor is connected to the source Ps6 of the sixth PMOS transistor, and the source Ps5 of the fifth PMOS transistor is connected to the power supply VDD. The gate Pg6 of the sixth PMOS transistor is connected to the clock signal CLK, and its drain Pd6 is connected to the drain Nd5 of the fifth NMOS transistor. Its source Ps6 is connected to the drain Pd5 of the fifth PMOS transistor. The gate Ng5 of the fifth NMOS transistor is connected to the gate Pg5 of the fifth PMOS transistor, its drain Nd5 is connected to the drain Pd6 of the sixth PMOS transistor, and its source Ns5 is connected to ground VSS.

[0041] like Figure 4 As shown, the second-stage inverting logic includes a seventh PMOS transistor P7, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg7 of the seventh PMOS transistor is connected to the clock signal CLK, the drain Pd7 of the seventh PMOS transistor is connected to the drain Pd6 of the seventh NMOS transistor, and the source Ps7 of the seventh PMOS transistor is connected to the power supply VDD. The gate Ng6 of the sixth NMOS transistor is connected to the clock signal CLK, the drain Nd6 is connected to the source Ns5 of the seventh NMOS transistor, and the source Ns6 is connected to the source Ns5 of the seventh NMOS transistor. The gate Ng7 of the seventh NMOS transistor is connected to the output signal MS1 of the first inverting logic, the drain Nd7 is connected to the drain Pd7 of the seventh PMOS transistor, and the source Ns75 is connected to the drain Nd6 of the sixth NMOS transistor.

[0042] like Figure 5 As shown, the first-stage shadow inversion logic includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, and an eighth NMOS transistor N8. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg8 of the eighth PMOS transistor is connected to the gate Ng8 of the eighth NMOS transistor and the output signal S of the delay unit. The drain Pd8 of the eighth PMOS transistor is connected to the source Ps9 of the ninth PMOS transistor, and the source Ps8 of the eighth PMOS transistor is connected to the power supply VDD. The gate Pg9 of the ninth PMOS transistor is connected to the clock signal CLK, the drain Pd9 is connected to the drain Nd8 of the eighth NMOS transistor, and the source Ps9 is connected to the drain Pd8 of the eighth PMOS transistor. The gate Ng8 of the eighth NMOS transistor is connected to the gate Pg8 of the eighth PMOS transistor, the drain Nd8 is connected to the drain Pd9 of the ninth PMOS transistor, and the source Ns8 is connected to ground VSS.

[0043] like Figure 6 As shown, the second-stage shadow inversion logic includes a ninth PMOS transistor P9, an eighth NMOS transistor N8, and a ninth NMOS transistor N9. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg9 of the ninth PMOS transistor is connected to the clock signal CLK, the drain Pd9 of the ninth PMOS transistor is connected to the drain Pd9 of the ninth NMOS transistor, and the source Ps9 of the ninth PMOS transistor is connected to the power supply VDD. The gate Ng8 of the eighth NMOS transistor is connected to the clock signal CLK, the drain Nd8 is connected to the source Ns9 of the ninth NMOS transistor, and the source Ns8 is connected to ground VSS. The gate Ng7 of the ninth NMOS transistor is connected to the output signal SS1 of the first-stage shadow inversion logic, the drain Nd9 is connected to the drain Pd9 of the ninth PMOS transistor, and the source Ns9 is connected to the drain Nd8 of the eighth NMOS transistor.

[0044] like Figure 7 As shown, the third-stage inverting logic includes the tenth PMOS transistor P10, the eleventh PMOS transistor P11, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, and the twelfth NMOS transistor N12. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg10 of the tenth PMOS transistor is connected to the gate Ng10 of the tenth NMOS transistor and the output signal MS2 of the second-stage inverting logic. The drain Pd10 is connected to the source Ps11 of the eleventh PMOS transistor, and the source Ps10 is connected to the power supply VDD. The gate Pg11 of the eleventh PMOS transistor is connected to the gate Ng11 of the eleventh NMOS transistor and the output signal SS2 of the second-stage shadow inverting logic. The drain Pd11 is connected to the... The drain Nd12 and source Ps11 of the 12th NMOS transistor are connected to the drain Pd10 of the 10th PMOS transistor; the gate Ng10 of the 10th NMOS transistor is connected to the gate Pg10 of the 10th PMOS transistor, the drain Nd10 is connected to the drain Nd11 of the 11th NMOS transistor, and the source is connected to ground VSS; the gate Ng11 of the 11th NMOS transistor is connected to the gate Pg11 of the 11th PMOS transistor, the drain Nd11 is connected to the source Ns12 of the 12th NMOS transistor, and the source Ns11 is connected to the drain Nd10 of the 10th NMOS transistor; the gate Ng12 of the 12th NMOS transistor is connected to the clock signal CLK, the drain Nd12 is connected to the drain Pd11 of the 11th PMOS transistor, and the source Ns12 is connected to the drain Nd11 of the 11th NMOS transistor.

[0045] like Figure 8As shown, the fourth-stage inverting logic includes a twelfth PMOS transistor P12 and a thirteenth NMOS transistor N13. The gate Pg12 of the twelfth PMOS transistor is connected to the output signal FS of the third-stage inverting logic and the gate Ng13 of the thirteenth NMOS transistor. The drain Pd12 of the twelfth PMOS transistor is connected to the drain Nd13 of the thirteenth NMOS transistor, and the source Ps12 of the twelfth PMOS transistor is connected to the power supply VDD. The gate Ng13 of the thirteenth NMOS transistor is connected to the gate Pg12 of the twelfth PMOS transistor, the drain Nd13 is connected to the drain Pd12 of the twelfth PMOS transistor, and the source Ns13 is connected to ground VSS. In the fourth-stage inverting logic, the drains Pd12 of the twelfth PMOS transistor and Nd13 of the thirteenth NMOS transistor are connected as the output signal Q.

[0046] like Figure 9 As shown, a schematic diagram of the SEU fault injection simulation results for a standard TSPC-type D flip-flop without resistance to single-event upsets and single-event transients is presented. Fault injection is performed on the sensitive node inside the TSPC-type D flip-flop using a dual exponential current source. The pulse amplitude is set to 320 μA, the duration to 200 picoseconds, the rise time to 50 picoseconds, and the fall time to 150 picoseconds. Figure 9 As can be seen, under the influence of the fault pulse generated after the simulated particle bombardment, the output Q of the ordinary TSPC type D flip-flop, which does not have resistance to single-event upsets and single-event transients, produced an erroneous flip.

[0047] like Figure 10 As shown, the SEU fault injection simulation results of the TSPC type D flip-flop with resistance to single-event upsets and single-event transients proposed in this invention are presented. A fault injection is performed on the sensitive node MS1 inside the proposed D flip-flop using a radiation pulse with the same parameters as described above. Figure 10 As can be seen, the fault injection signal did not affect the output signal Q.

[0048] like Figure 11 As shown, a schematic diagram of the SET fault injection simulation results for a standard TSPC type D trigger without resistance to single-event upsets and single-event transients is presented. Fault injection is performed at the input data terminal D, and the transient pulse duration is set to 200 picoseconds. Figure 11 As can be seen, under the influence of the fault pulse generated at the simulated particle bombardment data terminal, the output Q of the ordinary TSPC type D flip-flop, which does not have resistance to single-event upsets and single-event transients, produced an erroneous flip.

[0049] like Figure 12As shown, simulation results of fault injection at the data terminal SET of the TSPC type D trigger with resistance to single-event upsets and single-event transients are presented. Fault injection is performed at the input data terminal D, and the transient pulse duration is set to 200 picoseconds. From Figure 12 As can be seen, the fault injection signal at the data input end did not affect the output signal Q.

Claims

1. A TSPC type D flip-flop resistant to single event upsets and single event transients, characterized in that, include: The system comprises a first-level inverting logic unit, a second-level inverting logic unit, a third-level inverting logic unit, and a fourth-level inverting logic unit connected in sequence. It also includes a delay unit, a first-level shadow inverting logic unit, and a second-level shadow inverting logic unit connected in sequence. The second-level shadow inverting logic unit is connected to the third-level inverting logic unit. The first-level inverting logic unit, the second-level inverting logic unit, the third-level inverting logic unit, the first-level shadow inverting logic unit, and the second-level shadow inverting logic unit are all controlled by the same clock signal CLK. The input of the first-level inverting logic unit and the delay unit is the same input data signal D. The first-level inverting logic unit and the first-level shadow inverting logic unit have the same structure. The second-level inverting logic unit and the second-level shadow inverting logic unit have the same structure. The delay unit includes: The gate and drain of PMOS transistor P1, the gate of PMOS transistor P2, the gate and drain of NMOS transistor N1, and the gate of NMOS transistor N2 are connected together as the input terminal of the delay unit, receiving the input data signal D. The source of PMOS transistor P1, the gate of PMOS transistor P3, the source of NMOS transistor N1, and the gate of NMOS transistor N3 are connected together. The source of PMOS transistor P2 is connected to the power supply VDD, the drain of PMOS transistor P2 is connected to the source of PMOS transistor P3, and the source of NMOS transistor N2 is grounded. The drain of transistor N2 is connected to the source of NMOS transistor N3, and the drain of NMOS transistor N2 is connected to the source of NMOS transistor N3. The source of NMOS transistor N2 is grounded. The drain of PMOS transistor P3, the gate of PMOS transistor P4, the drain of NMOS transistor N3, and the gate of NMOS transistor N4 are connected. The source of PMOS transistor P4 is connected to the power supply VDD, the source of NMOS transistor N4 is grounded, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4. This serves as the output terminal of the delay unit, outputting the signal S.

2. The TSPC type D flip-flop against single-event upsets and single-event transients of claim 1, wherein, The first-level inverse logic unit includes: The gate of PMOS transistor P5 is connected to the gate of NMOS transistor N5, serving as the input terminal of the first-stage inverting logic unit, receiving the input data signal D. The source of PMOS transistor P5 is connected to the power supply VDD, and the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6. The gate of PMOS transistor P6 serves as the clock input terminal of the first-stage inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N5 is grounded, and the drain of PMOS transistor P6 is connected to the drain of NMOS transistor N5, serving as the output terminal of the first-stage inverting logic unit, outputting the signal MS1.

3. The TSPC type D flip-flop against single-event upsets and single-event transients of claim 1, wherein, The second-level inverse logic unit includes: The gate of NMOS transistor N7 serves as the input of the second-stage inverting logic unit, receiving signal MS1. The drain of NMOS transistor N7 is connected to the drain of PMOS transistor P7, and the source of PMOS transistor P7 is connected to the power supply VDD. The gates of PMOS transistor P7 and NMOS transistor N6 together serve as the clock input of the second-stage inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N6 is grounded, and the source of NMOS transistor N7 is connected to the drain of NMOS transistor N6, serving as the output of the second-stage inverting logic unit, outputting signal MS2.

4. The TSPC type D flip-flop against single-event upsets and single-event transients of claim 1, wherein, The first-level shadow inversion logic unit includes: The gate of PMOS transistor P8 is connected to the gate of NMOS transistor N8, serving as the input terminal of the first-stage shadow inverting logic unit, receiving the input data signal S. The source of PMOS transistor P8 is connected to the power supply VDD, and the drain of PMOS transistor P8 is connected to the source of PMOS transistor P9. The gate of PMOS transistor P9 serves as the clock input terminal of the first-stage shadow inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N8 is grounded, and the drain of PMOS transistor P9 is connected to the drain of NMOS transistor N8, serving as the output terminal of the first-stage shadow inverting logic unit, outputting the signal SS1.

5. The TSPC type D flip-flop against single-event upsets and single-event transients of claim 1, wherein, The second-level shadow inversion logic unit includes: The gate of NMOS transistor N9 serves as the input of the second-stage shadow inverting logic unit, receiving signal SS1. The drain of NMOS transistor N9 is connected to the drain of PMOS transistor P9, and the source of PMOS transistor P9 is connected to the power supply VDD. The gates of PMOS transistor P9 and NMOS transistor N8 together serve as the clock input of the second-stage shadow inverting logic unit, receiving the clock signal CLK. The source of NMOS transistor N8 is grounded, and the source of NMOS transistor N9 is connected to the drain of NMOS transistor N8, serving as the output of the second-stage shadow inverting logic unit, outputting signal SS2.

6. The TSPC type D flip-flop against single-event upsets and single-event transients of claim 1, wherein, The third-level inverse logic unit includes: The gate of PMOS transistor P10 is connected to the gate of NMOS transistor N10, serving as the first input of the third-stage inverting logic unit, receiving signal MS2. The gate of PMOS transistor P11 is connected to the gate of NMOS transistor N11, serving as the second input of the third-stage inverting logic unit, receiving signal SS2. The gate of NMOS transistor N12 serves as the clock input of the third-stage inverting logic unit, receiving clock signal CLK. The source of PMOS transistor P10 is connected to power supply VDD. The drain of PMOS transistor P10 is connected to the source of PMOS transistor P11. The drain of PMOS transistor P11 is connected to the drain of NMOS transistor N12, serving as the output of the third-stage inverting logic unit, outputting signal FS. The source of NMOS transistor N12 is connected to the drain of NMOS transistor N11. The source of NMOS transistor N11 is connected to the drain of NMOS transistor N10. The source of NMOS transistor N10 is grounded.

7. The TSPC type D flip-flop against single-event upsets and single-event transients of claim 1, wherein, The fourth-level inverse logic unit includes: The gate of PMOS transistor P12 is connected to the gate of NMOS transistor N13, serving as the input terminal of the fourth-stage inverting logic unit to receive the signal FS. The source of PMOS transistor P12 is connected to the power supply VDD, and the drain of PMOS transistor P12 is connected to the drain of NMOS transistor N13, serving as the output terminal of the fourth-stage inverting logic unit to output the signal Q. The source of NMOS transistor N13 is grounded.

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