An anti-single event upset flip-flop circuit and flip-flop

Abstract

The application discloses an anti-single event upset flip-flop circuit and a flip-flop, wherein the flip-flop circuit comprises a logic input circuit, a first main-stage gate circuit, a second main-stage gate circuit, a first slave-stage gate circuit, a second slave-stage gate circuit, a main-stage latch, a slave-stage latch and at least one inverter in an existing circuit connection relationship. The application can solve the technical problem that the level of the prior art is flipped and cannot be recovered when a particle is incident on the circuit in a radiation environment.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to an anti-single-event flip-flop circuit and flip-flop. Background Technology

[0002] In a radiation environment, charged particles incident on a digital circuit chip will cause ionizing radiation. A certain number of electron-hole pairs will be generated around the trajectory of the particles. When enough electron-hole pairs are deposited along the incident direction of the particles, the current caused by the electron-hole pairs collected by the depletion layer will cause the drain level to flip, forming a single-event upset.

[0003] The level at a combinational logic cell recovers after a single-event flip ends. When an event flip occurs in a sequential logic cell (such as a flip-flop) or a memory array, the flip is locked due to the presence of internal feedback structures, and the level cannot be recovered, resulting in a change in the circuit level. Summary of the Invention

[0004] This application provides an anti-single-event upset trigger circuit and trigger, which solves the technical problem in the prior art where the circuit level flips and cannot be recovered when a particle is incident on the circuit in a radiation environment.

[0005] On one hand, this application provides a single-event upset (SOME)-resistant trigger circuit through one embodiment of the present application. The trigger circuit includes: a logic input circuit, a first master-level gate circuit, a second master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter, wherein:

[0006] The logic input circuit, the first master-level gate circuit, and the first slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the second master-level gate circuit, and the second slave-level gate circuit are connected in sequence. One end of the master-level latch is connected to the output of the first master-level gate circuit and the input of the first slave-level gate circuit. The other end of the master-level latch is connected to the output of the second master-level gate circuit and the input of the second slave-level gate circuit. The output of the first slave-level gate circuit is connected to one end of the slave-level latch, and the output of the second slave-level gate circuit is connected to the other end of the slave-level latch.

[0007] Optionally, the logic input circuit, the first master-level gate circuit, the master-level latch, the first slave-level gate circuit, and the slave-level latch form a first transmission channel, and the logic input circuit, the first inverter, the second master-level gate circuit, the master-level latch, the second slave-level gate circuit, and the slave-level latch form a second transmission channel; wherein:

[0008] The logic input circuit is used to provide input signals;

[0009] Both the first transmission channel and the second transmission channel are used to transmit the input signal.

[0010] Optionally, the at least one inverter further includes a second inverter and a third inverter, wherein the second inverter is connected to the output of the first slave gate circuit, and the third inverter is connected to the output of the second slave gate circuit.

[0011] Optionally, the master latch or the slave latch is a latch with a reinforced structure to prevent the level of the feedback structure of the trigger circuit from flipping and being locked (unrecoverable) when particles are incident in a radiation environment, thus causing a change in the output level of the trigger circuit.

[0012] Optionally, the reinforcement structure includes a first latch circuit and a second latch circuit connected in parallel, and either the first latch circuit or the second latch circuit includes a delay element.

[0013] Optionally, the first latch circuit includes a first delay element and a fourth inverter connected in series, and the second latch circuit includes a second delay element and a fifth inverter connected in series, wherein the first delay element and the second delay element, the fourth inverter and the fifth inverter are respectively staggered.

[0014] Optionally, the first latch circuit includes a fourth inverter, and the second latch circuit includes a first delay element and a fifth inverter connected in series, wherein the fourth inverter and the fifth inverter are configured in opposite directions.

[0015] Optionally, the first latch circuit includes a first delay element and a fourth inverter connected in series, and the second latch circuit includes a fifth inverter, wherein the fourth inverter and the fifth inverter are configured in opposite directions.

[0016] Optionally, the delay element includes a resistor and / or a capacitor.

[0017] On the other hand, this application provides a trigger through one embodiment of the present application, the trigger including the trigger circuit described above.

[0018] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: This application provides a trigger circuit, including a logic input circuit with a circuit connection relationship, a first master-level gate circuit, a second master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter. The master-level latch and the slave-level latch are used to harden the circuit against single-event upsets (SWEs), preventing changes in the circuit's output level due to SWEs, i.e., SWEs resistance. This effectively solves the technical problem in the prior art where the circuit level flips and cannot be recovered when particles are incident on the circuit in a radiation environment. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a non-hardened trigger circuit provided by existing technology.

[0021] Figure 2 This is a schematic diagram of a trigger circuit provided in an embodiment of this application.

[0022] Figure 3 This is a schematic diagram of the working principle of a trigger circuit provided in an embodiment of this application.

[0023] Figure 4 (a)- Figure 4 (c) is a schematic diagram of the structure of several gate control circuits provided in the embodiments of this application.

[0024] Figure 5 (a)- Figure 5 (c) is a schematic diagram of several latch reinforcement structures provided in the embodiments of this application.

[0025] Figure 6 (a)- Figure 6 (c) is a schematic diagram of the structure of several delay elements provided in the embodiments of this application.

[0026] Figure 7 (a)- Figure 7 (d) is a schematic diagram of the logic input structure of several flip-flops provided in the embodiments of this application.

[0027] Figure label:

[0028] 11-Logic input circuit; 131-First master-level gate circuit; 132-Second master-level gate circuit; 141-First slave-level gate circuit; 142-Second slave-level gate circuit; 151-Master-level latch; 152-Slave-level latch; 12-Inverter; 15-Latch structure; 13-Gate circuit; 34-Latch circuit; 16-Delay element; 1-First transistor; 2-Second transistor; 3-Third transistor; 4-Fourth transistor. Detailed Implementation

[0029] This application provides a trigger circuit and a trigger, which solves the technical problem in the prior art where the level flips and cannot be recovered when particles are incident on the circuit in a radiation environment.

[0030] The technical solution of this application embodiment is to solve the above-mentioned technical problems. The overall idea is as follows: This application provides a trigger circuit including: a logic input circuit, a first master-level gate circuit, a second master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter, wherein:

[0031] The logic input circuit, the first master-level gate circuit, and the first slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the second master-level gate circuit, and the second slave-level gate circuit are connected in sequence. One end of the master-level latch is connected to the output of the first master-level gate circuit and the input of the first slave-level gate circuit. The other end of the master-level latch is connected to the output of the second master-level gate circuit and the input of the second slave-level gate circuit. The output of the first slave-level gate circuit is connected to one end of the slave-level latch, and the output of the second slave-level gate circuit is connected to the other end of the slave-level latch.

[0032] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0033] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0034] In the process of filing this application, the applicant also discovered that flip-flops are the most commonly used sequential devices in digital circuits. This application mainly focuses on the ruggedization design of flip-flops to address the single-event upset effect.

[0035] Please see Figure 1 This is a schematic diagram of a trigger circuit provided by existing technology. For example... Figure 1 The illustrated flip-flop circuit 100 includes a master-slave two-stage latch structure 15. Both latch structures are identical, each comprising a feedback loop consisting of an inverter 12 and a gate circuit 13. The clock signal is latched at high and low levels by controlling the gate circuit. In the diagram, c and cn are connected to the non-inverting (c) and inverting (cn) terminals of the clock signal CK circuit, respectively. The latch, as a structure with storage and memory functions in the flip-flop circuit, is the core of the single-event upset (SET) hardened design for the flip-flop. Therefore, a flip-flop circuit hardened based on a latch structure is required.

[0036] Please see Figure 2 This is a schematic diagram of another trigger circuit provided in an embodiment of this application. Figure 2 The flip-flop circuit 200 shown includes: a logic input circuit 11, a first master-level gate circuit 131, a second master-level gate circuit 132, a first slave-level gate circuit 141, a second slave-level gate circuit 142, a master-level latch 151, a slave-level latch 152, and at least one inverter 12, wherein:

[0037] The logic input circuit 11, the first master-level gate circuit 131, and the first slave-level gate circuit 141 are connected in sequence. The logic input circuit 11, the first inverter 121 of the at least one inverter, the second master-level gate circuit 132, and the second slave-level gate circuit 142 are connected in sequence. One end of the master-level latch 151 is connected to the output terminal of the first master-level gate circuit 131 and the input terminal of the first slave-level gate circuit 141, respectively. The other end of the master-level latch 151 is connected to the output terminal of the second master-level gate circuit 132 and the input terminal of the second slave-level gate circuit 142, respectively. The output terminal of the first slave-level gate circuit 141 is connected to one end of the slave-level latch 152, and the output terminal of the second slave-level gate circuit 142 is connected to the other end of the slave-level latch 152.

[0038] As shown in the figure, the logic input circuit 11, the first master-level gate circuit 131, the master-level latch 151, the first slave-level gate circuit 141, and the slave-level latch 152 form a first transmission channel, also known as a first transmission path, which is illustrated as transmission channel a. The logic input circuit 11, the first inverter 121, the second master-level gate circuit 132, the master-level latch 151, the second slave-level gate circuit 142, and the slave-level latch 152 form a second transmission channel, also known as a second transmission path, which is illustrated as transmission channel b. In the figure, terminals c and cn are connected to clock signals, where cn represents the inverted signal corresponding to the input clock signal. For details, please refer to [reference needed]. Figure 1 The clock signal circuit CK shown is not described in detail here. The logic input circuit 11 is used to provide the input signal; both the first transmission channel and the second transmission channel are used to transmit the input signal according to the input clock signal.

[0039] In practical applications, taking an edge-triggered (rising edge) D flip-flop as an example, please refer to [link to relevant documentation]. Figure 3 The diagram illustrates the working principle of a flip-flop circuit. The circuit operates in two phases:

[0040] Phase 1: When the input clock signal is a low-level signal (the dashed line in the diagram represents the start point, and the solid line represents the end point), for the first transmission channel (transmission channel a in the diagram), the first master-level gate circuit 131 is turned on. At this time, the master-level latch 151 is in the data signal transmission state, and the input signal D is transmitted from the input terminal to the master-level latch 151, and simultaneously transmitted to the output terminal Xa of the master-level latch 151. At the same time, the first slave-level gate circuit 141 is turned off. At this time, the slave-level latch 152 is in the data signal latching state, and the output terminal Ya of the slave-level latch 152 maintains the data signal output in the previous phase / previous moment.

[0041] Phase Two: When the input clock signal transitions from a low level to a high level—that is, at the rising edge of the clock (solid line in the diagram)—for the first transmission channel (transmission channel a in the diagram), the first slave gate circuit 141 is activated. At this time, the slave latch 152 is in data signal transmission mode. The input signal D is input from the output terminal Xa of the master latch 151 to the slave latch 152, and simultaneously transmitted to the output terminal Ya of the slave latch 152. At the same time, the first master gate circuit 131 is deactivated. At this time, the master latch 151 is in data signal latching mode, and the output terminal Xa of the master latch 151 maintains the data signal output in the previous phase / previous moment.

[0042] It should be noted that this invention only describes the actual working principle of the first transmission channel as an example. The working principle of the second transmission channel (transmission channel b in the figure) is exactly the same as that of transmission channel a, except that the output level signal is reversed. The trigger circuit provided by this invention still consists of a master latch 151 and a slave latch 152. Taking the master latch 151 as an example, this invention can first process the input signal D into two inverted data signals "1" and "0". The two signals are respectively controlled by the clock signal to be transmitted to the two input / output terminals (also called nodes) of the master latch, and then transmitted to the slave latch 152 in a time-division manner. The transmission method of the slave latch 152 is the same as that of the master latch 151.

[0043] The latch structure 15 of the present invention has two storage nodes that are both inputs and outputs. The input signal is directly transmitted simultaneously through two channels (a and b) of the first transmission channel and the second transmission channel, without the need for the feedback structure of the master and slave latches, which can accelerate the transmission speed of the data signal.

[0044] In an optional embodiment, the control terminals of the master-level gate circuit and the slave-level gate circuit can be reversed (c and cn are swapped) to transform them into falling-edge D flip-flops.

[0045] In an optional embodiment, the at least one inverter 12 further includes a second inverter 122 and a third inverter 123. One end of the second inverter 122 is connected to the output of the first slave-level gate circuit 141, and the other end of the second inverter 122 is an output Qn of the entire flip-flop circuit. One end of the third inverter 123 is connected to the output of the second slave-level gate circuit 142, and the other end of the third inverter 123 is another output Q of the entire flip-flop circuit.

[0046] In an optional embodiment, please refer to Figure 4 (a)- Figure 4 (c) shows schematic diagrams of several possible gated circuits. Please refer to [link / reference]. Figure 4 (a) is a symbolic diagram of a gated circuit. In one specific embodiment, the gated circuit involved in this application includes four transistors connected in series, such as MOSFETs, specifically as follows: Figure 4 As shown in (b). IN represents the input terminal of the gate circuit, and OUT represents the output terminal of the gate circuit. OEN and OE are connected to a pair of clock signals with opposite phases. OEN is connected to the inverted clock signal (also represented as cn), and OE is connected to the same-phase clock signal (also represented as c); or OEN is connected to the same-phase clock signal (c), and OE is connected to the inverted clock signal (cn).

[0047] In another specific embodiment, the gated circuit involved in this application includes four transistors: a first transistor 1, a second transistor 2, a third transistor 3, and a fourth transistor 4. The first transistor 1 and the second transistor 2 are connected in series, and then connected in series with a combined device formed by the third transistor 3 and the fourth transistor 4 connected in parallel. In other words, an interconnection terminal of the series connection is connected to a connection terminal of the parallel connection, specifically as follows... Figure 5 As shown in (c).

[0048] In an optional embodiment, the latch involved in this application (specifically, the master latch 151 or the slave latch 152) is a latch with a reinforced structure to prevent the level of the feedback structure of the entire trigger circuit from flipping and being locked (unrecoverable) when particles are incident in a radiation environment, causing the output level of the trigger circuit to change.

[0049] In an optional embodiment, the latch (specifically, the reinforced structure within the latch) includes a first latch circuit 341 and a second latch circuit 342 connected in parallel, each of the first latch circuit 341 and the second latch circuit 342 including a delay element 16. See also... Figure 5 (a)- Figure 5 (c) shows a schematic diagram of several possible latch reinforcement structures.

[0050] In one specific embodiment, please refer to Figure 5 (a) The first latch circuit 341 includes a first delay element 161 and a fourth inverter 124 connected in series, and the second latch circuit 342 includes a second delay element 162 and a fifth inverter 125 connected in series. The first delay element 161 and the second delay element 162, and the fourth inverter 124 and the fifth inverter 125 are staggered, as shown in the figure. In the figure, INOUT1 and INOUT2 are the two input / output terminals of the latch, such as the input / output terminals Xa and Xb of the master latch 151 and the input / output terminals Ya and Yb of the slave latch 152.

[0051] In another specific embodiment, please refer to Figure 5 (b) The first latch circuit 341 includes a fourth inverter 124, and the second latch circuit 342 includes a first delay element 161 and a fifth inverter 125 connected in series. The fourth inverter 124 and the fifth inverter 125 are arranged in opposite directions, as shown in the figure.

[0052] In another specific embodiment, please refer to Figure 5(c) The first latch circuit 341 includes a first delay element 161 and a fourth inverter 124 connected in series, and the second latch circuit 342 includes a fifth inverter 125. The fourth inverter 124 and the fifth inverter 125 are configured in opposite directions, as shown in the figure.

[0053] In optional embodiments, the delay element involved in this application includes any one or more of the following: resistors, capacitors, or other devices with delay functions. For example, please refer to... Figure 6 (a)- Figure 6 (c) shows schematic diagrams of several possible delay elements. For example... Figure 6 In (a), the delay element is a resistor. For example... Figure 6 In (b), the delay element is a capacitor. For example... Figure 6 In (c), the delay element consists of a resistor and a capacitor. In the diagram, A and B represent the two ports of the delay element.

[0054] This invention strengthens the latch by adding a delay element to the feedback loop. The principle is as follows: when a node (output terminal) is affected by a single-particle incident radiation (level flip), the load delay characteristic of the delay element is used to maintain the node level at the other end of the feedback loop unchanged, and the level of the affected node is restored after the ionizing radiation ends.

[0055] Compared to existing unhardened trigger circuits, this invention adds only a small area overhead. Single-event immunity of the trigger can be achieved by adjusting delay components (resistance and / or capacitance values) for different radiation energies and process dimensions. The input signal is transmitted directly through two transmission channels simultaneously, eliminating the need for feedback structures via master and slave latches, thus improving circuit speed.

[0056] This application also provides a trigger, the trigger comprising the above-mentioned... Figures 2-6 The trigger circuit described in the embodiment. The edge-triggered trigger includes, but is not limited to, D triggers, synchronous reset D triggers, D scan triggers, synchronous reset scan triggers, RS triggers, or other types of triggers.

[0057] For example, please see Figure 7 (a)- Figure 7 (d) shows the logic input structure diagrams of several possible flip-flops. Among them, Figure 7 (a) represents a D flip-flop. Figure 7 (b) indicates a synchronously reset D flip-flop. Figure 7 (c) represents a D-scan trigger. Figure 7 (d) indicates a synchronous reset scan D flip-flop.

[0058] This application is also applicable to single-event upset (SWE) protection for other sequential circuits such as latch circuits. One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: This application provides a trigger circuit, including a logic input circuit with a circuit connection relationship, a first master-level gate circuit, a second master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter. The master-level latch and the slave-level latch are used to reinforce the circuit against SWE, preventing changes in the circuit output level due to the SWE effect, i.e., SWE resistance. This effectively solves the technical problem in the prior art where the circuit level flips and cannot be recovered when particles are incident on the circuit in a radiated environment.

[0059] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0060] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A single-event upset trigger circuit, characterized in that, The flip-flop circuit includes: a logic input circuit, a first master-level gate circuit, a second master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter, wherein: The logic input circuit, the first master-level gate circuit, and the first slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the second master-level gate circuit, and the second slave-level gate circuit are connected in sequence. One end of the master-level latch is connected to the output of the first master-level gate circuit and the input of the first slave-level gate circuit. The other end of the master-level latch is connected to the output of the second master-level gate circuit and the input of the second slave-level gate circuit. The output of the first slave-level gate circuit is connected to one end of the slave-level latch, and the output of the second slave-level gate circuit is connected to the other end of the slave-level latch. The master latch or the slave latch is a latch with a reinforced structure to prevent the level of the trigger circuit from flipping and being locked when particles are incident in a radiation environment, which would cause the output level of the trigger circuit to change. The reinforcement structure includes a first latch circuit and a second latch circuit connected in parallel, and either the first latch circuit or the second latch circuit includes a delay element. The first latch circuit includes a first delay element and a fourth inverter connected in series, and the second latch circuit includes a second delay element and a fifth inverter connected in series, wherein the first delay element and the second delay element, and the fourth inverter and the fifth inverter are respectively staggered. Alternatively, the first latch circuit includes a fourth inverter, and the second latch circuit includes a first delay element and a fifth inverter connected in series, wherein the fourth inverter and the fifth inverter are configured in opposite directions; Alternatively, the first latch circuit includes a first delay element and a fourth inverter connected in series, and the second latch circuit includes a fifth inverter, wherein the fourth inverter and the fifth inverter are configured in opposite directions.

2. The circuit according to claim 1, characterized in that, The logic input circuit, the first master-level gate circuit, the master-level latch, the first slave-level gate circuit, and the slave-level latch form a first transmission channel; the logic input circuit, the first inverter, the second master-level gate circuit, the master-level latch, the second slave-level gate circuit, and the slave-level latch form a second transmission channel; wherein: The logic input circuit is used to provide input signals; Both the first transmission channel and the second transmission channel are used to transmit the input signal.

3. The circuit according to claim 1, characterized in that, The at least one inverter further includes a second inverter and a third inverter, wherein the second inverter is connected to the output terminal of the first slave gate circuit, and the third inverter is connected to the output terminal of the second slave gate circuit.

4. The circuit according to claim 1, characterized in that, The delay element includes a resistor and / or a capacitor.

5. A trigger, characterized in that, The trigger includes the anti-single-event flip-flop trigger circuit as described in any one of claims 1-4 above.

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